diff --git a/flist/cortexm0_ip_ASIC.flist b/flist/cortexm0_ip_ASIC.flist
new file mode 100644
index 0000000000000000000000000000000000000000..a1457c86380ac00c3e2416fbb567149649a5d128
--- /dev/null
+++ b/flist/cortexm0_ip_ASIC.flist
@@ -0,0 +1,151 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Cortex-M0 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Cortex-M0
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Accelerator Module search path    =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+
+// Cortex-M0 Core IP
+// -y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_alu.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_ctl.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_dec.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_gpr.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_mul.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_pfu.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_psr.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_spu.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_bpu.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_ctl.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_dwt.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_if.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_sel.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix_sel.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_main.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_reg.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_tarmac.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_clk.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_dbg.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_sys.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v
+
+// Cortex-M0 Debug Access Port IP
+// -y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_cdc.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_mast_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_mast.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_cdc.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_jtag_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_jtag.v
+
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_pwr.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_sw_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_sw.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v
+
+// Cortex-M0 Top-level Integration
+// -y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_rst_ctl.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v
+
+// Cortex-M0 Cell Models
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_acg.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_capt_sync.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_addr.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_data.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_addr.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_data.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_reset.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_jt_cdc_comb_and.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_sw_cdc_capt_reset.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_acg.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_reset.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_set.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_reset.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_set.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v
+
+// Cortex-M0 Wrappers
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers/CORTEXM0IMP.v
+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers/CORTEXM0INTEGRATIONIMP.v
+
+// Cortex-M0 UALDIS
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_dec_t16.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_dec_t32.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ualdis.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_big_decimal.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_cond_field.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_decimal.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_expand_imm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_hex.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_imm_shift.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_reg_list.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_reg_name.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_fun_tab_align.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_add_sp.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_add_sub_sp.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_add_sub.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_adr.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_b_cond.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_bkpt.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_b.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_bx_blx.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_cbz.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_cps.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_dp_hi_reg.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_dp_imm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_dp_reg.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_extend.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_hints.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_it.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_ldm_stm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_literal.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_ls_h_imm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_ls_imm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_ls_reg.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_ls_sp.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_prefix_t32.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_push_pop.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_rev.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_setend.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_shift_imm.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_svc.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_undefined.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t16_unpredictable.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_b_bl.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_b_cond.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_dsb_dmb_isb.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_hints.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_mrs.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_msr.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_opcode_t16.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog/ual_t32_undefined.v
diff --git a/flist/slcorem0_ASIC.flist b/flist/slcorem0_ASIC.flist
new file mode 100644
index 0000000000000000000000000000000000000000..395cf3c470fc6231dd1bf0c4aef7d86361c0489a
--- /dev/null
+++ b/flist/slcorem0_ASIC.flist
@@ -0,0 +1,19 @@
+//-----------------------------------------------------------------------------
+// SLCore-M0 Top-level Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for SLCore-M0 IP
+//-----------------------------------------------------------------------------
+
+// Include Cortex-M0 IP
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/cortexm0_ip_ASIC.flist
+
+// SLCore IP 
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist