//-----------------------------------------------------------------------------
// SHA-2 Accelerator Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for SHA-2 Accelerator example
//-----------------------------------------------------------------------------

// ============= Verilog library extensions ===========
+libext+.v+.vlib

// =============    Accelerator Module search path    =============
-y $DESIGN/sha-2-accelerator/hdl/src/
+incdir+$DESIGN/sha-2-accelerator/hdl/src/

$DESIGN/sha-2-accelerator/hdl/src/fifo_vr.sv
$DESIGN/sha-2-accelerator/hdl/src/sha256_hash_compression.sv
$DESIGN/sha-2-accelerator/hdl/src/sha256_hashing_stream.sv
$DESIGN/sha-2-accelerator/hdl/src/sha256_message_build.sv

// $DESIGN/sha-2-accelerator/hdl/src/sha256_1_3_arbitrator.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_config_sync.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_engine.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_buf.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_issue.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_validator.sv
// $DESIGN/sha-2-accelerator/hdl/src/sha256_packet_manager.sv