From d88e763e75bb1df34f528dfdb5eb57541088efe2 Mon Sep 17 00:00:00 2001
From: dam1n19 <d.a.mapstone@soton.ac.uk>
Date: Wed, 7 Dec 2022 23:12:43 +0000
Subject: [PATCH] refactor: ATO2-24: Further restructured code to improve
readability
---
hdl/src/primatives/vr_fifo.sv | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hdl/src/primatives/vr_fifo.sv b/hdl/src/primatives/vr_fifo.sv
index 33e5455..41ebcb4 100644
--- a/hdl/src/primatives/vr_fifo.sv
+++ b/hdl/src/primatives/vr_fifo.sv
@@ -8,12 +8,11 @@
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module vr_fifo
- #(
- parameter DEPTH = 4, // FIFO Row Depth
- parameter DATA_W = 32, // FIFO Row Width
- parameter PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width
- )(
+module vr_fifo #(
+ parameter DEPTH = 4, // FIFO Row Depth
+ parameter DATA_W = 32, // FIFO Row Width
+ parameter PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width
+)(
input logic clk,
input logic nrst,
input logic en,
@@ -27,7 +26,7 @@ module vr_fifo
output logic [DATA_W-1:0] out_data,
input logic out_ready,
output logic out_valid
- );
+);
assign out_data = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
--
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