From a94524306e81af21652dbcc4f83befb0dfcd36ae Mon Sep 17 00:00:00 2001
From: dam1n19 <d.a.mapstone@soton.ac.uk>
Date: Wed, 7 Dec 2022 23:10:56 +0000
Subject: [PATCH] refactor: ATO2-24: restructured code to make it more readable
---
hdl/src/primatives/vr_fifo.sv | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hdl/src/primatives/vr_fifo.sv b/hdl/src/primatives/vr_fifo.sv
index c5d73b7..33e5455 100644
--- a/hdl/src/primatives/vr_fifo.sv
+++ b/hdl/src/primatives/vr_fifo.sv
@@ -29,12 +29,7 @@ module vr_fifo
output logic out_valid
);
- logic [DATA_W-1:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
- logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
- logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
- logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
-
- assign ptr_dif = write_ptr - read_ptr;
+ assign out_data = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
logic in_shake; // Successful Write Handshake
logic out_shake; // Successful Read Handshake
@@ -42,7 +37,14 @@ module vr_fifo
assign in_shake = (in_valid == 1'b1) && (in_ready == 1'b1);
assign out_shake = (out_valid == 1'b1) && (out_ready == 1'b1);
- // Conditions to write and read from FIFO's
+ logic [DATA_W-1:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
+ logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
+ logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
+ logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
+
+ assign ptr_dif = write_ptr - read_ptr;
+
+ // EXAMPLE: Conditions to write and read from FIFO's
// Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read
// 000 - 000 = 000 | Y | N
// 001 - 000 = 001 | Y | Y
@@ -55,8 +57,6 @@ module vr_fifo
// WriteValid: WritePtr - ReadPtr < 3'd4
// ReadValid: WritePtr - ReadPtr - 1 < 3'd4
- assign out_data = fifo [read_ptr[PTR_W-2:0]]; // Out Data is dereferenced value of the Read Pointer
-
always_ff @(posedge clk, negedge nrst) begin
if (!nrst) begin
// Under Reset
--
GitLab