diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
index 8b62d62bfbf2ed3f9f64add58275c3ca9b8cc75d..fb36012dbe7927f5b44a22363377a3551e713788 100755
--- a/flow/simulators/ivlog_sim.sh
+++ b/flow/simulators/ivlog_sim.sh
@@ -13,4 +13,4 @@
mkdir -p $SHA_2_ACC_DIR/simulate/sim/
iverilog -I $SHA_2_ACC_DIR/hdl/verif/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SHA_2_ACC_DIR/simulate/sim/$1.vvp $SHA_2_ACC_DIR/hdl/verif/tb_$1.sv
-cd $SHA_2_ACC_DIR/simulate/sim/ && vvp $1.vvp
\ No newline at end of file
+cd $SHA_2_ACC_DIR/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/flow/socsim b/flow/socsim
index 23dadfc47df4b2c334595f39125c247f928ad2f6..4c98dbf9a753f3873b7bc88e1312b4040d2ed08c 100755
--- a/flow/socsim
+++ b/flow/socsim
@@ -15,4 +15,4 @@ DEFAULT_SIMULATOR="ivlog"
if [[ -z "${SIMULATOR}" ]]; then
SIMULATOR=$DEFAULT_SIMULATOR
fi
-$SHA_2_ACC_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $1
+$SHA_2_ACC_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $@
diff --git a/hdl/verif/tb_sha256_hash_compression.sv b/hdl/verif/tb_sha256_hash_compression.sv
index 7c272aa9abc429c18508aa8abce49f7ca492d488..8bd190565fb995e9cc56c0511f8c2162aeb7d973 100644
--- a/hdl/verif/tb_sha256_hash_compression.sv
+++ b/hdl/verif/tb_sha256_hash_compression.sv
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Message Builder Testbench
+// SoC Labs Basic SHA-2 Hash Compression Testbench
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -48,10 +48,13 @@ module tb_sha256_hash_compression;
logic [511:0] data_in_queue [$];
logic data_in_last_queue [$];
+ int data_in_gap_queue [$];
logic data_in_wait_queue;
+
logic [255:0] data_out_queue [$];
logic data_out_last_queue [$];
+ int data_out_stall_queue [$];
logic data_out_wait_queue;
// Handle Valid and Data for data_in
@@ -60,15 +63,27 @@ module tb_sha256_hash_compression;
data_in <= 512'd0;
data_in_valid <= 1'b0;
data_in_last <= 1'b0;
+ data_in_gap <= 0;
data_in_wait_queue <= 1'b1;
end else if (data_in_drive_en) begin
+ if (data_in_gap > 0) begin
+ data_in_gap <= data_in_gap -1;
+ data_in_valid <= 1'b0;
+ end else begin
+ data_in_valid <= 1'b1;
+ end
if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
(data_in_wait_queue == 1'b1)) begin
// Data transfer just completed or transfers already up to date
- if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0)) begin
+ if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0) && (data_in_gap_queue.size() > 0)) begin
data_in <= data_in_queue.pop_front();
data_in_last <= data_in_last_queue.pop_front();
- data_in_valid <= 1'b1;
+ if (data_in_gap_queue[0] == 0) begin
+ data_in_valid <= 1'b1;
+ end else begin
+ data_in_valid <= 1'b0;
+ end
+ data_in_gap <= data_in_gap_queue.pop_front();
data_in_wait_queue <= 1'b0;
end else begin
// No data currently avaiable in queue to write but transfers up to date
@@ -79,25 +94,40 @@ module tb_sha256_hash_compression;
end
end
+
logic [255:0] data_out_check;
logic data_out_last_check;
- logic check_output;
- logic test_end;
- int packet_num;
+ int data_in_gap;
+ int data_out_stall;
- // Handle Output Ready Driving
- always_ff @(posedge clk, negedge nrst) begin: data_out_recieve
- if (!nrst) begin
- data_out_ready <= 1'b0;
- check_output <= 1'b0;
- test_end <= 1'b0;
- end else begin
- // Synchronise Ready to Clock
- if (data_out_drive_ready) begin
- data_out_ready <= 1'b1;
- end else begin
+ int packet_num;
+
+ // Handle Output Ready Signal Verification
+ always @(posedge clk) begin
+ // Check Override Control on Ready
+ if (data_out_drive_ready) begin
+ // Count down to zero before enabling Ready
+ if (data_out_stall > 0) begin
+ data_out_stall <= data_out_stall - 1;
data_out_ready <= 1'b0;
+ end else begin
+ // Wait for handshake before updating stall value
+ if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
+ if (data_out_stall_queue.size() > 0) begin
+ if (data_out_stall_queue[0] == 0) begin
+ data_out_ready <= 1'b1;
+ end else begin
+ data_out_ready <= 1'b0;
+ end
+ data_out_stall <= data_out_stall_queue.pop_front();
+ end
+ // Keep Ready Asserted until handshake seen
+ end else begin
+ data_out_ready <= 1'b1;
+ end
end
+ end else begin
+ data_out_ready <= 1'b0;
end
end
@@ -109,14 +139,14 @@ module tb_sha256_hash_compression;
$error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
$finish;
end
- $display("data_out match! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
+ if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
assert (data_out_last == data_out_last_check) else begin
$error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
$finish;
end
- $display("data_out_last match! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
+ if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
- data_out_check <= data_out_queue.pop_front();
+ data_out_check <= data_out_queue.pop_front();
data_out_last_check <= data_out_last_queue.pop_front();
if (data_out_last_check == 1'b1) begin
packet_num <= packet_num + 1;
@@ -133,47 +163,55 @@ module tb_sha256_hash_compression;
logic [511:0] input_data; // Temporary Input Data Storage
logic input_data_last; // Temporary Input Data Last
+ int input_data_gap; // Temporary Input Gap
+
logic [255:0] output_data; // Temporary Output Data Storage
logic output_data_last; // Temporary Output Data Last
+ int output_data_stall; // Temporary Output Stall
initial begin
$dumpfile("sha256_hash_compression.vcd");
- $dumpvars(0, tb_sha256_hash_compression);
- for (int i = 0; i < 16; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.M[i]);
- end
- for (int i = 0; i < 8; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.H[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.next_H[i]);
- end
- for (int i = 0; i < 64; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.W[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.next_W[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.ssig1_next_W[i]);
+ if ($test$plusargs ("DEBUG")) begin
+ $dumpvars(0, tb_sha256_hash_compression);
+ for (int i = 0; i < 16; i++) begin
+ $dumpvars(0, tb_sha256_hash_compression.uut.M[i]);
+ end
+ for (int i = 0; i < 8; i++) begin
+ $dumpvars(0, tb_sha256_hash_compression.uut.H[i]);
+ $dumpvars(0, tb_sha256_hash_compression.uut.next_H[i]);
+ end
+ for (int i = 0; i < 64; i++) begin
+ $dumpvars(0, tb_sha256_hash_compression.uut.W[i]);
+ $dumpvars(0, tb_sha256_hash_compression.uut.next_W[i]);
+ $dumpvars(0, tb_sha256_hash_compression.uut.ssig1_next_W[i]);
+ end
end
data_in_drive_en = 0;
data_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/testbench/inout_message_block_stim_ref.csv", "r");
- while ($fscanf (fd, "%x,%b", input_data, input_data_last) == 2) begin
+ fd = $fopen("../stimulus/testbench/input_message_block_stim.csv", "r");
+ while ($fscanf (fd, "%x,%b,%d", input_data, input_data_last, input_data_gap) == 3) begin
data_in_queue.push_back(input_data);
data_in_last_queue.push_back(input_data_last);
+ data_in_gap_queue.push_back(input_data_gap);
end
$fclose(fd);
// Read output data into Queue
fd = $fopen("../stimulus/testbench/output_hash_ref.csv", "r");
- while ($fscanf (fd, "%x,%b", output_data, output_data_last) == 2) begin
+ while ($fscanf (fd, "%x,%b,%d", output_data, output_data_last, output_data_stall) == 3) begin
data_out_queue.push_back(output_data);
data_out_last_queue.push_back(output_data_last);
+ data_out_stall_queue.push_back(output_data_stall);
end
$fclose(fd);
// Initialise First Checking Values
- data_out_check = data_out_queue.pop_front();
+ data_out_check = data_out_queue.pop_front();
data_out_last_check = data_out_last_queue.pop_front();
+ data_out_stall = data_out_stall_queue.pop_front();
// Enable Hash Compression
en = 1;
diff --git a/hdl/verif/tb_sha256_message_build.sv b/hdl/verif/tb_sha256_message_build.sv
index 7755fceaf9b7d25600391d9e65d72e7997d57cbc..eadec31c943637eace6d8bf6c6174cd5a88825c9 100644
--- a/hdl/verif/tb_sha256_message_build.sv
+++ b/hdl/verif/tb_sha256_message_build.sv
@@ -119,7 +119,7 @@ module tb_sha256_message_build;
cfg_scheme <= 2'd0;
cfg_valid <= 1'b0;
cfg_last <= 1'b0;
- cfg_gap <= 0;
+ cfg_gap <= 0;
cfg_wait_queue <= 1'b1;
end else if (cfg_drive_en) begin
if (cfg_gap > 0) begin
@@ -196,12 +196,12 @@ module tb_sha256_message_build;
$error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
$finish;
end
- $display("data_out match! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
+ if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
assert (data_out_last == data_out_last_check) else begin
$error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
$finish;
end
- $display("data_out_last match! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
+ if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
data_out_check <= data_out_queue.pop_front();
data_out_last_check <= data_out_last_queue.pop_front();
@@ -272,7 +272,7 @@ module tb_sha256_message_build;
data_out_stall = data_out_stall_queue.pop_front();
// Defaultly enable Message Builder
- en = 1;
+ en = 1;
// Defaultly set Sync Reset Low
sync_rst = 0;