From 2052816dcfebf3ce82f6e45cb2e60b1368c033d5 Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Tue, 28 Feb 2023 10:32:19 +0000
Subject: [PATCH] Updated Readme

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index d913a32..f362c9a 100644
--- a/README.md
+++ b/README.md
@@ -14,6 +14,7 @@ HDL contains all the verilog files. This is seperated into:
 src contains SystemVerilog design files and verif contains the SystemVerilog testbenches and verification resources.
 
 The simulate directory contains the socsim script, along with a directory called "simulators" which contains simulator-specific scripts and a "sim" directory which contains dumps and logs from simulation runs. The files in this directory should not be commited to the Git.
+
 ## Setting Up Environment
 To be able to simulate in this repository, you will first need to source the sourceme:
 ```
-- 
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