diff --git a/hdl/verif/tb_sha256_config_sync.sv b/hdl/verif/tb_sha256_config_sync.sv
index b71746637e0945c923d670805ea0954d6ab44530..f8589bcf0e5af9ef53e16dba4284191d4f348473 100644
--- a/hdl/verif/tb_sha256_config_sync.sv
+++ b/hdl/verif/tb_sha256_config_sync.sv
@@ -272,7 +272,7 @@ module tb_sha256_config_sync;
cfg_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/testbench/input_id_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_id_stim.csv", "r");
while ($fscanf (fd, "%d,%b,%d", temp_id_in, temp_id_in_last, temp_id_in_gap) == 3) begin
id_in_queue.push_back(temp_id_in);
id_in_last_queue.push_back(temp_id_in_last);
@@ -281,7 +281,7 @@ module tb_sha256_config_sync;
$fclose(fd);
// Read input cfg into Queue
- fd = $fopen("../stimulus/testbench/input_cfg_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_cfg_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%b,%d", temp_cfg_in_size, temp_cfg_in_scheme, temp_cfg_in_last, temp_cfg_in_gap) == 4) begin
cfg_in_size_queue.push_back(temp_cfg_in_size);
cfg_in_scheme_queue.push_back(temp_cfg_in_scheme);
@@ -291,7 +291,7 @@ module tb_sha256_config_sync;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_cfg_sync_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_cfg_sync_ref.csv", "r");
while ($fscanf (fd, "%x,%x,%d,%b,%d", temp_cfg_out_size, temp_cfg_out_scheme, temp_cfg_out_id, temp_cfg_out_last, temp_cfg_out_stall) == 5) begin
cfg_out_size_queue.push_back(temp_cfg_out_size);
cfg_out_scheme_queue.push_back(temp_cfg_out_scheme);
diff --git a/hdl/verif/tb_sha256_engine.sv b/hdl/verif/tb_sha256_engine.sv
index 7b00a73980c2102f90e97c98d08b263b4a74ad68..585a494c655587cc46e39a704464bb166780ce33 100644
--- a/hdl/verif/tb_sha256_engine.sv
+++ b/hdl/verif/tb_sha256_engine.sv
@@ -296,7 +296,7 @@ module tb_sha256_engine;
data_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/testbench/input_data_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_data_stim.csv", "r");
while ($fscanf (fd, "%x,%b,%d", input_data, input_data_last, input_data_gap) == 3) begin
data_in_queue.push_back(input_data);
data_in_last_queue.push_back(input_data_last);
@@ -305,7 +305,7 @@ module tb_sha256_engine;
$fclose(fd);
// Read input cfg into Queue
- fd = $fopen("../stimulus/testbench/input_cfg_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_cfg_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%b,%d", input_cfg_size, input_cfg_scheme, input_cfg_last, input_cfg_gap) == 4) begin
cfg_size_queue.push_back(input_cfg_size);
cfg_scheme_queue.push_back(input_cfg_scheme);
@@ -315,7 +315,7 @@ module tb_sha256_engine;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_hash_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_hash_ref.csv", "r");
while ($fscanf (fd, "%x,%b,%d", output_data, output_data_last, output_data_stall) == 3) begin
data_out_queue.push_back(output_data);
data_out_last_queue.push_back(output_data_last);
@@ -324,7 +324,7 @@ module tb_sha256_engine;
$fclose(fd);
// Read Message Block data into Queue
- fd = $fopen("../stimulus/testbench/output_message_block_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_message_block_ref.csv", "r");
while ($fscanf (fd, "%x,%b,%d", message_block_data, message_block_data_last, message_block_stall) == 3) begin
message_block_queue.push_back(message_block_data);
message_block_last_queue.push_back(message_block_data_last);
diff --git a/hdl/verif/tb_sha256_hash_compression.sv b/hdl/verif/tb_sha256_hash_compression.sv
index 3b441ab73915f6da861af533a5f37fc50ea6d281..7315a15f8567e7bb3c5bf98dfde6b872510d673d 100644
--- a/hdl/verif/tb_sha256_hash_compression.sv
+++ b/hdl/verif/tb_sha256_hash_compression.sv
@@ -204,7 +204,7 @@ module tb_sha256_hash_compression;
data_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/testbench/input_message_block_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_message_block_stim.csv", "r");
while ($fscanf (fd, "%x,%d,%b,%d", temp_data_in, temp_data_in_id, temp_data_in_last, temp_data_in_gap) == 4) begin
data_in_queue.push_back(temp_data_in);
data_in_id_queue.push_back(temp_data_in_id);
@@ -214,7 +214,7 @@ module tb_sha256_hash_compression;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_hash_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_hash_ref.csv", "r");
while ($fscanf (fd, "%x,%d,%b,%d", temp_data_out, temp_data_out_id, temp_data_out_last, temp_data_out_stall) == 4) begin
data_out_queue.push_back(temp_data_out);
data_out_id_queue.push_back(temp_data_out_id);
diff --git a/hdl/verif/tb_sha256_id_buf.sv b/hdl/verif/tb_sha256_id_buf.sv
index 85569290f47677a62f5265ce4f95ec3c3425a41e..640b7aba2c343a22edbb04489fa83050a20ebb8e 100644
--- a/hdl/verif/tb_sha256_id_buf.sv
+++ b/hdl/verif/tb_sha256_id_buf.sv
@@ -207,7 +207,7 @@ module tb_sha256_id_buf;
id_out_drive_ready = 0;
// Read input data into Queue in
- fd = $fopen("../stimulus/testbench/input_buf_id_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_buf_id_stim.csv", "r");
while ($fscanf (fd, "%d,%b,%d", temp_id_in, temp_id_in_last, temp_id_in_gap) == 3) begin
id_in_queue.push_back(temp_id_in);
id_in_last_queue.push_back(temp_id_in_last);
@@ -216,7 +216,7 @@ module tb_sha256_id_buf;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_buf_id_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_buf_id_ref.csv", "r");
while ($fscanf (fd, "%d,%b,%d,%d", temp_id_out, temp_id_out_last, temp_status_id_out, temp_id_out_stall) == 4) begin
id_out_queue.push_back(temp_id_out);
id_out_last_queue.push_back(temp_id_out_last);
diff --git a/hdl/verif/tb_sha256_id_issue.sv b/hdl/verif/tb_sha256_id_issue.sv
index 124e77e9bf0947d0ff0314a2b33f9cf7da9a0ec7..7121f3d62c5b1baef91414521592452afa75063b 100644
--- a/hdl/verif/tb_sha256_id_issue.sv
+++ b/hdl/verif/tb_sha256_id_issue.sv
@@ -192,7 +192,7 @@ module tb_sha256_id_issue;
id_out_buf_drive_ready = 0;
// Read output cfg data into Queue
- fd = $fopen("../stimulus/testbench/output_id_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_id_ref.csv", "r");
while ($fscanf (fd, "%d,%b,%d", id_cfg_data, id_cfg_last, id_cfg_stall) == 3) begin
id_out_cfg_queue.push_back(id_cfg_data);
id_out_cfg_last_queue.push_back(id_cfg_last);
@@ -201,7 +201,7 @@ module tb_sha256_id_issue;
$fclose(fd);
// Read output buf data into Queue
- fd = $fopen("../stimulus/testbench/output_id_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_id_ref.csv", "r");
while ($fscanf (fd, "%d,%b,%d", id_buf_data, id_buf_last, id_buf_stall) == 3) begin
id_out_buf_queue.push_back(id_buf_data);
id_out_buf_last_queue.push_back(id_buf_last);
diff --git a/hdl/verif/tb_sha256_id_validator.sv b/hdl/verif/tb_sha256_id_validator.sv
index 15df193b64395cd0ee7392f90bf2aa79bb14a64e..39e17390369eaf87117eff0bbfbe8855595e3555 100644
--- a/hdl/verif/tb_sha256_id_validator.sv
+++ b/hdl/verif/tb_sha256_id_validator.sv
@@ -281,7 +281,7 @@ module tb_sha256_id_validator;
hash_out_drive_ready = 0;
// Read input data into Queuein
- fd = $fopen("../stimulus/testbench/input_validator_id_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_validator_id_stim.csv", "r");
while ($fscanf (fd, "%d,%b,%d", temp_id_in_buf, temp_id_in_buf_last, temp_id_in_buf_gap) == 3) begin
id_in_buf_queue.push_back(temp_id_in_buf);
id_in_buf_last_queue.push_back(temp_id_in_buf_last);
@@ -290,7 +290,7 @@ module tb_sha256_id_validator;
$fclose(fd);
// Read input cfg into Queue
- fd = $fopen("../stimulus/testbench/input_hash_in_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_hash_in_stim.csv", "r");
while ($fscanf (fd, "%x,%d,%b,%d", temp_hash_in, temp_hash_in_id, temp_hash_in_last, temp_hash_in_gap) == 4) begin
hash_in_queue.push_back(temp_hash_in);
hash_in_id_queue.push_back(temp_hash_in_id);
@@ -300,7 +300,7 @@ module tb_sha256_id_validator;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_hash_out_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_hash_out_ref.csv", "r");
while ($fscanf (fd, "%x,%b,%b,%d", temp_hash_out, temp_hash_out_err, temp_hash_out_last, temp_hash_out_stall) == 4) begin
hash_out_queue.push_back(temp_hash_out);
hash_out_err_queue.push_back(temp_hash_out_err);
diff --git a/hdl/verif/tb_sha256_message_build.sv b/hdl/verif/tb_sha256_message_build.sv
index f45c52d236c040eae7057dcc1a4437b82bcc35a8..b6d66c2d180fadd723e00f2821c63217ed137f35 100644
--- a/hdl/verif/tb_sha256_message_build.sv
+++ b/hdl/verif/tb_sha256_message_build.sv
@@ -263,7 +263,7 @@ module tb_sha256_message_build;
data_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/testbench/input_data_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_data_stim.csv", "r");
while ($fscanf (fd, "%x,%b,%d", temp_data_in, temp_data_in_last, temp_data_in_gap) == 3) begin
data_in_queue.push_back(temp_data_in);
data_in_last_queue.push_back(temp_data_in_last);
@@ -272,7 +272,7 @@ module tb_sha256_message_build;
$fclose(fd);
// Read input cfg into Queue
- fd = $fopen("../stimulus/testbench/input_cfg_sync_stim.csv", "r");
+ fd = $fopen("../stimulus/unit/input_cfg_sync_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%d,%b,%d", temp_cfg_in_size, temp_cfg_in_scheme, temp_cfg_in_id, temp_cfg_in_last, temp_cfg_in_gap) == 5) begin
cfg_size_queue.push_back(temp_cfg_in_size);
cfg_scheme_queue.push_back(temp_cfg_in_scheme);
@@ -283,7 +283,7 @@ module tb_sha256_message_build;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/testbench/output_message_block_ref.csv", "r");
+ fd = $fopen("../stimulus/unit/output_message_block_ref.csv", "r");
while ($fscanf (fd, "%x,%d,%b,%d", temp_data_out, temp_data_out_id, temp_data_out_last, temp_data_out_stall) == 4) begin
data_out_queue.push_back(temp_data_out);
data_out_id_queue.push_back(temp_data_out_id);
diff --git a/hdl/wrapper/packet_const.sv b/hdl/wrapper/packet_const.sv
new file mode 100644
index 0000000000000000000000000000000000000000..16256b88ca3f4d934703cef1d3e3a416f4b4a87b
--- /dev/null
+++ b/hdl/wrapper/packet_const.sv
@@ -0,0 +1,84 @@
+module packet_const #(
+ parameter PACKETWIDTH=512,
+ parameter ADDRWIDTH=11
+)(
+ input logic hclk, // clock
+ input logic hresetn, // reset
+
+ //Register interface
+ input logic [ADDRWIDTH-1:0] addr,
+ input logic read_en,
+ input logic write_en,
+ input logic [3:0] byte_strobe,
+ input logic [31:0] wdata,
+ output logic [31:0] rdata,
+
+ output logic [PACKETWIDTH-1:0] data_out,
+ output logic data_out_last,
+ output logic data_out_valid,
+ input logic data_out_ready
+);
+
+// 4KiB of Address Space for Accelerator (11:0)
+// Capture Address to be used for comparision to test for address jumping
+logic [ADDRWIDTH-1:0] last_wr_addr;
+// Create Construction Buffer
+logic [PACKETWIDTH-1:0] const_buffer;
+logic const_buffer_last;
+
+logic [ADDRWIDTH-1:0] addr_top_bit;
+assign addr_top_bit = (addr[5:2] * 32) - 1;
+
+// Dump data on one of two conditions
+// - An address ends [5:0] in 0x3C i.e. [5:2] == 0xF
+// - Address Moved to different 512 bit word
+// Write Condition
+always_ff @(posedge hclk or negedge hresetn) begin
+ if (~hresetn) begin
+ // Reset Construction Buffer
+ const_buffer <= {PACKETWIDTH{1'b0}};
+ end else begin
+ if (write_en) begin
+ // If not (awaiting handshake AND address generates new data payload)
+ if (!((data_out_valid && !data_out_ready) && (addr[5:2] == 4'hF))) begin
+ // Buffer Address for future Comparison
+ last_wr_addr <= addr;
+
+ // If 512 Word Address Changed, Clear Buffer
+ if (last_wr_addr[ADDRWIDTH-1:6] != addr [ADDRWIDTH-1:6]) const_buffer <= {PACKETWIDTH{1'b0}};
+
+ // Write Word into Construction Buffer
+ const_buffer[addr_top_bit -: 32] <= wdata;
+
+ // If last 32 bit word of 512 bit buffer
+ if (addr[5:2] == 4'hF) begin
+ // Produce Data Output
+ data_out <= {wdata,const_buffer[479:0]}; // Top word won't be in const_buffer
+ // - until next cycle to splice it in to out data combinatorially
+ // Calculate Last Flag
+ data_out_last <= (addr[ADDRWIDTH-1:6] == 5'h1F) ? 1'b1 : 1'b0;
+ // Take Valid High
+ data_out_valid <= 1'b1;
+ // Reset Construction Buffer
+ const_buffer <= 512'd0;
+ end
+ end else begin
+ // TODO: Implement Error Propogation/Waitstates
+ end
+ end
+ end
+end
+
+// Read Condition
+always_comb begin
+ if (read_en) begin
+ // Read appropriate 32 bits from buffer
+ //
+ rdata = const_buffer[addr_top_bit -: 32];
+ end else begin
+ rdata = 32'd0;
+ end
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/hdl/wrapper/wrap_sha256_hash_compression.sv b/hdl/wrapper/wrap_sha256_hash_compression.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ef65f128eb00617b09bd7a702c72cea473cf10fb
--- /dev/null
+++ b/hdl/wrapper/wrap_sha256_hash_compression.sv
@@ -0,0 +1,261 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Basic SHA-2 Hash Compression AHB Wrapper
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
+// each register can be accessed by byte, half word or word.
+// The example slave always output ready and OKAY response to the master
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "reg_to_512_vr.sv"
+`include "fifo_vr.sv"
+
+module wrap_sha256_hash_compression #(
+ // Parameter for address width
+ parameter ADDRWIDTH=12) // Peripheral Address Width
+ (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to master
+ input wire HSELS,
+ input wire [ADDRWIDTH-1:0] HADDRS,
+ input wire [1:0] HTRANSS,
+ input wire [2:0] HSIZES,
+ input wire HWRITES,
+ input wire HREADYS,
+ input wire [31:0] HWDATAS,
+
+ output wire HREADYOUTS,
+ output wire HRESPS,
+ output wire [31:0] HRDATAS);
+
+
+ // ----------------------------------------
+ // Internal wires declarations
+
+ // Register module interface signals
+ wire [ADDRWIDTH-1:0] in_buf_addr;
+ wire in_buf_read_en;
+ wire in_buf_write_en;
+ wire [3:0] in_buf_byte_strobe;
+ wire [31:0] in_buf_wdata;
+ wire [31:0] in_buf_rdata;
+
+ //-----------------------------------------------------------
+ // Module logic start
+ //----------------------------------------------------------
+
+ // Interface block to convert AHB transfers to simple read/write
+ // controls.
+ cmsdk_ahb_eg_slave_interface
+ #(.ADDRWIDTH (ADDRWIDTH))
+ u_ahb_eg_slave_interface (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Input slave port: 32 bit data bus interface
+ .hsels (HSELS),
+ .haddrs (HADDRS),
+ .htranss (HTRANSS),
+ .hsizes (HSIZES),
+ .hwrites (HWRITES),
+ .hreadys (HREADYS),
+ .hwdatas (HWDATAS),
+
+ .hreadyouts (HREADYOUTS),
+ .hresps (HRESPS),
+ .hrdatas (HRDATAS),
+
+ // Register interface
+ .addr (in_buf_addr),
+ .read_en (in_buf_read_en),
+ .write_en (in_buf_write_en),
+ .byte_strobe (in_buf_byte_strobe),
+ .wdata (in_buf_wdata),
+ .rdata (in_buf_rdata)
+ );
+
+ reg_to_512_vr
+ #(.ADDRWIDTH (ADDRWIDTH))
+ u_reg_to_512_vr (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Register interface
+ .addr (in_buf_addr),
+ .read_en (in_buf_read_en),
+ .write_en (in_buf_write_en),
+ .byte_strobe (in_buf_byte_strobe),
+ .wdata (in_buf_wdata),
+ .rdata (in_buf_rdata)
+ );
+ cmsdk_ahb_eg_slave_interface
+ #(.ADDRWIDTH (ADDRWIDTH))
+ u_ahb_eg_slave_interface (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Input slave port: 32 bit data bus interface
+ .hsels (HSELS),
+ .haddrs (HADDRS),
+ .htranss (HTRANSS),
+ .hsizes (HSIZES),
+ .hwrites (HWRITES),
+ .hreadys (HREADYS),
+ .hwdatas (HWDATAS),
+
+ .hreadyouts (HREADYOUTS),
+ .hresps (HRESPS),
+ .hrdatas (HRDATAS),
+
+ // Register interface
+ .addr (reg_addr),
+ .read_en (reg_read_en),
+ .write_en (reg_write_en),
+ .byte_strobe (reg_byte_strobe),
+ .wdata (reg_wdata),
+ .rdata (reg_rdata)
+ );
+
+ // Simple data register block with four 32-bit registers
+ cmsdk_ahb_eg_slave_reg
+ #(.ADDRWIDTH (ADDRWIDTH))
+ u_ahb_eg_slave_reg (
+
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Register interface
+ .addr (reg_addr),
+ .read_en (reg_read_en),
+ .write_en (reg_write_en),
+ .byte_strobe (reg_byte_strobe),
+ .wdata (reg_wdata),
+ .ecorevnum (ECOREVNUM),
+ .rdata (reg_rdata)
+
+ );
+
+ //-----------------------------------------------------------
+ //Module logic end
+ //----------------------------------------------------------
+`ifdef ARM_AHB_ASSERT_ON
+
+ `include "std_ovl_defines.h"
+ // ------------------------------------------------------------
+ // Assertions
+ // ------------------------------------------------------------
+
+ wire ovl_trans_req = HREADYS & HSELS & HTRANSS[1];
+
+ // Check the reg_write_en signal generated
+ assert_next
+ #(`OVL_ERROR, 1,1,0,
+ `OVL_ASSERT,
+ "Error! register write signal was not generated! "
+ )
+ u_ovl_ahb_eg_slave_reg_write
+ (.clk ( HCLK ),
+ .reset_n (HRESETn),
+ .start_event ((ovl_trans_req & HWRITES)),
+ .test_expr (reg_write_en == 1'b1)
+ );
+
+
+ // Check the reg_read_en signal generated
+ assert_next
+ #(`OVL_ERROR, 1,1,0,
+ `OVL_ASSERT,
+ "Error! register read signal was not generated! "
+ )
+ u_ovl_ahb_eg_slave_reg_read
+ (.clk ( HCLK ),
+ .reset_n (HRESETn),
+ .start_event ((ovl_trans_req & (~HWRITES))),
+ .test_expr (reg_read_en == 1'b1)
+ );
+
+
+
+ // Check register read and write operation won't assert at the same cycle
+ assert_never
+ #(`OVL_ERROR,
+ `OVL_ASSERT,
+ "Error! register read and write active at the same cycle!")
+ u_ovl_ahb_eg_slave_rd_wr_illegal
+ (.clk(HCLK),
+ .reset_n(HRESETn),
+ .test_expr((reg_write_en & reg_read_en))
+ );
+
+`endif
+
+endmodule
+
+
+
+ // Data In data and Handshaking
+ logic [511:0] engine_data_in;
+ logic [5:0] engine_data_in_id;
+ logic engine_data_in_last;
+ logic enigne_data_in_valid;
+ logic enigne_data_in_ready;
+
+ // Data Out data and Handshaking
+ logic [255:0] engine_data_out;
+ logic [5:0] engine_data_out_id;
+ logic engine_data_out_last;
+ logic engine_data_out_valid;
+ logic engine_data_out_ready;
+
+ // Input Buffer
+ fifo_vr #(16, // Depth
+ 512 // Data Width
+ ) data_in_buffer (
+ .clk (clk),
+ .nrst (nrst),
+ .en (en),
+ .sync_rst (sync_rst),
+ .data_in (data_in),
+ .data_in_valid (data_in_valid),
+ .data_in_ready (data_in_ready),
+ .data_in_last (data_in_last),
+ .data_out (data_in_buffered),
+ .data_out_last (data_in_last_buffered),
+ .data_out_valid (data_in_valid_buffered),
+ .data_out_ready (data_in_ready_buffered)
+ );
+
+ // Input Word Combiner
+
+endmodule
\ No newline at end of file
diff --git a/model/py/hash_model.py b/model/py/hash_model.py
index a8decd76a7df91be685b21183c41f2b3c066c26e..ce88343708093bf89d870404d0b933b1413901b9 100644
--- a/model/py/hash_model.py
+++ b/model/py/hash_model.py
@@ -252,49 +252,49 @@ def main():
# Write out Input ID Seed to Text File
input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_id_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_id_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(expected_id_list):
writer.writerow([expected_id_list[idx], "1", id_gap_list[idx]])
# Write out Buffer Input ID to Text File
input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_buf_id_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_buf_id_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(id_buf_id_list):
writer.writerow([id_buf_id_list[idx], "1", id_gap_list[idx]])
# Write out Input Validator ID Seed to Text File
input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_validator_id_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_validator_id_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(id_validator_buf_list):
writer.writerow([id_validator_buf_list[idx], "1", id_gap_list[idx]])
# Write out Output ID Values to Text File
input_header = ["expected_id_value, id_last, stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_id_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_id_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(expected_id_list):
writer.writerow([word, "1", expected_id_stall_list[idx]])
# Write out Output ID Values to Text File
input_header = ["expected_id_value, id_last, status_id, stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_buf_id_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_buf_id_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(id_buf_id_list):
writer.writerow([word, "1", word, expected_id_stall_list[idx]])
# Write out Input Data Stimulus to Text File
input_header = ["input_data", "input_data_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_data_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_data_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(in_data_words_list):
writer.writerow(["{0:x}".format(int(word, 2)), in_data_words_last_list[idx], in_data_words_gap_list[idx]])
# Write out Input Data 32bit AHB Stimulus to Text File
input_header = ["input_data_32word", "input_data_32word_last", "input_data_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_data_32bit_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(in_data_words_list):
sub_word_count = 0
@@ -308,49 +308,49 @@ def main():
# Write out Cfg Stimulus to Text File
input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_cfg_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_cfg_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(in_cfg_words_list):
writer.writerow(["{0:x}".format(int(word, 2)), "0", "1", in_cfg_words_gap_list[idx]])
# Write out Cfg Stimulus to Text File
input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_id", "input_cfg_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_cfg_sync_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_cfg_sync_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(in_cfg_words_list):
writer.writerow(["{0:x}".format(int(word, 2)), "0", expected_id_list[idx] ,"1", in_cfg_words_gap_list[idx]])
# Write out Cfg sync reference to Text File
input_header = ["output_cfg_size", "output_cfg_scheme", "output_cfg_id", "output_cfg_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_cfg_sync_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_cfg_sync_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(sync_cfg_size_list):
writer.writerow(["{0:x}".format(int(word, 2)), "0", sync_cfg_id_list[idx], "1", sync_cfg_stall_list[idx]])
# Write out Expected output to text file
output_header = ["output_data", "output_data_id", "output_data_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_message_block_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_message_block_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(message_block_list):
writer.writerow(["{0:x}".format(int(word, 2)), message_block_id_list[idx], message_block_last_list[idx], message_block_stall_list[idx]])
# Write out Message Block (Input) to text file
output_header = ["message_block_data", "message_block_id", "message_block_data_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_message_block_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_message_block_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(message_block_list):
writer.writerow(["{0:x}".format(int(word, 2)), message_block_id_list[idx], message_block_last_list[idx], message_block_gap_list[idx]])
# Write out hash value to text file
output_header = ["output_data", "output_id", "output_data_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_hash_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_hash_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(hash_list):
writer.writerow([word, expected_id_list[idx], "1", hash_stall_list[idx]])
# Write out hash value to text file
output_header = ["output_data", "output_sub_word_last", "output_data_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_hash_32bit_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "output_hash_32bit_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(hash_list):
sub_word_count = 0
@@ -364,14 +364,14 @@ def main():
# Write out Validator Hash Input to text file
output_header = ["hash_in", "hash_in_id", "hash_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "input_hash_in_stim.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_hash_in_stim.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(hash_list):
writer.writerow([word, id_validator_hash_list[idx], "1", hash_gap_list[idx]])
# Write out hash out (include error) value to text file
output_header = ["hash", "hash_err", "hash_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/testbench/" + "output_hash_out_ref.csv", "w", encoding="UTF8", newline='') as f:
+ with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_hash_out_ref.csv", "w", encoding="UTF8", newline='') as f:
writer = csv.writer(f)
for idx, word in enumerate(val_hash_list):
writer.writerow([word, hash_err_list[idx], "1", hash_stall_list[idx]])
diff --git a/simulate/stimulus/testbench/input_data_32bit_stim.csv b/simulate/stimulus/system/input_data_32bit_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_data_32bit_stim.csv
rename to simulate/stimulus/system/input_data_32bit_stim.csv
diff --git a/simulate/stimulus/testbench/output_hash_32bit_ref.csv b/simulate/stimulus/system/output_hash_32bit_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_hash_32bit_ref.csv
rename to simulate/stimulus/system/output_hash_32bit_ref.csv
diff --git a/simulate/stimulus/testbench/input_buf_id_stim.csv b/simulate/stimulus/unit/input_buf_id_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_buf_id_stim.csv
rename to simulate/stimulus/unit/input_buf_id_stim.csv
diff --git a/simulate/stimulus/testbench/input_cfg_stim.csv b/simulate/stimulus/unit/input_cfg_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_cfg_stim.csv
rename to simulate/stimulus/unit/input_cfg_stim.csv
diff --git a/simulate/stimulus/testbench/input_cfg_sync_stim.csv b/simulate/stimulus/unit/input_cfg_sync_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_cfg_sync_stim.csv
rename to simulate/stimulus/unit/input_cfg_sync_stim.csv
diff --git a/simulate/stimulus/testbench/input_data_stim.csv b/simulate/stimulus/unit/input_data_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_data_stim.csv
rename to simulate/stimulus/unit/input_data_stim.csv
diff --git a/simulate/stimulus/testbench/input_hash_in_stim.csv b/simulate/stimulus/unit/input_hash_in_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_hash_in_stim.csv
rename to simulate/stimulus/unit/input_hash_in_stim.csv
diff --git a/simulate/stimulus/testbench/input_id_stim.csv b/simulate/stimulus/unit/input_id_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_id_stim.csv
rename to simulate/stimulus/unit/input_id_stim.csv
diff --git a/simulate/stimulus/testbench/input_message_block_stim.csv b/simulate/stimulus/unit/input_message_block_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_message_block_stim.csv
rename to simulate/stimulus/unit/input_message_block_stim.csv
diff --git a/simulate/stimulus/testbench/input_validator_id_stim.csv b/simulate/stimulus/unit/input_validator_id_stim.csv
similarity index 100%
rename from simulate/stimulus/testbench/input_validator_id_stim.csv
rename to simulate/stimulus/unit/input_validator_id_stim.csv
diff --git a/simulate/stimulus/testbench/output_buf_id_ref.csv b/simulate/stimulus/unit/output_buf_id_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_buf_id_ref.csv
rename to simulate/stimulus/unit/output_buf_id_ref.csv
diff --git a/simulate/stimulus/testbench/output_cfg_sync_ref.csv b/simulate/stimulus/unit/output_cfg_sync_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_cfg_sync_ref.csv
rename to simulate/stimulus/unit/output_cfg_sync_ref.csv
diff --git a/simulate/stimulus/testbench/output_hash_out_ref.csv b/simulate/stimulus/unit/output_hash_out_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_hash_out_ref.csv
rename to simulate/stimulus/unit/output_hash_out_ref.csv
diff --git a/simulate/stimulus/testbench/output_hash_ref.csv b/simulate/stimulus/unit/output_hash_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_hash_ref.csv
rename to simulate/stimulus/unit/output_hash_ref.csv
diff --git a/simulate/stimulus/testbench/output_id_ref.csv b/simulate/stimulus/unit/output_id_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_id_ref.csv
rename to simulate/stimulus/unit/output_id_ref.csv
diff --git a/simulate/stimulus/testbench/output_message_block_ref.csv b/simulate/stimulus/unit/output_message_block_ref.csv
similarity index 100%
rename from simulate/stimulus/testbench/output_message_block_ref.csv
rename to simulate/stimulus/unit/output_message_block_ref.csv