From b741c3ae734723a0bc344a98626af61b8ae909ce Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Tue, 23 May 2023 15:49:23 +0100
Subject: [PATCH] updated nanosoc wrapper layer and file lists
---
flist/nanosoc/nanosoc_tb.flist | 3 +-
flist/project/accelerator.flist | 12 +++--
flist/project/system.flist | 3 +-
system/src/nanosoc_exp.v | 28 +++++++---
system/src/nanosoc_exp_wrapper.v | 85 ++++++++++++++++++++++++++++++
wrapper/src/wrapper_accelerator.sv | 17 +++++-
6 files changed, 133 insertions(+), 15 deletions(-)
create mode 100644 system/src/nanosoc_exp_wrapper.v
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
index e5438e8..335e41b 100644
--- a/flist/nanosoc/nanosoc_tb.flist
+++ b/flist/nanosoc/nanosoc_tb.flist
@@ -30,4 +30,5 @@ $(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_acc_log_to_file.v
diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index ca1d834..3af2f7a 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -13,8 +13,10 @@
// ============= Accelerator Module search path =============
-$(SHA256_ACC_DIR)/src/rtl/sha256.v
-$(SHA256_ACC_DIR)/src/rtl/sha256_core.v
-$(SHA256_ACC_DIR)/src/rtl/sha256_w_mem.v
-$(SHA256_ACC_DIR)/src/rtl/sha256_k_constants.v
-$(SHA256_ACC_DIR)/src/interfaces/stream/rtl/sha256_stream.v
\ No newline at end of file
+//-y (PROJECT_DIR)/sha256/src/rtl/
+//-y (PROJECT_DIR)/sha256/src/interfaces/stream/rtl/
+
+-y $(SHA256_ACC_DIR)/src/rtl/
+-y $(SHA256_ACC_DIR)/src/interfaces/stream/rtl/
++incdir+$(SHA256_ACC_DIR)/src/rtl/
++incdir+$(SHA256_ACC_DIR)/src/interfaces/stream/rtl/
diff --git a/flist/project/system.flist b/flist/project/system.flist
index c1829e8..b4b0564 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -58,10 +58,11 @@
-f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
// - NanoSoC Custom Expansion Region
+$(PROJECT_DIR)/system/src/nanosoc_exp_wrapper.v
$(PROJECT_DIR)/system/src/nanosoc_exp.v
// - Top level
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
// ============= Bootrom Filelist ================
-$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
index b19b900..26b9ddf 100644
--- a/system/src/nanosoc_exp.v
+++ b/system/src/nanosoc_exp.v
@@ -12,9 +12,14 @@
`include "cmsdk_ahb_slave_mux.v"
module nanosoc_exp #(
- parameter ADDRWIDTH=29, // Region Address Width
- parameter ACCEL_ADDRWIDTH=13 // Region Address Width
- )(
+ parameter ADDRWIDTH=29, // Region Decode Address Width
+ parameter ACCEL_ADDRWIDTH=13, // Region Address Width
+ parameter INPACKETWIDTH=512,
+ parameter CFGSIZEWIDTH=64,
+ parameter CFGSCHEMEWIDTH=2,
+ parameter OUTPACKETWIDTH=256,
+ parameter CFGNUMIRQ=0
+) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
@@ -32,8 +37,17 @@ module nanosoc_exp #(
output wire HRESPS,
output wire [31:0] HRDATAS,
- output wire ip_data_req,
- output wire op_data_req
+ // Input Data Request Signal to DMAC
+ output wire in_data_req,
+// input wire in_data_last,
+
+ // Output Data Request Signal to DMAC
+ output wire out_data_req
+// input wire out_data_last,
+
+ // Interrupts
+// output wire [CFGNUMIRQ-1:0] irq
+
);
//********************************************************************************
@@ -58,8 +72,8 @@ wire [31:0] HRDATA1;
// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default target
- assign HSEL0 = (HADDRS[ADDRWIDTH-1:16] < 'h200) ? 1'b1:1'b0;
- assign HSEL1 = HSEL0 ? 1'b0:1'b1;
+ assign HSEL0 = (HSELS & (HADDRS[ADDRWIDTH-1:12] == 'h00010)) ? 1'b1:1'b0;
+ assign HSEL1 = HSEL0 ? 1'b0:HSELS;
//********************************************************************************
// Slave multiplexer module:
diff --git a/system/src/nanosoc_exp_wrapper.v b/system/src/nanosoc_exp_wrapper.v
new file mode 100644
index 0000000..eba73e4
--- /dev/null
+++ b/system/src/nanosoc_exp_wrapper.v
@@ -0,0 +1,85 @@
+//-----------------------------------------------------------------------------
+// Nanosoc Expansion Region AHB Address Region
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_exp_wrapper #(
+ parameter AHBADDRWIDTH=29, // Region Decode Address Width
+ parameter ACCEL_ADDRWIDTH=12, // Region Address Width
+ parameter INPACKETWIDTH=512,
+ parameter CFGSIZEWIDTH=64,
+ parameter CFGSCHEMEWIDTH=2,
+ parameter OUTPACKETWIDTH=256,
+ parameter CFGNUMIRQ=4
+ )(
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSEL_i,
+ input wire [AHBADDRWIDTH-1:0] HADDR_i,
+ input wire [1:0] HTRANS_i,
+ input wire [2:0] HSIZE_i,
+ input wire [3:0] HPROT_i,
+ input wire HWRITE_i,
+ input wire HREADY_i,
+ input wire [31:0] HWDATA_i,
+
+ output wire HREADYOUT_o,
+ output wire HRESP_o,
+ output wire [31:0] HRDATA_o,
+
+ // Input Data Request Signal to DMAC
+ output wire exp_drq_ip_o,
+ input wire exp_dlast_ip_i,
+
+ // Output Data Request Signal to DMAC
+ output wire exp_drq_op_o,
+ input wire exp_dlast_op_i,
+
+ // Interrupts
+ output wire [CFGNUMIRQ-1:0] exp_irq_o
+
+ );
+
+//********************************************************************************
+// Slave module 1: Accelerator AHB target module
+//********************************************************************************
+
+// Instantiate your accelerator wrapper HERE
+nanosoc_exp #(
+ .AHBADDRWIDTH(12),
+ .INPACKETWIDTH(512),
+ .CFGSIZEWIDTH(64),
+ .CFGSCHEMEWIDTH(2),
+ .OUTPACKETWIDTH(256),
+ .CFGNUMIRQ(0)
+) nanosoc_exp (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ // AHB port: 32 bit data bus interface
+ .HSELS (HSEL_i),
+ .HADDRS (HADDR_i[28:0]),
+ .HTRANSS (HTRANS_i),
+ .HSIZES (HSIZE_i),
+ .HPROTS (HPROT_i),
+ .HWRITES (HWRITE_i),
+ .HREADYS (HREADY_i),
+ .HWDATAS (HWDATA_i),
+ .HREADYOUTS (HREADYOUT_o),
+ .HRESPS (HRESP_o),
+ .HRDATAS (HRDATA_o),
+ .in_data_req (exp_drq_ip_o),
+ .out_data_req (exp_drq_op_o)
+);
+
+// tie off interrupts at this stage
+assign exp_irq_o[CFGNUMIRQ-1:0] = {CFGNUMIRQ{1'b0}};
+
+endmodule
diff --git a/wrapper/src/wrapper_accelerator.sv b/wrapper/src/wrapper_accelerator.sv
index 878cda9..b992c1c 100644
--- a/wrapper/src/wrapper_accelerator.sv
+++ b/wrapper/src/wrapper_accelerator.sv
@@ -9,12 +9,25 @@
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
+// import secworks sha256 IP but fix up default nettype
+`include "sha256_stream.v"
+`default_nettype wire
+`include "sha256.v"
+`default_nettype wire
+`include "sha256_core.v"
+`default_nettype wire
+`include "sha256_w_mem.v"
+`default_nettype wire
+`include "sha256_k_constants.v"
+`default_nettype wire
+
module wrapper_accelerator #(
parameter AHBADDRWIDTH=13,
parameter INPACKETWIDTH=512,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=256
+ parameter OUTPACKETWIDTH=256,
+ parameter CFGNUMIRQ=0
) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
@@ -520,4 +533,6 @@ module wrapper_accelerator #(
.data_out_last (out_hash_last),
.status_ptr_dif ()
);
+
endmodule
+
--
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