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5b1ffaf6 · 5b1ffaf6 · 5b1ffaf6 · 5b1ffaf6 · 5b1ffaf6 · 5b1ffaf6
--- a/testcodes/uart_driver_tests/uart_driver_tests.hex
+++ b/testcodes/uart_driver_tests/uart_driver_tests.hex
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+A0
+69
+00
+28
 03
+DA
+40
+42
+A0
+61
+01
+20
+05
+43
+E8
+07
+01
 D0
+10
+20
+85
+43
 00
-29
-01
+2E
+24
 D0
+30
+46
+41
+38
+19
+28
+03
+D8
+01
+20
+C0
 02
-23
-11
-32
+05
+43
+20
+36
 20
 46
+25
+60
+31
+46
+02
+9A
+15
+46
+FE
+F7
+C7
+F9
 00
-F0
-8E
-F8
-70
+28
+0C
+D0
+01
+28
+07
+D0
+ED
+1D
+E8
+08
+00
+E0
+0D
+E0
+C0
+00
+08
+30
+02
+90
+77
+E7
+2D
+1D
+02
+95
+74
+E7
+62
+68
+30
+46
+A1
+68
+90
+47
+20
+6A
+40
+1C
+6C
+E7
+20
+6A
+FE
 BD
-2E
-03
+00
+00
+3A
+04
 00
 00
 10
@@ -7210,8 +7658,8 @@ B5
 E0
 FF
 F7
-17
-FF
+45
+FE
 40
 1C
 08
@@ -7230,8 +7678,8 @@ D1
 20
 FF
 F7
-0D
-FF
+3B
+FE
 10
 BD
 00
@@ -7540,10 +7988,10 @@ C0
 D4
 20
 46
-C0
-46
-C0
-46
+FF
+F7
+2F
+FE
 00
 26
 08
@@ -7580,10 +8028,10 @@ C0
 D5
 20
 46
-C0
-46
-C0
-46
+FF
+F7
+1B
+FE
 06
 E0
 62
@@ -7636,10 +8084,10 @@ F3
 DC
 20
 46
-C0
-46
-C0
-46
+FF
+F7
+15
+FE
 20
 78
 00
@@ -7676,8 +8124,8 @@ F8
 46
 FF
 F7
-39
-FE
+67
+FD
 00
 28
 02
@@ -7694,8 +8142,8 @@ BD
 BD
 00
 00
-67
-FC
+C3
+FA
 FF
 FF
 01
@@ -7774,7 +8222,7 @@ B0
 46
 FF
 F7
-49
+45
 FE
 0F
 B0
@@ -7812,7 +8260,7 @@ B0
 B5
 FF
 F7
-D8
+06
 FD
 60
 BC
@@ -7860,8 +8308,8 @@ C0
 46
 FE
 F7
-5C
-F9
+7C
+F8
 10
 BD
 00
@@ -7874,6 +8322,22 @@ BD
 00
 00
 30
+30
+38
+0A
+28
+01
+D2
+01
+20
+70
+47
+00
+20
+70
+47
+00
+00
 48
 65
 6C
@@ -7994,6 +8458,26 @@ BD
 30
 78
 00
+04
+00
+00
+08
+00
+00
+00
+00
+00
+00
+00
+02
+00
+01
+00
+00
+10
+00
+00
+00
 0A
 43
 6F
@@ -8366,8 +8850,8 @@ BD
 2E
 00
 00
-D0
-20
+B4
+22
 00
 00
 00
@@ -8382,8 +8866,8 @@ D0
 01
 00
 00
-F0
-20
+D4
+22
 00
 00
 20
@@ -8423,9 +8907,9 @@ F0
 00
 00
 00
-E1
-F5
-05
+1C
+4E
+0E
 00
 00
 00

--- a/testcodes/watchdog_demo/watchdog_demo.hex
+++ b/testcodes/watchdog_demo/watchdog_demo.hex
@@ -250,12 +250,12 @@ AB
 43
 18
 47
-88
-0B
+10
+0C
 00
 00
-A8
-0B
+30
+0C
 00
 00
 10
@@ -322,7 +322,7 @@ B5
 D1
 00
 F0
-67
+AB
 FC
 10
 BD
@@ -340,7 +340,7 @@ B5
 BD
 00
 F0
-28
+6C
 FD
 11
 46
@@ -354,7 +354,7 @@ F0
 F9
 00
 F0
-40
+84
 FD
 03
 B4
@@ -456,13 +456,13 @@ A2
 A0
 00
 F0
-50
+94
 FC
 A6
 A0
 00
 F0
-4D
+91
 FC
 AB
 4F
@@ -488,19 +488,19 @@ A7
 A0
 00
 F0
-D0
-FB
+14
+FC
 04
 E0
 AA
 A0
 00
 F0
-CC
-FB
+10
+FC
 00
 F0
-BB
+ED
 FB
 6D
 1C
@@ -512,7 +512,7 @@ B0
 A0
 00
 F0
-34
+78
 FC
 91
 48
@@ -524,7 +524,7 @@ B7
 A0
 00
 F0
-2E
+72
 FC
 89
 49
@@ -574,7 +574,7 @@ A0
 1C
 00
 F0
-15
+59
 FC
 0A
 2E
@@ -606,17 +606,17 @@ B8
 A0
 00
 F0
-05
+49
 FC
 00
 F0
-84
+B6
 FB
 BF
 A0
 00
 F0
-00
+44
 FC
 74
 60
@@ -660,8 +660,8 @@ BA
 A0
 00
 F0
-EA
-FB
+2E
+FC
 74
 60
 01
@@ -728,14 +728,14 @@ B2
 A0
 00
 F0
-C8
-FB
+0C
+FC
 B5
 A0
 00
 F0
-C5
-FB
+09
+FC
 BB
 4D
 2E
@@ -746,7 +746,7 @@ A0
 46
 00
 F0
-4F
+93
 FB
 02
 2E
@@ -758,7 +758,7 @@ BD
 A0
 00
 F0
-B9
+FD
 FB
 02
 27
@@ -772,7 +772,7 @@ A0
 46
 00
 F0
-42
+86
 FB
 00
 2D
@@ -792,13 +792,13 @@ C6
 A0
 00
 F0
-A8
+EC
 FB
 CE
 A0
 00
 F0
-A5
+E9
 FB
 4A
 48
@@ -850,7 +850,7 @@ D1
 A0
 00
 F0
-8B
+CF
 FB
 64
 1C
@@ -860,7 +860,7 @@ D8
 A0
 00
 F0
-86
+CA
 FB
 64
 1C
@@ -876,7 +876,7 @@ DE
 A0
 00
 F0
-7E
+C2
 FB
 64
 1C
@@ -892,12 +892,12 @@ EE
 A0
 00
 F0
-76
+BA
 FB
 00
 F0
-F5
-FA
+27
+FB
 F8
 BD
 FA
@@ -938,7 +938,7 @@ F2
 48
 00
 F0
-5F
+A3
 FB
 F0
 48
@@ -964,12 +964,12 @@ ED
 A0
 00
 F0
-52
+96
 FB
 00
 F0
-D1
-FA
+03
+FB
 00
 20
 10
@@ -986,7 +986,7 @@ F1
 A0
 00
 F0
-47
+8B
 FB
 FF
 F7
@@ -1004,27 +1004,27 @@ F4
 A0
 00
 F0
-3E
+82
 FB
 83
 A0
 00
 F0
-3B
+7F
 FB
 00
 F0
-BA
+EC
 FA
 F8
 A0
 00
 F0
-36
+7A
 FB
 00
 F0
-B5
+E7
 FA
 00
 20
@@ -1034,7 +1034,7 @@ F9
 A0
 00
 F0
-2F
+73
 FB
 62
 48
@@ -1066,11 +1066,11 @@ F6
 A0
 00
 F0
-1F
+63
 FB
 00
 F0
-9E
+D0
 FA
 00
 20
@@ -1906,7 +1906,7 @@ C0
 FF
 01
 40
-28
+B0
 0C
 00
 00
@@ -2122,7 +2122,7 @@ B5
 A0
 00
 F0
-0F
+53
 F9
 19
 4C
@@ -2168,11 +2168,11 @@ E7
 48
 00
 F0
-F8
-F8
+3C
+F9
 00
 F0
-77
+A9
 F8
 20
 68
@@ -2255,9 +2255,9 @@ CC
 70
 47
 00
-E1
-F5
-05
+1C
+4E
+0E
 10
 00
 00
@@ -2324,7 +2324,7 @@ C0
 B2
 00
 F0
-1E
+36
 F8
 10
 BD
@@ -2332,11 +2332,11 @@ BD
 B5
 00
 F0
-20
+42
 F8
 00
 F0
-18
+30
 F8
 10
 BD
@@ -2352,42 +2352,96 @@ C0
 B2
 00
 F0
-10
+28
 F8
 10
 BD
 FE
 E7
-41
-20
-10
+2E
+48
+00
+21
+81
+60
+2E
 49
-40
 01
-08
 61
 01
-22
-8A
+21
+81
 60
-0E
-49
-08
-61
+2D
+48
 03
+21
+01
+61
+81
+60
+2C
+49
+20
 20
 88
+61
+70
+47
+2C
+48
+2A
+49
+01
 60
-0D
+2B
+49
+81
+61
+01
+21
+C1
+60
+C3
+21
+81
+60
+01
+69
+C9
+07
+FC
+D0
+24
 49
 20
 20
 88
 61
+21
+48
+00
+21
+81
+60
+30
+21
+01
+61
+03
+21
+81
+60
 70
 47
-0A
+1D
 49
+8A
+68
+D2
+07
+04
+D0
 4A
 68
 D2
@@ -2398,13 +2452,59 @@ D1
 60
 70
 47
+17
+4A
+53
+68
+DB
 07
+FC
+D1
+10
+60
+08
+60
+70
+47
+13
+4B
+15
 48
+59
+68
+42
+68
+89
+07
+C9
+17
+92
+07
+D2
+17
+49
+1C
+52
+1C
+11
+42
+F5
+D1
+59
+68
+89
+07
+01
+D5
+18
+68
+03
+E0
 41
 68
 89
 07
-FC
+01
 D5
 00
 68
@@ -2412,24 +2512,48 @@ C0
 B2
 70
 47
-04
+0A
 48
 04
-22
-41
+21
+82
 68
-C9
+D2
+07
+04
+D0
+42
+68
+D2
 07
 FC
 D1
-02
+01
 60
 FE
 E7
+03
+4A
+53
+68
+DB
+07
+FC
+D1
+11
+60
+01
+60
+F7
+E7
 00
 60
 00
 40
+6A
+18
+00
+00
 00
 E0
 00
@@ -2438,6 +2562,18 @@ E0
 10
 01
 40
+8E
+0C
+01
+00
+00
+20
+00
+40
+24
+F4
+00
+00
 70
 47
 00
@@ -2536,7 +2672,7 @@ FF
 46
 FF
 F7
-A8
+64
 FB
 00
 28
@@ -2674,7 +2810,7 @@ B5
 E0
 FF
 F7
-4D
+09
 FF
 40
 1C
@@ -2694,8 +2830,8 @@ D1
 20
 FF
 F7
-43
 FF
+FE
 10
 BD
 00
@@ -2912,7 +3048,7 @@ F8
 46
 FF
 F7
-E1
+9D
 FE
 00
 28
@@ -2930,7 +3066,7 @@ BD
 BD
 00
 00
-B7
+2F
 FD
 FF
 FF
@@ -3008,7 +3144,7 @@ B0
 B5
 FF
 F7
-94
+50
 FE
 60
 BC
@@ -3056,7 +3192,7 @@ C0
 46
 FF
 F7
-B9
+75
 FA
 10
 BD
@@ -3202,8 +3338,8 @@ BD
 00
 00
 00
-A4
-0C
+2C
+0D
 00
 00
 00
@@ -3218,8 +3354,8 @@ A4
 01
 00
 00
-BC
-0C
+44
+0D
 00
 00
 18
@@ -3251,9 +3387,9 @@ BC
 00
 00
 00
-E1
-F5
-05
+1C
+4E
+0E
 00
 00
 00

--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -68,15 +68,16 @@ module nanosoc_tb;
  wire        debug_running; // indicate debug test is running
  wire        debug_err;     // indicate debug test has error

-  wire        debug_test_en1;
-  wire        debug_test_en2;
+  wire        debug_test_en1; // UART2 output trace (CMSDK)
+  wire        debug_test_en2; // FT1248 output trace (nanosoc V1)
+  wire        debug_test_en3; // EXTIO output trace (nanosoc V2)
  wire        debug_test_en; // To enable the debug tester connection to MCU GPIO P0
                             // This signal is controlled by software,
                             // Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
                             // the command, use "UartPutc((char) 0x11)" to send debug test
                             // enable command, use "UartPutc((char) 0x12)" to send debug test
                             // disable command. Refer to tb_uart_capture.v file for detail
-  assign debug_test_en = debug_test_en1 | debug_test_en2; // FT1248 or UART2 control
+  assign debug_test_en = debug_test_en1 | debug_test_en2 | debug_test_en3; // UART2, FT1248 or EXTIO

  //-----------------------------------------
  // System options
@@ -117,7 +118,7 @@ initial
 `ifdef VCD_SIM
 initial begin
  $dumpfile("waves.vcd");
-  $dumpvars(0,u_nanosoc_chip_pads);
+  $dumpvars(6,u_nanosoc_chip_pads);
  end
 `endif // VCD_SIM

@@ -204,7 +205,8 @@ initial begin
  pullup(P1[ 4]);
  pullup(P1[ 5]);
  pullup(P1[ 6]);
-  pullup(P1[ 7]);
+//  pullup(P1[ 7]);
+  pulldown(P1[ 7]);
  pullup(P1[ 8]);
  pullup(P1[ 9]);
  pullup(P1[10]);
@@ -214,6 +216,178 @@ initial begin
  pullup(P1[14]);
  pullup(P1[15]);

+`ifdef FAST_SIM
+  parameter FAST_LOAD = 1;
+`else
+  parameter FAST_LOAD = 0;
+`endif
+
+ // --------------------------------------------------------------------------------
+ // EXTIO8x4 stream interface - enabled when P1[7] is low
+ //   default in previous testbenches was pullup (for FT1248, UART2)
+ //
+ //          v1 mapping was:    v2 config
+ //   P1[0] - ft_miso_in        ioreq1
+ //   P1[1] - ft_clk_out        ioreq2
+ //   P1[2] - ft_miosio_io      ioack
+ //   P1[3] - ft_ssn_out        iodata[0]
+ //   P1[4] - uart2_rxd         iodata[1]
+ //   P1[5] - uart2_txd         iodata[2]
+ //   P1[6] - reserved (1)      iodata[3]
+ //   P1[7] - reserved (1)      zero
+ // --------------------------------------------------------------------------------
+
+// 4-channel AXIS interface - Subordinate side
+  wire       axis_rx0_tready; 
+  wire       axis_rx0_tvalid;
+  wire [7:0] axis_rx0_tdata8;
+  wire       axis_rx1_tready; 
+  wire       axis_rx1_tvalid;
+  wire [7:0] axis_rx1_tdata8;
+  wire       axis_tx0_tready; 
+  wire       axis_tx0_tvalid;
+  wire [7:0] axis_tx0_tdata8;
+  wire       axis_tx1_tready; 
+  wire       axis_tx1_tvalid;
+  wire [7:0] axis_tx1_tdata8;
+// external io interface
+  tri  [3:0] iodata4;
+  wire [3:0] iodata4_i;
+  wire [3:0] iodata4_o;
+  wire [3:0] iodata4_e;
+  wire [3:0] iodata4_t;
+  wire       ioreq1;
+  wire       ioreq2;
+  wire       ioack;
+
+wire test_done;
+
+wire FT1248MODE = P1[7];
+wire end_sim = test_done & !FT1248MODE & !ioreq1 & !ioreq2 & !ioack;
+  always @(posedge PCLK)
+    if (end_sim) begin
+      $stop;
+    end
+
+extio8x4_axis_target u_extio8x4_axis_target
+  (
+  .clk             ( CLK             ),
+  .resetn          ( NRST            ),
+  .testmode        ( TEST            ),
+// RX 4-channel AXIS interface
+  .axis_rx0_tready ( axis_rx0_tready ),
+  .axis_rx0_tvalid ( axis_rx0_tvalid ),
+  .axis_rx0_tdata8 ( axis_rx0_tdata8 ),
+  .axis_rx1_tready ( axis_rx1_tready ),
+  .axis_rx1_tvalid ( axis_rx1_tvalid ),
+  .axis_rx1_tdata8 ( axis_rx1_tdata8 ),
+  .axis_tx0_tready ( axis_tx0_tready ),
+  .axis_tx0_tvalid ( axis_tx0_tvalid ),
+  .axis_tx0_tdata8 ( axis_tx0_tdata8 ),
+  .axis_tx1_tready ( axis_tx1_tready ),
+  .axis_tx1_tvalid ( axis_tx1_tvalid ),
+  .axis_tx1_tdata8 ( axis_tx1_tdata8 ),
+// external io interface
+  .iodata4_i       ( iodata4_i       ),
+  .iodata4_o       ( iodata4_o       ),
+  .iodata4_e       ( iodata4_e       ),
+  .iodata4_t       ( iodata4_t       ),
+  .ioreq1_a        ( ioreq1          ),
+  .ioreq2_a        ( ioreq2          ),
+  .ioack_o         ( ioack           )
+  );
+
+// tristate buffer emulation
+   assign ioreq1    = FT1248MODE ? 1'b0 : P1[0];
+   assign ioreq2    = FT1248MODE ? 1'b0 : P1[1];
+   bufif0 #1 (P1[2], ioack,        FT1248MODE);
+   bufif0 #1 (P1[3], iodata4_o[0], (iodata4_t[0] | FT1248MODE));
+   bufif0 #1 (P1[4], iodata4_o[1], (iodata4_t[1] | FT1248MODE));
+   bufif0 #1 (P1[5], iodata4_o[2], (iodata4_t[2] | FT1248MODE));
+   bufif0 #1 (P1[6], iodata4_o[3], (iodata4_t[3] | FT1248MODE));
+   assign iodata4_i = {4{FT1248MODE}} | P1[6:3];
+
+`ifndef COCOTB_SIM
+
+  nanosoc_axi_stream_io_8_txd_from_file #(
+    .TXDFILENAME(ADP_FILENAME),
+//    .CODEFILENAME("null.hex"),
+    .FAST_LOAD(FAST_LOAD)
+  ) u_nanosoc_axi_stream_io_adp_txd_from_file (
+    .aclk       (CLK),
+    .aresetn    (NRST),
+    .txd8_ready (axis_rx0_tready),
+    .txd8_valid (axis_rx0_tvalid),
+    .txd8_data  (axis_rx0_tdata8)
+  );
+
+`ifndef COCOTB_SIM
+  nanosoc_axi_stream_io_8_rxd_to_file#(
+    .RXDFILENAME("logs/extadp_in.log")
+  ) u_nanosoc_axi_stream_io_8_adprxd_to_file (
+    .aclk         (CLK),
+    .aresetn      (NRST),
+    .eof_received ( ),
+    .rxd8_ready   ( ), //axis_rx0_tready),
+    .rxd8_valid   (axis_rx0_tvalid & axis_rx0_tready),
+    .rxd8_data    (axis_rx0_tdata8)
+  );
+`endif
+
+/*
+  nanosoc_axi_stream_io_8_txd_from_file #(
+    .TXDFILENAME(ADP_FILENAME),
+//    .CODEFILENAME("null.hex"),
+    .FAST_LOAD(FAST_LOAD)
+  ) u_nanosoc_axi_stream_io_dat_txd_from_file (
+    .aclk       (CLK),
+    .aresetn    (NRST),
+    .txd8_ready (axis_rx1_tready),
+    .txd8_valid (axis_rx1_tvalid),
+    .txd8_data  (axis_rx1_tdata8)
+  );
+*/
+
+  nanosoc_axi_stream_io_8_rxd_to_file#(
+    .RXDFILENAME("logs/extadp_out.log"),
+    .VERBOSE(0)
+  ) u_nanosoc_axi_stream_io_stream_adp_rxd_to_file (
+    .aclk         (CLK),
+    .aresetn      (NRST),
+    .eof_received (test_done),
+    .rxd8_ready   (axis_tx0_tready),
+    .rxd8_valid   (axis_tx0_tvalid),
+    .rxd8_data    (axis_tx0_tdata8)
+  );
+
+  soclabs_axis8_capture  #(.LOGFILENAME("logs/extio_adp_out.log"))
+    u_soclabs_axis8_capture1(
+    .RESETn               (NRST),
+    .CLK                  (CLK),
+    .RXD8_READY   (    ),
+    .RXD8_VALID   (axis_tx0_tvalid & axis_tx0_tready),
+    .RXD8_DATA    (axis_tx0_tdata8),
+    .DEBUG_TESTER_ENABLE  (debug_test_en3),
+    .SIMULATIONEND        (),      // This signal set to 1 at the end of simulation.
+    .AUXCTRL              ()
+  );
+
+
+  nanosoc_axi_stream_io_8_rxd_to_file#(
+    .RXDFILENAME("logs/extdat_out.log")
+  ) u_nanosoc_axi_stream_io_extdata_8_rxd_to_file (
+    .aclk         (CLK),
+    .aresetn      (NRST),
+    .eof_received ( ),
+    .rxd8_ready   ( ), //axis_tx1_tready),
+    .rxd8_valid   (axis_tx1_tvalid & axis_tx1_tready),
+    .rxd8_data    (axis_tx1_tdata8)
+  );
+
+assign axis_tx1_tready = axis_rx1_tready;
+assign axis_rx1_tvalid = axis_tx1_tvalid;
+assign axis_rx1_tdata8 = axis_tx1_tdata8;
+`endif

 // --------------------------------------------------------------------------------
 // UART output capture
@@ -246,7 +420,8 @@ initial begin

  wire baudx16_clk = bauddiv[8]; //prefer:// !baudclken;

-  wire UARTXD =  P1[5];
+///  wire UARTXD =  P1[5];
+  wire UARTXD =  P1[5] | FT1248MODE; // high if in EXTIO mode
  reg  UARTXD_del;
  always @(negedge NRST or posedge baudx16_clk)
    if (!NRST)
@@ -286,7 +461,7 @@ reg baud_clk_del;
    .RESETn               (NRST),
    .CLK                  (uart_clk), //PCLK),
    .RXD                  (UARTXD), // UART 2 use for StdOut
-    .DEBUG_TESTER_ENABLE  (debug_test_en2),
+    .DEBUG_TESTER_ENABLE  (debug_test_en1),
    .SIMULATIONEND        (),      // This signal set to 1 at the end of simulation.
    .AUXCTRL              ()
  );
@@ -296,16 +471,32 @@ reg baud_clk_del;
 // FTDI IO capture
 // --------------------------------------------------------------------------------

-  // UART connection cross over for UART test
-  //  assign P1[0] = P1[3];  // UART 0 RXD = UART 1 TXD
-  //  assign P1[2] = P1[1];  // UART 1 RXD = UART 0 TXD
+  // UART connection
+///  assign P1[4] = P1[5]; // loopback UART2
+
+  bufif1 #1 (P1[4], P1[5], FT1248MODE);

-  assign P1[4] = P1[5]; // loopback UART2
+///  wire ft_clk_out = P1[1];
+///  wire ft_miso_in;
+///  assign P1[0] = ft_miso_in;
+///  wire ft_ssn_out = P1[3];

-  wire ft_clk_out = P1[1];
+  wire ft_clk_out;
  wire ft_miso_in;
-  assign P1[0] = ft_miso_in;
-  wire ft_ssn_out = P1[3];
+  wire ft_ssn_out;
+
+  assign ft_clk_out = (FT1248MODE) ?  P1[1] : 1'b0;
+  bufif1 #1 (P1[0], ft_miso_in, FT1248MODE);
+  assign ft_ssn_out = (FT1248MODE) ?  P1[3] : 1'b1;
+
+  wire ft_miosio_o;
+  wire ft_miosio_z;
+  wire ft_miosio_i;
+///  assign ft_miosio_i  = P1[2]; // & ft_miosio_z;
+///  assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
+  assign ft_miosio_i = (FT1248MODE) ? P1[2] : 1'b0; // & ft_miosio_z;
+  bufif1 #1 (P1[2], ft_miosio_o, (FT1248MODE & !ft_miosio_z));
+

  //
  // AXI stream io testing
@@ -319,15 +510,10 @@ reg baud_clk_del;
  wire rxd8_tvalid;
  wire [7:0] rxd8_tdata ;

-`ifdef FAST_SIM
-  parameter FAST_LOAD = 1;
-`else
-  parameter FAST_LOAD = 0;
-`endif
-
 `ifndef COCOTB_SIM
  nanosoc_axi_stream_io_8_txd_from_file #(
    .TXDFILENAME(ADP_FILENAME),
+//    .CODEFILENAME("null.hex"),
    .FAST_LOAD(FAST_LOAD)
  ) u_nanosoc_axi_stream_io_8_txd_from_file (
    .aclk       (CLK),
@@ -338,11 +524,6 @@ reg baud_clk_del;
  );
 `endif

-  wire ft_miosio_o;
-  wire ft_miosio_z;
-  wire ft_miosio_i  = P1[2]; // & ft_miosio_z;
-  assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-
  nanosoc_ft1248x1_to_axi_streamio_v1_0 u_nanosoc_ft1248x1_to_axi_streamio_v1_0
  (
  .ft_clk_i     (ft_clk_out),
@@ -367,6 +548,7 @@ reg baud_clk_del;
  ) u_nanosoc_axi_stream_io_8_rxd_to_file (
    .aclk         (CLK),
    .aresetn      (NRST),
+    .eof_received ( ),
    .rxd8_ready   (rxd8_tready),
    .rxd8_valid   (rxd8_tvalid),
    .rxd8_data    (rxd8_tdata)
@@ -381,7 +563,7 @@ nanosoc_track_tb_iostream
  .rxd8_ready   (rxd8_tready),
  .rxd8_valid   (rxd8_tvalid),
  .rxd8_data    (rxd8_tdata),
-  .DEBUG_TESTER_ENABLE  (debug_test_en1),
+  .DEBUG_TESTER_ENABLE  (debug_test_en2),
  .AUXCTRL      ( ),
  .SIMULATIONEND( )
  );
@@ -410,7 +592,7 @@ nanosoc_ft1248x1_track
    .RESETn               (NRST),
    .CLK                  (ft_clk2uart),
    .RXD                  (ft_rxd2uart),
-    .DEBUG_TESTER_ENABLE  (debug_test_en1),
+    .DEBUG_TESTER_ENABLE  ( ), //debug_test_en2), //driven by u_nanosoc_track_tb_iostream
    .SIMULATIONEND        (),      // This signal set to 1 at the end of simulation.
    .AUXCTRL              ()
  );

--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -113,6 +113,7 @@ SROM_Ax32
  .VSS        (VSS),
  .VDDACC     (VDDACC),
 `endif
+  .SE         (1'b0),
  .CLK        (CLK),  // input
  .TEST       (TEST),  // output
  .NRST       (NRST),   // active low reset
@@ -337,6 +338,7 @@ reg baud_clk_del;
  ) u_nanosoc_axi_stream_io_8_rxd_to_file (
    .aclk         (CLK),
    .aresetn      (NRST),
+    .eof_received ( ),
    .rxd8_ready   (rxd8_tready),
    .rxd8_valid   (rxd8_tvalid),
    .rxd8_data    (rxd8_tdata)

--- a/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+++ b/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
@@ -21,6 +21,7 @@ module nanosoc_axi_stream_io_8_rxd_to_file
  (
  input  wire       aclk,
  input  wire       aresetn,
+  output wire       eof_received,
  output wire       rxd8_ready,
  input  wire       rxd8_valid,
  input  wire [7:0] rxd8_data
@@ -40,7 +41,9 @@ module nanosoc_axi_stream_io_8_rxd_to_file
   
   reg       nxt_end_simulation;
   reg       reg_end_simulation;
-  
+
+assign eof_received = nxt_end_simulation;
+
   initial
     begin
       ready <= 0;
@@ -62,8 +65,10 @@ module nanosoc_axi_stream_io_8_rxd_to_file
           ch = (rxd8_data & 8'hff);
           if  (ch==8'h04) // Stop simulation if 0x04 is received
             nxt_end_simulation <= 1'b1;
-           else
+           else begin
             $fwrite(fd, "%c", ch);
+             if (VERBOSE) $write("%c", ch);
+             end
         end
         $write("** %m : log file closed after stream RX terminated **\n");
         $fclose(fd);

--- a/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+++ b/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
@@ -147,7 +147,10 @@ localparam BUFSIZE = (64 * 1024);
   $write("** %m : input file length measured as: %d **\n", flen); 
       if (flen > 0) flen=flen-1; // correct for extra char count(???)
       // now output the entire adp buffer to the stream
-       flen = flen + clen+25;
+       if (FAST_LOAD==0)
+           flen = flen + clen+25;
+       else
+           flen = flen + clen+17;
       fp = 0;
       valid <= 0;
       begin

--- a/verif/trace/verilog/soclabs_axis8_capture.v
+++ b/verif/trace/verilog/soclabs_axis8_capture.v
+//-----------------------------------------------------------------------------
+// soclabs 8-bit-axi-character stream capture
+// based on Arm UART RXD capture with file logging adapted from Arm CMSDK Uart Capture
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2024, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+//      Revision            : $Revision: 371321 $
+//
+//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : A device to capture serial data
+//-----------------------------------------------------------------------------
+// This module assume CLK is same frequency as baud rate.
+// In the example UART a test mode is used to enable data output as maximum
+// speed (PCLK).  In such case we can connect CLK signal directly to PCLK.
+// Otherwise, if the UART baud rate is reduced, the CLK rate has to be reduced
+// accordingly as well.
+//
+// This module stop the simulation when character 0x04 is received.
+// An output called SIMULATION_END is set for 1 cycle before simulation is
+// terminated to allow other testbench component like profiler (if any)
+// to output reports before the simulation stop.
+//
+// This model also support ESCAPE (0x1B, decimal 27) code sequence
+// ESC - 0x10 - XY    Capture XY to AUXCTRL output
+// ESC - 0x11         Set DEBUG_TESTER_ENABLE to 1
+// ESC - 0x12         Clear DEBUG_TESTER_ENABLE to 0
+
+
+module soclabs_axis8_capture
+  #(parameter LOGFILENAME = "soc_capture.log",
+    parameter VERBOSE = 0)
+  (
+  input  wire       RESETn,              // Power on reset
+  input  wire       CLK,                 // Clock (baud rate)
+  input  wire       RXD,                 // Received data
+
+  output wire       RXD8_READY,
+  input  wire       RXD8_VALID,
+  input  wire [7:0] RXD8_DATA,
+
+  output wire       SIMULATIONEND,       // Simulation end indicator
+  output wire       DEBUG_TESTER_ENABLE, // Enable debug tester
+  output wire [7:0] AUXCTRL);            // Auxiliary control
+
+  reg [8:0]        rx_shift_reg;
+  wire [8:0]       nxt_rx_shift;
+  reg [6:0]        string_length;
+  reg [7:0]        tube_string [127:0];
+  reg [7:0]        text_char;
+  integer          i;
+  reg              nxt_end_simulation;
+  reg              reg_end_simulation;
+  wire             char_received;
+  reg              reg_esc_code_mode;  // Escape code mode
+  reg              reg_aux_ctrl_mode;  // Auxiliary control capture mode
+  reg [7:0]        reg_aux_ctrl;       // Registered Auxiliary control
+  reg              reg_dbgtester_enable;
+
+   integer        mcd;       // channel descriptor for log file output
+   reg [40*8-1:0] log_file;  // File name can't be > *40* characters
+
+
+assign RXD8_READY = rx_shift_reg[0]; // ready except for a cycle processing
+
+`define SimSTDOUT 32'h00000001
+   initial
+     begin
+       $timeformat(-9, 0, " ns", 14);
+       log_file = LOGFILENAME;
+       mcd = $fopen(log_file);
+       mcd = mcd | `SimSTDOUT; // always echo to console
+       if(mcd == 0) begin
+         $fwrite(mcd,"soclabs_axis8_capture: Error, zero returned in response to $fopen\n");
+         $finish(2);
+       end
+       $fwrite(mcd,"soclabs_axis8_capture: Generating output file %0s using MCD %x @ %m\n",
+              log_file, mcd);
+     end
+
+  // Receive shift register
+  assign nxt_rx_shift  = {RXD,rx_shift_reg[8:1]};
+  assign char_received = (rx_shift_reg[0]==1'b0);
+/*
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      rx_shift_reg <= {9{1'b0}};
+    else
+      if (rx_shift_reg[0]==1'b0) // Start bit reach bit[0]
+        rx_shift_reg <= {9{1'b1}};
+      else
+        rx_shift_reg <= nxt_rx_shift;
+  end
+*/
+
+// ARM design wants valid char in rx_shift_reg[9:1]
+// and a zero in rx_shift_reg[0] to indicate valid start bit (so preset back to 1 after a clock cycle)
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      rx_shift_reg <= {9{1'b1}};
+    else if (rx_shift_reg[0]== 1'b0) // if LSB zero, preset a clock cycle later
+      rx_shift_reg <= {9{1'b1}};
+    else if (rx_shift_reg[0] & RXD8_VALID) //ready and valid data capture
+      rx_shift_reg[8:0] <= {RXD8_DATA[7:0], 1'b0}; 
+  end
+
+
+  // Escape code mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_esc_code_mode <= 1'b0;
+    else // Set to escape mode if ESC code is detected
+      if (char_received & (reg_esc_code_mode==1'b0) & (rx_shift_reg[8:1]==8'h1B))
+        reg_esc_code_mode <= 1'b1;
+      else if (char_received)
+        reg_esc_code_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture mode register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl_mode <= 1'b0;
+    else // Set to Aux control capture mode if ESC-0x10 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h10))
+        reg_aux_ctrl_mode <= 1'b1;
+      else if (char_received)
+        reg_aux_ctrl_mode <= 1'b0;
+  end
+
+  // Aux Ctrl capture data register
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_aux_ctrl <= {8{1'b0}};
+    else // Capture received data to Aux control output if reg_aux_ctrl_mode is set
+      if (char_received & (reg_aux_ctrl_mode==1'b1))
+        reg_aux_ctrl <= rx_shift_reg[8:1];
+  end
+
+  assign AUXCTRL = reg_aux_ctrl;
+
+  // Debug tester enable
+  always @(posedge CLK or negedge RESETn)
+  begin
+    if (~RESETn)
+      reg_dbgtester_enable <= 1'b0;
+    else // Enable debug tester if ESC-0x11 sequence is detected
+      if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h11))
+        reg_dbgtester_enable <= 1'b1;
+      else if (char_received & (reg_esc_code_mode==1'b1) & (rx_shift_reg[8:1]==8'h12))
+        // Disable debug tester if ESC-0x12 sequence is detected
+        reg_dbgtester_enable <= 1'b0;
+  end
+
+  assign DEBUG_TESTER_ENABLE = reg_dbgtester_enable;
+
+  // Message display
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_tube
+  if (~RESETn)
+    begin
+    string_length = 7'b0;
+    nxt_end_simulation <= 1'b0;
+    for (i=0; i<= 127; i=i+1) begin
+       tube_string [i] = 8'h00;
+    end
+    end
+  else
+    if (char_received)
+        begin
+        if ((rx_shift_reg[8:1]==8'h1B) | reg_esc_code_mode | reg_aux_ctrl_mode )
+          begin
+          // Escape code, or in escape code mode
+          // Data receive can be command, aux ctrl data
+          // Ignore this data
+          end
+        else if  (rx_shift_reg[8:1]==8'h04) // Stop simulation if 0x04 is received
+          nxt_end_simulation <= 1'b1;
+        else if ((rx_shift_reg[8:1]==8'h0d)|(rx_shift_reg[8:1]==8'h0A))
+          // New line
+          begin
+          tube_string[string_length] = 8'h00;
+          if (VERBOSE != 0)
+            $fwrite(mcd,"%t UART<%m>: ",$time);
+
+          for (i=0; i<= string_length; i=i+1)
+            begin
+            text_char = tube_string[i];
+            $fwrite(mcd,"%s",text_char);
+            end
+
+          $fwrite(mcd,"\n");
+          string_length = 7'b0;
+          end
+        else
+          begin
+          tube_string[string_length] = rx_shift_reg[8:1];
+          string_length = string_length + 1;
+          if (string_length >79) // line too long, display and clear buffer
+            begin
+            tube_string[string_length] = 8'h00;
+            if (VERBOSE != 0)
+              $fwrite(mcd,"%t UART<%m>: ",$time);
+
+            for (i=0; i<= string_length; i=i+1)
+              begin
+              text_char = tube_string[i];
+              $fwrite(mcd,"%s",text_char);
+              end
+
+            $fwrite(mcd,"\n");
+            string_length = 7'b0;
+
+            end
+
+          end
+
+        end
+
+  end // p_TUBE
+
+  // Delay for simulation end
+  always @ (posedge CLK or negedge RESETn)
+  begin: p_sim_end
+  if (~RESETn)
+    begin
+    reg_end_simulation <= 1'b0;
+    end
+  else
+    begin
+    reg_end_simulation  <= nxt_end_simulation;
+    if (reg_end_simulation==1'b1)
+      begin
+        if (VERBOSE != 0)
+          $fwrite(mcd,"%t stream_capture<%m>: Test Ended\n",$time);
+        else
+          $fwrite(mcd,"Test Ended\n");
+      $stop;
+      end
+    end
+  end
+
+  assign SIMULATIONEND = nxt_end_simulation & (~reg_end_simulation);
+
+endmodule
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