diff --git a/ASIC/44pin/Cadence/scripts/place.tcl b/ASIC/44pin/Cadence/scripts/place.tcl
index aefce0377b2dbe90135eb26016ee0cafd60d8f53..4a947134844890ba92eb796f81c09d0057452b66 100644
--- a/ASIC/44pin/Cadence/scripts/place.tcl
+++ b/ASIC/44pin/Cadence/scripts/place.tcl
@@ -20,5 +20,5 @@ place_design
 ### Delay Calculation 
 write_sdf design.sdf -ideal_clock_network 
 set_db add_tieoffs_max_fanout 10
-add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain TOP
-add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain ACCEL
+add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain TOP -exclude_pin tieoff_exclude
+add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain ACCEL -exclude_pin tieoff_exclude
diff --git a/ASIC/44pin/Cadence/scripts/tieoff_exclude b/ASIC/44pin/Cadence/scripts/tieoff_exclude
new file mode 100644
index 0000000000000000000000000000000000000000..a68416664b978fbcdb8cdf66b3c3bbe90c2d4983
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/tieoff_exclude
@@ -0,0 +1,38 @@
+uPAD_CLK_I/IE
+uPAD_CLK_I/PE
+uPAD_CLK_I/DS
+uPAD_CLK_I/I
+uPAD_CLK_I/OEN
+uPAD_TEST_I/IE
+uPAD_TEST_I/PE
+uPAD_TEST_I/DS
+uPAD_TEST_I/I
+uPAD_TEST_I/OEN
+uPAD_NRST_I/IE
+uPAD_NRST_I/PE
+uPAD_NRST_I/DS
+uPAD_NRST_I/I
+uPAD_NRST_I/OEN
+uPAD_SWDIO_IO/PE 
+uPAD_SWDIO_IO/DS
+uPAD_SWDCK_I/IE
+uPAD_SWDCK_I/PE
+uPAD_SWDCK_I/DS
+uPAD_SWDCK_I/I
+uPAD_SWDCK_I/OEN
+uPAD_P0_00/DS
+uPAD_P0_01/DS
+uPAD_P0_02/DS
+uPAD_P0_03/DS
+uPAD_P0_04/DS
+uPAD_P0_05/DS
+uPAD_P0_06/DS
+uPAD_P0_07/DS
+uPAD_P1_00/DS
+uPAD_P1_01/DS
+uPAD_P1_02/DS
+uPAD_P1_03/DS
+uPAD_P1_04/DS
+uPAD_P1_05/DS
+uPAD_P1_06/DS
+uPAD_P1_07/DS