diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000000000000000000000000000000000000..1e8a2a67029f62480ec7b57aeba96155a670748c
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "system/socdebug_tech"]
+ path = system/socdebug_tech
+ url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
diff --git a/system/html/v2html_doc.tgz b/system/html/v2html_doc.tgz
deleted file mode 100644
index c8c4493ab25b6ab1c29f849e265354240e7055af..0000000000000000000000000000000000000000
Binary files a/system/html/v2html_doc.tgz and /dev/null differ
diff --git a/system/socdebug_tech b/system/socdebug_tech
new file mode 160000
index 0000000000000000000000000000000000000000..6a6da3cfd4851abf6623991de6389f54593a9854
--- /dev/null
+++ b/system/socdebug_tech
@@ -0,0 +1 @@
+Subproject commit 6a6da3cfd4851abf6623991de6389f54593a9854
diff --git a/system/src/nanosoc_ahb_busmatrix/logs/nanosoc_ahb32_4x7.log b/system/src/nanosoc_ahb_busmatrix/logs/nanosoc_ahb32_4x7.log
deleted file mode 100644
index 6cfcb6733255c4dceb97960a4115a83db3f483f0..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_ahb_busmatrix/logs/nanosoc_ahb32_4x7.log
+++ /dev/null
@@ -1,60 +0,0 @@
-
-==============================================================
-= The confidential and proprietary information contained in this file may
-= only be used by a person authorised under and to the extent permitted
-= by a subsisting licensing agreement from Arm Limited or its affiliates.
-=
-= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
-= ALL RIGHTS RESERVED
-=
-= This entire notice must be reproduced on all copies of this file
-= and copies of this file may only be made by a person if such person is
-= permitted to do so under the terms of a subsisting license agreement
-= from Arm Limited or its affiliates.
-=
-= BuildBusMatrix.pl
-=
-= Run Date : 28/04/2023 17:24:27
-==============================================================
-
-Script accepted the following parameters:
-
- - Configuration file : '/home/dam1n19/Design/test1/secworks-sha256-project/nanosoc/system/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml'
- - Top-level name : 'nanosoc_ahb32_4x7_busmatrix'
- - Slave interfaces : 4
- - Master interfaces : 7
- - Architecture type : 'ahb2'
- - Arbitration scheme : 'burst'
- - Address map : user defined
- - Connectivity mapping : _adp -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
- _dma -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
- _dma2 -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
- _cpu -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9
- - Connectivity type : full
- - Routing data width : 32
- - Routing address width : 32
- - User signal width : 2
- - Timescales : no
- - Configuration directory : '/home/dam1n19/Design/test1/secworks-sha256-project/nanosoc/system/src/nanosoc_ahb_busmatrix/verilog'
- - Source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/verilog/src'
- - IPXact target directory : '/home/dam1n19/Design/test1/secworks-sha256-project/nanosoc/system/src/nanosoc_ahb_busmatrix/ipxact'
- - IPXact source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/ipxact/src'
- - Overwrite mode : enabled
-
-Creating the bus matrix variant...
-
- - Rendering 'nanosoc_ahb32_4x7_busmatrix_default_slave.v'
- - Rendering 'nanosoc_ahb32_4x7_busmatrix.v'
- - Rendering 'nanosoc_ahb32_4x7_busmatrix.xml'
- - Rendering 'nanosoc_ahb32_4x7_arbiter.v'
- - Rendering 'nanosoc_ahb32_4x7_inititator_input.v'
- - Rendering 'nanosoc_ahb32_4x7_matrix_decode_dma.v'
- - Rendering 'nanosoc_ahb32_4x7_target_output.v'
- - Rendering 'nanosoc_ahb32_4x7_matrix_decode_adp.v'
- - Rendering 'nanosoc_ahb32_4x7_busmatrix_lite.v'
- - Rendering 'nanosoc_ahb32_4x7_matrix_decode_cpu.v'
- - Rendering 'nanosoc_ahb32_4x7_matrix_decode_dma2.v'
- - Rendering 'nanosoc_ahb32_4x7_busmatrix_lite.xml'
-
-Done!
-
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v b/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
deleted file mode 100644
index ce2264e1a2dfe3efa4074cdcca8d48ec9c49ffd1..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
+++ /dev/null
@@ -1,983 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//
-//------------------------------------------------------------------------------
-// Abstract : BusMatrixLite is a wrapper module that wraps around
-// the BusMatrix module to give AHB Lite compliant
-// slave and master interfaces.
-//
-//-----------------------------------------------------------------------------
-
-
-
-module nanosoc_ahb32_4x7_busmatrix_lite (
-
- // Common AHB signals
- HCLK,
- HRESETn,
-
- // System Address Remap control
- REMAP,
-
- // Input port SI0 (inputs from master 0)
- HADDR_adp,
- HTRANS_adp,
- HWRITE_adp,
- HSIZE_adp,
- HBURST_adp,
- HPROT_adp,
- HWDATA_adp,
- HMASTLOCK_adp,
- HAUSER_adp,
- HWUSER_adp,
-
- // Input port SI1 (inputs from master 1)
- HADDR_dma,
- HTRANS_dma,
- HWRITE_dma,
- HSIZE_dma,
- HBURST_dma,
- HPROT_dma,
- HWDATA_dma,
- HMASTLOCK_dma,
- HAUSER_dma,
- HWUSER_dma,
-
- // Input port SI2 (inputs from master 2)
- HADDR_dma2,
- HTRANS_dma2,
- HWRITE_dma2,
- HSIZE_dma2,
- HBURST_dma2,
- HPROT_dma2,
- HWDATA_dma2,
- HMASTLOCK_dma2,
- HAUSER_dma2,
- HWUSER_dma2,
-
- // Input port SI3 (inputs from master 3)
- HADDR_cpu,
- HTRANS_cpu,
- HWRITE_cpu,
- HSIZE_cpu,
- HBURST_cpu,
- HPROT_cpu,
- HWDATA_cpu,
- HMASTLOCK_cpu,
- HAUSER_cpu,
- HWUSER_cpu,
-
- // Output port MI0 (inputs from slave 0)
- HRDATA_rom1,
- HREADYOUT_rom1,
- HRESP_rom1,
- HRUSER_rom1,
-
- // Output port MI1 (inputs from slave 1)
- HRDATA_ram2,
- HREADYOUT_ram2,
- HRESP_ram2,
- HRUSER_ram2,
-
- // Output port MI2 (inputs from slave 2)
- HRDATA_ram3,
- HREADYOUT_ram3,
- HRESP_ram3,
- HRUSER_ram3,
-
- // Output port MI3 (inputs from slave 3)
- HRDATA_sys,
- HREADYOUT_sys,
- HRESP_sys,
- HRUSER_sys,
-
- // Output port MI4 (inputs from slave 4)
- HRDATA_ram8,
- HREADYOUT_ram8,
- HRESP_ram8,
- HRUSER_ram8,
-
- // Output port MI5 (inputs from slave 5)
- HRDATA_ram9,
- HREADYOUT_ram9,
- HRESP_ram9,
- HRUSER_ram9,
-
- // Output port MI6 (inputs from slave 6)
- HRDATA_exp,
- HREADYOUT_exp,
- HRESP_exp,
- HRUSER_exp,
-
- // Scan test dummy signals; not connected until scan insertion
- SCANENABLE, // Scan Test Mode Enable
- SCANINHCLK, // Scan Chain Input
-
-
- // Output port MI0 (outputs to slave 0)
- HSEL_rom1,
- HADDR_rom1,
- HTRANS_rom1,
- HWRITE_rom1,
- HSIZE_rom1,
- HBURST_rom1,
- HPROT_rom1,
- HWDATA_rom1,
- HMASTLOCK_rom1,
- HREADYMUX_rom1,
- HAUSER_rom1,
- HWUSER_rom1,
-
- // Output port MI1 (outputs to slave 1)
- HSEL_ram2,
- HADDR_ram2,
- HTRANS_ram2,
- HWRITE_ram2,
- HSIZE_ram2,
- HBURST_ram2,
- HPROT_ram2,
- HWDATA_ram2,
- HMASTLOCK_ram2,
- HREADYMUX_ram2,
- HAUSER_ram2,
- HWUSER_ram2,
-
- // Output port MI2 (outputs to slave 2)
- HSEL_ram3,
- HADDR_ram3,
- HTRANS_ram3,
- HWRITE_ram3,
- HSIZE_ram3,
- HBURST_ram3,
- HPROT_ram3,
- HWDATA_ram3,
- HMASTLOCK_ram3,
- HREADYMUX_ram3,
- HAUSER_ram3,
- HWUSER_ram3,
-
- // Output port MI3 (outputs to slave 3)
- HSEL_sys,
- HADDR_sys,
- HTRANS_sys,
- HWRITE_sys,
- HSIZE_sys,
- HBURST_sys,
- HPROT_sys,
- HWDATA_sys,
- HMASTLOCK_sys,
- HREADYMUX_sys,
- HAUSER_sys,
- HWUSER_sys,
-
- // Output port MI4 (outputs to slave 4)
- HSEL_ram8,
- HADDR_ram8,
- HTRANS_ram8,
- HWRITE_ram8,
- HSIZE_ram8,
- HBURST_ram8,
- HPROT_ram8,
- HWDATA_ram8,
- HMASTLOCK_ram8,
- HREADYMUX_ram8,
- HAUSER_ram8,
- HWUSER_ram8,
-
- // Output port MI5 (outputs to slave 5)
- HSEL_ram9,
- HADDR_ram9,
- HTRANS_ram9,
- HWRITE_ram9,
- HSIZE_ram9,
- HBURST_ram9,
- HPROT_ram9,
- HWDATA_ram9,
- HMASTLOCK_ram9,
- HREADYMUX_ram9,
- HAUSER_ram9,
- HWUSER_ram9,
-
- // Output port MI6 (outputs to slave 6)
- HSEL_exp,
- HADDR_exp,
- HTRANS_exp,
- HWRITE_exp,
- HSIZE_exp,
- HBURST_exp,
- HPROT_exp,
- HWDATA_exp,
- HMASTLOCK_exp,
- HREADYMUX_exp,
- HAUSER_exp,
- HWUSER_exp,
-
- // Input port SI0 (outputs to master 0)
- HRDATA_adp,
- HREADY_adp,
- HRESP_adp,
- HRUSER_adp,
-
- // Input port SI1 (outputs to master 1)
- HRDATA_dma,
- HREADY_dma,
- HRESP_dma,
- HRUSER_dma,
-
- // Input port SI2 (outputs to master 2)
- HRDATA_dma2,
- HREADY_dma2,
- HRESP_dma2,
- HRUSER_dma2,
-
- // Input port SI3 (outputs to master 3)
- HRDATA_cpu,
- HREADY_cpu,
- HRESP_cpu,
- HRUSER_cpu,
-
- // Scan test dummy signals; not connected until scan insertion
- SCANOUTHCLK // Scan Chain Output
-
- );
-
-// -----------------------------------------------------------------------------
-// Input and Output declarations
-// -----------------------------------------------------------------------------
-
- // Common AHB signals
- input HCLK; // AHB System Clock
- input HRESETn; // AHB System Reset
-
- // System Address Remap control
- input [3:0] REMAP; // System Address REMAP control
-
- // Input port SI0 (inputs from master 0)
- input [31:0] HADDR_adp; // Address bus
- input [1:0] HTRANS_adp; // Transfer type
- input HWRITE_adp; // Transfer direction
- input [2:0] HSIZE_adp; // Transfer size
- input [2:0] HBURST_adp; // Burst type
- input [3:0] HPROT_adp; // Protection control
- input [31:0] HWDATA_adp; // Write data
- input HMASTLOCK_adp; // Locked Sequence
- input [1:0] HAUSER_adp; // Address USER signals
- input [1:0] HWUSER_adp; // Write-data USER signals
-
- // Input port SI1 (inputs from master 1)
- input [31:0] HADDR_dma; // Address bus
- input [1:0] HTRANS_dma; // Transfer type
- input HWRITE_dma; // Transfer direction
- input [2:0] HSIZE_dma; // Transfer size
- input [2:0] HBURST_dma; // Burst type
- input [3:0] HPROT_dma; // Protection control
- input [31:0] HWDATA_dma; // Write data
- input HMASTLOCK_dma; // Locked Sequence
- input [1:0] HAUSER_dma; // Address USER signals
- input [1:0] HWUSER_dma; // Write-data USER signals
-
- // Input port SI2 (inputs from master 2)
- input [31:0] HADDR_dma2; // Address bus
- input [1:0] HTRANS_dma2; // Transfer type
- input HWRITE_dma2; // Transfer direction
- input [2:0] HSIZE_dma2; // Transfer size
- input [2:0] HBURST_dma2; // Burst type
- input [3:0] HPROT_dma2; // Protection control
- input [31:0] HWDATA_dma2; // Write data
- input HMASTLOCK_dma2; // Locked Sequence
- input [1:0] HAUSER_dma2; // Address USER signals
- input [1:0] HWUSER_dma2; // Write-data USER signals
-
- // Input port SI3 (inputs from master 3)
- input [31:0] HADDR_cpu; // Address bus
- input [1:0] HTRANS_cpu; // Transfer type
- input HWRITE_cpu; // Transfer direction
- input [2:0] HSIZE_cpu; // Transfer size
- input [2:0] HBURST_cpu; // Burst type
- input [3:0] HPROT_cpu; // Protection control
- input [31:0] HWDATA_cpu; // Write data
- input HMASTLOCK_cpu; // Locked Sequence
- input [1:0] HAUSER_cpu; // Address USER signals
- input [1:0] HWUSER_cpu; // Write-data USER signals
-
- // Output port MI0 (inputs from slave 0)
- input [31:0] HRDATA_rom1; // Read data bus
- input HREADYOUT_rom1; // HREADY feedback
- input HRESP_rom1; // Transfer response
- input [1:0] HRUSER_rom1; // Read-data USER signals
-
- // Output port MI1 (inputs from slave 1)
- input [31:0] HRDATA_ram2; // Read data bus
- input HREADYOUT_ram2; // HREADY feedback
- input HRESP_ram2; // Transfer response
- input [1:0] HRUSER_ram2; // Read-data USER signals
-
- // Output port MI2 (inputs from slave 2)
- input [31:0] HRDATA_ram3; // Read data bus
- input HREADYOUT_ram3; // HREADY feedback
- input HRESP_ram3; // Transfer response
- input [1:0] HRUSER_ram3; // Read-data USER signals
-
- // Output port MI3 (inputs from slave 3)
- input [31:0] HRDATA_sys; // Read data bus
- input HREADYOUT_sys; // HREADY feedback
- input HRESP_sys; // Transfer response
- input [1:0] HRUSER_sys; // Read-data USER signals
-
- // Output port MI4 (inputs from slave 4)
- input [31:0] HRDATA_ram8; // Read data bus
- input HREADYOUT_ram8; // HREADY feedback
- input HRESP_ram8; // Transfer response
- input [1:0] HRUSER_ram8; // Read-data USER signals
-
- // Output port MI5 (inputs from slave 5)
- input [31:0] HRDATA_ram9; // Read data bus
- input HREADYOUT_ram9; // HREADY feedback
- input HRESP_ram9; // Transfer response
- input [1:0] HRUSER_ram9; // Read-data USER signals
-
- // Output port MI6 (inputs from slave 6)
- input [31:0] HRDATA_exp; // Read data bus
- input HREADYOUT_exp; // HREADY feedback
- input HRESP_exp; // Transfer response
- input [1:0] HRUSER_exp; // Read-data USER signals
-
- // Scan test dummy signals; not connected until scan insertion
- input SCANENABLE; // Scan enable signal
- input SCANINHCLK; // HCLK scan input
-
-
- // Output port MI0 (outputs to slave 0)
- output HSEL_rom1; // Slave Select
- output [31:0] HADDR_rom1; // Address bus
- output [1:0] HTRANS_rom1; // Transfer type
- output HWRITE_rom1; // Transfer direction
- output [2:0] HSIZE_rom1; // Transfer size
- output [2:0] HBURST_rom1; // Burst type
- output [3:0] HPROT_rom1; // Protection control
- output [31:0] HWDATA_rom1; // Write data
- output HMASTLOCK_rom1; // Locked Sequence
- output HREADYMUX_rom1; // Transfer done
- output [1:0] HAUSER_rom1; // Address USER signals
- output [1:0] HWUSER_rom1; // Write-data USER signals
-
- // Output port MI1 (outputs to slave 1)
- output HSEL_ram2; // Slave Select
- output [31:0] HADDR_ram2; // Address bus
- output [1:0] HTRANS_ram2; // Transfer type
- output HWRITE_ram2; // Transfer direction
- output [2:0] HSIZE_ram2; // Transfer size
- output [2:0] HBURST_ram2; // Burst type
- output [3:0] HPROT_ram2; // Protection control
- output [31:0] HWDATA_ram2; // Write data
- output HMASTLOCK_ram2; // Locked Sequence
- output HREADYMUX_ram2; // Transfer done
- output [1:0] HAUSER_ram2; // Address USER signals
- output [1:0] HWUSER_ram2; // Write-data USER signals
-
- // Output port MI2 (outputs to slave 2)
- output HSEL_ram3; // Slave Select
- output [31:0] HADDR_ram3; // Address bus
- output [1:0] HTRANS_ram3; // Transfer type
- output HWRITE_ram3; // Transfer direction
- output [2:0] HSIZE_ram3; // Transfer size
- output [2:0] HBURST_ram3; // Burst type
- output [3:0] HPROT_ram3; // Protection control
- output [31:0] HWDATA_ram3; // Write data
- output HMASTLOCK_ram3; // Locked Sequence
- output HREADYMUX_ram3; // Transfer done
- output [1:0] HAUSER_ram3; // Address USER signals
- output [1:0] HWUSER_ram3; // Write-data USER signals
-
- // Output port MI3 (outputs to slave 3)
- output HSEL_sys; // Slave Select
- output [31:0] HADDR_sys; // Address bus
- output [1:0] HTRANS_sys; // Transfer type
- output HWRITE_sys; // Transfer direction
- output [2:0] HSIZE_sys; // Transfer size
- output [2:0] HBURST_sys; // Burst type
- output [3:0] HPROT_sys; // Protection control
- output [31:0] HWDATA_sys; // Write data
- output HMASTLOCK_sys; // Locked Sequence
- output HREADYMUX_sys; // Transfer done
- output [1:0] HAUSER_sys; // Address USER signals
- output [1:0] HWUSER_sys; // Write-data USER signals
-
- // Output port MI4 (outputs to slave 4)
- output HSEL_ram8; // Slave Select
- output [31:0] HADDR_ram8; // Address bus
- output [1:0] HTRANS_ram8; // Transfer type
- output HWRITE_ram8; // Transfer direction
- output [2:0] HSIZE_ram8; // Transfer size
- output [2:0] HBURST_ram8; // Burst type
- output [3:0] HPROT_ram8; // Protection control
- output [31:0] HWDATA_ram8; // Write data
- output HMASTLOCK_ram8; // Locked Sequence
- output HREADYMUX_ram8; // Transfer done
- output [1:0] HAUSER_ram8; // Address USER signals
- output [1:0] HWUSER_ram8; // Write-data USER signals
-
- // Output port MI5 (outputs to slave 5)
- output HSEL_ram9; // Slave Select
- output [31:0] HADDR_ram9; // Address bus
- output [1:0] HTRANS_ram9; // Transfer type
- output HWRITE_ram9; // Transfer direction
- output [2:0] HSIZE_ram9; // Transfer size
- output [2:0] HBURST_ram9; // Burst type
- output [3:0] HPROT_ram9; // Protection control
- output [31:0] HWDATA_ram9; // Write data
- output HMASTLOCK_ram9; // Locked Sequence
- output HREADYMUX_ram9; // Transfer done
- output [1:0] HAUSER_ram9; // Address USER signals
- output [1:0] HWUSER_ram9; // Write-data USER signals
-
- // Output port MI6 (outputs to slave 6)
- output HSEL_exp; // Slave Select
- output [31:0] HADDR_exp; // Address bus
- output [1:0] HTRANS_exp; // Transfer type
- output HWRITE_exp; // Transfer direction
- output [2:0] HSIZE_exp; // Transfer size
- output [2:0] HBURST_exp; // Burst type
- output [3:0] HPROT_exp; // Protection control
- output [31:0] HWDATA_exp; // Write data
- output HMASTLOCK_exp; // Locked Sequence
- output HREADYMUX_exp; // Transfer done
- output [1:0] HAUSER_exp; // Address USER signals
- output [1:0] HWUSER_exp; // Write-data USER signals
-
- // Input port SI0 (outputs to master 0)
- output [31:0] HRDATA_adp; // Read data bus
- output HREADY_adp; // HREADY feedback
- output HRESP_adp; // Transfer response
- output [1:0] HRUSER_adp; // Read-data USER signals
-
- // Input port SI1 (outputs to master 1)
- output [31:0] HRDATA_dma; // Read data bus
- output HREADY_dma; // HREADY feedback
- output HRESP_dma; // Transfer response
- output [1:0] HRUSER_dma; // Read-data USER signals
-
- // Input port SI2 (outputs to master 2)
- output [31:0] HRDATA_dma2; // Read data bus
- output HREADY_dma2; // HREADY feedback
- output HRESP_dma2; // Transfer response
- output [1:0] HRUSER_dma2; // Read-data USER signals
-
- // Input port SI3 (outputs to master 3)
- output [31:0] HRDATA_cpu; // Read data bus
- output HREADY_cpu; // HREADY feedback
- output HRESP_cpu; // Transfer response
- output [1:0] HRUSER_cpu; // Read-data USER signals
-
- // Scan test dummy signals; not connected until scan insertion
- output SCANOUTHCLK; // Scan Chain Output
-
-// -----------------------------------------------------------------------------
-// Wire declarations
-// -----------------------------------------------------------------------------
-
- // Common AHB signals
- wire HCLK; // AHB System Clock
- wire HRESETn; // AHB System Reset
-
- // System Address Remap control
- wire [3:0] REMAP; // System REMAP signal
-
- // Input Port SI0
- wire [31:0] HADDR_adp; // Address bus
- wire [1:0] HTRANS_adp; // Transfer type
- wire HWRITE_adp; // Transfer direction
- wire [2:0] HSIZE_adp; // Transfer size
- wire [2:0] HBURST_adp; // Burst type
- wire [3:0] HPROT_adp; // Protection control
- wire [31:0] HWDATA_adp; // Write data
- wire HMASTLOCK_adp; // Locked Sequence
-
- wire [31:0] HRDATA_adp; // Read data bus
- wire HREADY_adp; // HREADY feedback
- wire HRESP_adp; // Transfer response
- wire [1:0] HAUSER_adp; // Address USER signals
- wire [1:0] HWUSER_adp; // Write-data USER signals
- wire [1:0] HRUSER_adp; // Read-data USER signals
-
- // Input Port SI1
- wire [31:0] HADDR_dma; // Address bus
- wire [1:0] HTRANS_dma; // Transfer type
- wire HWRITE_dma; // Transfer direction
- wire [2:0] HSIZE_dma; // Transfer size
- wire [2:0] HBURST_dma; // Burst type
- wire [3:0] HPROT_dma; // Protection control
- wire [31:0] HWDATA_dma; // Write data
- wire HMASTLOCK_dma; // Locked Sequence
-
- wire [31:0] HRDATA_dma; // Read data bus
- wire HREADY_dma; // HREADY feedback
- wire HRESP_dma; // Transfer response
- wire [1:0] HAUSER_dma; // Address USER signals
- wire [1:0] HWUSER_dma; // Write-data USER signals
- wire [1:0] HRUSER_dma; // Read-data USER signals
-
- // Input Port SI2
- wire [31:0] HADDR_dma2; // Address bus
- wire [1:0] HTRANS_dma2; // Transfer type
- wire HWRITE_dma2; // Transfer direction
- wire [2:0] HSIZE_dma2; // Transfer size
- wire [2:0] HBURST_dma2; // Burst type
- wire [3:0] HPROT_dma2; // Protection control
- wire [31:0] HWDATA_dma2; // Write data
- wire HMASTLOCK_dma2; // Locked Sequence
-
- wire [31:0] HRDATA_dma2; // Read data bus
- wire HREADY_dma2; // HREADY feedback
- wire HRESP_dma2; // Transfer response
- wire [1:0] HAUSER_dma2; // Address USER signals
- wire [1:0] HWUSER_dma2; // Write-data USER signals
- wire [1:0] HRUSER_dma2; // Read-data USER signals
-
- // Input Port SI3
- wire [31:0] HADDR_cpu; // Address bus
- wire [1:0] HTRANS_cpu; // Transfer type
- wire HWRITE_cpu; // Transfer direction
- wire [2:0] HSIZE_cpu; // Transfer size
- wire [2:0] HBURST_cpu; // Burst type
- wire [3:0] HPROT_cpu; // Protection control
- wire [31:0] HWDATA_cpu; // Write data
- wire HMASTLOCK_cpu; // Locked Sequence
-
- wire [31:0] HRDATA_cpu; // Read data bus
- wire HREADY_cpu; // HREADY feedback
- wire HRESP_cpu; // Transfer response
- wire [1:0] HAUSER_cpu; // Address USER signals
- wire [1:0] HWUSER_cpu; // Write-data USER signals
- wire [1:0] HRUSER_cpu; // Read-data USER signals
-
- // Output Port MI0
- wire HSEL_rom1; // Slave Select
- wire [31:0] HADDR_rom1; // Address bus
- wire [1:0] HTRANS_rom1; // Transfer type
- wire HWRITE_rom1; // Transfer direction
- wire [2:0] HSIZE_rom1; // Transfer size
- wire [2:0] HBURST_rom1; // Burst type
- wire [3:0] HPROT_rom1; // Protection control
- wire [31:0] HWDATA_rom1; // Write data
- wire HMASTLOCK_rom1; // Locked Sequence
- wire HREADYMUX_rom1; // Transfer done
-
- wire [31:0] HRDATA_rom1; // Read data bus
- wire HREADYOUT_rom1; // HREADY feedback
- wire HRESP_rom1; // Transfer response
- wire [1:0] HAUSER_rom1; // Address USER signals
- wire [1:0] HWUSER_rom1; // Write-data USER signals
- wire [1:0] HRUSER_rom1; // Read-data USER signals
-
- // Output Port MI1
- wire HSEL_ram2; // Slave Select
- wire [31:0] HADDR_ram2; // Address bus
- wire [1:0] HTRANS_ram2; // Transfer type
- wire HWRITE_ram2; // Transfer direction
- wire [2:0] HSIZE_ram2; // Transfer size
- wire [2:0] HBURST_ram2; // Burst type
- wire [3:0] HPROT_ram2; // Protection control
- wire [31:0] HWDATA_ram2; // Write data
- wire HMASTLOCK_ram2; // Locked Sequence
- wire HREADYMUX_ram2; // Transfer done
-
- wire [31:0] HRDATA_ram2; // Read data bus
- wire HREADYOUT_ram2; // HREADY feedback
- wire HRESP_ram2; // Transfer response
- wire [1:0] HAUSER_ram2; // Address USER signals
- wire [1:0] HWUSER_ram2; // Write-data USER signals
- wire [1:0] HRUSER_ram2; // Read-data USER signals
-
- // Output Port MI2
- wire HSEL_ram3; // Slave Select
- wire [31:0] HADDR_ram3; // Address bus
- wire [1:0] HTRANS_ram3; // Transfer type
- wire HWRITE_ram3; // Transfer direction
- wire [2:0] HSIZE_ram3; // Transfer size
- wire [2:0] HBURST_ram3; // Burst type
- wire [3:0] HPROT_ram3; // Protection control
- wire [31:0] HWDATA_ram3; // Write data
- wire HMASTLOCK_ram3; // Locked Sequence
- wire HREADYMUX_ram3; // Transfer done
-
- wire [31:0] HRDATA_ram3; // Read data bus
- wire HREADYOUT_ram3; // HREADY feedback
- wire HRESP_ram3; // Transfer response
- wire [1:0] HAUSER_ram3; // Address USER signals
- wire [1:0] HWUSER_ram3; // Write-data USER signals
- wire [1:0] HRUSER_ram3; // Read-data USER signals
-
- // Output Port MI3
- wire HSEL_sys; // Slave Select
- wire [31:0] HADDR_sys; // Address bus
- wire [1:0] HTRANS_sys; // Transfer type
- wire HWRITE_sys; // Transfer direction
- wire [2:0] HSIZE_sys; // Transfer size
- wire [2:0] HBURST_sys; // Burst type
- wire [3:0] HPROT_sys; // Protection control
- wire [31:0] HWDATA_sys; // Write data
- wire HMASTLOCK_sys; // Locked Sequence
- wire HREADYMUX_sys; // Transfer done
-
- wire [31:0] HRDATA_sys; // Read data bus
- wire HREADYOUT_sys; // HREADY feedback
- wire HRESP_sys; // Transfer response
- wire [1:0] HAUSER_sys; // Address USER signals
- wire [1:0] HWUSER_sys; // Write-data USER signals
- wire [1:0] HRUSER_sys; // Read-data USER signals
-
- // Output Port MI4
- wire HSEL_ram8; // Slave Select
- wire [31:0] HADDR_ram8; // Address bus
- wire [1:0] HTRANS_ram8; // Transfer type
- wire HWRITE_ram8; // Transfer direction
- wire [2:0] HSIZE_ram8; // Transfer size
- wire [2:0] HBURST_ram8; // Burst type
- wire [3:0] HPROT_ram8; // Protection control
- wire [31:0] HWDATA_ram8; // Write data
- wire HMASTLOCK_ram8; // Locked Sequence
- wire HREADYMUX_ram8; // Transfer done
-
- wire [31:0] HRDATA_ram8; // Read data bus
- wire HREADYOUT_ram8; // HREADY feedback
- wire HRESP_ram8; // Transfer response
- wire [1:0] HAUSER_ram8; // Address USER signals
- wire [1:0] HWUSER_ram8; // Write-data USER signals
- wire [1:0] HRUSER_ram8; // Read-data USER signals
-
- // Output Port MI5
- wire HSEL_ram9; // Slave Select
- wire [31:0] HADDR_ram9; // Address bus
- wire [1:0] HTRANS_ram9; // Transfer type
- wire HWRITE_ram9; // Transfer direction
- wire [2:0] HSIZE_ram9; // Transfer size
- wire [2:0] HBURST_ram9; // Burst type
- wire [3:0] HPROT_ram9; // Protection control
- wire [31:0] HWDATA_ram9; // Write data
- wire HMASTLOCK_ram9; // Locked Sequence
- wire HREADYMUX_ram9; // Transfer done
-
- wire [31:0] HRDATA_ram9; // Read data bus
- wire HREADYOUT_ram9; // HREADY feedback
- wire HRESP_ram9; // Transfer response
- wire [1:0] HAUSER_ram9; // Address USER signals
- wire [1:0] HWUSER_ram9; // Write-data USER signals
- wire [1:0] HRUSER_ram9; // Read-data USER signals
-
- // Output Port MI6
- wire HSEL_exp; // Slave Select
- wire [31:0] HADDR_exp; // Address bus
- wire [1:0] HTRANS_exp; // Transfer type
- wire HWRITE_exp; // Transfer direction
- wire [2:0] HSIZE_exp; // Transfer size
- wire [2:0] HBURST_exp; // Burst type
- wire [3:0] HPROT_exp; // Protection control
- wire [31:0] HWDATA_exp; // Write data
- wire HMASTLOCK_exp; // Locked Sequence
- wire HREADYMUX_exp; // Transfer done
-
- wire [31:0] HRDATA_exp; // Read data bus
- wire HREADYOUT_exp; // HREADY feedback
- wire HRESP_exp; // Transfer response
- wire [1:0] HAUSER_exp; // Address USER signals
- wire [1:0] HWUSER_exp; // Write-data USER signals
- wire [1:0] HRUSER_exp; // Read-data USER signals
-
-
-// -----------------------------------------------------------------------------
-// Signal declarations
-// -----------------------------------------------------------------------------
- wire [3:0] tie_hi_4;
- wire tie_hi;
- wire tie_low;
- wire [1:0] i_hresp_adp;
- wire [1:0] i_hresp_dma;
- wire [1:0] i_hresp_dma2;
- wire [1:0] i_hresp_cpu;
-
- wire [3:0] i_hmaster_rom1;
- wire [1:0] i_hresp_rom1;
- wire [3:0] i_hmaster_ram2;
- wire [1:0] i_hresp_ram2;
- wire [3:0] i_hmaster_ram3;
- wire [1:0] i_hresp_ram3;
- wire [3:0] i_hmaster_sys;
- wire [1:0] i_hresp_sys;
- wire [3:0] i_hmaster_ram8;
- wire [1:0] i_hresp_ram8;
- wire [3:0] i_hmaster_ram9;
- wire [1:0] i_hresp_ram9;
- wire [3:0] i_hmaster_exp;
- wire [1:0] i_hresp_exp;
-
-// -----------------------------------------------------------------------------
-// Beginning of main code
-// -----------------------------------------------------------------------------
-
- assign tie_hi = 1'b1;
- assign tie_hi_4 = 4'b1111;
- assign tie_low = 1'b0;
-
-
- assign HRESP_adp = i_hresp_adp[0];
-
- assign HRESP_dma = i_hresp_dma[0];
-
- assign HRESP_dma2 = i_hresp_dma2[0];
-
- assign HRESP_cpu = i_hresp_cpu[0];
-
- assign i_hresp_rom1 = {{1{tie_low}}, HRESP_rom1};
- assign i_hresp_ram2 = {{1{tie_low}}, HRESP_ram2};
- assign i_hresp_ram3 = {{1{tie_low}}, HRESP_ram3};
- assign i_hresp_sys = {{1{tie_low}}, HRESP_sys};
- assign i_hresp_ram8 = {{1{tie_low}}, HRESP_ram8};
- assign i_hresp_ram9 = {{1{tie_low}}, HRESP_ram9};
- assign i_hresp_exp = {{1{tie_low}}, HRESP_exp};
-
-// BusMatrix instance
- nanosoc_ahb32_4x7_busmatrix unanosoc_ahb32_4x7_busmatrix (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .REMAP (REMAP),
-
- // Input port SI0 signals
- .HSEL_adp (tie_hi),
- .HADDR_adp (HADDR_adp),
- .HTRANS_adp (HTRANS_adp),
- .HWRITE_adp (HWRITE_adp),
- .HSIZE_adp (HSIZE_adp),
- .HBURST_adp (HBURST_adp),
- .HPROT_adp (HPROT_adp),
- .HWDATA_adp (HWDATA_adp),
- .HMASTLOCK_adp (HMASTLOCK_adp),
- .HMASTER_adp (tie_hi_4),
- .HREADY_adp (HREADY_adp),
- .HAUSER_adp (HAUSER_adp),
- .HWUSER_adp (HWUSER_adp),
- .HRDATA_adp (HRDATA_adp),
- .HREADYOUT_adp (HREADY_adp),
- .HRESP_adp (i_hresp_adp),
- .HRUSER_adp (HRUSER_adp),
-
- // Input port SI1 signals
- .HSEL_dma (tie_hi),
- .HADDR_dma (HADDR_dma),
- .HTRANS_dma (HTRANS_dma),
- .HWRITE_dma (HWRITE_dma),
- .HSIZE_dma (HSIZE_dma),
- .HBURST_dma (HBURST_dma),
- .HPROT_dma (HPROT_dma),
- .HWDATA_dma (HWDATA_dma),
- .HMASTLOCK_dma (HMASTLOCK_dma),
- .HMASTER_dma (tie_hi_4),
- .HREADY_dma (HREADY_dma),
- .HAUSER_dma (HAUSER_dma),
- .HWUSER_dma (HWUSER_dma),
- .HRDATA_dma (HRDATA_dma),
- .HREADYOUT_dma (HREADY_dma),
- .HRESP_dma (i_hresp_dma),
- .HRUSER_dma (HRUSER_dma),
-
- // Input port SI2 signals
- .HSEL_dma2 (tie_hi),
- .HADDR_dma2 (HADDR_dma2),
- .HTRANS_dma2 (HTRANS_dma2),
- .HWRITE_dma2 (HWRITE_dma2),
- .HSIZE_dma2 (HSIZE_dma2),
- .HBURST_dma2 (HBURST_dma2),
- .HPROT_dma2 (HPROT_dma2),
- .HWDATA_dma2 (HWDATA_dma2),
- .HMASTLOCK_dma2 (HMASTLOCK_dma2),
- .HMASTER_dma2 (tie_hi_4),
- .HREADY_dma2 (HREADY_dma2),
- .HAUSER_dma2 (HAUSER_dma2),
- .HWUSER_dma2 (HWUSER_dma2),
- .HRDATA_dma2 (HRDATA_dma2),
- .HREADYOUT_dma2 (HREADY_dma2),
- .HRESP_dma2 (i_hresp_dma2),
- .HRUSER_dma2 (HRUSER_dma2),
-
- // Input port SI3 signals
- .HSEL_cpu (tie_hi),
- .HADDR_cpu (HADDR_cpu),
- .HTRANS_cpu (HTRANS_cpu),
- .HWRITE_cpu (HWRITE_cpu),
- .HSIZE_cpu (HSIZE_cpu),
- .HBURST_cpu (HBURST_cpu),
- .HPROT_cpu (HPROT_cpu),
- .HWDATA_cpu (HWDATA_cpu),
- .HMASTLOCK_cpu (HMASTLOCK_cpu),
- .HMASTER_cpu (tie_hi_4),
- .HREADY_cpu (HREADY_cpu),
- .HAUSER_cpu (HAUSER_cpu),
- .HWUSER_cpu (HWUSER_cpu),
- .HRDATA_cpu (HRDATA_cpu),
- .HREADYOUT_cpu (HREADY_cpu),
- .HRESP_cpu (i_hresp_cpu),
- .HRUSER_cpu (HRUSER_cpu),
-
-
- // Output port MI0 signals
- .HSEL_rom1 (HSEL_rom1),
- .HADDR_rom1 (HADDR_rom1),
- .HTRANS_rom1 (HTRANS_rom1),
- .HWRITE_rom1 (HWRITE_rom1),
- .HSIZE_rom1 (HSIZE_rom1),
- .HBURST_rom1 (HBURST_rom1),
- .HPROT_rom1 (HPROT_rom1),
- .HWDATA_rom1 (HWDATA_rom1),
- .HMASTER_rom1 (i_hmaster_rom1),
- .HMASTLOCK_rom1 (HMASTLOCK_rom1),
- .HREADYMUX_rom1 (HREADYMUX_rom1),
- .HAUSER_rom1 (HAUSER_rom1),
- .HWUSER_rom1 (HWUSER_rom1),
- .HRDATA_rom1 (HRDATA_rom1),
- .HREADYOUT_rom1 (HREADYOUT_rom1),
- .HRESP_rom1 (i_hresp_rom1),
- .HRUSER_rom1 (HRUSER_rom1),
-
- // Output port MI1 signals
- .HSEL_ram2 (HSEL_ram2),
- .HADDR_ram2 (HADDR_ram2),
- .HTRANS_ram2 (HTRANS_ram2),
- .HWRITE_ram2 (HWRITE_ram2),
- .HSIZE_ram2 (HSIZE_ram2),
- .HBURST_ram2 (HBURST_ram2),
- .HPROT_ram2 (HPROT_ram2),
- .HWDATA_ram2 (HWDATA_ram2),
- .HMASTER_ram2 (i_hmaster_ram2),
- .HMASTLOCK_ram2 (HMASTLOCK_ram2),
- .HREADYMUX_ram2 (HREADYMUX_ram2),
- .HAUSER_ram2 (HAUSER_ram2),
- .HWUSER_ram2 (HWUSER_ram2),
- .HRDATA_ram2 (HRDATA_ram2),
- .HREADYOUT_ram2 (HREADYOUT_ram2),
- .HRESP_ram2 (i_hresp_ram2),
- .HRUSER_ram2 (HRUSER_ram2),
-
- // Output port MI2 signals
- .HSEL_ram3 (HSEL_ram3),
- .HADDR_ram3 (HADDR_ram3),
- .HTRANS_ram3 (HTRANS_ram3),
- .HWRITE_ram3 (HWRITE_ram3),
- .HSIZE_ram3 (HSIZE_ram3),
- .HBURST_ram3 (HBURST_ram3),
- .HPROT_ram3 (HPROT_ram3),
- .HWDATA_ram3 (HWDATA_ram3),
- .HMASTER_ram3 (i_hmaster_ram3),
- .HMASTLOCK_ram3 (HMASTLOCK_ram3),
- .HREADYMUX_ram3 (HREADYMUX_ram3),
- .HAUSER_ram3 (HAUSER_ram3),
- .HWUSER_ram3 (HWUSER_ram3),
- .HRDATA_ram3 (HRDATA_ram3),
- .HREADYOUT_ram3 (HREADYOUT_ram3),
- .HRESP_ram3 (i_hresp_ram3),
- .HRUSER_ram3 (HRUSER_ram3),
-
- // Output port MI3 signals
- .HSEL_sys (HSEL_sys),
- .HADDR_sys (HADDR_sys),
- .HTRANS_sys (HTRANS_sys),
- .HWRITE_sys (HWRITE_sys),
- .HSIZE_sys (HSIZE_sys),
- .HBURST_sys (HBURST_sys),
- .HPROT_sys (HPROT_sys),
- .HWDATA_sys (HWDATA_sys),
- .HMASTER_sys (i_hmaster_sys),
- .HMASTLOCK_sys (HMASTLOCK_sys),
- .HREADYMUX_sys (HREADYMUX_sys),
- .HAUSER_sys (HAUSER_sys),
- .HWUSER_sys (HWUSER_sys),
- .HRDATA_sys (HRDATA_sys),
- .HREADYOUT_sys (HREADYOUT_sys),
- .HRESP_sys (i_hresp_sys),
- .HRUSER_sys (HRUSER_sys),
-
- // Output port MI4 signals
- .HSEL_ram8 (HSEL_ram8),
- .HADDR_ram8 (HADDR_ram8),
- .HTRANS_ram8 (HTRANS_ram8),
- .HWRITE_ram8 (HWRITE_ram8),
- .HSIZE_ram8 (HSIZE_ram8),
- .HBURST_ram8 (HBURST_ram8),
- .HPROT_ram8 (HPROT_ram8),
- .HWDATA_ram8 (HWDATA_ram8),
- .HMASTER_ram8 (i_hmaster_ram8),
- .HMASTLOCK_ram8 (HMASTLOCK_ram8),
- .HREADYMUX_ram8 (HREADYMUX_ram8),
- .HAUSER_ram8 (HAUSER_ram8),
- .HWUSER_ram8 (HWUSER_ram8),
- .HRDATA_ram8 (HRDATA_ram8),
- .HREADYOUT_ram8 (HREADYOUT_ram8),
- .HRESP_ram8 (i_hresp_ram8),
- .HRUSER_ram8 (HRUSER_ram8),
-
- // Output port MI5 signals
- .HSEL_ram9 (HSEL_ram9),
- .HADDR_ram9 (HADDR_ram9),
- .HTRANS_ram9 (HTRANS_ram9),
- .HWRITE_ram9 (HWRITE_ram9),
- .HSIZE_ram9 (HSIZE_ram9),
- .HBURST_ram9 (HBURST_ram9),
- .HPROT_ram9 (HPROT_ram9),
- .HWDATA_ram9 (HWDATA_ram9),
- .HMASTER_ram9 (i_hmaster_ram9),
- .HMASTLOCK_ram9 (HMASTLOCK_ram9),
- .HREADYMUX_ram9 (HREADYMUX_ram9),
- .HAUSER_ram9 (HAUSER_ram9),
- .HWUSER_ram9 (HWUSER_ram9),
- .HRDATA_ram9 (HRDATA_ram9),
- .HREADYOUT_ram9 (HREADYOUT_ram9),
- .HRESP_ram9 (i_hresp_ram9),
- .HRUSER_ram9 (HRUSER_ram9),
-
- // Output port MI6 signals
- .HSEL_exp (HSEL_exp),
- .HADDR_exp (HADDR_exp),
- .HTRANS_exp (HTRANS_exp),
- .HWRITE_exp (HWRITE_exp),
- .HSIZE_exp (HSIZE_exp),
- .HBURST_exp (HBURST_exp),
- .HPROT_exp (HPROT_exp),
- .HWDATA_exp (HWDATA_exp),
- .HMASTER_exp (i_hmaster_exp),
- .HMASTLOCK_exp (HMASTLOCK_exp),
- .HREADYMUX_exp (HREADYMUX_exp),
- .HAUSER_exp (HAUSER_exp),
- .HWUSER_exp (HWUSER_exp),
- .HRDATA_exp (HRDATA_exp),
- .HREADYOUT_exp (HREADYOUT_exp),
- .HRESP_exp (i_hresp_exp),
- .HRUSER_exp (HRUSER_exp),
-
-
- // Scan test dummy signals; not connected until scan insertion
- .SCANENABLE (SCANENABLE),
- .SCANINHCLK (SCANINHCLK),
- .SCANOUTHCLK (SCANOUTHCLK)
- );
-
-
-endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml b/system/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml
deleted file mode 100644
index ad16c547e2cd9557c76adcc21501d8327ee53266..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml
+++ /dev/null
@@ -1,156 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1" ?>
-
-<!--//----------------------------------------------------------------------------- -->
-<!--// customised interconnect specification for ADP/DMA/ Cortex-M0 controller -->
-<!--// -->
-<!--// Contributors -->
-<!--// -->
-<!--// David Flynn (d.w.flynn@soton.ac.uk) -->
-<!--// -->
-<!--// Copyright (C) 2023, SoC Labs (www.soclabs.org) -->
-<!--//----------------------------------------------------------------------------- -->
-
-<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
-<!-- The confidential and proprietary information contained in this file -->
-<!-- may only be used by a person authorised under and to the extent -->
-<!-- permitted by a subsisting licensing agreement from Arm Limited or its affiliates. -->
-<!-- -->
-<!-- (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates. -->
-<!-- ALL RIGHTS RESERVED -->
-<!-- -->
-<!-- This entire notice must be reproduced on all copies of this file -->
-<!-- and copies of this file may only be made by a person if such person -->
-<!-- is permitted to do so under the terms of a subsisting license -->
-<!-- agreement from Arm Limited or its affiliates. -->
-<!-- -->
-<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
-<!-- Version and Release Control Information: -->
-<!-- -->
-<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
-<!-- -->
-<!-- Revision : $Revision: 371321 $ -->
-<!-- -->
-<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
-<!-- -->
-<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
-<!-- Purpose : based on Example XML file, defining an interconnect for -->
-<!-- (was 2 AHB Masters and 3 AHB Slaves.) -->
-<!-- 5 AHB subordinates and 3 AHB controllers -->
-<!-- -->
-<!-- Note : This information will overwrite parameters -->
-<!-- specified on the command line -->
-<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
-
-<cfgfile>
-
- <!-- - - - - *** DO NOT MODIFY ABOVE THIS LINE *** - - - - - - - - - - - -->
-
- <!-- Global definitions -->
-
- <architecture_version>ahb2</architecture_version>
- <arbitration_scheme>burst</arbitration_scheme>
- <routing_data_width>32</routing_data_width>
- <routing_address_width>32</routing_address_width>
- <user_signal_width>2</user_signal_width>
- <bus_matrix_name>nanosoc_ahb32_4x7_busmatrix</bus_matrix_name>
- <input_stage_name>nanosoc_ahb32_4x7_inititator_input</input_stage_name>
- <matrix_decode_name>nanosoc_ahb32_4x7_matrix_decode</matrix_decode_name>
- <output_arbiter_name>nanosoc_ahb32_4x7_arbiter</output_arbiter_name>
- <output_stage_name>nanosoc_ahb32_4x7_target_output</output_stage_name>
-
-
- <!-- Slave interface definitions -->
-
- <slave_interface name="_adp">
- <sparse_connect interface="_rom1"/>
- <sparse_connect interface="_ram2"/>
- <sparse_connect interface="_ram3"/>
- <sparse_connect interface="_sys"/>
- <sparse_connect interface="_exp"/>
- <sparse_connect interface="_ram8"/>
- <sparse_connect interface="_ram9"/>
- <address_region interface="_rom1" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
- <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
- <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
- <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
- <remap_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
- </slave_interface>
-
- <slave_interface name="_dma">
- <sparse_connect interface="_rom1"/>
- <sparse_connect interface="_ram2"/>
- <sparse_connect interface="_ram3"/>
- <sparse_connect interface="_sys"/>
- <sparse_connect interface="_exp"/>
- <sparse_connect interface="_ram8"/>
- <sparse_connect interface="_ram9"/>
- <address_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
- <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
- <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
- </slave_interface>
-
- <slave_interface name="_dma2">
- <sparse_connect interface="_rom1"/>
- <sparse_connect interface="_ram2"/>
- <sparse_connect interface="_ram3"/>
- <sparse_connect interface="_sys"/>
- <sparse_connect interface="_exp"/>
- <sparse_connect interface="_ram8"/>
- <sparse_connect interface="_ram9"/>
- <address_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
- <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
- <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
- </slave_interface>
-
- <slave_interface name="_cpu">
- <sparse_connect interface="_rom1"/>
- <sparse_connect interface="_ram2"/>
- <sparse_connect interface="_ram3"/>
- <sparse_connect interface="_sys"/>
- <sparse_connect interface="_exp"/>
- <sparse_connect interface="_ram8"/>
- <sparse_connect interface="_ram9"/>
- <address_region interface="_rom1" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
- <address_region interface="_rom1" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_ram2" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_ram3" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
- <address_region interface="_ram8" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
- <address_region interface="_ram9" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
- <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
- <address_region interface="_sys" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
- <remap_region interface="_ram2" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
- </slave_interface>
-
- <!-- Master interface definitions -->
-
- <master_interface name="_rom1"/>
- <master_interface name="_ram2"/>
- <master_interface name="_ram3"/>
- <master_interface name="_sys"/>
- <master_interface name="_ram8"/>
- <master_interface name="_ram9"/>
- <master_interface name="_exp"/>
-
- <!-- - - - - *** DO NOT MODIFY BELOW THIS LINE *** - - - - - - - - - - - -->
-
-</cfgfile>
diff --git a/system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml b/system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml
similarity index 78%
rename from system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml
rename to system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml
index 750b122f94aaae9d4629ba9b9cc9799525b148fb..56e0a18a673f064e13e411f9f532d6848c7645ad 100644
--- a/system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml
+++ b/system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.xml
@@ -44,13 +44,14 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__adp_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
</spirit:slave>
<spirit:portMaps>
@@ -213,18 +214,18 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Slave__dma</spirit:name>
- <spirit:description>Slave port _dma</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__dma_0</spirit:name>
+ <spirit:description>Slave port _dma_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_0_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
</spirit:slave>
@@ -252,7 +253,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_dma</spirit:name>
+ <spirit:name>HSEL_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -260,7 +261,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_dma</spirit:name>
+ <spirit:name>HADDR_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -268,7 +269,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:name>HTRANS_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -276,7 +277,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:name>HWRITE_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -284,7 +285,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:name>HSIZE_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -292,7 +293,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_dma</spirit:name>
+ <spirit:name>HBURST_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -300,18 +301,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_dma</spirit:name>
+ <spirit:name>HPROT_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_dma unmapped -->
+ <!-- HMASTER_dma_0 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:name>HWDATA_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -319,7 +320,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -327,7 +328,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_dma</spirit:name>
+ <spirit:name>HREADY_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -335,7 +336,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:name>HAUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -343,7 +344,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:name>HWUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -353,7 +354,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:name>HRDATA_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -361,7 +362,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_dma</spirit:name>
+ <spirit:name>HREADYOUT_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -369,7 +370,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_dma</spirit:name>
+ <spirit:name>HRESP_dma_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -381,25 +382,25 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:name>HRUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Slave__dma2</spirit:name>
- <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__dma_1</spirit:name>
+ <spirit:description>Slave port _dma_1</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma2_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_1_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
</spirit:slave>
@@ -427,7 +428,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_dma2</spirit:name>
+ <spirit:name>HSEL_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -435,7 +436,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:name>HADDR_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -443,7 +444,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:name>HTRANS_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -451,7 +452,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:name>HWRITE_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -459,7 +460,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:name>HSIZE_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -467,7 +468,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:name>HBURST_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -475,18 +476,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:name>HPROT_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_dma2 unmapped -->
+ <!-- HMASTER_dma_1 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:name>HWDATA_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -494,7 +495,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -502,7 +503,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:name>HREADY_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -510,7 +511,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:name>HAUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -518,7 +519,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:name>HWUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -528,7 +529,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:name>HRDATA_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -536,7 +537,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_dma2</spirit:name>
+ <spirit:name>HREADYOUT_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -544,7 +545,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:name>HRESP_dma_1</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -556,7 +557,7 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:name>HRUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -569,13 +570,14 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__cpu_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
</spirit:slave>
<spirit:portMaps>
@@ -740,12 +742,12 @@
<!--Master interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
- <spirit:description>Master port _rom1</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__bootrom</spirit:name>
+ <spirit:description>Master port _bootrom</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__bootrom_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -772,7 +774,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:name>HSEL_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -780,7 +782,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:name>HADDR_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -788,7 +790,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:name>HTRANS_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -796,7 +798,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:name>HWRITE_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -804,7 +806,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:name>HSIZE_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -812,7 +814,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:name>HBURST_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -820,18 +822,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:name>HPROT_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_rom1 unmapped -->
+ <!-- HMASTER_bootrom unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:name>HWDATA_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -839,7 +841,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -847,7 +849,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -855,7 +857,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:name>HAUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -863,7 +865,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:name>HWUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -873,7 +875,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:name>HRDATA_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -881,7 +883,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -889,7 +891,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:name>HRESP_bootrom</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -901,19 +903,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:name>HRUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
- <spirit:description>Master port _ram2</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__imem</spirit:name>
+ <spirit:description>Master port _imem</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__imem_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -940,7 +942,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:name>HSEL_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -948,7 +950,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:name>HADDR_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -956,7 +958,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:name>HTRANS_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -964,7 +966,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:name>HWRITE_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -972,7 +974,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:name>HSIZE_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -980,7 +982,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:name>HBURST_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -988,18 +990,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:name>HPROT_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_ram2 unmapped -->
+ <!-- HMASTER_imem unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:name>HWDATA_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1007,7 +1009,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1015,7 +1017,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:name>HREADYMUX_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1023,7 +1025,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:name>HAUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1031,7 +1033,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:name>HWUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1041,7 +1043,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:name>HRDATA_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1049,7 +1051,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:name>HREADYOUT_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1057,7 +1059,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:name>HRESP_imem</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -1069,19 +1071,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:name>HRUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
- <spirit:description>Master port _ram3</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__dmem</spirit:name>
+ <spirit:description>Master port _dmem</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__dmem_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1108,7 +1110,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:name>HSEL_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1116,7 +1118,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:name>HADDR_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1124,7 +1126,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:name>HTRANS_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1132,7 +1134,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:name>HWRITE_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1140,7 +1142,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:name>HSIZE_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1148,7 +1150,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:name>HBURST_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1156,18 +1158,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:name>HPROT_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_ram3 unmapped -->
+ <!-- HMASTER_dmem unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:name>HWDATA_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1175,7 +1177,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1183,7 +1185,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram3</spirit:name>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1191,7 +1193,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:name>HAUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1199,7 +1201,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:name>HWUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1209,7 +1211,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:name>HRDATA_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1217,7 +1219,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1225,7 +1227,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:name>HRESP_dmem</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -1237,19 +1239,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:name>HRUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
- <spirit:description>Master port _sys</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__sysio</spirit:name>
+ <spirit:description>Master port _sysio</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sysio_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1276,7 +1278,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_sys</spirit:name>
+ <spirit:name>HSEL_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1284,7 +1286,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_sys</spirit:name>
+ <spirit:name>HADDR_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1292,7 +1294,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:name>HTRANS_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1300,7 +1302,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:name>HWRITE_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1308,7 +1310,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:name>HSIZE_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1316,7 +1318,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_sys</spirit:name>
+ <spirit:name>HBURST_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1324,18 +1326,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_sys</spirit:name>
+ <spirit:name>HPROT_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_sys unmapped -->
+ <!-- HMASTER_sysio unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:name>HWDATA_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1343,7 +1345,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1351,7 +1353,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1359,7 +1361,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:name>HAUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1367,7 +1369,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:name>HWUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1377,7 +1379,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:name>HRDATA_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1385,7 +1387,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1393,7 +1395,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_sys</spirit:name>
+ <spirit:name>HRESP_sysio</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -1405,19 +1407,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:name>HRUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
- <spirit:description>Master port _ram8</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_l</spirit:name>
+ <spirit:description>Master port _expram_l</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_l_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1444,7 +1446,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:name>HSEL_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1452,7 +1454,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:name>HADDR_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1460,7 +1462,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:name>HTRANS_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1468,7 +1470,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:name>HWRITE_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1476,7 +1478,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:name>HSIZE_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1484,7 +1486,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:name>HBURST_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1492,18 +1494,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:name>HPROT_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_ram8 unmapped -->
+ <!-- HMASTER_expram_l unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:name>HWDATA_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1511,7 +1513,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1519,7 +1521,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1527,7 +1529,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:name>HAUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1535,7 +1537,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:name>HWUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1545,7 +1547,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:name>HRDATA_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1553,7 +1555,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1561,7 +1563,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:name>HRESP_expram_l</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -1573,19 +1575,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:name>HRUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
- <spirit:description>Master port _ram9</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_h</spirit:name>
+ <spirit:description>Master port _expram_h</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_h_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1612,7 +1614,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:name>HSEL_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1620,7 +1622,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:name>HADDR_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1628,7 +1630,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:name>HTRANS_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1636,7 +1638,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:name>HWRITE_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1644,7 +1646,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:name>HSIZE_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1652,7 +1654,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:name>HBURST_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1660,18 +1662,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:name>HPROT_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_ram9 unmapped -->
+ <!-- HMASTER_expram_h unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:name>HWDATA_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1679,7 +1681,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1687,7 +1689,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1695,7 +1697,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:name>HAUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1703,7 +1705,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:name>HWUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1713,7 +1715,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:name>HRDATA_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1721,7 +1723,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1729,7 +1731,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:name>HRESP_expram_h</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -1741,7 +1743,7 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:name>HRUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -1915,6 +1917,174 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__systable</spirit:name>
+ <spirit:description>Master port _systable</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__systable_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_systable unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<!--Scan test dummy signals -->
<spirit:busInterface>
<spirit:name>DFTInterface_Slave</spirit:name>
@@ -1974,17 +2144,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -1993,18 +2163,18 @@
<spirit:addressSpaces>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
- <spirit:description>_rom1 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__bootrom_AS</spirit:name>
+ <spirit:description>_bootrom address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_bootrom_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_bootrom_0x10000000_0x1fffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2013,18 +2183,18 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
- <spirit:description>_ram2 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__imem_AS</spirit:name>
+ <spirit:description>_imem address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_imem_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:name>_imem_0x20000000_0x2fffffff</spirit:name>
<spirit:addressOffset>0x20000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2033,13 +2203,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
- <spirit:description>_ram3 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__dmem_AS</spirit:name>
+ <spirit:description>_dmem address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:name>_dmem_0x30000000_0x3fffffff</spirit:name>
<spirit:addressOffset>0x30000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2048,33 +2218,28 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
- <spirit:description>_sys address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__sysio_AS</spirit:name>
+ <spirit:description>_sysio address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:name>_sysio_0x40000000_0x5fffffff</spirit:name>
<spirit:addressOffset>0x40000000</spirit:addressOffset>
<spirit:range>0x020000000</spirit:range>
</spirit:segment>
- <spirit:segment>
- <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
- <spirit:addressOffset>0xf0000000</spirit:addressOffset>
- <spirit:range>0x000040000</spirit:range>
- </spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
- <spirit:description>_ram8 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_l_AS</spirit:name>
+ <spirit:description>_expram_l address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:name>_expram_l_0x80000000_0x8fffffff</spirit:name>
<spirit:addressOffset>0x80000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2083,13 +2248,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
- <spirit:description>_ram9 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_h_AS</spirit:name>
+ <spirit:description>_expram_h address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:name>_expram_h_0x90000000_0x9fffffff</spirit:name>
<spirit:addressOffset>0x90000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2117,6 +2282,21 @@
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__systable_AS</spirit:name>
+ <spirit:description>_systable address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_systable_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
</spirit:addressSpaces>
<spirit:memoryMaps>
@@ -2125,31 +2305,31 @@
<spirit:name>AHBLiteTarget_Slave__adp_MM</spirit:name>
<spirit:description>_adp memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2160,17 +2340,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2181,31 +2361,31 @@
<spirit:baseAddress>0xa0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
<!-- Address_region 0xf0000000-0xf003ffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__adp_remap_0_remap_MM</spirit:name>
- <spirit:description>_adp remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__adp_remap_n0_remap_MM</spirit:name>
<spirit:description>_adp remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2213,41 +2393,41 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__dma_MM</spirit:name>
- <spirit:description>_dma memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__dma_0_MM</spirit:name>
+ <spirit:description>_dma_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2258,17 +2438,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2282,41 +2462,41 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__dma2_MM</spirit:name>
- <spirit:description>_dma2 memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__dma_1_MM</spirit:name>
+ <spirit:description>_dma_1 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2327,17 +2507,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2354,31 +2534,31 @@
<spirit:name>AHBLiteTarget_Slave__cpu_MM</spirit:name>
<spirit:description>_cpu memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2389,17 +2569,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2410,31 +2590,31 @@
<spirit:baseAddress>0xa0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
<!-- Address_region 0xf0000000-0xf003ffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteTarget_Slave__cpu_remap_0_remap_MM</spirit:name>
- <spirit:description>_cpu remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__cpu_remap_n0_remap_MM</spirit:name>
<spirit:description>_cpu remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2615,13 +2795,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_dma</spirit:name>
+ <spirit:name>HSEL_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_dma</spirit:name>
+ <spirit:name>HADDR_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2631,7 +2811,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:name>HTRANS_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2641,13 +2821,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:name>HWRITE_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:name>HSIZE_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2657,7 +2837,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_dma</spirit:name>
+ <spirit:name>HBURST_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2670,7 +2850,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_dma</spirit:name>
+ <spirit:name>HPROT_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2680,7 +2860,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_dma</spirit:name>
+ <spirit:name>HMASTER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2693,7 +2873,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:name>HWDATA_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2703,20 +2883,20 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_dma</spirit:name>
+ <spirit:name>HREADY_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:name>HAUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2726,7 +2906,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:name>HWUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2736,13 +2916,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_dma2</spirit:name>
+ <spirit:name>HSEL_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:name>HADDR_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2752,7 +2932,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:name>HTRANS_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2762,13 +2942,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:name>HWRITE_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:name>HSIZE_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2778,7 +2958,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:name>HBURST_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2791,7 +2971,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:name>HPROT_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2801,7 +2981,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_dma2</spirit:name>
+ <spirit:name>HMASTER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2814,7 +2994,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:name>HWDATA_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2824,20 +3004,20 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:name>HREADY_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:name>HAUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2847,7 +3027,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:name>HWUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2981,7 +3161,7 @@
<!-- Input signals of Master interfaces -->
<spirit:port>
- <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:name>HRDATA_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2991,13 +3171,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:name>HRESP_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3007,7 +3187,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:name>HRUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3017,7 +3197,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:name>HRDATA_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3027,13 +3207,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:name>HREADYOUT_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:name>HRESP_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3043,7 +3223,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:name>HRUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3053,7 +3233,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:name>HRDATA_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3063,13 +3243,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:name>HRESP_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3079,7 +3259,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:name>HRUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3089,7 +3269,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:name>HRDATA_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3099,13 +3279,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_sys</spirit:name>
+ <spirit:name>HRESP_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3115,7 +3295,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:name>HRUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3125,7 +3305,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:name>HRDATA_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3135,13 +3315,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:name>HRESP_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3151,7 +3331,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:name>HRUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3161,7 +3341,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:name>HRDATA_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3171,13 +3351,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:name>HRESP_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3187,7 +3367,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:name>HRUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3232,6 +3412,42 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<!-- Scan test dummy signals; not connected until scan insertion -->
@@ -3251,13 +3467,13 @@
<!-- Output signals of Master interfaces -->
<spirit:port>
- <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:name>HSEL_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:name>HADDR_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3267,7 +3483,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:name>HTRANS_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3277,13 +3493,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:name>HWRITE_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:name>HSIZE_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3293,7 +3509,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:name>HBURST_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3303,7 +3519,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:name>HPROT_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3313,7 +3529,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_rom1</spirit:name>
+ <spirit:name>HMASTER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3323,7 +3539,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:name>HWDATA_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3333,19 +3549,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:name>HAUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3355,7 +3571,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:name>HWUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3365,13 +3581,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:name>HSEL_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:name>HADDR_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3381,7 +3597,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:name>HTRANS_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3391,13 +3607,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:name>HWRITE_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:name>HSIZE_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3407,7 +3623,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:name>HBURST_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3417,7 +3633,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:name>HPROT_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3427,7 +3643,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_ram2</spirit:name>
+ <spirit:name>HMASTER_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3437,7 +3653,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:name>HWDATA_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3447,19 +3663,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:name>HREADYMUX_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:name>HAUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3469,7 +3685,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:name>HWUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3479,13 +3695,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:name>HSEL_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:name>HADDR_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3495,7 +3711,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:name>HTRANS_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3505,13 +3721,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:name>HWRITE_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:name>HSIZE_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3521,7 +3737,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:name>HBURST_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3531,7 +3747,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:name>HPROT_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3541,7 +3757,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_ram3</spirit:name>
+ <spirit:name>HMASTER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3551,7 +3767,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:name>HWDATA_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3561,19 +3777,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram3</spirit:name>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:name>HAUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3583,7 +3799,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:name>HWUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3593,13 +3809,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_sys</spirit:name>
+ <spirit:name>HSEL_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_sys</spirit:name>
+ <spirit:name>HADDR_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3609,7 +3825,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:name>HTRANS_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3619,13 +3835,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:name>HWRITE_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:name>HSIZE_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3635,7 +3851,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_sys</spirit:name>
+ <spirit:name>HBURST_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3645,7 +3861,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_sys</spirit:name>
+ <spirit:name>HPROT_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3655,7 +3871,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_sys</spirit:name>
+ <spirit:name>HMASTER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3665,7 +3881,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:name>HWDATA_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3675,19 +3891,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:name>HAUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3697,7 +3913,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:name>HWUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3707,13 +3923,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:name>HSEL_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:name>HADDR_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3723,7 +3939,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:name>HTRANS_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3733,13 +3949,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:name>HWRITE_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:name>HSIZE_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3749,7 +3965,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:name>HBURST_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3759,7 +3975,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:name>HPROT_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3769,7 +3985,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_ram8</spirit:name>
+ <spirit:name>HMASTER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3779,7 +3995,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:name>HWDATA_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3789,19 +4005,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:name>HAUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3811,7 +4027,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:name>HWUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3821,13 +4037,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:name>HSEL_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:name>HADDR_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3837,7 +4053,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:name>HTRANS_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3847,13 +4063,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:name>HWRITE_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:name>HSIZE_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3863,7 +4079,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:name>HBURST_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3873,7 +4089,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:name>HPROT_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3883,7 +4099,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_ram9</spirit:name>
+ <spirit:name>HMASTER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3893,7 +4109,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:name>HWDATA_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3903,19 +4119,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:name>HAUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3925,7 +4141,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:name>HWUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4048,6 +4264,120 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<!-- Output signals of Slave interfaces -->
@@ -4088,7 +4418,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:name>HRDATA_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4098,13 +4428,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_dma</spirit:name>
+ <spirit:name>HREADYOUT_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_dma</spirit:name>
+ <spirit:name>HRESP_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4114,7 +4444,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:name>HRUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4124,7 +4454,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:name>HRDATA_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4134,13 +4464,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_dma2</spirit:name>
+ <spirit:name>HREADYOUT_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:name>HRESP_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4150,7 +4480,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:name>HRUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4230,11 +4560,11 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
@@ -4242,11 +4572,67 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_exp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_systable.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_exp.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_systable.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
</spirit:fileSet>
diff --git a/system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml b/system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml
similarity index 77%
rename from system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml
rename to system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml
index 0ef75c3fc5856c3d78ebb7112e99a823ec341bb5..0a4c363025c9604aaec4f99e486dfd84cde1a49f 100644
--- a/system/src/nanosoc_ahb_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml
+++ b/system/src/nanosoc_busmatrix/ipxact/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.xml
@@ -44,13 +44,14 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__adp_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
</spirit:slave>
<spirit:portMaps>
@@ -190,18 +191,18 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteInitiator_Slave__dma</spirit:name>
- <spirit:description>Slave port _dma</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__dma_0</spirit:name>
+ <spirit:description>Slave port _dma_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_0_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
</spirit:slave>
@@ -229,7 +230,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_dma</spirit:name>
+ <spirit:name>HADDR_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -237,7 +238,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:name>HTRANS_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -245,7 +246,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:name>HWRITE_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -253,7 +254,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:name>HSIZE_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -261,7 +262,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_dma</spirit:name>
+ <spirit:name>HBURST_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -269,7 +270,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_dma</spirit:name>
+ <spirit:name>HPROT_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -277,7 +278,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:name>HWDATA_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -285,7 +286,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -293,7 +294,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:name>HAUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -301,7 +302,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:name>HWUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -311,7 +312,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:name>HRDATA_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -319,7 +320,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_dma</spirit:name>
+ <spirit:name>HREADY_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -327,7 +328,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_dma</spirit:name>
+ <spirit:name>HRESP_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -335,25 +336,25 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:name>HRUSER_dma_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteInitiator_Slave__dma2</spirit:name>
- <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__dma_1</spirit:name>
+ <spirit:description>Slave port _dma_1</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma2_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_1_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
</spirit:slave>
@@ -381,7 +382,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:name>HADDR_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -389,7 +390,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:name>HTRANS_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -397,7 +398,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:name>HWRITE_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -405,7 +406,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:name>HSIZE_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -413,7 +414,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:name>HBURST_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -421,7 +422,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:name>HPROT_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -429,7 +430,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:name>HWDATA_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -437,7 +438,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -445,7 +446,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:name>HAUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -453,7 +454,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:name>HWUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -463,7 +464,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:name>HRDATA_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -471,7 +472,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:name>HREADY_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -479,7 +480,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:name>HRESP_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -487,7 +488,7 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:name>HRUSER_dma_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -500,13 +501,14 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__cpu_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
</spirit:slave>
<spirit:portMaps>
@@ -648,12 +650,12 @@
<!--Master interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
- <spirit:description>Master port _rom1</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__bootrom</spirit:name>
+ <spirit:description>Master port _bootrom</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__bootrom_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -680,7 +682,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:name>HSEL_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -688,7 +690,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:name>HADDR_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -696,7 +698,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:name>HTRANS_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -704,7 +706,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:name>HWRITE_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -712,7 +714,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:name>HSIZE_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -720,7 +722,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:name>HBURST_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -728,7 +730,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:name>HPROT_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -736,7 +738,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:name>HWDATA_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -744,7 +746,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -752,7 +754,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -760,7 +762,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:name>HAUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -768,7 +770,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:name>HWUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -778,7 +780,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:name>HRDATA_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -786,7 +788,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -794,7 +796,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:name>HRESP_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -802,19 +804,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:name>HRUSER_bootrom</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
- <spirit:description>Master port _ram2</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__imem</spirit:name>
+ <spirit:description>Master port _imem</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__imem_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -841,7 +843,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:name>HSEL_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -849,7 +851,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:name>HADDR_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -857,7 +859,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:name>HTRANS_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -865,7 +867,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:name>HWRITE_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -873,7 +875,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:name>HSIZE_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -881,7 +883,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:name>HBURST_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -889,7 +891,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:name>HPROT_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -897,7 +899,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:name>HWDATA_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -905,7 +907,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -913,7 +915,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:name>HREADYMUX_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -921,7 +923,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:name>HAUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -929,7 +931,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:name>HWUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -939,7 +941,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:name>HRDATA_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -947,7 +949,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:name>HREADYOUT_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -955,7 +957,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:name>HRESP_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -963,19 +965,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:name>HRUSER_imem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
- <spirit:description>Master port _ram3</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__dmem</spirit:name>
+ <spirit:description>Master port _dmem</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__dmem_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1002,7 +1004,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:name>HSEL_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1010,7 +1012,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:name>HADDR_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1018,7 +1020,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:name>HTRANS_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1026,7 +1028,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:name>HWRITE_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1034,7 +1036,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:name>HSIZE_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1042,7 +1044,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:name>HBURST_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1050,7 +1052,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:name>HPROT_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1058,7 +1060,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:name>HWDATA_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1066,7 +1068,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1074,7 +1076,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram3</spirit:name>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1082,7 +1084,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:name>HAUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1090,7 +1092,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:name>HWUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1100,7 +1102,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:name>HRDATA_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1108,7 +1110,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1116,7 +1118,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:name>HRESP_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1124,19 +1126,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:name>HRUSER_dmem</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
- <spirit:description>Master port _sys</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__sysio</spirit:name>
+ <spirit:description>Master port _sysio</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sysio_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1163,7 +1165,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_sys</spirit:name>
+ <spirit:name>HSEL_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1171,7 +1173,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_sys</spirit:name>
+ <spirit:name>HADDR_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1179,7 +1181,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:name>HTRANS_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1187,7 +1189,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:name>HWRITE_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1195,7 +1197,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:name>HSIZE_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1203,7 +1205,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_sys</spirit:name>
+ <spirit:name>HBURST_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1211,7 +1213,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_sys</spirit:name>
+ <spirit:name>HPROT_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1219,7 +1221,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:name>HWDATA_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1227,7 +1229,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1235,7 +1237,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1243,7 +1245,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:name>HAUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1251,7 +1253,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:name>HWUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1261,7 +1263,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:name>HRDATA_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1269,7 +1271,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1277,7 +1279,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_sys</spirit:name>
+ <spirit:name>HRESP_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1285,19 +1287,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:name>HRUSER_sysio</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
- <spirit:description>Master port _ram8</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_l</spirit:name>
+ <spirit:description>Master port _expram_l</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_l_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1324,7 +1326,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:name>HSEL_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1332,7 +1334,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:name>HADDR_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1340,7 +1342,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:name>HTRANS_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1348,7 +1350,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:name>HWRITE_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1356,7 +1358,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:name>HSIZE_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1364,7 +1366,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:name>HBURST_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1372,7 +1374,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:name>HPROT_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1380,7 +1382,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:name>HWDATA_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1388,7 +1390,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1396,7 +1398,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1404,7 +1406,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:name>HAUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1412,7 +1414,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:name>HWUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1422,7 +1424,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:name>HRDATA_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1430,7 +1432,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1438,7 +1440,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:name>HRESP_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1446,19 +1448,19 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:name>HRUSER_expram_l</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
- <spirit:description>Master port _ram9</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_h</spirit:name>
+ <spirit:description>Master port _expram_h</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_h_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -1485,7 +1487,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:name>HSEL_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1493,7 +1495,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:name>HADDR_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1501,7 +1503,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:name>HTRANS_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1509,7 +1511,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:name>HWRITE_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1517,7 +1519,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:name>HSIZE_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1525,7 +1527,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:name>HBURST_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1533,7 +1535,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:name>HPROT_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1541,7 +1543,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:name>HWDATA_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1549,7 +1551,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1557,7 +1559,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1565,7 +1567,7 @@
<spirit:name>HAUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:name>HAUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1573,7 +1575,7 @@
<spirit:name>HWUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:name>HWUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1583,7 +1585,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:name>HRDATA_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1591,7 +1593,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1599,7 +1601,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:name>HRESP_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1607,7 +1609,7 @@
<spirit:name>HRUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:name>HRUSER_expram_h</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -1774,6 +1776,167 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__systable</spirit:name>
+ <spirit:description>Master port _systable</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__systable_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<!--Scan test dummy signals -->
<spirit:busInterface>
<spirit:name>DFTInterface_Slave</spirit:name>
@@ -1833,17 +1996,17 @@
<spirit:remapStates>
<spirit:remapState>
- <spirit:name>remap_0</spirit:name>
- <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
<spirit:remapPorts>
- <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -1852,18 +2015,18 @@
<spirit:addressSpaces>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
- <spirit:description>_rom1 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__bootrom_AS</spirit:name>
+ <spirit:description>_bootrom address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_bootrom_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_bootrom_0x10000000_0x1fffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -1872,18 +2035,18 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
- <spirit:description>_ram2 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__imem_AS</spirit:name>
+ <spirit:description>_imem address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_imem_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:name>_imem_0x20000000_0x2fffffff</spirit:name>
<spirit:addressOffset>0x20000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -1892,13 +2055,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
- <spirit:description>_ram3 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__dmem_AS</spirit:name>
+ <spirit:description>_dmem address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:name>_dmem_0x30000000_0x3fffffff</spirit:name>
<spirit:addressOffset>0x30000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -1907,33 +2070,28 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
- <spirit:description>_sys address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__sysio_AS</spirit:name>
+ <spirit:description>_sysio address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:name>_sysio_0x40000000_0x5fffffff</spirit:name>
<spirit:addressOffset>0x40000000</spirit:addressOffset>
<spirit:range>0x020000000</spirit:range>
</spirit:segment>
- <spirit:segment>
- <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
- <spirit:addressOffset>0xf0000000</spirit:addressOffset>
- <spirit:range>0x000040000</spirit:range>
- </spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
- <spirit:description>_ram8 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_l_AS</spirit:name>
+ <spirit:description>_expram_l address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:name>_expram_l_0x80000000_0x8fffffff</spirit:name>
<spirit:addressOffset>0x80000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -1942,13 +2100,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
- <spirit:description>_ram9 address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__expram_h_AS</spirit:name>
+ <spirit:description>_expram_h address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:name>_expram_h_0x90000000_0x9fffffff</spirit:name>
<spirit:addressOffset>0x90000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -1976,6 +2134,21 @@
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__systable_AS</spirit:name>
+ <spirit:description>_systable address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_systable_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
</spirit:addressSpaces>
<spirit:memoryMaps>
@@ -1984,31 +2157,31 @@
<spirit:name>AHBLiteInitiator_Slave__adp_MM</spirit:name>
<spirit:description>_adp memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2019,17 +2192,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2040,31 +2213,31 @@
<spirit:baseAddress>0xa0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
<!-- Address_region 0xf0000000-0xf003ffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__adp_remap_0_remap_MM</spirit:name>
- <spirit:description>_adp remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__adp_remap_n0_remap_MM</spirit:name>
<spirit:description>_adp remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2072,41 +2245,41 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__dma_MM</spirit:name>
- <spirit:description>_dma memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__dma_0_MM</spirit:name>
+ <spirit:description>_dma_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2117,17 +2290,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2141,41 +2314,41 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__dma2_MM</spirit:name>
- <spirit:description>_dma2 memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__dma_1_MM</spirit:name>
+ <spirit:description>_dma_1 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2186,17 +2359,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2213,31 +2386,31 @@
<spirit:name>AHBLiteInitiator_Slave__cpu_MM</spirit:name>
<spirit:description>_cpu memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
- spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
<!-- Address_region 0x40000000-0x5fffffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x40000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2248,17 +2421,17 @@
<spirit:baseAddress>0x60000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
- spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
<!-- Address_region 0x80000000-0x8fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x80000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
- spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
<!-- Address_region 0x90000000-0x9fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x90000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2269,31 +2442,31 @@
<spirit:baseAddress>0xa0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
- spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
<!-- Address_region 0xf0000000-0xf003ffff -->
- <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0xf0000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:memoryRemap spirit:state="remap_0">
- <spirit:name>AHBLiteInitiator_Slave__cpu_remap_0_remap_MM</spirit:name>
- <spirit:description>_cpu remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
- spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
- <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
- <spirit:baseAddress>0x00000000</spirit:baseAddress>
- </spirit:subspaceMap>
- </spirit:memoryRemap>
-
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__cpu_remap_n0_remap_MM</spirit:name>
<spirit:description>_cpu remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
- spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2448,7 +2621,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_dma</spirit:name>
+ <spirit:name>HADDR_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2458,7 +2631,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:name>HTRANS_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2468,13 +2641,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:name>HWRITE_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:name>HSIZE_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2484,7 +2657,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_dma</spirit:name>
+ <spirit:name>HBURST_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2497,7 +2670,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_dma</spirit:name>
+ <spirit:name>HPROT_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2507,7 +2680,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:name>HWDATA_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2517,13 +2690,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:name>HAUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2533,7 +2706,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:name>HWUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2543,7 +2716,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:name>HADDR_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2553,7 +2726,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:name>HTRANS_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2563,13 +2736,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:name>HWRITE_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:name>HSIZE_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2579,7 +2752,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:name>HBURST_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2592,7 +2765,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:name>HPROT_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2602,7 +2775,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:name>HWDATA_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2612,13 +2785,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:name>HAUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2628,7 +2801,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:name>HWUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2736,7 +2909,7 @@
<!-- Input signals of Master interfaces -->
<spirit:port>
- <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:name>HRDATA_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2746,19 +2919,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:name>HRESP_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:name>HRUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2768,7 +2941,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:name>HRDATA_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2778,19 +2951,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:name>HREADYOUT_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:name>HRESP_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:name>HRUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2800,7 +2973,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:name>HRDATA_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2810,19 +2983,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:name>HRESP_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:name>HRUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2832,7 +3005,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:name>HRDATA_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2842,19 +3015,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_sys</spirit:name>
+ <spirit:name>HRESP_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:name>HRUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2864,7 +3037,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:name>HRDATA_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2874,19 +3047,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:name>HRESP_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:name>HRUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2896,7 +3069,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:name>HRDATA_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2906,19 +3079,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:name>HRESP_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:name>HRUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2959,6 +3132,38 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<!-- Scan test dummy signals; not connected until scan insertion -->
@@ -2978,13 +3183,13 @@
<!-- Output signals of Master interfaces -->
<spirit:port>
- <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:name>HSEL_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:name>HADDR_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -2994,7 +3199,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:name>HTRANS_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3004,13 +3209,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:name>HWRITE_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:name>HSIZE_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3020,7 +3225,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:name>HBURST_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3030,7 +3235,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:name>HPROT_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3040,7 +3245,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:name>HWDATA_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3050,19 +3255,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:name>HAUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3072,7 +3277,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:name>HWUSER_bootrom</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3082,13 +3287,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:name>HSEL_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:name>HADDR_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3098,7 +3303,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:name>HTRANS_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3108,13 +3313,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:name>HWRITE_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:name>HSIZE_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3124,7 +3329,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:name>HBURST_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3134,7 +3339,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:name>HPROT_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3144,7 +3349,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:name>HWDATA_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3154,19 +3359,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:name>HREADYMUX_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:name>HAUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3176,7 +3381,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:name>HWUSER_imem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3186,13 +3391,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:name>HSEL_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:name>HADDR_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3202,7 +3407,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:name>HTRANS_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3212,13 +3417,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:name>HWRITE_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:name>HSIZE_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3228,7 +3433,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:name>HBURST_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3238,7 +3443,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:name>HPROT_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3248,7 +3453,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:name>HWDATA_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3258,19 +3463,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram3</spirit:name>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:name>HAUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3280,7 +3485,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:name>HWUSER_dmem</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3290,13 +3495,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_sys</spirit:name>
+ <spirit:name>HSEL_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_sys</spirit:name>
+ <spirit:name>HADDR_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3306,7 +3511,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:name>HTRANS_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3316,13 +3521,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:name>HWRITE_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:name>HSIZE_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3332,7 +3537,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_sys</spirit:name>
+ <spirit:name>HBURST_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3342,7 +3547,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_sys</spirit:name>
+ <spirit:name>HPROT_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3352,7 +3557,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:name>HWDATA_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3362,19 +3567,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:name>HAUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3384,7 +3589,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:name>HWUSER_sysio</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3394,13 +3599,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:name>HSEL_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:name>HADDR_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3410,7 +3615,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:name>HTRANS_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3420,13 +3625,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:name>HWRITE_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:name>HSIZE_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3436,7 +3641,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:name>HBURST_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3446,7 +3651,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:name>HPROT_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3456,7 +3661,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:name>HWDATA_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3466,19 +3671,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:name>HAUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3488,7 +3693,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:name>HWUSER_expram_l</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3498,13 +3703,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:name>HSEL_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:name>HADDR_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3514,7 +3719,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:name>HTRANS_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3524,13 +3729,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:name>HWRITE_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:name>HSIZE_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3540,7 +3745,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:name>HBURST_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3550,7 +3755,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:name>HPROT_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3560,7 +3765,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:name>HWDATA_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3570,19 +3775,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:name>HAUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3592,7 +3797,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:name>HWUSER_expram_h</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3705,6 +3910,110 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<!-- Output signals of Slave interfaces -->
@@ -3741,7 +4050,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:name>HRDATA_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3751,19 +4060,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_dma</spirit:name>
+ <spirit:name>HREADY_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_dma</spirit:name>
+ <spirit:name>HRESP_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:name>HRUSER_dma_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3773,7 +4082,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:name>HRDATA_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3783,19 +4092,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:name>HREADY_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:name>HRESP_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:name>HRUSER_dma_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3875,11 +4184,11 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
@@ -3887,11 +4196,67 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_exp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter_systable.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_exp.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output_systable.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
</spirit:fileSet>
diff --git a/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09c4f75645addf45dc508af828cfdb2297c1842c
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -0,0 +1,3995 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the main top of nanosoc_busmatrix -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>nanosoc_busmatrix</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__socdebug</spirit:name>
+ <spirit:description>Slave port _socdebug</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__socdebug_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_socdebug unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_socdebug</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma_0</spirit:name>
+ <spirit:description>Slave port _dma_0</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_0_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma_0 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma_0</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma_1</spirit:name>
+ <spirit:description>Slave port _dma_1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_1_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma_1 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma_1</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_cpu unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__bootrom</spirit:name>
+ <spirit:description>Master port _bootrom</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__bootrom_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_bootrom unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_bootrom</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__imem</spirit:name>
+ <spirit:description>Master port _imem</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__imem_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_imem unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_imem</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__dmem</spirit:name>
+ <spirit:description>Master port _dmem</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__dmem_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dmem unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dmem</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sysio</spirit:name>
+ <spirit:description>Master port _sysio</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sysio_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_sysio unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sysio</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__expram_l</spirit:name>
+ <spirit:description>Master port _expram_l</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_l_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_expram_l unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_expram_l</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__expram_h</spirit:name>
+ <spirit:description>Master port _expram_h</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_h_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_expram_h unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_expram_h</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_exp unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__systable</spirit:name>
+ <spirit:description>Master port _systable</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__systable_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_systable unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__bootrom_AS</spirit:name>
+ <spirit:description>_bootrom address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_bootrom_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_bootrom_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__imem_AS</spirit:name>
+ <spirit:description>_imem address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_imem_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_imem_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__dmem_AS</spirit:name>
+ <spirit:description>_dmem address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_dmem_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sysio_AS</spirit:name>
+ <spirit:description>_sysio address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sysio_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__expram_l_AS</spirit:name>
+ <spirit:description>_expram_l address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_expram_l_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__expram_h_AS</spirit:name>
+ <spirit:description>_expram_h address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_expram_h_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__systable_AS</spirit:name>
+ <spirit:description>_systable address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_systable_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__socdebug_MM</spirit:name>
+ <spirit:description>_socdebug memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__socdebug_remap_0_remap_MM</spirit:name>
+ <spirit:description>_socdebug remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__socdebug_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_socdebug remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma_0_MM</spirit:name>
+ <spirit:description>_dma_0 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma_1_MM</spirit:name>
+ <spirit:description>_dma_1 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>nanosoc_busmatrix bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>nanosoc_busmatrix</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HSEL_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HSEL_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>2</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HSEL_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>3</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for nanosoc_busmatrix</spirit:description>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_busmatrix.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_inititator_input.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_socdebug.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_0.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_1.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_cpu.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_exp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_systable.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_bootrom.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_imem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_sysio.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_expram_l.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_expram_h.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>nanosoc_busmatrix</spirit:description>
+
+</spirit:component>
diff --git a/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
new file mode 100644
index 0000000000000000000000000000000000000000..d20bd2e684569d45f35e6934bf4330ca6405531a
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -0,0 +1,3619 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the AHB-Lite wrapper of nanosoc_busmatrix_lite -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>nanosoc_busmatrix_lite</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__socdebug</spirit:name>
+ <spirit:description>Slave port _socdebug</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__socdebug_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_socdebug</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma_0</spirit:name>
+ <spirit:description>Slave port _dma_0</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_0_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma_1</spirit:name>
+ <spirit:description>Slave port _dma_1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_1_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__bootrom" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__imem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__dmem" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sysio" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_l" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__expram_h" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__systable" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__bootrom</spirit:name>
+ <spirit:description>Master port _bootrom</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__bootrom_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_bootrom</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__imem</spirit:name>
+ <spirit:description>Master port _imem</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__imem_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_imem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__dmem</spirit:name>
+ <spirit:description>Master port _dmem</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__dmem_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dmem</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sysio</spirit:name>
+ <spirit:description>Master port _sysio</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sysio_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sysio</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__expram_l</spirit:name>
+ <spirit:description>Master port _expram_l</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_l_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_expram_l</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__expram_h</spirit:name>
+ <spirit:description>Master port _expram_h</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__expram_h_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_expram_h</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__systable</spirit:name>
+ <spirit:description>Master port _systable</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__systable_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_systable</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__bootrom_AS</spirit:name>
+ <spirit:description>_bootrom address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_bootrom_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_bootrom_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__imem_AS</spirit:name>
+ <spirit:description>_imem address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_imem_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_imem_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__dmem_AS</spirit:name>
+ <spirit:description>_dmem address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_dmem_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sysio_AS</spirit:name>
+ <spirit:description>_sysio address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sysio_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__expram_l_AS</spirit:name>
+ <spirit:description>_expram_l address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_expram_l_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__expram_h_AS</spirit:name>
+ <spirit:description>_expram_h address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_expram_h_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__systable_AS</spirit:name>
+ <spirit:description>_systable address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_systable_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__socdebug_MM</spirit:name>
+ <spirit:description>_socdebug memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__socdebug_remap_0_remap_MM</spirit:name>
+ <spirit:description>_socdebug remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__socdebug_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_socdebug remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma_0_MM</spirit:name>
+ <spirit:description>_dma_0 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma_1_MM</spirit:name>
+ <spirit:description>_dma_1 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__dmem"
+ spirit:segmentRef="_dmem_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__dmem_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sysio"
+ spirit:segmentRef="_sysio_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sysio_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_l"
+ spirit:segmentRef="_expram_l_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_l_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__expram_h"
+ spirit:segmentRef="_expram_h_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__expram_h_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__systable"
+ spirit:segmentRef="_systable_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__systable_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__imem"
+ spirit:segmentRef="_imem_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__imem_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__bootrom"
+ spirit:segmentRef="_bootrom_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__bootrom_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>nanosoc_busmatrix_lite bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>nanosoc_busmatrix_lite</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HADDR_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_bootrom</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_imem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dmem</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
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+ <spirit:name>HWRITE_sysio</spirit:name>
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+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_sysio</spirit:name>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:name>HBURST_sysio</spirit:name>
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+ </spirit:port>
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+ <spirit:name>HPROT_sysio</spirit:name>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
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+ <spirit:name>HWDATA_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
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+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_sysio</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_expram_l</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
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+ <spirit:port>
+ <spirit:name>HTRANS_expram_l</spirit:name>
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+ </spirit:port>
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+ <spirit:wire>
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+ <spirit:name>HWDATA_expram_h</spirit:name>
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+ <spirit:name>HREADYMUX_expram_h</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
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+ <spirit:name>HWRITE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
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+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
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+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_systable</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_socdebug</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for nanosoc_busmatrix_lite</spirit:description>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_busmatrix.v</spirit:name>
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+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_inititator_input.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
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+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
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+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
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+ </spirit:file>
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+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>nanosoc_busmatrix_lite</spirit:description>
+
+</spirit:component>
diff --git a/system/src/nanosoc_busmatrix/logs/nanosoc.log b/system/src/nanosoc_busmatrix/logs/nanosoc.log
new file mode 100644
index 0000000000000000000000000000000000000000..e2affe3e8f623e89e5f061e85797a8c6a3b560f5
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/logs/nanosoc.log
@@ -0,0 +1,102 @@
+
+==============================================================
+= The confidential and proprietary information contained in this file may
+= only be used by a person authorised under and to the extent permitted
+= by a subsisting licensing agreement from Arm Limited or its affiliates.
+=
+= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
+= ALL RIGHTS RESERVED
+=
+= This entire notice must be reproduced on all copies of this file
+= and copies of this file may only be made by a person if such person is
+= permitted to do so under the terms of a subsisting license agreement
+= from Arm Limited or its affiliates.
+=
+= BuildBusMatrix.pl
+=
+= Run Date : 03/06/2023 21:57:27
+==============================================================
+
+Script accepted the following parameters:
+
+ - Configuration file : '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/xml/nanosoc.xml'
+ - Top-level name : 'nanosoc_busmatrix'
+ - Slave interfaces : 4
+ - Master interfaces : 8
+ - Architecture type : 'ahb2'
+ - Arbitration scheme : 'burst'
+ - Address map : user defined
+ - Connectivity mapping : _socdebug -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h, _systable,
+ _dma_0 -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h,
+ _dma_1 -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h,
+ _cpu -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h, _systable
+ - Connectivity type : sparse
+ - Routing data width : 32
+ - Routing address width : 32
+ - User signal width : 0
+ - Timescales : no
+ - Configuration directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog'
+ - Source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/verilog/src'
+ - IPXact target directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/ipxact'
+ - IPXact source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/ipxact/src'
+ - Overwrite mode : enabled
+
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_bootrom.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_exp.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_h.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_l.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_imem.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_sysio.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_systable.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_cpu.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_0.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_1.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_socshute.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_bootrom.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_dmem.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_h.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_l.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_imem.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_sysio.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v' file...
+
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/src/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml' file...
+
+Creating the bus matrix variant...
+
+ - Rendering 'nanosoc_arbiter_imem.v'
+ - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_matrix_decode_dma_0.v'
+ - Rendering 'nanosoc_arbiter_sysio.v'
+ - Rendering 'nanosoc_arbiter_bootrom.v'
+ - Rendering 'nanosoc_busmatrix.v'
+ - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_matrix_decode_dma_1.v'
+ - Rendering 'nanosoc_target_output_expram_h.v'
+ - Rendering 'nanosoc_arbiter_exp.v'
+ - Rendering 'nanosoc_arbiter_expram_l.v'
+ - Rendering 'nanosoc_target_output_systable.v'
+ - Rendering 'nanosoc_target_output_sysio.v'
+ - Rendering 'nanosoc_matrix_decode_cpu.v'
+ - Rendering 'nanosoc_arbiter_systable.v'
+ - Rendering 'nanosoc_target_output_exp.v'
+ - Rendering 'nanosoc_matrix_decode_socdebug.v'
+ - Rendering 'nanosoc_target_output_expram_l.v'
+ - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_busmatrix_lite.xml'
+ - Rendering 'nanosoc_arbiter_dmem.v'
+ - Rendering 'nanosoc_inititator_input.v'
+ - Rendering 'nanosoc_target_output_dmem.v'
+ - Rendering 'nanosoc_arbiter_expram_h.v'
+ - Rendering 'nanosoc_target_output_imem.v'
+ - Rendering 'nanosoc_target_output_bootrom.v'
+
+Done!
+
diff --git a/system/src/nanosoc_ahb_busmatrix/makefile b/system/src/nanosoc_busmatrix/makefile
similarity index 93%
rename from system/src/nanosoc_ahb_busmatrix/makefile
rename to system/src/nanosoc_busmatrix/makefile
index 5d6a83e330d2aa6130e73d790b93bb42ce02b88c..24b95e66b64344d9ee400581831de160118de4d6 100644
--- a/system/src/nanosoc_ahb_busmatrix/makefile
+++ b/system/src/nanosoc_busmatrix/makefile
@@ -12,10 +12,10 @@
.DEFAULT_GOAL := build
# Name of Bus Matrix to generate
-MATRIX_NAME ?= nanosoc_ahb32_4x7
+MATRIX_NAME ?= nanosoc
# Top-level directory of Bus Matrix
-BUILD_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix
+BUILD_DIR ?= $(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_busmatrix
# Directory location of BuildBusMatrix Script
SOURCE_DIR = $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_busmatrix
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_bootrom.v
similarity index 99%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_bootrom.v
index 9480d052f3d4b93584d1452b5c15503e652fbaa4..1bff1c888bd2eee25156535716b533a2038f6de2 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_bootrom.v
@@ -26,13 +26,13 @@
// of the input stages will be given access to the
// shared slave.
//
-// Notes : The bus matrix has full connectivity.
+// Notes : The bus matrix has sparse connectivity.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_arbiter (
+module nanosoc_arbiter_bootrom (
// Common AHB signals
HCLK ,
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v
new file mode 100644
index 0000000000000000000000000000000000000000..a7a2f62924d74780951965ec3b8e52bfe04afadf
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_dmem.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_dmem (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_exp.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_exp.v
new file mode 100644
index 0000000000000000000000000000000000000000..76af6da662b50a01c5fbe34f669518c20640858b
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_exp.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_exp (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_h.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_h.v
new file mode 100644
index 0000000000000000000000000000000000000000..0079998239ea1139fef8b2f79337a832e6246590
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_h.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_expram_h (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_l.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_l.v
new file mode 100644
index 0000000000000000000000000000000000000000..5dacc6c05fabb76b7ef9fd9dd6a8f75b6d8c4360
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_expram_l.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_expram_l (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_imem.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_imem.v
new file mode 100644
index 0000000000000000000000000000000000000000..271e90272f4e2191f6c2642e80009dc355f0a59a
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_imem.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_imem (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_sysio.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_sysio.v
new file mode 100644
index 0000000000000000000000000000000000000000..6af8977e2ed9c157c828d24e7743c062a6b54ea7
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_sysio.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_sysio (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_systable.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_systable.v
new file mode 100644
index 0000000000000000000000000000000000000000..64e34e0b8e5eb3fa90df3594a061bb698f8c566e
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_systable.v
@@ -0,0 +1,314 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_systable (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
similarity index 53%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index 610aa3f1565656a407abfdf4e4f3ed84219c2c67..490243aba00d3c1c743f2f0398a9b534c0ceb25f 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -30,20 +30,22 @@
//
// - Architecture type 'ahb2',
// - 4 slave ports (connecting to masters),
-// - 7 master ports (connecting to slaves),
+// - 8 master ports (connecting to slaves),
// - Routing address width of 32 bits,
// - Routing data width of 32 bits,
-// - xUSER signal width of 2 bits,
// - Arbiter type 'burst',
// - Connectivity mapping:
-// S<0..3> -> M<0..6>,
-// - Connectivity type 'full'.
+// _socdebug -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h, _systable,
+// _dma_0 -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h,
+// _dma_1 -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h,
+// _cpu -> _bootrom, _imem, _dmem, _sysio, _exp, _expram_l, _expram_h, _systable,
+// - Connectivity type 'sparse'.
//
//------------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_busmatrix (
+module nanosoc_busmatrix (
// Common AHB signals
HCLK,
@@ -53,49 +55,43 @@ module nanosoc_ahb32_4x7_busmatrix (
REMAP,
// Input port SI0 (inputs from master 0)
- HSEL_adp,
- HADDR_adp,
- HTRANS_adp,
- HWRITE_adp,
- HSIZE_adp,
- HBURST_adp,
- HPROT_adp,
- HMASTER_adp,
- HWDATA_adp,
- HMASTLOCK_adp,
- HREADY_adp,
- HAUSER_adp,
- HWUSER_adp,
+ HSEL_socdebug,
+ HADDR_socdebug,
+ HTRANS_socdebug,
+ HWRITE_socdebug,
+ HSIZE_socdebug,
+ HBURST_socdebug,
+ HPROT_socdebug,
+ HMASTER_socdebug,
+ HWDATA_socdebug,
+ HMASTLOCK_socdebug,
+ HREADY_socdebug,
// Input port SI1 (inputs from master 1)
- HSEL_dma,
- HADDR_dma,
- HTRANS_dma,
- HWRITE_dma,
- HSIZE_dma,
- HBURST_dma,
- HPROT_dma,
- HMASTER_dma,
- HWDATA_dma,
- HMASTLOCK_dma,
- HREADY_dma,
- HAUSER_dma,
- HWUSER_dma,
+ HSEL_dma_0,
+ HADDR_dma_0,
+ HTRANS_dma_0,
+ HWRITE_dma_0,
+ HSIZE_dma_0,
+ HBURST_dma_0,
+ HPROT_dma_0,
+ HMASTER_dma_0,
+ HWDATA_dma_0,
+ HMASTLOCK_dma_0,
+ HREADY_dma_0,
// Input port SI2 (inputs from master 2)
- HSEL_dma2,
- HADDR_dma2,
- HTRANS_dma2,
- HWRITE_dma2,
- HSIZE_dma2,
- HBURST_dma2,
- HPROT_dma2,
- HMASTER_dma2,
- HWDATA_dma2,
- HMASTLOCK_dma2,
- HREADY_dma2,
- HAUSER_dma2,
- HWUSER_dma2,
+ HSEL_dma_1,
+ HADDR_dma_1,
+ HTRANS_dma_1,
+ HWRITE_dma_1,
+ HSIZE_dma_1,
+ HBURST_dma_1,
+ HPROT_dma_1,
+ HMASTER_dma_1,
+ HWDATA_dma_1,
+ HMASTLOCK_dma_1,
+ HREADY_dma_1,
// Input port SI3 (inputs from master 3)
HSEL_cpu,
@@ -109,50 +105,46 @@ module nanosoc_ahb32_4x7_busmatrix (
HWDATA_cpu,
HMASTLOCK_cpu,
HREADY_cpu,
- HAUSER_cpu,
- HWUSER_cpu,
// Output port MI0 (inputs from slave 0)
- HRDATA_rom1,
- HREADYOUT_rom1,
- HRESP_rom1,
- HRUSER_rom1,
+ HRDATA_bootrom,
+ HREADYOUT_bootrom,
+ HRESP_bootrom,
// Output port MI1 (inputs from slave 1)
- HRDATA_ram2,
- HREADYOUT_ram2,
- HRESP_ram2,
- HRUSER_ram2,
+ HRDATA_imem,
+ HREADYOUT_imem,
+ HRESP_imem,
// Output port MI2 (inputs from slave 2)
- HRDATA_ram3,
- HREADYOUT_ram3,
- HRESP_ram3,
- HRUSER_ram3,
+ HRDATA_dmem,
+ HREADYOUT_dmem,
+ HRESP_dmem,
// Output port MI3 (inputs from slave 3)
- HRDATA_sys,
- HREADYOUT_sys,
- HRESP_sys,
- HRUSER_sys,
+ HRDATA_sysio,
+ HREADYOUT_sysio,
+ HRESP_sysio,
// Output port MI4 (inputs from slave 4)
- HRDATA_ram8,
- HREADYOUT_ram8,
- HRESP_ram8,
- HRUSER_ram8,
+ HRDATA_expram_l,
+ HREADYOUT_expram_l,
+ HRESP_expram_l,
// Output port MI5 (inputs from slave 5)
- HRDATA_ram9,
- HREADYOUT_ram9,
- HRESP_ram9,
- HRUSER_ram9,
+ HRDATA_expram_h,
+ HREADYOUT_expram_h,
+ HRESP_expram_h,
// Output port MI6 (inputs from slave 6)
HRDATA_exp,
HREADYOUT_exp,
HRESP_exp,
- HRUSER_exp,
+
+ // Output port MI7 (inputs from slave 7)
+ HRDATA_systable,
+ HREADYOUT_systable,
+ HRESP_systable,
// Scan test dummy signals; not connected until scan insertion
SCANENABLE, // Scan Test Mode Enable
@@ -160,94 +152,82 @@ module nanosoc_ahb32_4x7_busmatrix (
// Output port MI0 (outputs to slave 0)
- HSEL_rom1,
- HADDR_rom1,
- HTRANS_rom1,
- HWRITE_rom1,
- HSIZE_rom1,
- HBURST_rom1,
- HPROT_rom1,
- HMASTER_rom1,
- HWDATA_rom1,
- HMASTLOCK_rom1,
- HREADYMUX_rom1,
- HAUSER_rom1,
- HWUSER_rom1,
+ HSEL_bootrom,
+ HADDR_bootrom,
+ HTRANS_bootrom,
+ HWRITE_bootrom,
+ HSIZE_bootrom,
+ HBURST_bootrom,
+ HPROT_bootrom,
+ HMASTER_bootrom,
+ HWDATA_bootrom,
+ HMASTLOCK_bootrom,
+ HREADYMUX_bootrom,
// Output port MI1 (outputs to slave 1)
- HSEL_ram2,
- HADDR_ram2,
- HTRANS_ram2,
- HWRITE_ram2,
- HSIZE_ram2,
- HBURST_ram2,
- HPROT_ram2,
- HMASTER_ram2,
- HWDATA_ram2,
- HMASTLOCK_ram2,
- HREADYMUX_ram2,
- HAUSER_ram2,
- HWUSER_ram2,
+ HSEL_imem,
+ HADDR_imem,
+ HTRANS_imem,
+ HWRITE_imem,
+ HSIZE_imem,
+ HBURST_imem,
+ HPROT_imem,
+ HMASTER_imem,
+ HWDATA_imem,
+ HMASTLOCK_imem,
+ HREADYMUX_imem,
// Output port MI2 (outputs to slave 2)
- HSEL_ram3,
- HADDR_ram3,
- HTRANS_ram3,
- HWRITE_ram3,
- HSIZE_ram3,
- HBURST_ram3,
- HPROT_ram3,
- HMASTER_ram3,
- HWDATA_ram3,
- HMASTLOCK_ram3,
- HREADYMUX_ram3,
- HAUSER_ram3,
- HWUSER_ram3,
+ HSEL_dmem,
+ HADDR_dmem,
+ HTRANS_dmem,
+ HWRITE_dmem,
+ HSIZE_dmem,
+ HBURST_dmem,
+ HPROT_dmem,
+ HMASTER_dmem,
+ HWDATA_dmem,
+ HMASTLOCK_dmem,
+ HREADYMUX_dmem,
// Output port MI3 (outputs to slave 3)
- HSEL_sys,
- HADDR_sys,
- HTRANS_sys,
- HWRITE_sys,
- HSIZE_sys,
- HBURST_sys,
- HPROT_sys,
- HMASTER_sys,
- HWDATA_sys,
- HMASTLOCK_sys,
- HREADYMUX_sys,
- HAUSER_sys,
- HWUSER_sys,
+ HSEL_sysio,
+ HADDR_sysio,
+ HTRANS_sysio,
+ HWRITE_sysio,
+ HSIZE_sysio,
+ HBURST_sysio,
+ HPROT_sysio,
+ HMASTER_sysio,
+ HWDATA_sysio,
+ HMASTLOCK_sysio,
+ HREADYMUX_sysio,
// Output port MI4 (outputs to slave 4)
- HSEL_ram8,
- HADDR_ram8,
- HTRANS_ram8,
- HWRITE_ram8,
- HSIZE_ram8,
- HBURST_ram8,
- HPROT_ram8,
- HMASTER_ram8,
- HWDATA_ram8,
- HMASTLOCK_ram8,
- HREADYMUX_ram8,
- HAUSER_ram8,
- HWUSER_ram8,
+ HSEL_expram_l,
+ HADDR_expram_l,
+ HTRANS_expram_l,
+ HWRITE_expram_l,
+ HSIZE_expram_l,
+ HBURST_expram_l,
+ HPROT_expram_l,
+ HMASTER_expram_l,
+ HWDATA_expram_l,
+ HMASTLOCK_expram_l,
+ HREADYMUX_expram_l,
// Output port MI5 (outputs to slave 5)
- HSEL_ram9,
- HADDR_ram9,
- HTRANS_ram9,
- HWRITE_ram9,
- HSIZE_ram9,
- HBURST_ram9,
- HPROT_ram9,
- HMASTER_ram9,
- HWDATA_ram9,
- HMASTLOCK_ram9,
- HREADYMUX_ram9,
- HAUSER_ram9,
- HWUSER_ram9,
+ HSEL_expram_h,
+ HADDR_expram_h,
+ HTRANS_expram_h,
+ HWRITE_expram_h,
+ HSIZE_expram_h,
+ HBURST_expram_h,
+ HPROT_expram_h,
+ HMASTER_expram_h,
+ HWDATA_expram_h,
+ HMASTLOCK_expram_h,
+ HREADYMUX_expram_h,
// Output port MI6 (outputs to slave 6)
HSEL_exp,
@@ -261,32 +241,39 @@ module nanosoc_ahb32_4x7_busmatrix (
HWDATA_exp,
HMASTLOCK_exp,
HREADYMUX_exp,
- HAUSER_exp,
- HWUSER_exp,
+
+ // Output port MI7 (outputs to slave 7)
+ HSEL_systable,
+ HADDR_systable,
+ HTRANS_systable,
+ HWRITE_systable,
+ HSIZE_systable,
+ HBURST_systable,
+ HPROT_systable,
+ HMASTER_systable,
+ HWDATA_systable,
+ HMASTLOCK_systable,
+ HREADYMUX_systable,
// Input port SI0 (outputs to master 0)
- HRDATA_adp,
- HREADYOUT_adp,
- HRESP_adp,
- HRUSER_adp,
+ HRDATA_socdebug,
+ HREADYOUT_socdebug,
+ HRESP_socdebug,
// Input port SI1 (outputs to master 1)
- HRDATA_dma,
- HREADYOUT_dma,
- HRESP_dma,
- HRUSER_dma,
+ HRDATA_dma_0,
+ HREADYOUT_dma_0,
+ HRESP_dma_0,
// Input port SI2 (outputs to master 2)
- HRDATA_dma2,
- HREADYOUT_dma2,
- HRESP_dma2,
- HRUSER_dma2,
+ HRDATA_dma_1,
+ HREADYOUT_dma_1,
+ HRESP_dma_1,
// Input port SI3 (outputs to master 3)
HRDATA_cpu,
HREADYOUT_cpu,
HRESP_cpu,
- HRUSER_cpu,
// Scan test dummy signals; not connected until scan insertion
SCANOUTHCLK // Scan Chain Output
@@ -306,49 +293,43 @@ module nanosoc_ahb32_4x7_busmatrix (
input [3:0] REMAP; // REMAP input
// Input port SI0 (inputs from master 0)
- input HSEL_adp; // Slave Select
- input [31:0] HADDR_adp; // Address bus
- input [1:0] HTRANS_adp; // Transfer type
- input HWRITE_adp; // Transfer direction
- input [2:0] HSIZE_adp; // Transfer size
- input [2:0] HBURST_adp; // Burst type
- input [3:0] HPROT_adp; // Protection control
- input [3:0] HMASTER_adp; // Master select
- input [31:0] HWDATA_adp; // Write data
- input HMASTLOCK_adp; // Locked Sequence
- input HREADY_adp; // Transfer done
- input [1:0] HAUSER_adp; // Address USER signals
- input [1:0] HWUSER_adp; // Write-data USER signals
+ input HSEL_socdebug; // Slave Select
+ input [31:0] HADDR_socdebug; // Address bus
+ input [1:0] HTRANS_socdebug; // Transfer type
+ input HWRITE_socdebug; // Transfer direction
+ input [2:0] HSIZE_socdebug; // Transfer size
+ input [2:0] HBURST_socdebug; // Burst type
+ input [3:0] HPROT_socdebug; // Protection control
+ input [3:0] HMASTER_socdebug; // Master select
+ input [31:0] HWDATA_socdebug; // Write data
+ input HMASTLOCK_socdebug; // Locked Sequence
+ input HREADY_socdebug; // Transfer done
// Input port SI1 (inputs from master 1)
- input HSEL_dma; // Slave Select
- input [31:0] HADDR_dma; // Address bus
- input [1:0] HTRANS_dma; // Transfer type
- input HWRITE_dma; // Transfer direction
- input [2:0] HSIZE_dma; // Transfer size
- input [2:0] HBURST_dma; // Burst type
- input [3:0] HPROT_dma; // Protection control
- input [3:0] HMASTER_dma; // Master select
- input [31:0] HWDATA_dma; // Write data
- input HMASTLOCK_dma; // Locked Sequence
- input HREADY_dma; // Transfer done
- input [1:0] HAUSER_dma; // Address USER signals
- input [1:0] HWUSER_dma; // Write-data USER signals
+ input HSEL_dma_0; // Slave Select
+ input [31:0] HADDR_dma_0; // Address bus
+ input [1:0] HTRANS_dma_0; // Transfer type
+ input HWRITE_dma_0; // Transfer direction
+ input [2:0] HSIZE_dma_0; // Transfer size
+ input [2:0] HBURST_dma_0; // Burst type
+ input [3:0] HPROT_dma_0; // Protection control
+ input [3:0] HMASTER_dma_0; // Master select
+ input [31:0] HWDATA_dma_0; // Write data
+ input HMASTLOCK_dma_0; // Locked Sequence
+ input HREADY_dma_0; // Transfer done
// Input port SI2 (inputs from master 2)
- input HSEL_dma2; // Slave Select
- input [31:0] HADDR_dma2; // Address bus
- input [1:0] HTRANS_dma2; // Transfer type
- input HWRITE_dma2; // Transfer direction
- input [2:0] HSIZE_dma2; // Transfer size
- input [2:0] HBURST_dma2; // Burst type
- input [3:0] HPROT_dma2; // Protection control
- input [3:0] HMASTER_dma2; // Master select
- input [31:0] HWDATA_dma2; // Write data
- input HMASTLOCK_dma2; // Locked Sequence
- input HREADY_dma2; // Transfer done
- input [1:0] HAUSER_dma2; // Address USER signals
- input [1:0] HWUSER_dma2; // Write-data USER signals
+ input HSEL_dma_1; // Slave Select
+ input [31:0] HADDR_dma_1; // Address bus
+ input [1:0] HTRANS_dma_1; // Transfer type
+ input HWRITE_dma_1; // Transfer direction
+ input [2:0] HSIZE_dma_1; // Transfer size
+ input [2:0] HBURST_dma_1; // Burst type
+ input [3:0] HPROT_dma_1; // Protection control
+ input [3:0] HMASTER_dma_1; // Master select
+ input [31:0] HWDATA_dma_1; // Write data
+ input HMASTLOCK_dma_1; // Locked Sequence
+ input HREADY_dma_1; // Transfer done
// Input port SI3 (inputs from master 3)
input HSEL_cpu; // Slave Select
@@ -362,50 +343,46 @@ module nanosoc_ahb32_4x7_busmatrix (
input [31:0] HWDATA_cpu; // Write data
input HMASTLOCK_cpu; // Locked Sequence
input HREADY_cpu; // Transfer done
- input [1:0] HAUSER_cpu; // Address USER signals
- input [1:0] HWUSER_cpu; // Write-data USER signals
// Output port MI0 (inputs from slave 0)
- input [31:0] HRDATA_rom1; // Read data bus
- input HREADYOUT_rom1; // HREADY feedback
- input [1:0] HRESP_rom1; // Transfer response
- input [1:0] HRUSER_rom1; // Read-data USER signals
+ input [31:0] HRDATA_bootrom; // Read data bus
+ input HREADYOUT_bootrom; // HREADY feedback
+ input [1:0] HRESP_bootrom; // Transfer response
// Output port MI1 (inputs from slave 1)
- input [31:0] HRDATA_ram2; // Read data bus
- input HREADYOUT_ram2; // HREADY feedback
- input [1:0] HRESP_ram2; // Transfer response
- input [1:0] HRUSER_ram2; // Read-data USER signals
+ input [31:0] HRDATA_imem; // Read data bus
+ input HREADYOUT_imem; // HREADY feedback
+ input [1:0] HRESP_imem; // Transfer response
// Output port MI2 (inputs from slave 2)
- input [31:0] HRDATA_ram3; // Read data bus
- input HREADYOUT_ram3; // HREADY feedback
- input [1:0] HRESP_ram3; // Transfer response
- input [1:0] HRUSER_ram3; // Read-data USER signals
+ input [31:0] HRDATA_dmem; // Read data bus
+ input HREADYOUT_dmem; // HREADY feedback
+ input [1:0] HRESP_dmem; // Transfer response
// Output port MI3 (inputs from slave 3)
- input [31:0] HRDATA_sys; // Read data bus
- input HREADYOUT_sys; // HREADY feedback
- input [1:0] HRESP_sys; // Transfer response
- input [1:0] HRUSER_sys; // Read-data USER signals
+ input [31:0] HRDATA_sysio; // Read data bus
+ input HREADYOUT_sysio; // HREADY feedback
+ input [1:0] HRESP_sysio; // Transfer response
// Output port MI4 (inputs from slave 4)
- input [31:0] HRDATA_ram8; // Read data bus
- input HREADYOUT_ram8; // HREADY feedback
- input [1:0] HRESP_ram8; // Transfer response
- input [1:0] HRUSER_ram8; // Read-data USER signals
+ input [31:0] HRDATA_expram_l; // Read data bus
+ input HREADYOUT_expram_l; // HREADY feedback
+ input [1:0] HRESP_expram_l; // Transfer response
// Output port MI5 (inputs from slave 5)
- input [31:0] HRDATA_ram9; // Read data bus
- input HREADYOUT_ram9; // HREADY feedback
- input [1:0] HRESP_ram9; // Transfer response
- input [1:0] HRUSER_ram9; // Read-data USER signals
+ input [31:0] HRDATA_expram_h; // Read data bus
+ input HREADYOUT_expram_h; // HREADY feedback
+ input [1:0] HRESP_expram_h; // Transfer response
// Output port MI6 (inputs from slave 6)
input [31:0] HRDATA_exp; // Read data bus
input HREADYOUT_exp; // HREADY feedback
input [1:0] HRESP_exp; // Transfer response
- input [1:0] HRUSER_exp; // Read-data USER signals
+
+ // Output port MI7 (inputs from slave 7)
+ input [31:0] HRDATA_systable; // Read data bus
+ input HREADYOUT_systable; // HREADY feedback
+ input [1:0] HRESP_systable; // Transfer response
// Scan test dummy signals; not connected until scan insertion
input SCANENABLE; // Scan enable signal
@@ -413,94 +390,82 @@ module nanosoc_ahb32_4x7_busmatrix (
// Output port MI0 (outputs to slave 0)
- output HSEL_rom1; // Slave Select
- output [31:0] HADDR_rom1; // Address bus
- output [1:0] HTRANS_rom1; // Transfer type
- output HWRITE_rom1; // Transfer direction
- output [2:0] HSIZE_rom1; // Transfer size
- output [2:0] HBURST_rom1; // Burst type
- output [3:0] HPROT_rom1; // Protection control
- output [3:0] HMASTER_rom1; // Master select
- output [31:0] HWDATA_rom1; // Write data
- output HMASTLOCK_rom1; // Locked Sequence
- output HREADYMUX_rom1; // Transfer done
- output [1:0] HAUSER_rom1; // Address USER signals
- output [1:0] HWUSER_rom1; // Write-data USER signals
+ output HSEL_bootrom; // Slave Select
+ output [31:0] HADDR_bootrom; // Address bus
+ output [1:0] HTRANS_bootrom; // Transfer type
+ output HWRITE_bootrom; // Transfer direction
+ output [2:0] HSIZE_bootrom; // Transfer size
+ output [2:0] HBURST_bootrom; // Burst type
+ output [3:0] HPROT_bootrom; // Protection control
+ output [3:0] HMASTER_bootrom; // Master select
+ output [31:0] HWDATA_bootrom; // Write data
+ output HMASTLOCK_bootrom; // Locked Sequence
+ output HREADYMUX_bootrom; // Transfer done
// Output port MI1 (outputs to slave 1)
- output HSEL_ram2; // Slave Select
- output [31:0] HADDR_ram2; // Address bus
- output [1:0] HTRANS_ram2; // Transfer type
- output HWRITE_ram2; // Transfer direction
- output [2:0] HSIZE_ram2; // Transfer size
- output [2:0] HBURST_ram2; // Burst type
- output [3:0] HPROT_ram2; // Protection control
- output [3:0] HMASTER_ram2; // Master select
- output [31:0] HWDATA_ram2; // Write data
- output HMASTLOCK_ram2; // Locked Sequence
- output HREADYMUX_ram2; // Transfer done
- output [1:0] HAUSER_ram2; // Address USER signals
- output [1:0] HWUSER_ram2; // Write-data USER signals
+ output HSEL_imem; // Slave Select
+ output [31:0] HADDR_imem; // Address bus
+ output [1:0] HTRANS_imem; // Transfer type
+ output HWRITE_imem; // Transfer direction
+ output [2:0] HSIZE_imem; // Transfer size
+ output [2:0] HBURST_imem; // Burst type
+ output [3:0] HPROT_imem; // Protection control
+ output [3:0] HMASTER_imem; // Master select
+ output [31:0] HWDATA_imem; // Write data
+ output HMASTLOCK_imem; // Locked Sequence
+ output HREADYMUX_imem; // Transfer done
// Output port MI2 (outputs to slave 2)
- output HSEL_ram3; // Slave Select
- output [31:0] HADDR_ram3; // Address bus
- output [1:0] HTRANS_ram3; // Transfer type
- output HWRITE_ram3; // Transfer direction
- output [2:0] HSIZE_ram3; // Transfer size
- output [2:0] HBURST_ram3; // Burst type
- output [3:0] HPROT_ram3; // Protection control
- output [3:0] HMASTER_ram3; // Master select
- output [31:0] HWDATA_ram3; // Write data
- output HMASTLOCK_ram3; // Locked Sequence
- output HREADYMUX_ram3; // Transfer done
- output [1:0] HAUSER_ram3; // Address USER signals
- output [1:0] HWUSER_ram3; // Write-data USER signals
+ output HSEL_dmem; // Slave Select
+ output [31:0] HADDR_dmem; // Address bus
+ output [1:0] HTRANS_dmem; // Transfer type
+ output HWRITE_dmem; // Transfer direction
+ output [2:0] HSIZE_dmem; // Transfer size
+ output [2:0] HBURST_dmem; // Burst type
+ output [3:0] HPROT_dmem; // Protection control
+ output [3:0] HMASTER_dmem; // Master select
+ output [31:0] HWDATA_dmem; // Write data
+ output HMASTLOCK_dmem; // Locked Sequence
+ output HREADYMUX_dmem; // Transfer done
// Output port MI3 (outputs to slave 3)
- output HSEL_sys; // Slave Select
- output [31:0] HADDR_sys; // Address bus
- output [1:0] HTRANS_sys; // Transfer type
- output HWRITE_sys; // Transfer direction
- output [2:0] HSIZE_sys; // Transfer size
- output [2:0] HBURST_sys; // Burst type
- output [3:0] HPROT_sys; // Protection control
- output [3:0] HMASTER_sys; // Master select
- output [31:0] HWDATA_sys; // Write data
- output HMASTLOCK_sys; // Locked Sequence
- output HREADYMUX_sys; // Transfer done
- output [1:0] HAUSER_sys; // Address USER signals
- output [1:0] HWUSER_sys; // Write-data USER signals
+ output HSEL_sysio; // Slave Select
+ output [31:0] HADDR_sysio; // Address bus
+ output [1:0] HTRANS_sysio; // Transfer type
+ output HWRITE_sysio; // Transfer direction
+ output [2:0] HSIZE_sysio; // Transfer size
+ output [2:0] HBURST_sysio; // Burst type
+ output [3:0] HPROT_sysio; // Protection control
+ output [3:0] HMASTER_sysio; // Master select
+ output [31:0] HWDATA_sysio; // Write data
+ output HMASTLOCK_sysio; // Locked Sequence
+ output HREADYMUX_sysio; // Transfer done
// Output port MI4 (outputs to slave 4)
- output HSEL_ram8; // Slave Select
- output [31:0] HADDR_ram8; // Address bus
- output [1:0] HTRANS_ram8; // Transfer type
- output HWRITE_ram8; // Transfer direction
- output [2:0] HSIZE_ram8; // Transfer size
- output [2:0] HBURST_ram8; // Burst type
- output [3:0] HPROT_ram8; // Protection control
- output [3:0] HMASTER_ram8; // Master select
- output [31:0] HWDATA_ram8; // Write data
- output HMASTLOCK_ram8; // Locked Sequence
- output HREADYMUX_ram8; // Transfer done
- output [1:0] HAUSER_ram8; // Address USER signals
- output [1:0] HWUSER_ram8; // Write-data USER signals
+ output HSEL_expram_l; // Slave Select
+ output [31:0] HADDR_expram_l; // Address bus
+ output [1:0] HTRANS_expram_l; // Transfer type
+ output HWRITE_expram_l; // Transfer direction
+ output [2:0] HSIZE_expram_l; // Transfer size
+ output [2:0] HBURST_expram_l; // Burst type
+ output [3:0] HPROT_expram_l; // Protection control
+ output [3:0] HMASTER_expram_l; // Master select
+ output [31:0] HWDATA_expram_l; // Write data
+ output HMASTLOCK_expram_l; // Locked Sequence
+ output HREADYMUX_expram_l; // Transfer done
// Output port MI5 (outputs to slave 5)
- output HSEL_ram9; // Slave Select
- output [31:0] HADDR_ram9; // Address bus
- output [1:0] HTRANS_ram9; // Transfer type
- output HWRITE_ram9; // Transfer direction
- output [2:0] HSIZE_ram9; // Transfer size
- output [2:0] HBURST_ram9; // Burst type
- output [3:0] HPROT_ram9; // Protection control
- output [3:0] HMASTER_ram9; // Master select
- output [31:0] HWDATA_ram9; // Write data
- output HMASTLOCK_ram9; // Locked Sequence
- output HREADYMUX_ram9; // Transfer done
- output [1:0] HAUSER_ram9; // Address USER signals
- output [1:0] HWUSER_ram9; // Write-data USER signals
+ output HSEL_expram_h; // Slave Select
+ output [31:0] HADDR_expram_h; // Address bus
+ output [1:0] HTRANS_expram_h; // Transfer type
+ output HWRITE_expram_h; // Transfer direction
+ output [2:0] HSIZE_expram_h; // Transfer size
+ output [2:0] HBURST_expram_h; // Burst type
+ output [3:0] HPROT_expram_h; // Protection control
+ output [3:0] HMASTER_expram_h; // Master select
+ output [31:0] HWDATA_expram_h; // Write data
+ output HMASTLOCK_expram_h; // Locked Sequence
+ output HREADYMUX_expram_h; // Transfer done
// Output port MI6 (outputs to slave 6)
output HSEL_exp; // Slave Select
@@ -514,32 +479,39 @@ module nanosoc_ahb32_4x7_busmatrix (
output [31:0] HWDATA_exp; // Write data
output HMASTLOCK_exp; // Locked Sequence
output HREADYMUX_exp; // Transfer done
- output [1:0] HAUSER_exp; // Address USER signals
- output [1:0] HWUSER_exp; // Write-data USER signals
+
+ // Output port MI7 (outputs to slave 7)
+ output HSEL_systable; // Slave Select
+ output [31:0] HADDR_systable; // Address bus
+ output [1:0] HTRANS_systable; // Transfer type
+ output HWRITE_systable; // Transfer direction
+ output [2:0] HSIZE_systable; // Transfer size
+ output [2:0] HBURST_systable; // Burst type
+ output [3:0] HPROT_systable; // Protection control
+ output [3:0] HMASTER_systable; // Master select
+ output [31:0] HWDATA_systable; // Write data
+ output HMASTLOCK_systable; // Locked Sequence
+ output HREADYMUX_systable; // Transfer done
// Input port SI0 (outputs to master 0)
- output [31:0] HRDATA_adp; // Read data bus
- output HREADYOUT_adp; // HREADY feedback
- output [1:0] HRESP_adp; // Transfer response
- output [1:0] HRUSER_adp; // Read-data USER signals
+ output [31:0] HRDATA_socdebug; // Read data bus
+ output HREADYOUT_socdebug; // HREADY feedback
+ output [1:0] HRESP_socdebug; // Transfer response
// Input port SI1 (outputs to master 1)
- output [31:0] HRDATA_dma; // Read data bus
- output HREADYOUT_dma; // HREADY feedback
- output [1:0] HRESP_dma; // Transfer response
- output [1:0] HRUSER_dma; // Read-data USER signals
+ output [31:0] HRDATA_dma_0; // Read data bus
+ output HREADYOUT_dma_0; // HREADY feedback
+ output [1:0] HRESP_dma_0; // Transfer response
// Input port SI2 (outputs to master 2)
- output [31:0] HRDATA_dma2; // Read data bus
- output HREADYOUT_dma2; // HREADY feedback
- output [1:0] HRESP_dma2; // Transfer response
- output [1:0] HRUSER_dma2; // Read-data USER signals
+ output [31:0] HRDATA_dma_1; // Read data bus
+ output HREADYOUT_dma_1; // HREADY feedback
+ output [1:0] HRESP_dma_1; // Transfer response
// Input port SI3 (outputs to master 3)
output [31:0] HRDATA_cpu; // Read data bus
output HREADYOUT_cpu; // HREADY feedback
output [1:0] HRESP_cpu; // Transfer response
- output [1:0] HRUSER_cpu; // Read-data USER signals
// Scan test dummy signals; not connected until scan insertion
output SCANOUTHCLK; // Scan Chain Output
@@ -557,64 +529,55 @@ module nanosoc_ahb32_4x7_busmatrix (
wire [3:0] REMAP; // REMAP signal
// Input Port SI0
- wire HSEL_adp; // Slave Select
- wire [31:0] HADDR_adp; // Address bus
- wire [1:0] HTRANS_adp; // Transfer type
- wire HWRITE_adp; // Transfer direction
- wire [2:0] HSIZE_adp; // Transfer size
- wire [2:0] HBURST_adp; // Burst type
- wire [3:0] HPROT_adp; // Protection control
- wire [3:0] HMASTER_adp; // Master select
- wire [31:0] HWDATA_adp; // Write data
- wire HMASTLOCK_adp; // Locked Sequence
- wire HREADY_adp; // Transfer done
-
- wire [31:0] HRDATA_adp; // Read data bus
- wire HREADYOUT_adp; // HREADY feedback
- wire [1:0] HRESP_adp; // Transfer response
- wire [1:0] HAUSER_adp; // Address USER signals
- wire [1:0] HWUSER_adp; // Write-data USER signals
- wire [1:0] HRUSER_adp; // Read-data USER signals
+ wire HSEL_socdebug; // Slave Select
+ wire [31:0] HADDR_socdebug; // Address bus
+ wire [1:0] HTRANS_socdebug; // Transfer type
+ wire HWRITE_socdebug; // Transfer direction
+ wire [2:0] HSIZE_socdebug; // Transfer size
+ wire [2:0] HBURST_socdebug; // Burst type
+ wire [3:0] HPROT_socdebug; // Protection control
+ wire [3:0] HMASTER_socdebug; // Master select
+ wire [31:0] HWDATA_socdebug; // Write data
+ wire HMASTLOCK_socdebug; // Locked Sequence
+ wire HREADY_socdebug; // Transfer done
+
+ wire [31:0] HRDATA_socdebug; // Read data bus
+ wire HREADYOUT_socdebug; // HREADY feedback
+ wire [1:0] HRESP_socdebug; // Transfer response
// Input Port SI1
- wire HSEL_dma; // Slave Select
- wire [31:0] HADDR_dma; // Address bus
- wire [1:0] HTRANS_dma; // Transfer type
- wire HWRITE_dma; // Transfer direction
- wire [2:0] HSIZE_dma; // Transfer size
- wire [2:0] HBURST_dma; // Burst type
- wire [3:0] HPROT_dma; // Protection control
- wire [3:0] HMASTER_dma; // Master select
- wire [31:0] HWDATA_dma; // Write data
- wire HMASTLOCK_dma; // Locked Sequence
- wire HREADY_dma; // Transfer done
-
- wire [31:0] HRDATA_dma; // Read data bus
- wire HREADYOUT_dma; // HREADY feedback
- wire [1:0] HRESP_dma; // Transfer response
- wire [1:0] HAUSER_dma; // Address USER signals
- wire [1:0] HWUSER_dma; // Write-data USER signals
- wire [1:0] HRUSER_dma; // Read-data USER signals
+ wire HSEL_dma_0; // Slave Select
+ wire [31:0] HADDR_dma_0; // Address bus
+ wire [1:0] HTRANS_dma_0; // Transfer type
+ wire HWRITE_dma_0; // Transfer direction
+ wire [2:0] HSIZE_dma_0; // Transfer size
+ wire [2:0] HBURST_dma_0; // Burst type
+ wire [3:0] HPROT_dma_0; // Protection control
+ wire [3:0] HMASTER_dma_0; // Master select
+ wire [31:0] HWDATA_dma_0; // Write data
+ wire HMASTLOCK_dma_0; // Locked Sequence
+ wire HREADY_dma_0; // Transfer done
+
+ wire [31:0] HRDATA_dma_0; // Read data bus
+ wire HREADYOUT_dma_0; // HREADY feedback
+ wire [1:0] HRESP_dma_0; // Transfer response
// Input Port SI2
- wire HSEL_dma2; // Slave Select
- wire [31:0] HADDR_dma2; // Address bus
- wire [1:0] HTRANS_dma2; // Transfer type
- wire HWRITE_dma2; // Transfer direction
- wire [2:0] HSIZE_dma2; // Transfer size
- wire [2:0] HBURST_dma2; // Burst type
- wire [3:0] HPROT_dma2; // Protection control
- wire [3:0] HMASTER_dma2; // Master select
- wire [31:0] HWDATA_dma2; // Write data
- wire HMASTLOCK_dma2; // Locked Sequence
- wire HREADY_dma2; // Transfer done
-
- wire [31:0] HRDATA_dma2; // Read data bus
- wire HREADYOUT_dma2; // HREADY feedback
- wire [1:0] HRESP_dma2; // Transfer response
- wire [1:0] HAUSER_dma2; // Address USER signals
- wire [1:0] HWUSER_dma2; // Write-data USER signals
- wire [1:0] HRUSER_dma2; // Read-data USER signals
+ wire HSEL_dma_1; // Slave Select
+ wire [31:0] HADDR_dma_1; // Address bus
+ wire [1:0] HTRANS_dma_1; // Transfer type
+ wire HWRITE_dma_1; // Transfer direction
+ wire [2:0] HSIZE_dma_1; // Transfer size
+ wire [2:0] HBURST_dma_1; // Burst type
+ wire [3:0] HPROT_dma_1; // Protection control
+ wire [3:0] HMASTER_dma_1; // Master select
+ wire [31:0] HWDATA_dma_1; // Write data
+ wire HMASTLOCK_dma_1; // Locked Sequence
+ wire HREADY_dma_1; // Transfer done
+
+ wire [31:0] HRDATA_dma_1; // Read data bus
+ wire HREADYOUT_dma_1; // HREADY feedback
+ wire [1:0] HRESP_dma_1; // Transfer response
// Input Port SI3
wire HSEL_cpu; // Slave Select
@@ -632,129 +595,108 @@ module nanosoc_ahb32_4x7_busmatrix (
wire [31:0] HRDATA_cpu; // Read data bus
wire HREADYOUT_cpu; // HREADY feedback
wire [1:0] HRESP_cpu; // Transfer response
- wire [1:0] HAUSER_cpu; // Address USER signals
- wire [1:0] HWUSER_cpu; // Write-data USER signals
- wire [1:0] HRUSER_cpu; // Read-data USER signals
// Output Port MI0
- wire HSEL_rom1; // Slave Select
- wire [31:0] HADDR_rom1; // Address bus
- wire [1:0] HTRANS_rom1; // Transfer type
- wire HWRITE_rom1; // Transfer direction
- wire [2:0] HSIZE_rom1; // Transfer size
- wire [2:0] HBURST_rom1; // Burst type
- wire [3:0] HPROT_rom1; // Protection control
- wire [3:0] HMASTER_rom1; // Master select
- wire [31:0] HWDATA_rom1; // Write data
- wire HMASTLOCK_rom1; // Locked Sequence
- wire HREADYMUX_rom1; // Transfer done
-
- wire [31:0] HRDATA_rom1; // Read data bus
- wire HREADYOUT_rom1; // HREADY feedback
- wire [1:0] HRESP_rom1; // Transfer response
- wire [1:0] HAUSER_rom1; // Address USER signals
- wire [1:0] HWUSER_rom1; // Write-data USER signals
- wire [1:0] HRUSER_rom1; // Read-data USER signals
+ wire HSEL_bootrom; // Slave Select
+ wire [31:0] HADDR_bootrom; // Address bus
+ wire [1:0] HTRANS_bootrom; // Transfer type
+ wire HWRITE_bootrom; // Transfer direction
+ wire [2:0] HSIZE_bootrom; // Transfer size
+ wire [2:0] HBURST_bootrom; // Burst type
+ wire [3:0] HPROT_bootrom; // Protection control
+ wire [3:0] HMASTER_bootrom; // Master select
+ wire [31:0] HWDATA_bootrom; // Write data
+ wire HMASTLOCK_bootrom; // Locked Sequence
+ wire HREADYMUX_bootrom; // Transfer done
+
+ wire [31:0] HRDATA_bootrom; // Read data bus
+ wire HREADYOUT_bootrom; // HREADY feedback
+ wire [1:0] HRESP_bootrom; // Transfer response
// Output Port MI1
- wire HSEL_ram2; // Slave Select
- wire [31:0] HADDR_ram2; // Address bus
- wire [1:0] HTRANS_ram2; // Transfer type
- wire HWRITE_ram2; // Transfer direction
- wire [2:0] HSIZE_ram2; // Transfer size
- wire [2:0] HBURST_ram2; // Burst type
- wire [3:0] HPROT_ram2; // Protection control
- wire [3:0] HMASTER_ram2; // Master select
- wire [31:0] HWDATA_ram2; // Write data
- wire HMASTLOCK_ram2; // Locked Sequence
- wire HREADYMUX_ram2; // Transfer done
-
- wire [31:0] HRDATA_ram2; // Read data bus
- wire HREADYOUT_ram2; // HREADY feedback
- wire [1:0] HRESP_ram2; // Transfer response
- wire [1:0] HAUSER_ram2; // Address USER signals
- wire [1:0] HWUSER_ram2; // Write-data USER signals
- wire [1:0] HRUSER_ram2; // Read-data USER signals
+ wire HSEL_imem; // Slave Select
+ wire [31:0] HADDR_imem; // Address bus
+ wire [1:0] HTRANS_imem; // Transfer type
+ wire HWRITE_imem; // Transfer direction
+ wire [2:0] HSIZE_imem; // Transfer size
+ wire [2:0] HBURST_imem; // Burst type
+ wire [3:0] HPROT_imem; // Protection control
+ wire [3:0] HMASTER_imem; // Master select
+ wire [31:0] HWDATA_imem; // Write data
+ wire HMASTLOCK_imem; // Locked Sequence
+ wire HREADYMUX_imem; // Transfer done
+
+ wire [31:0] HRDATA_imem; // Read data bus
+ wire HREADYOUT_imem; // HREADY feedback
+ wire [1:0] HRESP_imem; // Transfer response
// Output Port MI2
- wire HSEL_ram3; // Slave Select
- wire [31:0] HADDR_ram3; // Address bus
- wire [1:0] HTRANS_ram3; // Transfer type
- wire HWRITE_ram3; // Transfer direction
- wire [2:0] HSIZE_ram3; // Transfer size
- wire [2:0] HBURST_ram3; // Burst type
- wire [3:0] HPROT_ram3; // Protection control
- wire [3:0] HMASTER_ram3; // Master select
- wire [31:0] HWDATA_ram3; // Write data
- wire HMASTLOCK_ram3; // Locked Sequence
- wire HREADYMUX_ram3; // Transfer done
-
- wire [31:0] HRDATA_ram3; // Read data bus
- wire HREADYOUT_ram3; // HREADY feedback
- wire [1:0] HRESP_ram3; // Transfer response
- wire [1:0] HAUSER_ram3; // Address USER signals
- wire [1:0] HWUSER_ram3; // Write-data USER signals
- wire [1:0] HRUSER_ram3; // Read-data USER signals
+ wire HSEL_dmem; // Slave Select
+ wire [31:0] HADDR_dmem; // Address bus
+ wire [1:0] HTRANS_dmem; // Transfer type
+ wire HWRITE_dmem; // Transfer direction
+ wire [2:0] HSIZE_dmem; // Transfer size
+ wire [2:0] HBURST_dmem; // Burst type
+ wire [3:0] HPROT_dmem; // Protection control
+ wire [3:0] HMASTER_dmem; // Master select
+ wire [31:0] HWDATA_dmem; // Write data
+ wire HMASTLOCK_dmem; // Locked Sequence
+ wire HREADYMUX_dmem; // Transfer done
+
+ wire [31:0] HRDATA_dmem; // Read data bus
+ wire HREADYOUT_dmem; // HREADY feedback
+ wire [1:0] HRESP_dmem; // Transfer response
// Output Port MI3
- wire HSEL_sys; // Slave Select
- wire [31:0] HADDR_sys; // Address bus
- wire [1:0] HTRANS_sys; // Transfer type
- wire HWRITE_sys; // Transfer direction
- wire [2:0] HSIZE_sys; // Transfer size
- wire [2:0] HBURST_sys; // Burst type
- wire [3:0] HPROT_sys; // Protection control
- wire [3:0] HMASTER_sys; // Master select
- wire [31:0] HWDATA_sys; // Write data
- wire HMASTLOCK_sys; // Locked Sequence
- wire HREADYMUX_sys; // Transfer done
-
- wire [31:0] HRDATA_sys; // Read data bus
- wire HREADYOUT_sys; // HREADY feedback
- wire [1:0] HRESP_sys; // Transfer response
- wire [1:0] HAUSER_sys; // Address USER signals
- wire [1:0] HWUSER_sys; // Write-data USER signals
- wire [1:0] HRUSER_sys; // Read-data USER signals
+ wire HSEL_sysio; // Slave Select
+ wire [31:0] HADDR_sysio; // Address bus
+ wire [1:0] HTRANS_sysio; // Transfer type
+ wire HWRITE_sysio; // Transfer direction
+ wire [2:0] HSIZE_sysio; // Transfer size
+ wire [2:0] HBURST_sysio; // Burst type
+ wire [3:0] HPROT_sysio; // Protection control
+ wire [3:0] HMASTER_sysio; // Master select
+ wire [31:0] HWDATA_sysio; // Write data
+ wire HMASTLOCK_sysio; // Locked Sequence
+ wire HREADYMUX_sysio; // Transfer done
+
+ wire [31:0] HRDATA_sysio; // Read data bus
+ wire HREADYOUT_sysio; // HREADY feedback
+ wire [1:0] HRESP_sysio; // Transfer response
// Output Port MI4
- wire HSEL_ram8; // Slave Select
- wire [31:0] HADDR_ram8; // Address bus
- wire [1:0] HTRANS_ram8; // Transfer type
- wire HWRITE_ram8; // Transfer direction
- wire [2:0] HSIZE_ram8; // Transfer size
- wire [2:0] HBURST_ram8; // Burst type
- wire [3:0] HPROT_ram8; // Protection control
- wire [3:0] HMASTER_ram8; // Master select
- wire [31:0] HWDATA_ram8; // Write data
- wire HMASTLOCK_ram8; // Locked Sequence
- wire HREADYMUX_ram8; // Transfer done
-
- wire [31:0] HRDATA_ram8; // Read data bus
- wire HREADYOUT_ram8; // HREADY feedback
- wire [1:0] HRESP_ram8; // Transfer response
- wire [1:0] HAUSER_ram8; // Address USER signals
- wire [1:0] HWUSER_ram8; // Write-data USER signals
- wire [1:0] HRUSER_ram8; // Read-data USER signals
+ wire HSEL_expram_l; // Slave Select
+ wire [31:0] HADDR_expram_l; // Address bus
+ wire [1:0] HTRANS_expram_l; // Transfer type
+ wire HWRITE_expram_l; // Transfer direction
+ wire [2:0] HSIZE_expram_l; // Transfer size
+ wire [2:0] HBURST_expram_l; // Burst type
+ wire [3:0] HPROT_expram_l; // Protection control
+ wire [3:0] HMASTER_expram_l; // Master select
+ wire [31:0] HWDATA_expram_l; // Write data
+ wire HMASTLOCK_expram_l; // Locked Sequence
+ wire HREADYMUX_expram_l; // Transfer done
+
+ wire [31:0] HRDATA_expram_l; // Read data bus
+ wire HREADYOUT_expram_l; // HREADY feedback
+ wire [1:0] HRESP_expram_l; // Transfer response
// Output Port MI5
- wire HSEL_ram9; // Slave Select
- wire [31:0] HADDR_ram9; // Address bus
- wire [1:0] HTRANS_ram9; // Transfer type
- wire HWRITE_ram9; // Transfer direction
- wire [2:0] HSIZE_ram9; // Transfer size
- wire [2:0] HBURST_ram9; // Burst type
- wire [3:0] HPROT_ram9; // Protection control
- wire [3:0] HMASTER_ram9; // Master select
- wire [31:0] HWDATA_ram9; // Write data
- wire HMASTLOCK_ram9; // Locked Sequence
- wire HREADYMUX_ram9; // Transfer done
-
- wire [31:0] HRDATA_ram9; // Read data bus
- wire HREADYOUT_ram9; // HREADY feedback
- wire [1:0] HRESP_ram9; // Transfer response
- wire [1:0] HAUSER_ram9; // Address USER signals
- wire [1:0] HWUSER_ram9; // Write-data USER signals
- wire [1:0] HRUSER_ram9; // Read-data USER signals
+ wire HSEL_expram_h; // Slave Select
+ wire [31:0] HADDR_expram_h; // Address bus
+ wire [1:0] HTRANS_expram_h; // Transfer type
+ wire HWRITE_expram_h; // Transfer direction
+ wire [2:0] HSIZE_expram_h; // Transfer size
+ wire [2:0] HBURST_expram_h; // Burst type
+ wire [3:0] HPROT_expram_h; // Protection control
+ wire [3:0] HMASTER_expram_h; // Master select
+ wire [31:0] HWDATA_expram_h; // Write data
+ wire HMASTLOCK_expram_h; // Locked Sequence
+ wire HREADYMUX_expram_h; // Transfer done
+
+ wire [31:0] HRDATA_expram_h; // Read data bus
+ wire HREADYOUT_expram_h; // HREADY feedback
+ wire [1:0] HRESP_expram_h; // Transfer response
// Output Port MI6
wire HSEL_exp; // Slave Select
@@ -772,9 +714,23 @@ module nanosoc_ahb32_4x7_busmatrix (
wire [31:0] HRDATA_exp; // Read data bus
wire HREADYOUT_exp; // HREADY feedback
wire [1:0] HRESP_exp; // Transfer response
- wire [1:0] HAUSER_exp; // Address USER signals
- wire [1:0] HWUSER_exp; // Write-data USER signals
- wire [1:0] HRUSER_exp; // Read-data USER signals
+
+ // Output Port MI7
+ wire HSEL_systable; // Slave Select
+ wire [31:0] HADDR_systable; // Address bus
+ wire [1:0] HTRANS_systable; // Transfer type
+ wire HWRITE_systable; // Transfer direction
+ wire [2:0] HSIZE_systable; // Transfer size
+ wire [2:0] HBURST_systable; // Burst type
+ wire [3:0] HPROT_systable; // Protection control
+ wire [3:0] HMASTER_systable; // Master select
+ wire [31:0] HWDATA_systable; // Write data
+ wire HMASTLOCK_systable; // Locked Sequence
+ wire HREADYMUX_systable; // Transfer done
+
+ wire [31:0] HRDATA_systable; // Read data bus
+ wire HREADYOUT_systable; // HREADY feedback
+ wire [1:0] HRESP_systable; // Transfer response
// -----------------------------------------------------------------------------
@@ -795,7 +751,6 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_held_tran0; // HeldTran signal
wire i_readyout0; // Readyout signal
wire [1:0] i_resp0; // Response signal
- wire [1:0] i_auser0; // HAUSER signal
// Bus-switch input SI1
wire i_sel1; // HSEL signal
@@ -811,7 +766,6 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_held_tran1; // HeldTran signal
wire i_readyout1; // Readyout signal
wire [1:0] i_resp1; // Response signal
- wire [1:0] i_auser1; // HAUSER signal
// Bus-switch input SI2
wire i_sel2; // HSEL signal
@@ -827,7 +781,6 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_held_tran2; // HeldTran signal
wire i_readyout2; // Readyout signal
wire [1:0] i_resp2; // Response signal
- wire [1:0] i_auser2; // HAUSER signal
// Bus-switch input SI3
wire i_sel3; // HSEL signal
@@ -843,7 +796,6 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_held_tran3; // HeldTran signal
wire i_readyout3; // Readyout signal
wire [1:0] i_resp3; // Response signal
- wire [1:0] i_auser3; // HAUSER signal
// Bus-switch SI0 to MI0 signals
wire i_sel0to0; // Routing selection signal
@@ -873,6 +825,10 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_sel0to6; // Routing selection signal
wire i_active0to6; // Active signal
+ // Bus-switch SI0 to MI7 signals
+ wire i_sel0to7; // Routing selection signal
+ wire i_active0to7; // Active signal
+
// Bus-switch SI1 to MI0 signals
wire i_sel1to0; // Routing selection signal
wire i_active1to0; // Active signal
@@ -957,13 +913,18 @@ module nanosoc_ahb32_4x7_busmatrix (
wire i_sel3to6; // Routing selection signal
wire i_active3to6; // Active signal
- wire i_hready_mux__rom1; // Internal HREADYMUXM for MI0
- wire i_hready_mux__ram2; // Internal HREADYMUXM for MI1
- wire i_hready_mux__ram3; // Internal HREADYMUXM for MI2
- wire i_hready_mux__sys; // Internal HREADYMUXM for MI3
- wire i_hready_mux__ram8; // Internal HREADYMUXM for MI4
- wire i_hready_mux__ram9; // Internal HREADYMUXM for MI5
+ // Bus-switch SI3 to MI7 signals
+ wire i_sel3to7; // Routing selection signal
+ wire i_active3to7; // Active signal
+
+ wire i_hready_mux__bootrom; // Internal HREADYMUXM for MI0
+ wire i_hready_mux__imem; // Internal HREADYMUXM for MI1
+ wire i_hready_mux__dmem; // Internal HREADYMUXM for MI2
+ wire i_hready_mux__sysio; // Internal HREADYMUXM for MI3
+ wire i_hready_mux__expram_l; // Internal HREADYMUXM for MI4
+ wire i_hready_mux__expram_h; // Internal HREADYMUXM for MI5
wire i_hready_mux__exp; // Internal HREADYMUXM for MI6
+ wire i_hready_mux__systable; // Internal HREADYMUXM for MI7
// -----------------------------------------------------------------------------
@@ -971,24 +932,23 @@ module nanosoc_ahb32_4x7_busmatrix (
// -----------------------------------------------------------------------------
// Input stage for SI0
- nanosoc_ahb32_4x7_inititator_input u_nanosoc_ahb32_4x7_inititator_input_0 (
+ nanosoc_inititator_input u_nanosoc_inititator_input_0 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_adp),
- .HADDRS (HADDR_adp),
- .HTRANSS (HTRANS_adp),
- .HWRITES (HWRITE_adp),
- .HSIZES (HSIZE_adp),
- .HBURSTS (HBURST_adp),
- .HPROTS (HPROT_adp),
- .HMASTERS (HMASTER_adp),
- .HMASTLOCKS (HMASTLOCK_adp),
- .HREADYS (HREADY_adp),
- .HAUSERS (HAUSER_adp),
+ .HSELS (HSEL_socdebug),
+ .HADDRS (HADDR_socdebug),
+ .HTRANSS (HTRANS_socdebug),
+ .HWRITES (HWRITE_socdebug),
+ .HSIZES (HSIZE_socdebug),
+ .HBURSTS (HBURST_socdebug),
+ .HPROTS (HPROT_socdebug),
+ .HMASTERS (HMASTER_socdebug),
+ .HMASTLOCKS (HMASTLOCK_socdebug),
+ .HREADYS (HREADY_socdebug),
// Internal Response
.active_ip (i_active0),
@@ -996,13 +956,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.resp_ip (i_resp0),
// Input Port Response
- .HREADYOUTS (HREADYOUT_adp),
- .HRESPS (HRESP_adp),
+ .HREADYOUTS (HREADYOUT_socdebug),
+ .HRESPS (HRESP_socdebug),
// Internal Address/Control Signals
.sel_ip (i_sel0),
.addr_ip (i_addr0),
- .auser_ip (i_auser0),
.trans_ip (i_trans0),
.write_ip (i_write0),
.size_ip (i_size0),
@@ -1016,24 +975,23 @@ module nanosoc_ahb32_4x7_busmatrix (
// Input stage for SI1
- nanosoc_ahb32_4x7_inititator_input u_nanosoc_ahb32_4x7_inititator_input_1 (
+ nanosoc_inititator_input u_nanosoc_inititator_input_1 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_dma),
- .HADDRS (HADDR_dma),
- .HTRANSS (HTRANS_dma),
- .HWRITES (HWRITE_dma),
- .HSIZES (HSIZE_dma),
- .HBURSTS (HBURST_dma),
- .HPROTS (HPROT_dma),
- .HMASTERS (HMASTER_dma),
- .HMASTLOCKS (HMASTLOCK_dma),
- .HREADYS (HREADY_dma),
- .HAUSERS (HAUSER_dma),
+ .HSELS (HSEL_dma_0),
+ .HADDRS (HADDR_dma_0),
+ .HTRANSS (HTRANS_dma_0),
+ .HWRITES (HWRITE_dma_0),
+ .HSIZES (HSIZE_dma_0),
+ .HBURSTS (HBURST_dma_0),
+ .HPROTS (HPROT_dma_0),
+ .HMASTERS (HMASTER_dma_0),
+ .HMASTLOCKS (HMASTLOCK_dma_0),
+ .HREADYS (HREADY_dma_0),
// Internal Response
.active_ip (i_active1),
@@ -1041,13 +999,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.resp_ip (i_resp1),
// Input Port Response
- .HREADYOUTS (HREADYOUT_dma),
- .HRESPS (HRESP_dma),
+ .HREADYOUTS (HREADYOUT_dma_0),
+ .HRESPS (HRESP_dma_0),
// Internal Address/Control Signals
.sel_ip (i_sel1),
.addr_ip (i_addr1),
- .auser_ip (i_auser1),
.trans_ip (i_trans1),
.write_ip (i_write1),
.size_ip (i_size1),
@@ -1061,24 +1018,23 @@ module nanosoc_ahb32_4x7_busmatrix (
// Input stage for SI2
- nanosoc_ahb32_4x7_inititator_input u_nanosoc_ahb32_4x7_inititator_input_2 (
+ nanosoc_inititator_input u_nanosoc_inititator_input_2 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_dma2),
- .HADDRS (HADDR_dma2),
- .HTRANSS (HTRANS_dma2),
- .HWRITES (HWRITE_dma2),
- .HSIZES (HSIZE_dma2),
- .HBURSTS (HBURST_dma2),
- .HPROTS (HPROT_dma2),
- .HMASTERS (HMASTER_dma2),
- .HMASTLOCKS (HMASTLOCK_dma2),
- .HREADYS (HREADY_dma2),
- .HAUSERS (HAUSER_dma2),
+ .HSELS (HSEL_dma_1),
+ .HADDRS (HADDR_dma_1),
+ .HTRANSS (HTRANS_dma_1),
+ .HWRITES (HWRITE_dma_1),
+ .HSIZES (HSIZE_dma_1),
+ .HBURSTS (HBURST_dma_1),
+ .HPROTS (HPROT_dma_1),
+ .HMASTERS (HMASTER_dma_1),
+ .HMASTLOCKS (HMASTLOCK_dma_1),
+ .HREADYS (HREADY_dma_1),
// Internal Response
.active_ip (i_active2),
@@ -1086,13 +1042,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.resp_ip (i_resp2),
// Input Port Response
- .HREADYOUTS (HREADYOUT_dma2),
- .HRESPS (HRESP_dma2),
+ .HREADYOUTS (HREADYOUT_dma_1),
+ .HRESPS (HRESP_dma_1),
// Internal Address/Control Signals
.sel_ip (i_sel2),
.addr_ip (i_addr2),
- .auser_ip (i_auser2),
.trans_ip (i_trans2),
.write_ip (i_write2),
.size_ip (i_size2),
@@ -1106,7 +1061,7 @@ module nanosoc_ahb32_4x7_busmatrix (
// Input stage for SI3
- nanosoc_ahb32_4x7_inititator_input u_nanosoc_ahb32_4x7_inititator_input_3 (
+ nanosoc_inititator_input u_nanosoc_inititator_input_3 (
// Common AHB signals
.HCLK (HCLK),
@@ -1123,7 +1078,6 @@ module nanosoc_ahb32_4x7_busmatrix (
.HMASTERS (HMASTER_cpu),
.HMASTLOCKS (HMASTLOCK_cpu),
.HREADYS (HREADY_cpu),
- .HAUSERS (HAUSER_cpu),
// Internal Response
.active_ip (i_active3),
@@ -1137,7 +1091,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Internal Address/Control Signals
.sel_ip (i_sel3),
.addr_ip (i_addr3),
- .auser_ip (i_auser3),
.trans_ip (i_trans3),
.write_ip (i_write3),
.size_ip (i_size3),
@@ -1151,7 +1104,7 @@ module nanosoc_ahb32_4x7_busmatrix (
// Matrix decoder for SI0
- nanosoc_ahb32_4x7_matrix_decode_adp u_nanosoc_ahb32_4x7_matrix_decode_adp (
+ nanosoc_matrix_decode_socdebug u_nanosoc_matrix_decode_socdebug (
// Common AHB signals
.HCLK (HCLK),
@@ -1161,59 +1114,58 @@ module nanosoc_ahb32_4x7_busmatrix (
.remapping_dec ( REMAP[0] ),
// Signals from Input stage SI0
- .HREADYS (HREADY_adp),
+ .HREADYS (HREADY_socdebug),
.sel_dec (i_sel0),
.decode_addr_dec (i_addr0[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans0),
// Control/Response for Output Stage MI0
.active_dec0 (i_active0to0),
- .readyout_dec0 (i_hready_mux__rom1),
- .resp_dec0 (HRESP_rom1),
- .rdata_dec0 (HRDATA_rom1),
- .ruser_dec0 (HRUSER_rom1),
+ .readyout_dec0 (i_hready_mux__bootrom),
+ .resp_dec0 (HRESP_bootrom),
+ .rdata_dec0 (HRDATA_bootrom),
// Control/Response for Output Stage MI1
.active_dec1 (i_active0to1),
- .readyout_dec1 (i_hready_mux__ram2),
- .resp_dec1 (HRESP_ram2),
- .rdata_dec1 (HRDATA_ram2),
- .ruser_dec1 (HRUSER_ram2),
+ .readyout_dec1 (i_hready_mux__imem),
+ .resp_dec1 (HRESP_imem),
+ .rdata_dec1 (HRDATA_imem),
// Control/Response for Output Stage MI2
.active_dec2 (i_active0to2),
- .readyout_dec2 (i_hready_mux__ram3),
- .resp_dec2 (HRESP_ram3),
- .rdata_dec2 (HRDATA_ram3),
- .ruser_dec2 (HRUSER_ram3),
+ .readyout_dec2 (i_hready_mux__dmem),
+ .resp_dec2 (HRESP_dmem),
+ .rdata_dec2 (HRDATA_dmem),
// Control/Response for Output Stage MI3
.active_dec3 (i_active0to3),
- .readyout_dec3 (i_hready_mux__sys),
- .resp_dec3 (HRESP_sys),
- .rdata_dec3 (HRDATA_sys),
- .ruser_dec3 (HRUSER_sys),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_sysio),
+ .rdata_dec3 (HRDATA_sysio),
// Control/Response for Output Stage MI4
.active_dec4 (i_active0to4),
- .readyout_dec4 (i_hready_mux__ram8),
- .resp_dec4 (HRESP_ram8),
- .rdata_dec4 (HRDATA_ram8),
- .ruser_dec4 (HRUSER_ram8),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_expram_l),
+ .rdata_dec4 (HRDATA_expram_l),
// Control/Response for Output Stage MI5
.active_dec5 (i_active0to5),
- .readyout_dec5 (i_hready_mux__ram9),
- .resp_dec5 (HRESP_ram9),
- .rdata_dec5 (HRDATA_ram9),
- .ruser_dec5 (HRUSER_ram9),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_expram_h),
+ .rdata_dec5 (HRDATA_expram_h),
// Control/Response for Output Stage MI6
.active_dec6 (i_active0to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
- .ruser_dec6 (HRUSER_exp),
+
+ // Control/Response for Output Stage MI7
+ .active_dec7 (i_active0to7),
+ .readyout_dec7 (i_hready_mux__systable),
+ .resp_dec7 (HRESP_systable),
+ .rdata_dec7 (HRDATA_systable),
.sel_dec0 (i_sel0to0),
.sel_dec1 (i_sel0to1),
@@ -1222,77 +1174,70 @@ module nanosoc_ahb32_4x7_busmatrix (
.sel_dec4 (i_sel0to4),
.sel_dec5 (i_sel0to5),
.sel_dec6 (i_sel0to6),
+ .sel_dec7 (i_sel0to7),
.active_dec (i_active0),
.HREADYOUTS (i_readyout0),
.HRESPS (i_resp0),
- .HRUSERS (HRUSER_adp),
- .HRDATAS (HRDATA_adp)
+ .HRDATAS (HRDATA_socdebug)
);
// Matrix decoder for SI1
- nanosoc_ahb32_4x7_matrix_decode_dma u_nanosoc_ahb32_4x7_matrix_decode_dma (
+ nanosoc_matrix_decode_dma_0 u_nanosoc_matrix_decode_dma_0 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI1
- .HREADYS (HREADY_dma),
+ .HREADYS (HREADY_dma_0),
.sel_dec (i_sel1),
.decode_addr_dec (i_addr1[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans1),
// Control/Response for Output Stage MI0
.active_dec0 (i_active1to0),
- .readyout_dec0 (i_hready_mux__rom1),
- .resp_dec0 (HRESP_rom1),
- .rdata_dec0 (HRDATA_rom1),
- .ruser_dec0 (HRUSER_rom1),
+ .readyout_dec0 (i_hready_mux__bootrom),
+ .resp_dec0 (HRESP_bootrom),
+ .rdata_dec0 (HRDATA_bootrom),
// Control/Response for Output Stage MI1
.active_dec1 (i_active1to1),
- .readyout_dec1 (i_hready_mux__ram2),
- .resp_dec1 (HRESP_ram2),
- .rdata_dec1 (HRDATA_ram2),
- .ruser_dec1 (HRUSER_ram2),
+ .readyout_dec1 (i_hready_mux__imem),
+ .resp_dec1 (HRESP_imem),
+ .rdata_dec1 (HRDATA_imem),
// Control/Response for Output Stage MI2
.active_dec2 (i_active1to2),
- .readyout_dec2 (i_hready_mux__ram3),
- .resp_dec2 (HRESP_ram3),
- .rdata_dec2 (HRDATA_ram3),
- .ruser_dec2 (HRUSER_ram3),
+ .readyout_dec2 (i_hready_mux__dmem),
+ .resp_dec2 (HRESP_dmem),
+ .rdata_dec2 (HRDATA_dmem),
// Control/Response for Output Stage MI3
.active_dec3 (i_active1to3),
- .readyout_dec3 (i_hready_mux__sys),
- .resp_dec3 (HRESP_sys),
- .rdata_dec3 (HRDATA_sys),
- .ruser_dec3 (HRUSER_sys),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_sysio),
+ .rdata_dec3 (HRDATA_sysio),
// Control/Response for Output Stage MI4
.active_dec4 (i_active1to4),
- .readyout_dec4 (i_hready_mux__ram8),
- .resp_dec4 (HRESP_ram8),
- .rdata_dec4 (HRDATA_ram8),
- .ruser_dec4 (HRUSER_ram8),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_expram_l),
+ .rdata_dec4 (HRDATA_expram_l),
// Control/Response for Output Stage MI5
.active_dec5 (i_active1to5),
- .readyout_dec5 (i_hready_mux__ram9),
- .resp_dec5 (HRESP_ram9),
- .rdata_dec5 (HRDATA_ram9),
- .ruser_dec5 (HRUSER_ram9),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_expram_h),
+ .rdata_dec5 (HRDATA_expram_h),
// Control/Response for Output Stage MI6
.active_dec6 (i_active1to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
- .ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel1to0),
.sel_dec1 (i_sel1to1),
@@ -1305,73 +1250,65 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_dec (i_active1),
.HREADYOUTS (i_readyout1),
.HRESPS (i_resp1),
- .HRUSERS (HRUSER_dma),
- .HRDATAS (HRDATA_dma)
+ .HRDATAS (HRDATA_dma_0)
);
// Matrix decoder for SI2
- nanosoc_ahb32_4x7_matrix_decode_dma2 u_nanosoc_ahb32_4x7_matrix_decode_dma2 (
+ nanosoc_matrix_decode_dma_1 u_nanosoc_matrix_decode_dma_1 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI2
- .HREADYS (HREADY_dma2),
+ .HREADYS (HREADY_dma_1),
.sel_dec (i_sel2),
.decode_addr_dec (i_addr2[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans2),
// Control/Response for Output Stage MI0
.active_dec0 (i_active2to0),
- .readyout_dec0 (i_hready_mux__rom1),
- .resp_dec0 (HRESP_rom1),
- .rdata_dec0 (HRDATA_rom1),
- .ruser_dec0 (HRUSER_rom1),
+ .readyout_dec0 (i_hready_mux__bootrom),
+ .resp_dec0 (HRESP_bootrom),
+ .rdata_dec0 (HRDATA_bootrom),
// Control/Response for Output Stage MI1
.active_dec1 (i_active2to1),
- .readyout_dec1 (i_hready_mux__ram2),
- .resp_dec1 (HRESP_ram2),
- .rdata_dec1 (HRDATA_ram2),
- .ruser_dec1 (HRUSER_ram2),
+ .readyout_dec1 (i_hready_mux__imem),
+ .resp_dec1 (HRESP_imem),
+ .rdata_dec1 (HRDATA_imem),
// Control/Response for Output Stage MI2
.active_dec2 (i_active2to2),
- .readyout_dec2 (i_hready_mux__ram3),
- .resp_dec2 (HRESP_ram3),
- .rdata_dec2 (HRDATA_ram3),
- .ruser_dec2 (HRUSER_ram3),
+ .readyout_dec2 (i_hready_mux__dmem),
+ .resp_dec2 (HRESP_dmem),
+ .rdata_dec2 (HRDATA_dmem),
// Control/Response for Output Stage MI3
.active_dec3 (i_active2to3),
- .readyout_dec3 (i_hready_mux__sys),
- .resp_dec3 (HRESP_sys),
- .rdata_dec3 (HRDATA_sys),
- .ruser_dec3 (HRUSER_sys),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_sysio),
+ .rdata_dec3 (HRDATA_sysio),
// Control/Response for Output Stage MI4
.active_dec4 (i_active2to4),
- .readyout_dec4 (i_hready_mux__ram8),
- .resp_dec4 (HRESP_ram8),
- .rdata_dec4 (HRDATA_ram8),
- .ruser_dec4 (HRUSER_ram8),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_expram_l),
+ .rdata_dec4 (HRDATA_expram_l),
// Control/Response for Output Stage MI5
.active_dec5 (i_active2to5),
- .readyout_dec5 (i_hready_mux__ram9),
- .resp_dec5 (HRESP_ram9),
- .rdata_dec5 (HRDATA_ram9),
- .ruser_dec5 (HRUSER_ram9),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_expram_h),
+ .rdata_dec5 (HRDATA_expram_h),
// Control/Response for Output Stage MI6
.active_dec6 (i_active2to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
- .ruser_dec6 (HRUSER_exp),
.sel_dec0 (i_sel2to0),
.sel_dec1 (i_sel2to1),
@@ -1384,14 +1321,13 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_dec (i_active2),
.HREADYOUTS (i_readyout2),
.HRESPS (i_resp2),
- .HRUSERS (HRUSER_dma2),
- .HRDATAS (HRDATA_dma2)
+ .HRDATAS (HRDATA_dma_1)
);
// Matrix decoder for SI3
- nanosoc_ahb32_4x7_matrix_decode_cpu u_nanosoc_ahb32_4x7_matrix_decode_cpu (
+ nanosoc_matrix_decode_cpu u_nanosoc_matrix_decode_cpu (
// Common AHB signals
.HCLK (HCLK),
@@ -1408,52 +1344,51 @@ module nanosoc_ahb32_4x7_busmatrix (
// Control/Response for Output Stage MI0
.active_dec0 (i_active3to0),
- .readyout_dec0 (i_hready_mux__rom1),
- .resp_dec0 (HRESP_rom1),
- .rdata_dec0 (HRDATA_rom1),
- .ruser_dec0 (HRUSER_rom1),
+ .readyout_dec0 (i_hready_mux__bootrom),
+ .resp_dec0 (HRESP_bootrom),
+ .rdata_dec0 (HRDATA_bootrom),
// Control/Response for Output Stage MI1
.active_dec1 (i_active3to1),
- .readyout_dec1 (i_hready_mux__ram2),
- .resp_dec1 (HRESP_ram2),
- .rdata_dec1 (HRDATA_ram2),
- .ruser_dec1 (HRUSER_ram2),
+ .readyout_dec1 (i_hready_mux__imem),
+ .resp_dec1 (HRESP_imem),
+ .rdata_dec1 (HRDATA_imem),
// Control/Response for Output Stage MI2
.active_dec2 (i_active3to2),
- .readyout_dec2 (i_hready_mux__ram3),
- .resp_dec2 (HRESP_ram3),
- .rdata_dec2 (HRDATA_ram3),
- .ruser_dec2 (HRUSER_ram3),
+ .readyout_dec2 (i_hready_mux__dmem),
+ .resp_dec2 (HRESP_dmem),
+ .rdata_dec2 (HRDATA_dmem),
// Control/Response for Output Stage MI3
.active_dec3 (i_active3to3),
- .readyout_dec3 (i_hready_mux__sys),
- .resp_dec3 (HRESP_sys),
- .rdata_dec3 (HRDATA_sys),
- .ruser_dec3 (HRUSER_sys),
+ .readyout_dec3 (i_hready_mux__sysio),
+ .resp_dec3 (HRESP_sysio),
+ .rdata_dec3 (HRDATA_sysio),
// Control/Response for Output Stage MI4
.active_dec4 (i_active3to4),
- .readyout_dec4 (i_hready_mux__ram8),
- .resp_dec4 (HRESP_ram8),
- .rdata_dec4 (HRDATA_ram8),
- .ruser_dec4 (HRUSER_ram8),
+ .readyout_dec4 (i_hready_mux__expram_l),
+ .resp_dec4 (HRESP_expram_l),
+ .rdata_dec4 (HRDATA_expram_l),
// Control/Response for Output Stage MI5
.active_dec5 (i_active3to5),
- .readyout_dec5 (i_hready_mux__ram9),
- .resp_dec5 (HRESP_ram9),
- .rdata_dec5 (HRDATA_ram9),
- .ruser_dec5 (HRUSER_ram9),
+ .readyout_dec5 (i_hready_mux__expram_h),
+ .resp_dec5 (HRESP_expram_h),
+ .rdata_dec5 (HRDATA_expram_h),
// Control/Response for Output Stage MI6
.active_dec6 (i_active3to6),
.readyout_dec6 (i_hready_mux__exp),
.resp_dec6 (HRESP_exp),
.rdata_dec6 (HRDATA_exp),
- .ruser_dec6 (HRUSER_exp),
+
+ // Control/Response for Output Stage MI7
+ .active_dec7 (i_active3to7),
+ .readyout_dec7 (i_hready_mux__systable),
+ .resp_dec7 (HRESP_systable),
+ .rdata_dec7 (HRDATA_systable),
.sel_dec0 (i_sel3to0),
.sel_dec1 (i_sel3to1),
@@ -1462,18 +1397,18 @@ module nanosoc_ahb32_4x7_busmatrix (
.sel_dec4 (i_sel3to4),
.sel_dec5 (i_sel3to5),
.sel_dec6 (i_sel3to6),
+ .sel_dec7 (i_sel3to7),
.active_dec (i_active3),
.HREADYOUTS (i_readyout3),
.HRESPS (i_resp3),
- .HRUSERS (HRUSER_cpu),
.HRDATAS (HRDATA_cpu)
);
// Output stage for MI0
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_0 (
+ nanosoc_target_output_bootrom u_nanosoc_target_output_bootrom_0 (
// Common AHB signals
.HCLK (HCLK),
@@ -1482,7 +1417,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to0),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1490,14 +1424,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to0),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1505,14 +1437,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to0),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -1520,14 +1450,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to0),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -1536,11 +1464,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_rom1),
+ .HREADYOUTM (HREADYOUT_bootrom),
.active_op0 (i_active0to0),
.active_op1 (i_active1to0),
@@ -1548,28 +1475,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to0),
// Slave Address/Control Signals
- .HSELM (HSEL_rom1),
- .HADDRM (HADDR_rom1),
- .HAUSERM (HAUSER_rom1),
- .HTRANSM (HTRANS_rom1),
- .HWRITEM (HWRITE_rom1),
- .HSIZEM (HSIZE_rom1),
- .HBURSTM (HBURST_rom1),
- .HPROTM (HPROT_rom1),
- .HMASTERM (HMASTER_rom1),
- .HMASTLOCKM (HMASTLOCK_rom1),
- .HREADYMUXM (i_hready_mux__rom1),
- .HWUSERM (HWUSER_rom1),
- .HWDATAM (HWDATA_rom1)
+ .HSELM (HSEL_bootrom),
+ .HADDRM (HADDR_bootrom),
+ .HTRANSM (HTRANS_bootrom),
+ .HWRITEM (HWRITE_bootrom),
+ .HSIZEM (HSIZE_bootrom),
+ .HBURSTM (HBURST_bootrom),
+ .HPROTM (HPROT_bootrom),
+ .HMASTERM (HMASTER_bootrom),
+ .HMASTLOCKM (HMASTLOCK_bootrom),
+ .HREADYMUXM (i_hready_mux__bootrom),
+ .HWDATAM (HWDATA_bootrom)
);
// Drive output with internal version
- assign HREADYMUX_rom1 = i_hready_mux__rom1;
+ assign HREADYMUX_bootrom = i_hready_mux__bootrom;
// Output stage for MI1
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_1 (
+ nanosoc_target_output_imem u_nanosoc_target_output_imem_1 (
// Common AHB signals
.HCLK (HCLK),
@@ -1578,7 +1503,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to1),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1586,14 +1510,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to1),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1601,14 +1523,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to1),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -1616,14 +1536,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to1),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -1632,11 +1550,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_ram2),
+ .HREADYOUTM (HREADYOUT_imem),
.active_op0 (i_active0to1),
.active_op1 (i_active1to1),
@@ -1644,28 +1561,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to1),
// Slave Address/Control Signals
- .HSELM (HSEL_ram2),
- .HADDRM (HADDR_ram2),
- .HAUSERM (HAUSER_ram2),
- .HTRANSM (HTRANS_ram2),
- .HWRITEM (HWRITE_ram2),
- .HSIZEM (HSIZE_ram2),
- .HBURSTM (HBURST_ram2),
- .HPROTM (HPROT_ram2),
- .HMASTERM (HMASTER_ram2),
- .HMASTLOCKM (HMASTLOCK_ram2),
- .HREADYMUXM (i_hready_mux__ram2),
- .HWUSERM (HWUSER_ram2),
- .HWDATAM (HWDATA_ram2)
+ .HSELM (HSEL_imem),
+ .HADDRM (HADDR_imem),
+ .HTRANSM (HTRANS_imem),
+ .HWRITEM (HWRITE_imem),
+ .HSIZEM (HSIZE_imem),
+ .HBURSTM (HBURST_imem),
+ .HPROTM (HPROT_imem),
+ .HMASTERM (HMASTER_imem),
+ .HMASTLOCKM (HMASTLOCK_imem),
+ .HREADYMUXM (i_hready_mux__imem),
+ .HWDATAM (HWDATA_imem)
);
// Drive output with internal version
- assign HREADYMUX_ram2 = i_hready_mux__ram2;
+ assign HREADYMUX_imem = i_hready_mux__imem;
// Output stage for MI2
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_2 (
+ nanosoc_target_output_dmem u_nanosoc_target_output_dmem_2 (
// Common AHB signals
.HCLK (HCLK),
@@ -1674,7 +1589,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to2),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1682,14 +1596,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to2),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1697,14 +1609,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to2),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -1712,14 +1622,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to2),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -1728,11 +1636,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_ram3),
+ .HREADYOUTM (HREADYOUT_dmem),
.active_op0 (i_active0to2),
.active_op1 (i_active1to2),
@@ -1740,28 +1647,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to2),
// Slave Address/Control Signals
- .HSELM (HSEL_ram3),
- .HADDRM (HADDR_ram3),
- .HAUSERM (HAUSER_ram3),
- .HTRANSM (HTRANS_ram3),
- .HWRITEM (HWRITE_ram3),
- .HSIZEM (HSIZE_ram3),
- .HBURSTM (HBURST_ram3),
- .HPROTM (HPROT_ram3),
- .HMASTERM (HMASTER_ram3),
- .HMASTLOCKM (HMASTLOCK_ram3),
- .HREADYMUXM (i_hready_mux__ram3),
- .HWUSERM (HWUSER_ram3),
- .HWDATAM (HWDATA_ram3)
+ .HSELM (HSEL_dmem),
+ .HADDRM (HADDR_dmem),
+ .HTRANSM (HTRANS_dmem),
+ .HWRITEM (HWRITE_dmem),
+ .HSIZEM (HSIZE_dmem),
+ .HBURSTM (HBURST_dmem),
+ .HPROTM (HPROT_dmem),
+ .HMASTERM (HMASTER_dmem),
+ .HMASTLOCKM (HMASTLOCK_dmem),
+ .HREADYMUXM (i_hready_mux__dmem),
+ .HWDATAM (HWDATA_dmem)
);
// Drive output with internal version
- assign HREADYMUX_ram3 = i_hready_mux__ram3;
+ assign HREADYMUX_dmem = i_hready_mux__dmem;
// Output stage for MI3
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_3 (
+ nanosoc_target_output_sysio u_nanosoc_target_output_sysio_3 (
// Common AHB signals
.HCLK (HCLK),
@@ -1770,7 +1675,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to3),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1778,14 +1682,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to3),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1793,14 +1695,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to3),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -1808,14 +1708,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to3),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -1824,11 +1722,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_sys),
+ .HREADYOUTM (HREADYOUT_sysio),
.active_op0 (i_active0to3),
.active_op1 (i_active1to3),
@@ -1836,28 +1733,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to3),
// Slave Address/Control Signals
- .HSELM (HSEL_sys),
- .HADDRM (HADDR_sys),
- .HAUSERM (HAUSER_sys),
- .HTRANSM (HTRANS_sys),
- .HWRITEM (HWRITE_sys),
- .HSIZEM (HSIZE_sys),
- .HBURSTM (HBURST_sys),
- .HPROTM (HPROT_sys),
- .HMASTERM (HMASTER_sys),
- .HMASTLOCKM (HMASTLOCK_sys),
- .HREADYMUXM (i_hready_mux__sys),
- .HWUSERM (HWUSER_sys),
- .HWDATAM (HWDATA_sys)
+ .HSELM (HSEL_sysio),
+ .HADDRM (HADDR_sysio),
+ .HTRANSM (HTRANS_sysio),
+ .HWRITEM (HWRITE_sysio),
+ .HSIZEM (HSIZE_sysio),
+ .HBURSTM (HBURST_sysio),
+ .HPROTM (HPROT_sysio),
+ .HMASTERM (HMASTER_sysio),
+ .HMASTLOCKM (HMASTLOCK_sysio),
+ .HREADYMUXM (i_hready_mux__sysio),
+ .HWDATAM (HWDATA_sysio)
);
// Drive output with internal version
- assign HREADYMUX_sys = i_hready_mux__sys;
+ assign HREADYMUX_sysio = i_hready_mux__sysio;
// Output stage for MI4
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_4 (
+ nanosoc_target_output_expram_l u_nanosoc_target_output_expram_l_4 (
// Common AHB signals
.HCLK (HCLK),
@@ -1866,7 +1761,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to4),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1874,14 +1768,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to4),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1889,14 +1781,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to4),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -1904,14 +1794,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to4),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -1920,11 +1808,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_ram8),
+ .HREADYOUTM (HREADYOUT_expram_l),
.active_op0 (i_active0to4),
.active_op1 (i_active1to4),
@@ -1932,28 +1819,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to4),
// Slave Address/Control Signals
- .HSELM (HSEL_ram8),
- .HADDRM (HADDR_ram8),
- .HAUSERM (HAUSER_ram8),
- .HTRANSM (HTRANS_ram8),
- .HWRITEM (HWRITE_ram8),
- .HSIZEM (HSIZE_ram8),
- .HBURSTM (HBURST_ram8),
- .HPROTM (HPROT_ram8),
- .HMASTERM (HMASTER_ram8),
- .HMASTLOCKM (HMASTLOCK_ram8),
- .HREADYMUXM (i_hready_mux__ram8),
- .HWUSERM (HWUSER_ram8),
- .HWDATAM (HWDATA_ram8)
+ .HSELM (HSEL_expram_l),
+ .HADDRM (HADDR_expram_l),
+ .HTRANSM (HTRANS_expram_l),
+ .HWRITEM (HWRITE_expram_l),
+ .HSIZEM (HSIZE_expram_l),
+ .HBURSTM (HBURST_expram_l),
+ .HPROTM (HPROT_expram_l),
+ .HMASTERM (HMASTER_expram_l),
+ .HMASTLOCKM (HMASTLOCK_expram_l),
+ .HREADYMUXM (i_hready_mux__expram_l),
+ .HWDATAM (HWDATA_expram_l)
);
// Drive output with internal version
- assign HREADYMUX_ram8 = i_hready_mux__ram8;
+ assign HREADYMUX_expram_l = i_hready_mux__expram_l;
// Output stage for MI5
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_5 (
+ nanosoc_target_output_expram_h u_nanosoc_target_output_expram_h_5 (
// Common AHB signals
.HCLK (HCLK),
@@ -1962,7 +1847,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to5),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -1970,14 +1854,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to5),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -1985,14 +1867,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to5),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -2000,14 +1880,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to5),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -2016,11 +1894,10 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_ram9),
+ .HREADYOUTM (HREADYOUT_expram_h),
.active_op0 (i_active0to5),
.active_op1 (i_active1to5),
@@ -2028,28 +1905,26 @@ module nanosoc_ahb32_4x7_busmatrix (
.active_op3 (i_active3to5),
// Slave Address/Control Signals
- .HSELM (HSEL_ram9),
- .HADDRM (HADDR_ram9),
- .HAUSERM (HAUSER_ram9),
- .HTRANSM (HTRANS_ram9),
- .HWRITEM (HWRITE_ram9),
- .HSIZEM (HSIZE_ram9),
- .HBURSTM (HBURST_ram9),
- .HPROTM (HPROT_ram9),
- .HMASTERM (HMASTER_ram9),
- .HMASTLOCKM (HMASTLOCK_ram9),
- .HREADYMUXM (i_hready_mux__ram9),
- .HWUSERM (HWUSER_ram9),
- .HWDATAM (HWDATA_ram9)
+ .HSELM (HSEL_expram_h),
+ .HADDRM (HADDR_expram_h),
+ .HTRANSM (HTRANS_expram_h),
+ .HWRITEM (HWRITE_expram_h),
+ .HSIZEM (HSIZE_expram_h),
+ .HBURSTM (HBURST_expram_h),
+ .HPROTM (HPROT_expram_h),
+ .HMASTERM (HMASTER_expram_h),
+ .HMASTLOCKM (HMASTLOCK_expram_h),
+ .HREADYMUXM (i_hready_mux__expram_h),
+ .HWDATAM (HWDATA_expram_h)
);
// Drive output with internal version
- assign HREADYMUX_ram9 = i_hready_mux__ram9;
+ assign HREADYMUX_expram_h = i_hready_mux__expram_h;
// Output stage for MI6
- nanosoc_ahb32_4x7_target_output u_nanosoc_ahb32_4x7_target_output_6 (
+ nanosoc_target_output_exp u_nanosoc_target_output_exp_6 (
// Common AHB signals
.HCLK (HCLK),
@@ -2058,7 +1933,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Port 0 Signals
.sel_op0 (i_sel0to6),
.addr_op0 (i_addr0),
- .auser_op0 (i_auser0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
.size_op0 (i_size0),
@@ -2066,14 +1940,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op0 (i_prot0),
.master_op0 (i_master0),
.mastlock_op0 (i_mastlock0),
- .wdata_op0 (HWDATA_adp),
- .wuser_op0 (HWUSER_adp),
+ .wdata_op0 (HWDATA_socdebug),
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
.sel_op1 (i_sel1to6),
.addr_op1 (i_addr1),
- .auser_op1 (i_auser1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
.size_op1 (i_size1),
@@ -2081,14 +1953,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_dma),
- .wuser_op1 (HWUSER_dma),
+ .wdata_op1 (HWDATA_dma_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
.sel_op2 (i_sel2to6),
.addr_op2 (i_addr2),
- .auser_op2 (i_auser2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
.size_op2 (i_size2),
@@ -2096,14 +1966,12 @@ module nanosoc_ahb32_4x7_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_dma2),
- .wuser_op2 (HWUSER_dma2),
+ .wdata_op2 (HWDATA_dma_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
.sel_op3 (i_sel3to6),
.addr_op3 (i_addr3),
- .auser_op3 (i_auser3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
.size_op3 (i_size3),
@@ -2112,7 +1980,6 @@ module nanosoc_ahb32_4x7_busmatrix (
.master_op3 (i_master3),
.mastlock_op3 (i_mastlock3),
.wdata_op3 (HWDATA_cpu),
- .wuser_op3 (HWUSER_cpu),
.held_tran_op3 (i_held_tran3),
// Slave read data and response
@@ -2126,7 +1993,6 @@ module nanosoc_ahb32_4x7_busmatrix (
// Slave Address/Control Signals
.HSELM (HSEL_exp),
.HADDRM (HADDR_exp),
- .HAUSERM (HAUSER_exp),
.HTRANSM (HTRANS_exp),
.HWRITEM (HWRITE_exp),
.HSIZEM (HSIZE_exp),
@@ -2135,7 +2001,6 @@ module nanosoc_ahb32_4x7_busmatrix (
.HMASTERM (HMASTER_exp),
.HMASTLOCKM (HMASTLOCK_exp),
.HREADYMUXM (i_hready_mux__exp),
- .HWUSERM (HWUSER_exp),
.HWDATAM (HWDATA_exp)
);
@@ -2144,6 +2009,64 @@ module nanosoc_ahb32_4x7_busmatrix (
assign HREADYMUX_exp = i_hready_mux__exp;
+ // Output stage for MI7
+ nanosoc_target_output_systable u_nanosoc_target_output_systable_7 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to7),
+ .addr_op0 (i_addr0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_socdebug),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to7),
+ .addr_op3 (i_addr3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_cpu),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_systable),
+
+ .active_op0 (i_active0to7),
+ .active_op3 (i_active3to7),
+
+ // Slave Address/Control Signals
+ .HSELM (HSEL_systable),
+ .HADDRM (HADDR_systable),
+ .HTRANSM (HTRANS_systable),
+ .HWRITEM (HWRITE_systable),
+ .HSIZEM (HSIZE_systable),
+ .HBURSTM (HBURST_systable),
+ .HPROTM (HPROT_systable),
+ .HMASTERM (HMASTER_systable),
+ .HMASTLOCKM (HMASTLOCK_systable),
+ .HREADYMUXM (i_hready_mux__systable),
+ .HWDATAM (HWDATA_systable)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_systable = i_hready_mux__systable;
+
+
endmodule
// --================================= End ===================================--
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
similarity index 98%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
index a43ec0c9bba5e0bc66e8856914a9ddaa40598d80..f96bab0acd2ced0fbee9377e9549d669cf8d0f11 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
@@ -28,7 +28,7 @@
-module nanosoc_ahb32_4x7_busmatrix_default_slave (
+module nanosoc_busmatrix_default_slave (
// Common AHB signals
HCLK,
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
new file mode 100644
index 0000000000000000000000000000000000000000..ddc19b025332831f49110881150a1b3407e148b7
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -0,0 +1,920 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : BusMatrixLite is a wrapper module that wraps around
+// the BusMatrix module to give AHB Lite compliant
+// slave and master interfaces.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_busmatrix_lite (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // System Address Remap control
+ REMAP,
+
+ // Input port SI0 (inputs from master 0)
+ HADDR_socdebug,
+ HTRANS_socdebug,
+ HWRITE_socdebug,
+ HSIZE_socdebug,
+ HBURST_socdebug,
+ HPROT_socdebug,
+ HWDATA_socdebug,
+ HMASTLOCK_socdebug,
+
+ // Input port SI1 (inputs from master 1)
+ HADDR_dma_0,
+ HTRANS_dma_0,
+ HWRITE_dma_0,
+ HSIZE_dma_0,
+ HBURST_dma_0,
+ HPROT_dma_0,
+ HWDATA_dma_0,
+ HMASTLOCK_dma_0,
+
+ // Input port SI2 (inputs from master 2)
+ HADDR_dma_1,
+ HTRANS_dma_1,
+ HWRITE_dma_1,
+ HSIZE_dma_1,
+ HBURST_dma_1,
+ HPROT_dma_1,
+ HWDATA_dma_1,
+ HMASTLOCK_dma_1,
+
+ // Input port SI3 (inputs from master 3)
+ HADDR_cpu,
+ HTRANS_cpu,
+ HWRITE_cpu,
+ HSIZE_cpu,
+ HBURST_cpu,
+ HPROT_cpu,
+ HWDATA_cpu,
+ HMASTLOCK_cpu,
+
+ // Output port MI0 (inputs from slave 0)
+ HRDATA_bootrom,
+ HREADYOUT_bootrom,
+ HRESP_bootrom,
+
+ // Output port MI1 (inputs from slave 1)
+ HRDATA_imem,
+ HREADYOUT_imem,
+ HRESP_imem,
+
+ // Output port MI2 (inputs from slave 2)
+ HRDATA_dmem,
+ HREADYOUT_dmem,
+ HRESP_dmem,
+
+ // Output port MI3 (inputs from slave 3)
+ HRDATA_sysio,
+ HREADYOUT_sysio,
+ HRESP_sysio,
+
+ // Output port MI4 (inputs from slave 4)
+ HRDATA_expram_l,
+ HREADYOUT_expram_l,
+ HRESP_expram_l,
+
+ // Output port MI5 (inputs from slave 5)
+ HRDATA_expram_h,
+ HREADYOUT_expram_h,
+ HRESP_expram_h,
+
+ // Output port MI6 (inputs from slave 6)
+ HRDATA_exp,
+ HREADYOUT_exp,
+ HRESP_exp,
+
+ // Output port MI7 (inputs from slave 7)
+ HRDATA_systable,
+ HREADYOUT_systable,
+ HRESP_systable,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANENABLE, // Scan Test Mode Enable
+ SCANINHCLK, // Scan Chain Input
+
+
+ // Output port MI0 (outputs to slave 0)
+ HSEL_bootrom,
+ HADDR_bootrom,
+ HTRANS_bootrom,
+ HWRITE_bootrom,
+ HSIZE_bootrom,
+ HBURST_bootrom,
+ HPROT_bootrom,
+ HWDATA_bootrom,
+ HMASTLOCK_bootrom,
+ HREADYMUX_bootrom,
+
+ // Output port MI1 (outputs to slave 1)
+ HSEL_imem,
+ HADDR_imem,
+ HTRANS_imem,
+ HWRITE_imem,
+ HSIZE_imem,
+ HBURST_imem,
+ HPROT_imem,
+ HWDATA_imem,
+ HMASTLOCK_imem,
+ HREADYMUX_imem,
+
+ // Output port MI2 (outputs to slave 2)
+ HSEL_dmem,
+ HADDR_dmem,
+ HTRANS_dmem,
+ HWRITE_dmem,
+ HSIZE_dmem,
+ HBURST_dmem,
+ HPROT_dmem,
+ HWDATA_dmem,
+ HMASTLOCK_dmem,
+ HREADYMUX_dmem,
+
+ // Output port MI3 (outputs to slave 3)
+ HSEL_sysio,
+ HADDR_sysio,
+ HTRANS_sysio,
+ HWRITE_sysio,
+ HSIZE_sysio,
+ HBURST_sysio,
+ HPROT_sysio,
+ HWDATA_sysio,
+ HMASTLOCK_sysio,
+ HREADYMUX_sysio,
+
+ // Output port MI4 (outputs to slave 4)
+ HSEL_expram_l,
+ HADDR_expram_l,
+ HTRANS_expram_l,
+ HWRITE_expram_l,
+ HSIZE_expram_l,
+ HBURST_expram_l,
+ HPROT_expram_l,
+ HWDATA_expram_l,
+ HMASTLOCK_expram_l,
+ HREADYMUX_expram_l,
+
+ // Output port MI5 (outputs to slave 5)
+ HSEL_expram_h,
+ HADDR_expram_h,
+ HTRANS_expram_h,
+ HWRITE_expram_h,
+ HSIZE_expram_h,
+ HBURST_expram_h,
+ HPROT_expram_h,
+ HWDATA_expram_h,
+ HMASTLOCK_expram_h,
+ HREADYMUX_expram_h,
+
+ // Output port MI6 (outputs to slave 6)
+ HSEL_exp,
+ HADDR_exp,
+ HTRANS_exp,
+ HWRITE_exp,
+ HSIZE_exp,
+ HBURST_exp,
+ HPROT_exp,
+ HWDATA_exp,
+ HMASTLOCK_exp,
+ HREADYMUX_exp,
+
+ // Output port MI7 (outputs to slave 7)
+ HSEL_systable,
+ HADDR_systable,
+ HTRANS_systable,
+ HWRITE_systable,
+ HSIZE_systable,
+ HBURST_systable,
+ HPROT_systable,
+ HWDATA_systable,
+ HMASTLOCK_systable,
+ HREADYMUX_systable,
+
+ // Input port SI0 (outputs to master 0)
+ HRDATA_socdebug,
+ HREADY_socdebug,
+ HRESP_socdebug,
+
+ // Input port SI1 (outputs to master 1)
+ HRDATA_dma_0,
+ HREADY_dma_0,
+ HRESP_dma_0,
+
+ // Input port SI2 (outputs to master 2)
+ HRDATA_dma_1,
+ HREADY_dma_1,
+ HRESP_dma_1,
+
+ // Input port SI3 (outputs to master 3)
+ HRDATA_cpu,
+ HREADY_cpu,
+ HRESP_cpu,
+
+ // Scan test dummy signals; not connected until scan insertion
+ SCANOUTHCLK // Scan Chain Output
+
+ );
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB System Clock
+ input HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ input [3:0] REMAP; // System Address REMAP control
+
+ // Input port SI0 (inputs from master 0)
+ input [31:0] HADDR_socdebug; // Address bus
+ input [1:0] HTRANS_socdebug; // Transfer type
+ input HWRITE_socdebug; // Transfer direction
+ input [2:0] HSIZE_socdebug; // Transfer size
+ input [2:0] HBURST_socdebug; // Burst type
+ input [3:0] HPROT_socdebug; // Protection control
+ input [31:0] HWDATA_socdebug; // Write data
+ input HMASTLOCK_socdebug; // Locked Sequence
+
+ // Input port SI1 (inputs from master 1)
+ input [31:0] HADDR_dma_0; // Address bus
+ input [1:0] HTRANS_dma_0; // Transfer type
+ input HWRITE_dma_0; // Transfer direction
+ input [2:0] HSIZE_dma_0; // Transfer size
+ input [2:0] HBURST_dma_0; // Burst type
+ input [3:0] HPROT_dma_0; // Protection control
+ input [31:0] HWDATA_dma_0; // Write data
+ input HMASTLOCK_dma_0; // Locked Sequence
+
+ // Input port SI2 (inputs from master 2)
+ input [31:0] HADDR_dma_1; // Address bus
+ input [1:0] HTRANS_dma_1; // Transfer type
+ input HWRITE_dma_1; // Transfer direction
+ input [2:0] HSIZE_dma_1; // Transfer size
+ input [2:0] HBURST_dma_1; // Burst type
+ input [3:0] HPROT_dma_1; // Protection control
+ input [31:0] HWDATA_dma_1; // Write data
+ input HMASTLOCK_dma_1; // Locked Sequence
+
+ // Input port SI3 (inputs from master 3)
+ input [31:0] HADDR_cpu; // Address bus
+ input [1:0] HTRANS_cpu; // Transfer type
+ input HWRITE_cpu; // Transfer direction
+ input [2:0] HSIZE_cpu; // Transfer size
+ input [2:0] HBURST_cpu; // Burst type
+ input [3:0] HPROT_cpu; // Protection control
+ input [31:0] HWDATA_cpu; // Write data
+ input HMASTLOCK_cpu; // Locked Sequence
+
+ // Output port MI0 (inputs from slave 0)
+ input [31:0] HRDATA_bootrom; // Read data bus
+ input HREADYOUT_bootrom; // HREADY feedback
+ input HRESP_bootrom; // Transfer response
+
+ // Output port MI1 (inputs from slave 1)
+ input [31:0] HRDATA_imem; // Read data bus
+ input HREADYOUT_imem; // HREADY feedback
+ input HRESP_imem; // Transfer response
+
+ // Output port MI2 (inputs from slave 2)
+ input [31:0] HRDATA_dmem; // Read data bus
+ input HREADYOUT_dmem; // HREADY feedback
+ input HRESP_dmem; // Transfer response
+
+ // Output port MI3 (inputs from slave 3)
+ input [31:0] HRDATA_sysio; // Read data bus
+ input HREADYOUT_sysio; // HREADY feedback
+ input HRESP_sysio; // Transfer response
+
+ // Output port MI4 (inputs from slave 4)
+ input [31:0] HRDATA_expram_l; // Read data bus
+ input HREADYOUT_expram_l; // HREADY feedback
+ input HRESP_expram_l; // Transfer response
+
+ // Output port MI5 (inputs from slave 5)
+ input [31:0] HRDATA_expram_h; // Read data bus
+ input HREADYOUT_expram_h; // HREADY feedback
+ input HRESP_expram_h; // Transfer response
+
+ // Output port MI6 (inputs from slave 6)
+ input [31:0] HRDATA_exp; // Read data bus
+ input HREADYOUT_exp; // HREADY feedback
+ input HRESP_exp; // Transfer response
+
+ // Output port MI7 (inputs from slave 7)
+ input [31:0] HRDATA_systable; // Read data bus
+ input HREADYOUT_systable; // HREADY feedback
+ input HRESP_systable; // Transfer response
+
+ // Scan test dummy signals; not connected until scan insertion
+ input SCANENABLE; // Scan enable signal
+ input SCANINHCLK; // HCLK scan input
+
+
+ // Output port MI0 (outputs to slave 0)
+ output HSEL_bootrom; // Slave Select
+ output [31:0] HADDR_bootrom; // Address bus
+ output [1:0] HTRANS_bootrom; // Transfer type
+ output HWRITE_bootrom; // Transfer direction
+ output [2:0] HSIZE_bootrom; // Transfer size
+ output [2:0] HBURST_bootrom; // Burst type
+ output [3:0] HPROT_bootrom; // Protection control
+ output [31:0] HWDATA_bootrom; // Write data
+ output HMASTLOCK_bootrom; // Locked Sequence
+ output HREADYMUX_bootrom; // Transfer done
+
+ // Output port MI1 (outputs to slave 1)
+ output HSEL_imem; // Slave Select
+ output [31:0] HADDR_imem; // Address bus
+ output [1:0] HTRANS_imem; // Transfer type
+ output HWRITE_imem; // Transfer direction
+ output [2:0] HSIZE_imem; // Transfer size
+ output [2:0] HBURST_imem; // Burst type
+ output [3:0] HPROT_imem; // Protection control
+ output [31:0] HWDATA_imem; // Write data
+ output HMASTLOCK_imem; // Locked Sequence
+ output HREADYMUX_imem; // Transfer done
+
+ // Output port MI2 (outputs to slave 2)
+ output HSEL_dmem; // Slave Select
+ output [31:0] HADDR_dmem; // Address bus
+ output [1:0] HTRANS_dmem; // Transfer type
+ output HWRITE_dmem; // Transfer direction
+ output [2:0] HSIZE_dmem; // Transfer size
+ output [2:0] HBURST_dmem; // Burst type
+ output [3:0] HPROT_dmem; // Protection control
+ output [31:0] HWDATA_dmem; // Write data
+ output HMASTLOCK_dmem; // Locked Sequence
+ output HREADYMUX_dmem; // Transfer done
+
+ // Output port MI3 (outputs to slave 3)
+ output HSEL_sysio; // Slave Select
+ output [31:0] HADDR_sysio; // Address bus
+ output [1:0] HTRANS_sysio; // Transfer type
+ output HWRITE_sysio; // Transfer direction
+ output [2:0] HSIZE_sysio; // Transfer size
+ output [2:0] HBURST_sysio; // Burst type
+ output [3:0] HPROT_sysio; // Protection control
+ output [31:0] HWDATA_sysio; // Write data
+ output HMASTLOCK_sysio; // Locked Sequence
+ output HREADYMUX_sysio; // Transfer done
+
+ // Output port MI4 (outputs to slave 4)
+ output HSEL_expram_l; // Slave Select
+ output [31:0] HADDR_expram_l; // Address bus
+ output [1:0] HTRANS_expram_l; // Transfer type
+ output HWRITE_expram_l; // Transfer direction
+ output [2:0] HSIZE_expram_l; // Transfer size
+ output [2:0] HBURST_expram_l; // Burst type
+ output [3:0] HPROT_expram_l; // Protection control
+ output [31:0] HWDATA_expram_l; // Write data
+ output HMASTLOCK_expram_l; // Locked Sequence
+ output HREADYMUX_expram_l; // Transfer done
+
+ // Output port MI5 (outputs to slave 5)
+ output HSEL_expram_h; // Slave Select
+ output [31:0] HADDR_expram_h; // Address bus
+ output [1:0] HTRANS_expram_h; // Transfer type
+ output HWRITE_expram_h; // Transfer direction
+ output [2:0] HSIZE_expram_h; // Transfer size
+ output [2:0] HBURST_expram_h; // Burst type
+ output [3:0] HPROT_expram_h; // Protection control
+ output [31:0] HWDATA_expram_h; // Write data
+ output HMASTLOCK_expram_h; // Locked Sequence
+ output HREADYMUX_expram_h; // Transfer done
+
+ // Output port MI6 (outputs to slave 6)
+ output HSEL_exp; // Slave Select
+ output [31:0] HADDR_exp; // Address bus
+ output [1:0] HTRANS_exp; // Transfer type
+ output HWRITE_exp; // Transfer direction
+ output [2:0] HSIZE_exp; // Transfer size
+ output [2:0] HBURST_exp; // Burst type
+ output [3:0] HPROT_exp; // Protection control
+ output [31:0] HWDATA_exp; // Write data
+ output HMASTLOCK_exp; // Locked Sequence
+ output HREADYMUX_exp; // Transfer done
+
+ // Output port MI7 (outputs to slave 7)
+ output HSEL_systable; // Slave Select
+ output [31:0] HADDR_systable; // Address bus
+ output [1:0] HTRANS_systable; // Transfer type
+ output HWRITE_systable; // Transfer direction
+ output [2:0] HSIZE_systable; // Transfer size
+ output [2:0] HBURST_systable; // Burst type
+ output [3:0] HPROT_systable; // Protection control
+ output [31:0] HWDATA_systable; // Write data
+ output HMASTLOCK_systable; // Locked Sequence
+ output HREADYMUX_systable; // Transfer done
+
+ // Input port SI0 (outputs to master 0)
+ output [31:0] HRDATA_socdebug; // Read data bus
+ output HREADY_socdebug; // HREADY feedback
+ output HRESP_socdebug; // Transfer response
+
+ // Input port SI1 (outputs to master 1)
+ output [31:0] HRDATA_dma_0; // Read data bus
+ output HREADY_dma_0; // HREADY feedback
+ output HRESP_dma_0; // Transfer response
+
+ // Input port SI2 (outputs to master 2)
+ output [31:0] HRDATA_dma_1; // Read data bus
+ output HREADY_dma_1; // HREADY feedback
+ output HRESP_dma_1; // Transfer response
+
+ // Input port SI3 (outputs to master 3)
+ output [31:0] HRDATA_cpu; // Read data bus
+ output HREADY_cpu; // HREADY feedback
+ output HRESP_cpu; // Transfer response
+
+ // Scan test dummy signals; not connected until scan insertion
+ output SCANOUTHCLK; // Scan Chain Output
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ wire HCLK; // AHB System Clock
+ wire HRESETn; // AHB System Reset
+
+ // System Address Remap control
+ wire [3:0] REMAP; // System REMAP signal
+
+ // Input Port SI0
+ wire [31:0] HADDR_socdebug; // Address bus
+ wire [1:0] HTRANS_socdebug; // Transfer type
+ wire HWRITE_socdebug; // Transfer direction
+ wire [2:0] HSIZE_socdebug; // Transfer size
+ wire [2:0] HBURST_socdebug; // Burst type
+ wire [3:0] HPROT_socdebug; // Protection control
+ wire [31:0] HWDATA_socdebug; // Write data
+ wire HMASTLOCK_socdebug; // Locked Sequence
+
+ wire [31:0] HRDATA_socdebug; // Read data bus
+ wire HREADY_socdebug; // HREADY feedback
+ wire HRESP_socdebug; // Transfer response
+
+ // Input Port SI1
+ wire [31:0] HADDR_dma_0; // Address bus
+ wire [1:0] HTRANS_dma_0; // Transfer type
+ wire HWRITE_dma_0; // Transfer direction
+ wire [2:0] HSIZE_dma_0; // Transfer size
+ wire [2:0] HBURST_dma_0; // Burst type
+ wire [3:0] HPROT_dma_0; // Protection control
+ wire [31:0] HWDATA_dma_0; // Write data
+ wire HMASTLOCK_dma_0; // Locked Sequence
+
+ wire [31:0] HRDATA_dma_0; // Read data bus
+ wire HREADY_dma_0; // HREADY feedback
+ wire HRESP_dma_0; // Transfer response
+
+ // Input Port SI2
+ wire [31:0] HADDR_dma_1; // Address bus
+ wire [1:0] HTRANS_dma_1; // Transfer type
+ wire HWRITE_dma_1; // Transfer direction
+ wire [2:0] HSIZE_dma_1; // Transfer size
+ wire [2:0] HBURST_dma_1; // Burst type
+ wire [3:0] HPROT_dma_1; // Protection control
+ wire [31:0] HWDATA_dma_1; // Write data
+ wire HMASTLOCK_dma_1; // Locked Sequence
+
+ wire [31:0] HRDATA_dma_1; // Read data bus
+ wire HREADY_dma_1; // HREADY feedback
+ wire HRESP_dma_1; // Transfer response
+
+ // Input Port SI3
+ wire [31:0] HADDR_cpu; // Address bus
+ wire [1:0] HTRANS_cpu; // Transfer type
+ wire HWRITE_cpu; // Transfer direction
+ wire [2:0] HSIZE_cpu; // Transfer size
+ wire [2:0] HBURST_cpu; // Burst type
+ wire [3:0] HPROT_cpu; // Protection control
+ wire [31:0] HWDATA_cpu; // Write data
+ wire HMASTLOCK_cpu; // Locked Sequence
+
+ wire [31:0] HRDATA_cpu; // Read data bus
+ wire HREADY_cpu; // HREADY feedback
+ wire HRESP_cpu; // Transfer response
+
+ // Output Port MI0
+ wire HSEL_bootrom; // Slave Select
+ wire [31:0] HADDR_bootrom; // Address bus
+ wire [1:0] HTRANS_bootrom; // Transfer type
+ wire HWRITE_bootrom; // Transfer direction
+ wire [2:0] HSIZE_bootrom; // Transfer size
+ wire [2:0] HBURST_bootrom; // Burst type
+ wire [3:0] HPROT_bootrom; // Protection control
+ wire [31:0] HWDATA_bootrom; // Write data
+ wire HMASTLOCK_bootrom; // Locked Sequence
+ wire HREADYMUX_bootrom; // Transfer done
+
+ wire [31:0] HRDATA_bootrom; // Read data bus
+ wire HREADYOUT_bootrom; // HREADY feedback
+ wire HRESP_bootrom; // Transfer response
+
+ // Output Port MI1
+ wire HSEL_imem; // Slave Select
+ wire [31:0] HADDR_imem; // Address bus
+ wire [1:0] HTRANS_imem; // Transfer type
+ wire HWRITE_imem; // Transfer direction
+ wire [2:0] HSIZE_imem; // Transfer size
+ wire [2:0] HBURST_imem; // Burst type
+ wire [3:0] HPROT_imem; // Protection control
+ wire [31:0] HWDATA_imem; // Write data
+ wire HMASTLOCK_imem; // Locked Sequence
+ wire HREADYMUX_imem; // Transfer done
+
+ wire [31:0] HRDATA_imem; // Read data bus
+ wire HREADYOUT_imem; // HREADY feedback
+ wire HRESP_imem; // Transfer response
+
+ // Output Port MI2
+ wire HSEL_dmem; // Slave Select
+ wire [31:0] HADDR_dmem; // Address bus
+ wire [1:0] HTRANS_dmem; // Transfer type
+ wire HWRITE_dmem; // Transfer direction
+ wire [2:0] HSIZE_dmem; // Transfer size
+ wire [2:0] HBURST_dmem; // Burst type
+ wire [3:0] HPROT_dmem; // Protection control
+ wire [31:0] HWDATA_dmem; // Write data
+ wire HMASTLOCK_dmem; // Locked Sequence
+ wire HREADYMUX_dmem; // Transfer done
+
+ wire [31:0] HRDATA_dmem; // Read data bus
+ wire HREADYOUT_dmem; // HREADY feedback
+ wire HRESP_dmem; // Transfer response
+
+ // Output Port MI3
+ wire HSEL_sysio; // Slave Select
+ wire [31:0] HADDR_sysio; // Address bus
+ wire [1:0] HTRANS_sysio; // Transfer type
+ wire HWRITE_sysio; // Transfer direction
+ wire [2:0] HSIZE_sysio; // Transfer size
+ wire [2:0] HBURST_sysio; // Burst type
+ wire [3:0] HPROT_sysio; // Protection control
+ wire [31:0] HWDATA_sysio; // Write data
+ wire HMASTLOCK_sysio; // Locked Sequence
+ wire HREADYMUX_sysio; // Transfer done
+
+ wire [31:0] HRDATA_sysio; // Read data bus
+ wire HREADYOUT_sysio; // HREADY feedback
+ wire HRESP_sysio; // Transfer response
+
+ // Output Port MI4
+ wire HSEL_expram_l; // Slave Select
+ wire [31:0] HADDR_expram_l; // Address bus
+ wire [1:0] HTRANS_expram_l; // Transfer type
+ wire HWRITE_expram_l; // Transfer direction
+ wire [2:0] HSIZE_expram_l; // Transfer size
+ wire [2:0] HBURST_expram_l; // Burst type
+ wire [3:0] HPROT_expram_l; // Protection control
+ wire [31:0] HWDATA_expram_l; // Write data
+ wire HMASTLOCK_expram_l; // Locked Sequence
+ wire HREADYMUX_expram_l; // Transfer done
+
+ wire [31:0] HRDATA_expram_l; // Read data bus
+ wire HREADYOUT_expram_l; // HREADY feedback
+ wire HRESP_expram_l; // Transfer response
+
+ // Output Port MI5
+ wire HSEL_expram_h; // Slave Select
+ wire [31:0] HADDR_expram_h; // Address bus
+ wire [1:0] HTRANS_expram_h; // Transfer type
+ wire HWRITE_expram_h; // Transfer direction
+ wire [2:0] HSIZE_expram_h; // Transfer size
+ wire [2:0] HBURST_expram_h; // Burst type
+ wire [3:0] HPROT_expram_h; // Protection control
+ wire [31:0] HWDATA_expram_h; // Write data
+ wire HMASTLOCK_expram_h; // Locked Sequence
+ wire HREADYMUX_expram_h; // Transfer done
+
+ wire [31:0] HRDATA_expram_h; // Read data bus
+ wire HREADYOUT_expram_h; // HREADY feedback
+ wire HRESP_expram_h; // Transfer response
+
+ // Output Port MI6
+ wire HSEL_exp; // Slave Select
+ wire [31:0] HADDR_exp; // Address bus
+ wire [1:0] HTRANS_exp; // Transfer type
+ wire HWRITE_exp; // Transfer direction
+ wire [2:0] HSIZE_exp; // Transfer size
+ wire [2:0] HBURST_exp; // Burst type
+ wire [3:0] HPROT_exp; // Protection control
+ wire [31:0] HWDATA_exp; // Write data
+ wire HMASTLOCK_exp; // Locked Sequence
+ wire HREADYMUX_exp; // Transfer done
+
+ wire [31:0] HRDATA_exp; // Read data bus
+ wire HREADYOUT_exp; // HREADY feedback
+ wire HRESP_exp; // Transfer response
+
+ // Output Port MI7
+ wire HSEL_systable; // Slave Select
+ wire [31:0] HADDR_systable; // Address bus
+ wire [1:0] HTRANS_systable; // Transfer type
+ wire HWRITE_systable; // Transfer direction
+ wire [2:0] HSIZE_systable; // Transfer size
+ wire [2:0] HBURST_systable; // Burst type
+ wire [3:0] HPROT_systable; // Protection control
+ wire [31:0] HWDATA_systable; // Write data
+ wire HMASTLOCK_systable; // Locked Sequence
+ wire HREADYMUX_systable; // Transfer done
+
+ wire [31:0] HRDATA_systable; // Read data bus
+ wire HREADYOUT_systable; // HREADY feedback
+ wire HRESP_systable; // Transfer response
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire [3:0] tie_hi_4;
+ wire tie_hi;
+ wire tie_low;
+ wire [1:0] i_hresp_socdebug;
+ wire [1:0] i_hresp_dma_0;
+ wire [1:0] i_hresp_dma_1;
+ wire [1:0] i_hresp_cpu;
+
+ wire [3:0] i_hmaster_bootrom;
+ wire [1:0] i_hresp_bootrom;
+ wire [3:0] i_hmaster_imem;
+ wire [1:0] i_hresp_imem;
+ wire [3:0] i_hmaster_dmem;
+ wire [1:0] i_hresp_dmem;
+ wire [3:0] i_hmaster_sysio;
+ wire [1:0] i_hresp_sysio;
+ wire [3:0] i_hmaster_expram_l;
+ wire [1:0] i_hresp_expram_l;
+ wire [3:0] i_hmaster_expram_h;
+ wire [1:0] i_hresp_expram_h;
+ wire [3:0] i_hmaster_exp;
+ wire [1:0] i_hresp_exp;
+ wire [3:0] i_hmaster_systable;
+ wire [1:0] i_hresp_systable;
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+ assign tie_hi = 1'b1;
+ assign tie_hi_4 = 4'b1111;
+ assign tie_low = 1'b0;
+
+
+ assign HRESP_socdebug = i_hresp_socdebug[0];
+
+ assign HRESP_dma_0 = i_hresp_dma_0[0];
+
+ assign HRESP_dma_1 = i_hresp_dma_1[0];
+
+ assign HRESP_cpu = i_hresp_cpu[0];
+
+ assign i_hresp_bootrom = {{1{tie_low}}, HRESP_bootrom};
+ assign i_hresp_imem = {{1{tie_low}}, HRESP_imem};
+ assign i_hresp_dmem = {{1{tie_low}}, HRESP_dmem};
+ assign i_hresp_sysio = {{1{tie_low}}, HRESP_sysio};
+ assign i_hresp_expram_l = {{1{tie_low}}, HRESP_expram_l};
+ assign i_hresp_expram_h = {{1{tie_low}}, HRESP_expram_h};
+ assign i_hresp_exp = {{1{tie_low}}, HRESP_exp};
+ assign i_hresp_systable = {{1{tie_low}}, HRESP_systable};
+
+// BusMatrix instance
+ nanosoc_busmatrix unanosoc_busmatrix (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .REMAP (REMAP),
+
+ // Input port SI0 signals
+ .HSEL_socdebug (tie_hi),
+ .HADDR_socdebug (HADDR_socdebug),
+ .HTRANS_socdebug (HTRANS_socdebug),
+ .HWRITE_socdebug (HWRITE_socdebug),
+ .HSIZE_socdebug (HSIZE_socdebug),
+ .HBURST_socdebug (HBURST_socdebug),
+ .HPROT_socdebug (HPROT_socdebug),
+ .HWDATA_socdebug (HWDATA_socdebug),
+ .HMASTLOCK_socdebug (HMASTLOCK_socdebug),
+ .HMASTER_socdebug (tie_hi_4),
+ .HREADY_socdebug (HREADY_socdebug),
+ .HRDATA_socdebug (HRDATA_socdebug),
+ .HREADYOUT_socdebug (HREADY_socdebug),
+ .HRESP_socdebug (i_hresp_socdebug),
+
+ // Input port SI1 signals
+ .HSEL_dma_0 (tie_hi),
+ .HADDR_dma_0 (HADDR_dma_0),
+ .HTRANS_dma_0 (HTRANS_dma_0),
+ .HWRITE_dma_0 (HWRITE_dma_0),
+ .HSIZE_dma_0 (HSIZE_dma_0),
+ .HBURST_dma_0 (HBURST_dma_0),
+ .HPROT_dma_0 (HPROT_dma_0),
+ .HWDATA_dma_0 (HWDATA_dma_0),
+ .HMASTLOCK_dma_0 (HMASTLOCK_dma_0),
+ .HMASTER_dma_0 (tie_hi_4),
+ .HREADY_dma_0 (HREADY_dma_0),
+ .HRDATA_dma_0 (HRDATA_dma_0),
+ .HREADYOUT_dma_0 (HREADY_dma_0),
+ .HRESP_dma_0 (i_hresp_dma_0),
+
+ // Input port SI2 signals
+ .HSEL_dma_1 (tie_hi),
+ .HADDR_dma_1 (HADDR_dma_1),
+ .HTRANS_dma_1 (HTRANS_dma_1),
+ .HWRITE_dma_1 (HWRITE_dma_1),
+ .HSIZE_dma_1 (HSIZE_dma_1),
+ .HBURST_dma_1 (HBURST_dma_1),
+ .HPROT_dma_1 (HPROT_dma_1),
+ .HWDATA_dma_1 (HWDATA_dma_1),
+ .HMASTLOCK_dma_1 (HMASTLOCK_dma_1),
+ .HMASTER_dma_1 (tie_hi_4),
+ .HREADY_dma_1 (HREADY_dma_1),
+ .HRDATA_dma_1 (HRDATA_dma_1),
+ .HREADYOUT_dma_1 (HREADY_dma_1),
+ .HRESP_dma_1 (i_hresp_dma_1),
+
+ // Input port SI3 signals
+ .HSEL_cpu (tie_hi),
+ .HADDR_cpu (HADDR_cpu),
+ .HTRANS_cpu (HTRANS_cpu),
+ .HWRITE_cpu (HWRITE_cpu),
+ .HSIZE_cpu (HSIZE_cpu),
+ .HBURST_cpu (HBURST_cpu),
+ .HPROT_cpu (HPROT_cpu),
+ .HWDATA_cpu (HWDATA_cpu),
+ .HMASTLOCK_cpu (HMASTLOCK_cpu),
+ .HMASTER_cpu (tie_hi_4),
+ .HREADY_cpu (HREADY_cpu),
+ .HRDATA_cpu (HRDATA_cpu),
+ .HREADYOUT_cpu (HREADY_cpu),
+ .HRESP_cpu (i_hresp_cpu),
+
+
+ // Output port MI0 signals
+ .HSEL_bootrom (HSEL_bootrom),
+ .HADDR_bootrom (HADDR_bootrom),
+ .HTRANS_bootrom (HTRANS_bootrom),
+ .HWRITE_bootrom (HWRITE_bootrom),
+ .HSIZE_bootrom (HSIZE_bootrom),
+ .HBURST_bootrom (HBURST_bootrom),
+ .HPROT_bootrom (HPROT_bootrom),
+ .HWDATA_bootrom (HWDATA_bootrom),
+ .HMASTER_bootrom (i_hmaster_bootrom),
+ .HMASTLOCK_bootrom (HMASTLOCK_bootrom),
+ .HREADYMUX_bootrom (HREADYMUX_bootrom),
+ .HRDATA_bootrom (HRDATA_bootrom),
+ .HREADYOUT_bootrom (HREADYOUT_bootrom),
+ .HRESP_bootrom (i_hresp_bootrom),
+
+ // Output port MI1 signals
+ .HSEL_imem (HSEL_imem),
+ .HADDR_imem (HADDR_imem),
+ .HTRANS_imem (HTRANS_imem),
+ .HWRITE_imem (HWRITE_imem),
+ .HSIZE_imem (HSIZE_imem),
+ .HBURST_imem (HBURST_imem),
+ .HPROT_imem (HPROT_imem),
+ .HWDATA_imem (HWDATA_imem),
+ .HMASTER_imem (i_hmaster_imem),
+ .HMASTLOCK_imem (HMASTLOCK_imem),
+ .HREADYMUX_imem (HREADYMUX_imem),
+ .HRDATA_imem (HRDATA_imem),
+ .HREADYOUT_imem (HREADYOUT_imem),
+ .HRESP_imem (i_hresp_imem),
+
+ // Output port MI2 signals
+ .HSEL_dmem (HSEL_dmem),
+ .HADDR_dmem (HADDR_dmem),
+ .HTRANS_dmem (HTRANS_dmem),
+ .HWRITE_dmem (HWRITE_dmem),
+ .HSIZE_dmem (HSIZE_dmem),
+ .HBURST_dmem (HBURST_dmem),
+ .HPROT_dmem (HPROT_dmem),
+ .HWDATA_dmem (HWDATA_dmem),
+ .HMASTER_dmem (i_hmaster_dmem),
+ .HMASTLOCK_dmem (HMASTLOCK_dmem),
+ .HREADYMUX_dmem (HREADYMUX_dmem),
+ .HRDATA_dmem (HRDATA_dmem),
+ .HREADYOUT_dmem (HREADYOUT_dmem),
+ .HRESP_dmem (i_hresp_dmem),
+
+ // Output port MI3 signals
+ .HSEL_sysio (HSEL_sysio),
+ .HADDR_sysio (HADDR_sysio),
+ .HTRANS_sysio (HTRANS_sysio),
+ .HWRITE_sysio (HWRITE_sysio),
+ .HSIZE_sysio (HSIZE_sysio),
+ .HBURST_sysio (HBURST_sysio),
+ .HPROT_sysio (HPROT_sysio),
+ .HWDATA_sysio (HWDATA_sysio),
+ .HMASTER_sysio (i_hmaster_sysio),
+ .HMASTLOCK_sysio (HMASTLOCK_sysio),
+ .HREADYMUX_sysio (HREADYMUX_sysio),
+ .HRDATA_sysio (HRDATA_sysio),
+ .HREADYOUT_sysio (HREADYOUT_sysio),
+ .HRESP_sysio (i_hresp_sysio),
+
+ // Output port MI4 signals
+ .HSEL_expram_l (HSEL_expram_l),
+ .HADDR_expram_l (HADDR_expram_l),
+ .HTRANS_expram_l (HTRANS_expram_l),
+ .HWRITE_expram_l (HWRITE_expram_l),
+ .HSIZE_expram_l (HSIZE_expram_l),
+ .HBURST_expram_l (HBURST_expram_l),
+ .HPROT_expram_l (HPROT_expram_l),
+ .HWDATA_expram_l (HWDATA_expram_l),
+ .HMASTER_expram_l (i_hmaster_expram_l),
+ .HMASTLOCK_expram_l (HMASTLOCK_expram_l),
+ .HREADYMUX_expram_l (HREADYMUX_expram_l),
+ .HRDATA_expram_l (HRDATA_expram_l),
+ .HREADYOUT_expram_l (HREADYOUT_expram_l),
+ .HRESP_expram_l (i_hresp_expram_l),
+
+ // Output port MI5 signals
+ .HSEL_expram_h (HSEL_expram_h),
+ .HADDR_expram_h (HADDR_expram_h),
+ .HTRANS_expram_h (HTRANS_expram_h),
+ .HWRITE_expram_h (HWRITE_expram_h),
+ .HSIZE_expram_h (HSIZE_expram_h),
+ .HBURST_expram_h (HBURST_expram_h),
+ .HPROT_expram_h (HPROT_expram_h),
+ .HWDATA_expram_h (HWDATA_expram_h),
+ .HMASTER_expram_h (i_hmaster_expram_h),
+ .HMASTLOCK_expram_h (HMASTLOCK_expram_h),
+ .HREADYMUX_expram_h (HREADYMUX_expram_h),
+ .HRDATA_expram_h (HRDATA_expram_h),
+ .HREADYOUT_expram_h (HREADYOUT_expram_h),
+ .HRESP_expram_h (i_hresp_expram_h),
+
+ // Output port MI6 signals
+ .HSEL_exp (HSEL_exp),
+ .HADDR_exp (HADDR_exp),
+ .HTRANS_exp (HTRANS_exp),
+ .HWRITE_exp (HWRITE_exp),
+ .HSIZE_exp (HSIZE_exp),
+ .HBURST_exp (HBURST_exp),
+ .HPROT_exp (HPROT_exp),
+ .HWDATA_exp (HWDATA_exp),
+ .HMASTER_exp (i_hmaster_exp),
+ .HMASTLOCK_exp (HMASTLOCK_exp),
+ .HREADYMUX_exp (HREADYMUX_exp),
+ .HRDATA_exp (HRDATA_exp),
+ .HREADYOUT_exp (HREADYOUT_exp),
+ .HRESP_exp (i_hresp_exp),
+
+ // Output port MI7 signals
+ .HSEL_systable (HSEL_systable),
+ .HADDR_systable (HADDR_systable),
+ .HTRANS_systable (HTRANS_systable),
+ .HWRITE_systable (HWRITE_systable),
+ .HSIZE_systable (HSIZE_systable),
+ .HBURST_systable (HBURST_systable),
+ .HPROT_systable (HPROT_systable),
+ .HWDATA_systable (HWDATA_systable),
+ .HMASTER_systable (i_hmaster_systable),
+ .HMASTLOCK_systable (HMASTLOCK_systable),
+ .HREADYMUX_systable (HREADYMUX_systable),
+ .HRDATA_systable (HRDATA_systable),
+ .HREADYOUT_systable (HREADYOUT_systable),
+ .HRESP_systable (i_hresp_systable),
+
+
+ // Scan test dummy signals; not connected until scan insertion
+ .SCANENABLE (SCANENABLE),
+ .SCANINHCLK (SCANINHCLK),
+ .SCANOUTHCLK (SCANOUTHCLK)
+ );
+
+
+endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
similarity index 97%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
index f44b208ff4aa4909edc5a1fafd20867a342d7dfa..d770544cbae49d558bc2dc307f80a4a09ec16aa3 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
@@ -29,7 +29,7 @@
-module nanosoc_ahb32_4x7_inititator_input (
+module nanosoc_inititator_input (
// Common AHB signals
HCLK,
@@ -38,7 +38,6 @@ module nanosoc_ahb32_4x7_inititator_input (
// Input Port Address/Control Signals
HSELS,
HADDRS,
- HAUSERS,
HTRANSS,
HWRITES,
HSIZES,
@@ -60,7 +59,6 @@ module nanosoc_ahb32_4x7_inititator_input (
// Internal Address/Control Signals
sel_ip,
addr_ip,
- auser_ip,
trans_ip,
write_ip,
size_ip,
@@ -81,7 +79,6 @@ module nanosoc_ahb32_4x7_inititator_input (
input HRESETn; // AHB System Reset
input HSELS; // Slave Select from AHB
input [31:0] HADDRS; // Address bus from AHB
- input [1:0] HAUSERS; // Additional user adress bus
input [1:0] HTRANSS; // Transfer type from AHB
input HWRITES; // Transfer direction from AHB
input [2:0] HSIZES; // Transfer size from AHB
@@ -98,7 +95,6 @@ module nanosoc_ahb32_4x7_inititator_input (
output [1:0] HRESPS; // Transfer response to AHB
output sel_ip; // HSEL output
output [31:0] addr_ip; // HADDR output
- output [1:0] auser_ip; // HAUSER output
output [1:0] trans_ip; // HTRANS output
output write_ip; // HWRITE output
output [2:0] size_ip; // HSIZE output
@@ -144,7 +140,6 @@ module nanosoc_ahb32_4x7_inititator_input (
wire HRESETn; // AHB System Reset
wire HSELS; // Slave Select from AHB
wire [31:0] HADDRS; // Address bus from AHB
- wire [1:0] HAUSERS; // Additional user adress bus
wire [1:0] HTRANSS; // Transfer type from AHB
wire HWRITES; // Transfer direction from AHB
wire [2:0] HSIZES; // Transfer size from AHB
@@ -157,7 +152,6 @@ module nanosoc_ahb32_4x7_inititator_input (
reg [1:0] HRESPS; // Transfer response to AHB
reg sel_ip; // HSEL output
reg [31:0] addr_ip; // HADDR output
- reg [1:0] auser_ip; // HAUSER output
wire [1:0] trans_ip; // HTRANS output
reg write_ip; // HWRITE output
reg [2:0] size_ip; // HSIZE output
@@ -184,7 +178,6 @@ module nanosoc_ahb32_4x7_inititator_input (
// valid transfer
reg [1:0] reg_trans; // Registered HTRANSS
reg [31:0] reg_addr; // Registered HADDRS
- reg [1:0] reg_auser;
reg reg_write; // Registered HWRITES
reg [2:0] reg_size; // Registered HSIZES
reg [2:0] reg_burst; // Registered HBURSTS
@@ -221,7 +214,6 @@ module nanosoc_ahb32_4x7_inititator_input (
begin
reg_trans <= 2'b00;
reg_addr <= {32{1'b0}};
- reg_auser <= {2{1'b0}};
reg_write <= 1'b0 ;
reg_size <= 3'b000;
reg_burst <= 3'b000;
@@ -234,7 +226,6 @@ module nanosoc_ahb32_4x7_inititator_input (
begin
reg_trans <= HTRANSS;
reg_addr <= HADDRS;
- reg_auser <= HAUSERS;
reg_write <= HWRITES;
reg_size <= HSIZES;
reg_burst <= HBURSTS;
@@ -301,7 +292,6 @@ module nanosoc_ahb32_4x7_inititator_input (
always @ ( pend_tran_reg or HSELS or HTRANSS or HADDRS or HWRITES or
HSIZES or HBURSTS or HPROTS or HMASTERS or HMASTLOCKS or
- HAUSERS or reg_auser or
reg_addr or reg_write or reg_size or reg_burst or reg_prot or
reg_master or reg_mastlock
)
@@ -311,7 +301,6 @@ module nanosoc_ahb32_4x7_inititator_input (
sel_ip = HSELS;
trans_int = HTRANSS;
addr_ip = HADDRS;
- auser_ip = HAUSERS;
write_ip = HWRITES;
size_ip = HSIZES;
burst_int = HBURSTS;
@@ -324,7 +313,6 @@ module nanosoc_ahb32_4x7_inititator_input (
sel_ip = 1'b1;
trans_int = `TRN_NONSEQ;
addr_ip = reg_addr;
- auser_ip = reg_auser;
write_ip = reg_write;
size_ip = reg_size;
burst_int = reg_burst;
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_cpu.v
similarity index 91%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_cpu.v
index f918dcb94daa5b41ca7e961395e6ac7b9f9209aa..6ef8fbc7fe46b4fee26a14cc28d856d4f1fe86e9 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_cpu.v
@@ -27,13 +27,13 @@
// that do not map to an Output port are diverted to
// the local default slave.
//
-// Notes : The bus matrix has full connectivity.
+// Notes : The bus matrix has sparse connectivity.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_matrix_decode_cpu (
+module nanosoc_matrix_decode_cpu (
// Common AHB signals
HCLK,
@@ -53,49 +53,48 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
readyout_dec0,
resp_dec0,
rdata_dec0,
- ruser_dec0,
// Bus-switch output 1
active_dec1,
readyout_dec1,
resp_dec1,
rdata_dec1,
- ruser_dec1,
// Bus-switch output 2
active_dec2,
readyout_dec2,
resp_dec2,
rdata_dec2,
- ruser_dec2,
// Bus-switch output 3
active_dec3,
readyout_dec3,
resp_dec3,
rdata_dec3,
- ruser_dec3,
// Bus-switch output 4
active_dec4,
readyout_dec4,
resp_dec4,
rdata_dec4,
- ruser_dec4,
// Bus-switch output 5
active_dec5,
readyout_dec5,
resp_dec5,
rdata_dec5,
- ruser_dec5,
// Bus-switch output 6
active_dec6,
readyout_dec6,
resp_dec6,
rdata_dec6,
- ruser_dec6,
+
+ // Bus-switch output 7
+ active_dec7,
+ readyout_dec7,
+ resp_dec7,
+ rdata_dec7,
// Output port selection signals
sel_dec0,
@@ -105,12 +104,12 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
sel_dec4,
sel_dec5,
sel_dec6,
+ sel_dec7,
// Selected Output port data and control signals
active_dec,
HREADYOUTS,
HRESPS,
- HRUSERS,
HRDATAS
);
@@ -138,49 +137,48 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
input readyout_dec0; // HREADYOUT input
input [1:0] resp_dec0; // HRESP input
input [31:0] rdata_dec0; // HRDATA input
- input [1:0] ruser_dec0; // HRUSER input
// Bus-switch output MI1
input active_dec1; // Output stage MI1 active_dec signal
input readyout_dec1; // HREADYOUT input
input [1:0] resp_dec1; // HRESP input
input [31:0] rdata_dec1; // HRDATA input
- input [1:0] ruser_dec1; // HRUSER input
// Bus-switch output MI2
input active_dec2; // Output stage MI2 active_dec signal
input readyout_dec2; // HREADYOUT input
input [1:0] resp_dec2; // HRESP input
input [31:0] rdata_dec2; // HRDATA input
- input [1:0] ruser_dec2; // HRUSER input
// Bus-switch output MI3
input active_dec3; // Output stage MI3 active_dec signal
input readyout_dec3; // HREADYOUT input
input [1:0] resp_dec3; // HRESP input
input [31:0] rdata_dec3; // HRDATA input
- input [1:0] ruser_dec3; // HRUSER input
// Bus-switch output MI4
input active_dec4; // Output stage MI4 active_dec signal
input readyout_dec4; // HREADYOUT input
input [1:0] resp_dec4; // HRESP input
input [31:0] rdata_dec4; // HRDATA input
- input [1:0] ruser_dec4; // HRUSER input
// Bus-switch output MI5
input active_dec5; // Output stage MI5 active_dec signal
input readyout_dec5; // HREADYOUT input
input [1:0] resp_dec5; // HRESP input
input [31:0] rdata_dec5; // HRDATA input
- input [1:0] ruser_dec5; // HRUSER input
// Bus-switch output MI6
input active_dec6; // Output stage MI6 active_dec signal
input readyout_dec6; // HREADYOUT input
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
- input [1:0] ruser_dec6; // HRUSER input
+
+ // Bus-switch output MI7
+ input active_dec7; // Output stage MI7 active_dec signal
+ input readyout_dec7; // HREADYOUT input
+ input [1:0] resp_dec7; // HRESP input
+ input [31:0] rdata_dec7; // HRDATA input
// Output port selection signals
output sel_dec0; // HSEL output
@@ -190,12 +188,12 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
output sel_dec4; // HSEL output
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
+ output sel_dec7; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
output HREADYOUTS; // HREADY feedback output
output [1:0] HRESPS; // Transfer response
- output [1:0] HRUSERS; // User read Data
output [31:0] HRDATAS; // Read Data
@@ -220,7 +218,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec0; // HREADYOUT input
wire [1:0] resp_dec0; // HRESP input
wire [31:0] rdata_dec0; // HRDATA input
- wire [1:0] ruser_dec0; // HRUSER input
reg sel_dec0; // HSEL output
// Bus-switch output MI1
@@ -228,7 +225,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec1; // HREADYOUT input
wire [1:0] resp_dec1; // HRESP input
wire [31:0] rdata_dec1; // HRDATA input
- wire [1:0] ruser_dec1; // HRUSER input
reg sel_dec1; // HSEL output
// Bus-switch output MI2
@@ -236,7 +232,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec2; // HREADYOUT input
wire [1:0] resp_dec2; // HRESP input
wire [31:0] rdata_dec2; // HRDATA input
- wire [1:0] ruser_dec2; // HRUSER input
reg sel_dec2; // HSEL output
// Bus-switch output MI3
@@ -244,7 +239,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec3; // HREADYOUT input
wire [1:0] resp_dec3; // HRESP input
wire [31:0] rdata_dec3; // HRDATA input
- wire [1:0] ruser_dec3; // HRUSER input
reg sel_dec3; // HSEL output
// Bus-switch output MI4
@@ -252,7 +246,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec4; // HREADYOUT input
wire [1:0] resp_dec4; // HRESP input
wire [31:0] rdata_dec4; // HRDATA input
- wire [1:0] ruser_dec4; // HRUSER input
reg sel_dec4; // HSEL output
// Bus-switch output MI5
@@ -260,7 +253,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec5; // HREADYOUT input
wire [1:0] resp_dec5; // HRESP input
wire [31:0] rdata_dec5; // HRDATA input
- wire [1:0] ruser_dec5; // HRUSER input
reg sel_dec5; // HSEL output
// Bus-switch output MI6
@@ -268,9 +260,15 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
wire readyout_dec6; // HREADYOUT input
wire [1:0] resp_dec6; // HRESP input
wire [31:0] rdata_dec6; // HRDATA input
- wire [1:0] ruser_dec6; // HRUSER input
reg sel_dec6; // HSEL output
+ // Bus-switch output MI7
+ wire active_dec7; // active_dec signal
+ wire readyout_dec7; // HREADYOUT input
+ wire [1:0] resp_dec7; // HRESP input
+ wire [31:0] rdata_dec7; // HRDATA input
+ reg sel_dec7; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -280,7 +278,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
reg active_dec; // Combinatorial active_dec O/P signal
reg HREADYOUTS; // Combinatorial HREADYOUT signal
reg [1:0] HRESPS; // Combinatorial HRESPS signal
- reg [1:0] HRUSERS;
reg [31:0] HRDATAS; // Read data bus
reg [3:0] addr_out_port; // Address output ports
@@ -300,7 +297,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- nanosoc_ahb32_4x7_busmatrix_default_slave u_nanosoc_ahb32_4x7_busmatrix_default_slave (
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
@@ -357,9 +354,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
addr_out_port = 4'b0011; // Select Output port MI3
- // Static address region 0xf0000000-0xf003ffff
- else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0011; // Select Output port MI3
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
@@ -376,6 +370,10 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0111; // Select Output port MI7
+
else
addr_out_port = 4'b1000; // Select the default slave
end
@@ -403,9 +401,6 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
addr_out_port = 4'b0011; // Select Output port MI3
- // Static address region 0xf0000000-0xf003ffff
- else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0011; // Select Output port MI3
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
@@ -422,6 +417,10 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0111; // Select Output port MI7
+
else
addr_out_port = 4'b1000; // Select the default slave
end
@@ -445,6 +444,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
sel_dec4 = 1'b0;
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
+ sel_dec7 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
@@ -456,6 +456,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
4'b0100 : sel_dec4 = 1'b1;
4'b0101 : sel_dec5 = 1'b1;
4'b0110 : sel_dec6 = 1'b1;
+ 4'b0111 : sel_dec7 = 1'b1;
4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
@@ -465,6 +466,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
sel_dec4 = 1'bx;
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
+ sel_dec7 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -480,6 +482,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
active_dec4 or
active_dec5 or
active_dec6 or
+ active_dec7 or
addr_out_port
)
begin : p_active_comb
@@ -491,6 +494,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
4'b0100 : active_dec = active_dec4;
4'b0101 : active_dec = active_dec5;
4'b0110 : active_dec = active_dec6;
+ 4'b0111 : active_dec = active_dec7;
4'b1000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
@@ -530,6 +534,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
readyout_dec4 or
readyout_dec5 or
readyout_dec6 or
+ readyout_dec7 or
data_out_port
)
begin : p_ready_comb
@@ -541,6 +546,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
4'b0100 : HREADYOUTS = readyout_dec4;
4'b0101 : HREADYOUTS = readyout_dec5;
4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b0111 : HREADYOUTS = readyout_dec7;
4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
@@ -556,6 +562,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
resp_dec4 or
resp_dec5 or
resp_dec6 or
+ resp_dec7 or
data_out_port
)
begin : p_resp_comb
@@ -567,6 +574,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
4'b0100 : HRESPS = resp_dec4;
4'b0101 : HRESPS = resp_dec5;
4'b0110 : HRESPS = resp_dec6;
+ 4'b0111 : HRESPS = resp_dec7;
4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
@@ -581,6 +589,7 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
rdata_dec4 or
rdata_dec5 or
rdata_dec6 or
+ rdata_dec7 or
data_out_port
)
begin : p_rdata_comb
@@ -592,36 +601,12 @@ module nanosoc_ahb32_4x7_matrix_decode_cpu (
4'b0100 : HRDATAS = rdata_dec4;
4'b0101 : HRDATAS = rdata_dec5;
4'b0110 : HRDATAS = rdata_dec6;
+ 4'b0111 : HRDATAS = rdata_dec7;
4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
- // HRUSERS output decode
- always @ (
- ruser_dec0 or
- ruser_dec1 or
- ruser_dec2 or
- ruser_dec3 or
- ruser_dec4 or
- ruser_dec5 or
- ruser_dec6 or
- data_out_port
- )
- begin : p_ruser_comb
- case (data_out_port)
- 4'b0000 : HRUSERS = ruser_dec0;
- 4'b0001 : HRUSERS = ruser_dec1;
- 4'b0010 : HRUSERS = ruser_dec2;
- 4'b0011 : HRUSERS = ruser_dec3;
- 4'b0100 : HRUSERS = ruser_dec4;
- 4'b0101 : HRUSERS = ruser_dec5;
- 4'b0110 : HRUSERS = ruser_dec6;
- 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
- default : HRUSERS = {2{1'bx}};
- endcase // case (data_out_port)
- end // block: p_ruser_comb
-
endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_0.v
similarity index 90%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_0.v
index 8620f63109a1386e426090a04163c037b97b5b4d..19ffc405f9ac202b3d3fc54addda7307754179c7 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_0.v
@@ -27,13 +27,13 @@
// that do not map to an Output port are diverted to
// the local default slave.
//
-// Notes : The bus matrix has full connectivity.
+// Notes : The bus matrix has sparse connectivity.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_matrix_decode_dma (
+module nanosoc_matrix_decode_dma_0 (
// Common AHB signals
HCLK,
@@ -50,49 +50,42 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
readyout_dec0,
resp_dec0,
rdata_dec0,
- ruser_dec0,
// Bus-switch output 1
active_dec1,
readyout_dec1,
resp_dec1,
rdata_dec1,
- ruser_dec1,
// Bus-switch output 2
active_dec2,
readyout_dec2,
resp_dec2,
rdata_dec2,
- ruser_dec2,
// Bus-switch output 3
active_dec3,
readyout_dec3,
resp_dec3,
rdata_dec3,
- ruser_dec3,
// Bus-switch output 4
active_dec4,
readyout_dec4,
resp_dec4,
rdata_dec4,
- ruser_dec4,
// Bus-switch output 5
active_dec5,
readyout_dec5,
resp_dec5,
rdata_dec5,
- ruser_dec5,
// Bus-switch output 6
active_dec6,
readyout_dec6,
resp_dec6,
rdata_dec6,
- ruser_dec6,
// Output port selection signals
sel_dec0,
@@ -107,7 +100,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
active_dec,
HREADYOUTS,
HRESPS,
- HRUSERS,
HRDATAS
);
@@ -132,49 +124,42 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
input readyout_dec0; // HREADYOUT input
input [1:0] resp_dec0; // HRESP input
input [31:0] rdata_dec0; // HRDATA input
- input [1:0] ruser_dec0; // HRUSER input
// Bus-switch output MI1
input active_dec1; // Output stage MI1 active_dec signal
input readyout_dec1; // HREADYOUT input
input [1:0] resp_dec1; // HRESP input
input [31:0] rdata_dec1; // HRDATA input
- input [1:0] ruser_dec1; // HRUSER input
// Bus-switch output MI2
input active_dec2; // Output stage MI2 active_dec signal
input readyout_dec2; // HREADYOUT input
input [1:0] resp_dec2; // HRESP input
input [31:0] rdata_dec2; // HRDATA input
- input [1:0] ruser_dec2; // HRUSER input
// Bus-switch output MI3
input active_dec3; // Output stage MI3 active_dec signal
input readyout_dec3; // HREADYOUT input
input [1:0] resp_dec3; // HRESP input
input [31:0] rdata_dec3; // HRDATA input
- input [1:0] ruser_dec3; // HRUSER input
// Bus-switch output MI4
input active_dec4; // Output stage MI4 active_dec signal
input readyout_dec4; // HREADYOUT input
input [1:0] resp_dec4; // HRESP input
input [31:0] rdata_dec4; // HRDATA input
- input [1:0] ruser_dec4; // HRUSER input
// Bus-switch output MI5
input active_dec5; // Output stage MI5 active_dec signal
input readyout_dec5; // HREADYOUT input
input [1:0] resp_dec5; // HRESP input
input [31:0] rdata_dec5; // HRDATA input
- input [1:0] ruser_dec5; // HRUSER input
// Bus-switch output MI6
input active_dec6; // Output stage MI6 active_dec signal
input readyout_dec6; // HREADYOUT input
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
- input [1:0] ruser_dec6; // HRUSER input
// Output port selection signals
output sel_dec0; // HSEL output
@@ -189,7 +174,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
output active_dec; // Combinatorial active_dec O/P
output HREADYOUTS; // HREADY feedback output
output [1:0] HRESPS; // Transfer response
- output [1:0] HRUSERS; // User read Data
output [31:0] HRDATAS; // Read Data
@@ -212,7 +196,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec0; // HREADYOUT input
wire [1:0] resp_dec0; // HRESP input
wire [31:0] rdata_dec0; // HRDATA input
- wire [1:0] ruser_dec0; // HRUSER input
reg sel_dec0; // HSEL output
// Bus-switch output MI1
@@ -220,7 +203,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec1; // HREADYOUT input
wire [1:0] resp_dec1; // HRESP input
wire [31:0] rdata_dec1; // HRDATA input
- wire [1:0] ruser_dec1; // HRUSER input
reg sel_dec1; // HSEL output
// Bus-switch output MI2
@@ -228,7 +210,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec2; // HREADYOUT input
wire [1:0] resp_dec2; // HRESP input
wire [31:0] rdata_dec2; // HRDATA input
- wire [1:0] ruser_dec2; // HRUSER input
reg sel_dec2; // HSEL output
// Bus-switch output MI3
@@ -236,7 +217,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec3; // HREADYOUT input
wire [1:0] resp_dec3; // HRESP input
wire [31:0] rdata_dec3; // HRDATA input
- wire [1:0] ruser_dec3; // HRUSER input
reg sel_dec3; // HSEL output
// Bus-switch output MI4
@@ -244,7 +224,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec4; // HREADYOUT input
wire [1:0] resp_dec4; // HRESP input
wire [31:0] rdata_dec4; // HRDATA input
- wire [1:0] ruser_dec4; // HRUSER input
reg sel_dec4; // HSEL output
// Bus-switch output MI5
@@ -252,7 +231,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec5; // HREADYOUT input
wire [1:0] resp_dec5; // HRESP input
wire [31:0] rdata_dec5; // HRDATA input
- wire [1:0] ruser_dec5; // HRUSER input
reg sel_dec5; // HSEL output
// Bus-switch output MI6
@@ -260,7 +238,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
wire readyout_dec6; // HREADYOUT input
wire [1:0] resp_dec6; // HRESP input
wire [31:0] rdata_dec6; // HRDATA input
- wire [1:0] ruser_dec6; // HRUSER input
reg sel_dec6; // HSEL output
@@ -272,7 +249,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
reg active_dec; // Combinatorial active_dec O/P signal
reg HREADYOUTS; // Combinatorial HREADYOUT signal
reg [1:0] HRESPS; // Combinatorial HRESPS signal
- reg [1:0] HRUSERS;
reg [31:0] HRDATAS; // Read data bus
reg [3:0] addr_out_port; // Address output ports
@@ -292,7 +268,7 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- nanosoc_ahb32_4x7_busmatrix_default_slave u_nanosoc_ahb32_4x7_busmatrix_default_slave (
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
@@ -533,31 +509,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma (
endcase // case (data_out_port)
end // block: p_rdata_comb
- // HRUSERS output decode
- always @ (
- ruser_dec0 or
- ruser_dec1 or
- ruser_dec2 or
- ruser_dec3 or
- ruser_dec4 or
- ruser_dec5 or
- ruser_dec6 or
- data_out_port
- )
- begin : p_ruser_comb
- case (data_out_port)
- 4'b0000 : HRUSERS = ruser_dec0;
- 4'b0001 : HRUSERS = ruser_dec1;
- 4'b0010 : HRUSERS = ruser_dec2;
- 4'b0011 : HRUSERS = ruser_dec3;
- 4'b0100 : HRUSERS = ruser_dec4;
- 4'b0101 : HRUSERS = ruser_dec5;
- 4'b0110 : HRUSERS = ruser_dec6;
- 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
- default : HRUSERS = {2{1'bx}};
- endcase // case (data_out_port)
- end // block: p_ruser_comb
-
endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_1.v
similarity index 90%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_1.v
index c841e8400d7e0a4ce571728cb08b6ee072161bcb..c4b99993d51ed148f1181dad10a992ebc9b5cd74 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_dma_1.v
@@ -27,13 +27,13 @@
// that do not map to an Output port are diverted to
// the local default slave.
//
-// Notes : The bus matrix has full connectivity.
+// Notes : The bus matrix has sparse connectivity.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_matrix_decode_dma2 (
+module nanosoc_matrix_decode_dma_1 (
// Common AHB signals
HCLK,
@@ -50,49 +50,42 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
readyout_dec0,
resp_dec0,
rdata_dec0,
- ruser_dec0,
// Bus-switch output 1
active_dec1,
readyout_dec1,
resp_dec1,
rdata_dec1,
- ruser_dec1,
// Bus-switch output 2
active_dec2,
readyout_dec2,
resp_dec2,
rdata_dec2,
- ruser_dec2,
// Bus-switch output 3
active_dec3,
readyout_dec3,
resp_dec3,
rdata_dec3,
- ruser_dec3,
// Bus-switch output 4
active_dec4,
readyout_dec4,
resp_dec4,
rdata_dec4,
- ruser_dec4,
// Bus-switch output 5
active_dec5,
readyout_dec5,
resp_dec5,
rdata_dec5,
- ruser_dec5,
// Bus-switch output 6
active_dec6,
readyout_dec6,
resp_dec6,
rdata_dec6,
- ruser_dec6,
// Output port selection signals
sel_dec0,
@@ -107,7 +100,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
active_dec,
HREADYOUTS,
HRESPS,
- HRUSERS,
HRDATAS
);
@@ -132,49 +124,42 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
input readyout_dec0; // HREADYOUT input
input [1:0] resp_dec0; // HRESP input
input [31:0] rdata_dec0; // HRDATA input
- input [1:0] ruser_dec0; // HRUSER input
// Bus-switch output MI1
input active_dec1; // Output stage MI1 active_dec signal
input readyout_dec1; // HREADYOUT input
input [1:0] resp_dec1; // HRESP input
input [31:0] rdata_dec1; // HRDATA input
- input [1:0] ruser_dec1; // HRUSER input
// Bus-switch output MI2
input active_dec2; // Output stage MI2 active_dec signal
input readyout_dec2; // HREADYOUT input
input [1:0] resp_dec2; // HRESP input
input [31:0] rdata_dec2; // HRDATA input
- input [1:0] ruser_dec2; // HRUSER input
// Bus-switch output MI3
input active_dec3; // Output stage MI3 active_dec signal
input readyout_dec3; // HREADYOUT input
input [1:0] resp_dec3; // HRESP input
input [31:0] rdata_dec3; // HRDATA input
- input [1:0] ruser_dec3; // HRUSER input
// Bus-switch output MI4
input active_dec4; // Output stage MI4 active_dec signal
input readyout_dec4; // HREADYOUT input
input [1:0] resp_dec4; // HRESP input
input [31:0] rdata_dec4; // HRDATA input
- input [1:0] ruser_dec4; // HRUSER input
// Bus-switch output MI5
input active_dec5; // Output stage MI5 active_dec signal
input readyout_dec5; // HREADYOUT input
input [1:0] resp_dec5; // HRESP input
input [31:0] rdata_dec5; // HRDATA input
- input [1:0] ruser_dec5; // HRUSER input
// Bus-switch output MI6
input active_dec6; // Output stage MI6 active_dec signal
input readyout_dec6; // HREADYOUT input
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
- input [1:0] ruser_dec6; // HRUSER input
// Output port selection signals
output sel_dec0; // HSEL output
@@ -189,7 +174,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
output active_dec; // Combinatorial active_dec O/P
output HREADYOUTS; // HREADY feedback output
output [1:0] HRESPS; // Transfer response
- output [1:0] HRUSERS; // User read Data
output [31:0] HRDATAS; // Read Data
@@ -212,7 +196,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec0; // HREADYOUT input
wire [1:0] resp_dec0; // HRESP input
wire [31:0] rdata_dec0; // HRDATA input
- wire [1:0] ruser_dec0; // HRUSER input
reg sel_dec0; // HSEL output
// Bus-switch output MI1
@@ -220,7 +203,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec1; // HREADYOUT input
wire [1:0] resp_dec1; // HRESP input
wire [31:0] rdata_dec1; // HRDATA input
- wire [1:0] ruser_dec1; // HRUSER input
reg sel_dec1; // HSEL output
// Bus-switch output MI2
@@ -228,7 +210,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec2; // HREADYOUT input
wire [1:0] resp_dec2; // HRESP input
wire [31:0] rdata_dec2; // HRDATA input
- wire [1:0] ruser_dec2; // HRUSER input
reg sel_dec2; // HSEL output
// Bus-switch output MI3
@@ -236,7 +217,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec3; // HREADYOUT input
wire [1:0] resp_dec3; // HRESP input
wire [31:0] rdata_dec3; // HRDATA input
- wire [1:0] ruser_dec3; // HRUSER input
reg sel_dec3; // HSEL output
// Bus-switch output MI4
@@ -244,7 +224,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec4; // HREADYOUT input
wire [1:0] resp_dec4; // HRESP input
wire [31:0] rdata_dec4; // HRDATA input
- wire [1:0] ruser_dec4; // HRUSER input
reg sel_dec4; // HSEL output
// Bus-switch output MI5
@@ -252,7 +231,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec5; // HREADYOUT input
wire [1:0] resp_dec5; // HRESP input
wire [31:0] rdata_dec5; // HRDATA input
- wire [1:0] ruser_dec5; // HRUSER input
reg sel_dec5; // HSEL output
// Bus-switch output MI6
@@ -260,7 +238,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
wire readyout_dec6; // HREADYOUT input
wire [1:0] resp_dec6; // HRESP input
wire [31:0] rdata_dec6; // HRDATA input
- wire [1:0] ruser_dec6; // HRUSER input
reg sel_dec6; // HSEL output
@@ -272,7 +249,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
reg active_dec; // Combinatorial active_dec O/P signal
reg HREADYOUTS; // Combinatorial HREADYOUT signal
reg [1:0] HRESPS; // Combinatorial HRESPS signal
- reg [1:0] HRUSERS;
reg [31:0] HRDATAS; // Read data bus
reg [3:0] addr_out_port; // Address output ports
@@ -292,7 +268,7 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- nanosoc_ahb32_4x7_busmatrix_default_slave u_nanosoc_ahb32_4x7_busmatrix_default_slave (
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
@@ -533,31 +509,6 @@ module nanosoc_ahb32_4x7_matrix_decode_dma2 (
endcase // case (data_out_port)
end // block: p_rdata_comb
- // HRUSERS output decode
- always @ (
- ruser_dec0 or
- ruser_dec1 or
- ruser_dec2 or
- ruser_dec3 or
- ruser_dec4 or
- ruser_dec5 or
- ruser_dec6 or
- data_out_port
- )
- begin : p_ruser_comb
- case (data_out_port)
- 4'b0000 : HRUSERS = ruser_dec0;
- 4'b0001 : HRUSERS = ruser_dec1;
- 4'b0010 : HRUSERS = ruser_dec2;
- 4'b0011 : HRUSERS = ruser_dec3;
- 4'b0100 : HRUSERS = ruser_dec4;
- 4'b0101 : HRUSERS = ruser_dec5;
- 4'b0110 : HRUSERS = ruser_dec6;
- 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
- default : HRUSERS = {2{1'bx}};
- endcase // case (data_out_port)
- end // block: p_ruser_comb
-
endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_socdebug.v
similarity index 91%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_socdebug.v
index e748865cc5595a0b0701279e79a9a282b1a84ebf..31471bac4ebbc4f78ab4b7b2b6f3df62f0617e72 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_socdebug.v
@@ -27,13 +27,13 @@
// that do not map to an Output port are diverted to
// the local default slave.
//
-// Notes : The bus matrix has full connectivity.
+// Notes : The bus matrix has sparse connectivity.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_matrix_decode_adp (
+module nanosoc_matrix_decode_socdebug (
// Common AHB signals
HCLK,
@@ -53,49 +53,48 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
readyout_dec0,
resp_dec0,
rdata_dec0,
- ruser_dec0,
// Bus-switch output 1
active_dec1,
readyout_dec1,
resp_dec1,
rdata_dec1,
- ruser_dec1,
// Bus-switch output 2
active_dec2,
readyout_dec2,
resp_dec2,
rdata_dec2,
- ruser_dec2,
// Bus-switch output 3
active_dec3,
readyout_dec3,
resp_dec3,
rdata_dec3,
- ruser_dec3,
// Bus-switch output 4
active_dec4,
readyout_dec4,
resp_dec4,
rdata_dec4,
- ruser_dec4,
// Bus-switch output 5
active_dec5,
readyout_dec5,
resp_dec5,
rdata_dec5,
- ruser_dec5,
// Bus-switch output 6
active_dec6,
readyout_dec6,
resp_dec6,
rdata_dec6,
- ruser_dec6,
+
+ // Bus-switch output 7
+ active_dec7,
+ readyout_dec7,
+ resp_dec7,
+ rdata_dec7,
// Output port selection signals
sel_dec0,
@@ -105,12 +104,12 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
sel_dec4,
sel_dec5,
sel_dec6,
+ sel_dec7,
// Selected Output port data and control signals
active_dec,
HREADYOUTS,
HRESPS,
- HRUSERS,
HRDATAS
);
@@ -138,49 +137,48 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
input readyout_dec0; // HREADYOUT input
input [1:0] resp_dec0; // HRESP input
input [31:0] rdata_dec0; // HRDATA input
- input [1:0] ruser_dec0; // HRUSER input
// Bus-switch output MI1
input active_dec1; // Output stage MI1 active_dec signal
input readyout_dec1; // HREADYOUT input
input [1:0] resp_dec1; // HRESP input
input [31:0] rdata_dec1; // HRDATA input
- input [1:0] ruser_dec1; // HRUSER input
// Bus-switch output MI2
input active_dec2; // Output stage MI2 active_dec signal
input readyout_dec2; // HREADYOUT input
input [1:0] resp_dec2; // HRESP input
input [31:0] rdata_dec2; // HRDATA input
- input [1:0] ruser_dec2; // HRUSER input
// Bus-switch output MI3
input active_dec3; // Output stage MI3 active_dec signal
input readyout_dec3; // HREADYOUT input
input [1:0] resp_dec3; // HRESP input
input [31:0] rdata_dec3; // HRDATA input
- input [1:0] ruser_dec3; // HRUSER input
// Bus-switch output MI4
input active_dec4; // Output stage MI4 active_dec signal
input readyout_dec4; // HREADYOUT input
input [1:0] resp_dec4; // HRESP input
input [31:0] rdata_dec4; // HRDATA input
- input [1:0] ruser_dec4; // HRUSER input
// Bus-switch output MI5
input active_dec5; // Output stage MI5 active_dec signal
input readyout_dec5; // HREADYOUT input
input [1:0] resp_dec5; // HRESP input
input [31:0] rdata_dec5; // HRDATA input
- input [1:0] ruser_dec5; // HRUSER input
// Bus-switch output MI6
input active_dec6; // Output stage MI6 active_dec signal
input readyout_dec6; // HREADYOUT input
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
- input [1:0] ruser_dec6; // HRUSER input
+
+ // Bus-switch output MI7
+ input active_dec7; // Output stage MI7 active_dec signal
+ input readyout_dec7; // HREADYOUT input
+ input [1:0] resp_dec7; // HRESP input
+ input [31:0] rdata_dec7; // HRDATA input
// Output port selection signals
output sel_dec0; // HSEL output
@@ -190,12 +188,12 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
output sel_dec4; // HSEL output
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
+ output sel_dec7; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
output HREADYOUTS; // HREADY feedback output
output [1:0] HRESPS; // Transfer response
- output [1:0] HRUSERS; // User read Data
output [31:0] HRDATAS; // Read Data
@@ -220,7 +218,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec0; // HREADYOUT input
wire [1:0] resp_dec0; // HRESP input
wire [31:0] rdata_dec0; // HRDATA input
- wire [1:0] ruser_dec0; // HRUSER input
reg sel_dec0; // HSEL output
// Bus-switch output MI1
@@ -228,7 +225,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec1; // HREADYOUT input
wire [1:0] resp_dec1; // HRESP input
wire [31:0] rdata_dec1; // HRDATA input
- wire [1:0] ruser_dec1; // HRUSER input
reg sel_dec1; // HSEL output
// Bus-switch output MI2
@@ -236,7 +232,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec2; // HREADYOUT input
wire [1:0] resp_dec2; // HRESP input
wire [31:0] rdata_dec2; // HRDATA input
- wire [1:0] ruser_dec2; // HRUSER input
reg sel_dec2; // HSEL output
// Bus-switch output MI3
@@ -244,7 +239,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec3; // HREADYOUT input
wire [1:0] resp_dec3; // HRESP input
wire [31:0] rdata_dec3; // HRDATA input
- wire [1:0] ruser_dec3; // HRUSER input
reg sel_dec3; // HSEL output
// Bus-switch output MI4
@@ -252,7 +246,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec4; // HREADYOUT input
wire [1:0] resp_dec4; // HRESP input
wire [31:0] rdata_dec4; // HRDATA input
- wire [1:0] ruser_dec4; // HRUSER input
reg sel_dec4; // HSEL output
// Bus-switch output MI5
@@ -260,7 +253,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec5; // HREADYOUT input
wire [1:0] resp_dec5; // HRESP input
wire [31:0] rdata_dec5; // HRDATA input
- wire [1:0] ruser_dec5; // HRUSER input
reg sel_dec5; // HSEL output
// Bus-switch output MI6
@@ -268,9 +260,15 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
wire readyout_dec6; // HREADYOUT input
wire [1:0] resp_dec6; // HRESP input
wire [31:0] rdata_dec6; // HRDATA input
- wire [1:0] ruser_dec6; // HRUSER input
reg sel_dec6; // HSEL output
+ // Bus-switch output MI7
+ wire active_dec7; // active_dec signal
+ wire readyout_dec7; // HREADYOUT input
+ wire [1:0] resp_dec7; // HRESP input
+ wire [31:0] rdata_dec7; // HRDATA input
+ reg sel_dec7; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -280,7 +278,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
reg active_dec; // Combinatorial active_dec O/P signal
reg HREADYOUTS; // Combinatorial HREADYOUT signal
reg [1:0] HRESPS; // Combinatorial HRESPS signal
- reg [1:0] HRUSERS;
reg [31:0] HRDATAS; // Read data bus
reg [3:0] addr_out_port; // Address output ports
@@ -300,7 +297,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- nanosoc_ahb32_4x7_busmatrix_default_slave u_nanosoc_ahb32_4x7_busmatrix_default_slave (
+ nanosoc_busmatrix_default_slave u_nanosoc_busmatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
@@ -357,9 +354,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
addr_out_port = 4'b0011; // Select Output port MI3
- // Static address region 0xf0000000-0xf003ffff
- else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0011; // Select Output port MI3
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
@@ -376,6 +370,10 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0111; // Select Output port MI7
+
else
addr_out_port = 4'b1000; // Select the default slave
end
@@ -403,9 +401,6 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
addr_out_port = 4'b0011; // Select Output port MI3
- // Static address region 0xf0000000-0xf003ffff
- else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0011; // Select Output port MI3
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
@@ -422,6 +417,10 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
addr_out_port = 4'b0110; // Select Output port MI6
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 4'b0111; // Select Output port MI7
+
else
addr_out_port = 4'b1000; // Select the default slave
end
@@ -445,6 +444,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
sel_dec4 = 1'b0;
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
+ sel_dec7 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
@@ -456,6 +456,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
4'b0100 : sel_dec4 = 1'b1;
4'b0101 : sel_dec5 = 1'b1;
4'b0110 : sel_dec6 = 1'b1;
+ 4'b0111 : sel_dec7 = 1'b1;
4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
@@ -465,6 +466,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
sel_dec4 = 1'bx;
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
+ sel_dec7 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -480,6 +482,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
active_dec4 or
active_dec5 or
active_dec6 or
+ active_dec7 or
addr_out_port
)
begin : p_active_comb
@@ -491,6 +494,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
4'b0100 : active_dec = active_dec4;
4'b0101 : active_dec = active_dec5;
4'b0110 : active_dec = active_dec6;
+ 4'b0111 : active_dec = active_dec7;
4'b1000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
@@ -530,6 +534,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
readyout_dec4 or
readyout_dec5 or
readyout_dec6 or
+ readyout_dec7 or
data_out_port
)
begin : p_ready_comb
@@ -541,6 +546,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
4'b0100 : HREADYOUTS = readyout_dec4;
4'b0101 : HREADYOUTS = readyout_dec5;
4'b0110 : HREADYOUTS = readyout_dec6;
+ 4'b0111 : HREADYOUTS = readyout_dec7;
4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
@@ -556,6 +562,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
resp_dec4 or
resp_dec5 or
resp_dec6 or
+ resp_dec7 or
data_out_port
)
begin : p_resp_comb
@@ -567,6 +574,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
4'b0100 : HRESPS = resp_dec4;
4'b0101 : HRESPS = resp_dec5;
4'b0110 : HRESPS = resp_dec6;
+ 4'b0111 : HRESPS = resp_dec7;
4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
@@ -581,6 +589,7 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
rdata_dec4 or
rdata_dec5 or
rdata_dec6 or
+ rdata_dec7 or
data_out_port
)
begin : p_rdata_comb
@@ -592,36 +601,12 @@ module nanosoc_ahb32_4x7_matrix_decode_adp (
4'b0100 : HRDATAS = rdata_dec4;
4'b0101 : HRDATAS = rdata_dec5;
4'b0110 : HRDATAS = rdata_dec6;
+ 4'b0111 : HRDATAS = rdata_dec7;
4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
- // HRUSERS output decode
- always @ (
- ruser_dec0 or
- ruser_dec1 or
- ruser_dec2 or
- ruser_dec3 or
- ruser_dec4 or
- ruser_dec5 or
- ruser_dec6 or
- data_out_port
- )
- begin : p_ruser_comb
- case (data_out_port)
- 4'b0000 : HRUSERS = ruser_dec0;
- 4'b0001 : HRUSERS = ruser_dec1;
- 4'b0010 : HRUSERS = ruser_dec2;
- 4'b0011 : HRUSERS = ruser_dec3;
- 4'b0100 : HRUSERS = ruser_dec4;
- 4'b0101 : HRUSERS = ruser_dec5;
- 4'b0110 : HRUSERS = ruser_dec6;
- 4'b1000 : HRUSERS = {2{1'b0}}; // Select the default slave
- default : HRUSERS = {2{1'bx}};
- endcase // case (data_out_port)
- end // block: p_ruser_comb
-
endmodule
diff --git a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_bootrom.v
similarity index 89%
rename from system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v
rename to system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_bootrom.v
index 083e5b33120aee40baf7c702e2ebe4ba94b9f692..ac68ef830fa96e1c9673dc0d8394bd0a0b67bad7 100644
--- a/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_bootrom.v
@@ -25,14 +25,14 @@
// Abstract : The Output Stage is used to route the required input
// stage to the shared slave output.
//
-// Notes : The bus matrix has full connectivity,
+// Notes : The bus matrix has sparse connectivity,
// and has a burst arbiter scheme.
//
//-----------------------------------------------------------------------------
-module nanosoc_ahb32_4x7_target_output (
+module nanosoc_target_output_bootrom (
// Common AHB signals
HCLK,
@@ -41,7 +41,6 @@ module nanosoc_ahb32_4x7_target_output (
// Port 0 Signals
sel_op0,
addr_op0,
- auser_op0,
trans_op0,
write_op0,
size_op0,
@@ -50,13 +49,11 @@ module nanosoc_ahb32_4x7_target_output (
master_op0,
mastlock_op0,
wdata_op0,
- wuser_op0,
held_tran_op0,
// Port 1 Signals
sel_op1,
addr_op1,
- auser_op1,
trans_op1,
write_op1,
size_op1,
@@ -65,13 +62,11 @@ module nanosoc_ahb32_4x7_target_output (
master_op1,
mastlock_op1,
wdata_op1,
- wuser_op1,
held_tran_op1,
// Port 2 Signals
sel_op2,
addr_op2,
- auser_op2,
trans_op2,
write_op2,
size_op2,
@@ -80,13 +75,11 @@ module nanosoc_ahb32_4x7_target_output (
master_op2,
mastlock_op2,
wdata_op2,
- wuser_op2,
held_tran_op2,
// Port 3 Signals
sel_op3,
addr_op3,
- auser_op3,
trans_op3,
write_op3,
size_op3,
@@ -95,7 +88,6 @@ module nanosoc_ahb32_4x7_target_output (
master_op3,
mastlock_op3,
wdata_op3,
- wuser_op3,
held_tran_op3,
// Slave read data and response
@@ -109,7 +101,6 @@ module nanosoc_ahb32_4x7_target_output (
// Slave Address/Control Signals
HSELM,
HADDRM,
- HAUSERM,
HTRANSM,
HWRITEM,
HSIZEM,
@@ -118,7 +109,6 @@ module nanosoc_ahb32_4x7_target_output (
HMASTERM,
HMASTLOCKM,
HREADYMUXM,
- HWUSERM,
HWDATAM
);
@@ -135,7 +125,6 @@ module nanosoc_ahb32_4x7_target_output (
// Bus-switch input 0
input sel_op0; // Port 0 HSEL signal
input [31:0] addr_op0; // Port 0 HADDR signal
- input [1:0] auser_op0; // Port 0 HAUSER signal
input [1:0] trans_op0; // Port 0 HTRANS signal
input write_op0; // Port 0 HWRITE signal
input [2:0] size_op0; // Port 0 HSIZE signal
@@ -144,13 +133,11 @@ module nanosoc_ahb32_4x7_target_output (
input [3:0] master_op0; // Port 0 HMASTER signal
input mastlock_op0; // Port 0 HMASTLOCK signal
input [31:0] wdata_op0; // Port 0 HWDATA signal
- input [1:0] wuser_op0; // Port 0 HWUSER signal
input held_tran_op0; // Port 0 HeldTran signal
// Bus-switch input 1
input sel_op1; // Port 1 HSEL signal
input [31:0] addr_op1; // Port 1 HADDR signal
- input [1:0] auser_op1; // Port 1 HAUSER signal
input [1:0] trans_op1; // Port 1 HTRANS signal
input write_op1; // Port 1 HWRITE signal
input [2:0] size_op1; // Port 1 HSIZE signal
@@ -159,13 +146,11 @@ module nanosoc_ahb32_4x7_target_output (
input [3:0] master_op1; // Port 1 HMASTER signal
input mastlock_op1; // Port 1 HMASTLOCK signal
input [31:0] wdata_op1; // Port 1 HWDATA signal
- input [1:0] wuser_op1; // Port 1 HWUSER signal
input held_tran_op1; // Port 1 HeldTran signal
// Bus-switch input 2
input sel_op2; // Port 2 HSEL signal
input [31:0] addr_op2; // Port 2 HADDR signal
- input [1:0] auser_op2; // Port 2 HAUSER signal
input [1:0] trans_op2; // Port 2 HTRANS signal
input write_op2; // Port 2 HWRITE signal
input [2:0] size_op2; // Port 2 HSIZE signal
@@ -174,13 +159,11 @@ module nanosoc_ahb32_4x7_target_output (
input [3:0] master_op2; // Port 2 HMASTER signal
input mastlock_op2; // Port 2 HMASTLOCK signal
input [31:0] wdata_op2; // Port 2 HWDATA signal
- input [1:0] wuser_op2; // Port 2 HWUSER signal
input held_tran_op2; // Port 2 HeldTran signal
// Bus-switch input 3
input sel_op3; // Port 3 HSEL signal
input [31:0] addr_op3; // Port 3 HADDR signal
- input [1:0] auser_op3; // Port 3 HAUSER signal
input [1:0] trans_op3; // Port 3 HTRANS signal
input write_op3; // Port 3 HWRITE signal
input [2:0] size_op3; // Port 3 HSIZE signal
@@ -189,7 +172,6 @@ module nanosoc_ahb32_4x7_target_output (
input [3:0] master_op3; // Port 3 HMASTER signal
input mastlock_op3; // Port 3 HMASTLOCK signal
input [31:0] wdata_op3; // Port 3 HWDATA signal
- input [1:0] wuser_op3; // Port 3 HWUSER signal
input held_tran_op3; // Port 3 HeldTran signal
input HREADYOUTM; // HREADY feedback
@@ -202,7 +184,6 @@ module nanosoc_ahb32_4x7_target_output (
// Slave Address/Control Signals
output HSELM; // Slave select line
output [31:0] HADDRM; // Address
- output [1:0] HAUSERM; // User Address bus
output [1:0] HTRANSM; // Transfer type
output HWRITEM; // Transfer direction
output [2:0] HSIZEM; // Transfer size
@@ -211,7 +192,6 @@ module nanosoc_ahb32_4x7_target_output (
output [3:0] HMASTERM; // Master ID
output HMASTLOCKM; // Locked transfer
output HREADYMUXM; // Transfer done
- output [1:0] HWUSERM; // User data bus
output [31:0] HWDATAM; // Write data
@@ -224,7 +204,6 @@ module nanosoc_ahb32_4x7_target_output (
// Bus-switch input 0
wire sel_op0; // Port 0 HSEL signal
wire [31:0] addr_op0; // Port 0 HADDR signal
- wire [1:0] auser_op0; // Port 0 HAUSER signal
wire [1:0] trans_op0; // Port 0 HTRANS signal
wire write_op0; // Port 0 HWRITE signal
wire [2:0] size_op0; // Port 0 HSIZE signal
@@ -233,14 +212,12 @@ module nanosoc_ahb32_4x7_target_output (
wire [3:0] master_op0; // Port 0 HMASTER signal
wire mastlock_op0; // Port 0 HMASTLOCK signal
wire [31:0] wdata_op0; // Port 0 HWDATA signal
- wire [1:0] wuser_op0; // Port 0 HWUSER signal
wire held_tran_op0; // Port 0 HeldTran signal
reg active_op0; // Port 0 Active signal
// Bus-switch input 1
wire sel_op1; // Port 1 HSEL signal
wire [31:0] addr_op1; // Port 1 HADDR signal
- wire [1:0] auser_op1; // Port 1 HAUSER signal
wire [1:0] trans_op1; // Port 1 HTRANS signal
wire write_op1; // Port 1 HWRITE signal
wire [2:0] size_op1; // Port 1 HSIZE signal
@@ -249,14 +226,12 @@ module nanosoc_ahb32_4x7_target_output (
wire [3:0] master_op1; // Port 1 HMASTER signal
wire mastlock_op1; // Port 1 HMASTLOCK signal
wire [31:0] wdata_op1; // Port 1 HWDATA signal
- wire [1:0] wuser_op1; // Port 1 HWUSER signal
wire held_tran_op1; // Port 1 HeldTran signal
reg active_op1; // Port 1 Active signal
// Bus-switch input 2
wire sel_op2; // Port 2 HSEL signal
wire [31:0] addr_op2; // Port 2 HADDR signal
- wire [1:0] auser_op2; // Port 2 HAUSER signal
wire [1:0] trans_op2; // Port 2 HTRANS signal
wire write_op2; // Port 2 HWRITE signal
wire [2:0] size_op2; // Port 2 HSIZE signal
@@ -265,14 +240,12 @@ module nanosoc_ahb32_4x7_target_output (
wire [3:0] master_op2; // Port 2 HMASTER signal
wire mastlock_op2; // Port 2 HMASTLOCK signal
wire [31:0] wdata_op2; // Port 2 HWDATA signal
- wire [1:0] wuser_op2; // Port 2 HWUSER signal
wire held_tran_op2; // Port 2 HeldTran signal
reg active_op2; // Port 2 Active signal
// Bus-switch input 3
wire sel_op3; // Port 3 HSEL signal
wire [31:0] addr_op3; // Port 3 HADDR signal
- wire [1:0] auser_op3; // Port 3 HAUSER signal
wire [1:0] trans_op3; // Port 3 HTRANS signal
wire write_op3; // Port 3 HWRITE signal
wire [2:0] size_op3; // Port 3 HSIZE signal
@@ -281,14 +254,12 @@ module nanosoc_ahb32_4x7_target_output (
wire [3:0] master_op3; // Port 3 HMASTER signal
wire mastlock_op3; // Port 3 HMASTLOCK signal
wire [31:0] wdata_op3; // Port 3 HWDATA signal
- wire [1:0] wuser_op3; // Port 3 HWUSER signal
wire held_tran_op3; // Port 3 HeldTran signal
reg active_op3; // Port 3 Active signal
// Slave Address/Control Signals
wire HSELM; // Slave select line
reg [31:0] HADDRM; // Address
- reg [1:0] HAUSERM; // User Address bus
wire [1:0] HTRANSM; // Transfer type
reg HWRITEM; // Transfer direction
reg [2:0] HSIZEM; // Transfer size
@@ -297,7 +268,6 @@ module nanosoc_ahb32_4x7_target_output (
reg [3:0] HMASTERM; // Master ID
wire HMASTLOCKM; // Locked transfer
wire HREADYMUXM; // Transfer done
- reg [1:0] HWUSERM; // User data bus
reg [31:0] HWDATAM; // Write data
wire HREADYOUTM; // HREADY feedback
@@ -341,7 +311,7 @@ module nanosoc_ahb32_4x7_target_output (
assign req_port3 = held_tran_op3 & sel_op3;
// Arbiter instance for resolving requests to this output stage
- nanosoc_ahb32_4x7_arbiter u_output_arb (
+ nanosoc_arbiter_bootrom u_output_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -393,19 +363,15 @@ module nanosoc_ahb32_4x7_target_output (
always @ (
sel_op0 or addr_op0 or trans_op0 or write_op0 or
size_op0 or burst_op0 or prot_op0 or
- auser_op0 or
master_op0 or mastlock_op0 or
sel_op1 or addr_op1 or trans_op1 or write_op1 or
size_op1 or burst_op1 or prot_op1 or
- auser_op1 or
master_op1 or mastlock_op1 or
sel_op2 or addr_op2 or trans_op2 or write_op2 or
size_op2 or burst_op2 or prot_op2 or
- auser_op2 or
master_op2 or mastlock_op2 or
sel_op3 or addr_op3 or trans_op3 or write_op3 or
size_op3 or burst_op3 or prot_op3 or
- auser_op3 or
master_op3 or mastlock_op3 or
addr_in_port or no_port
)
@@ -413,7 +379,6 @@ module nanosoc_ahb32_4x7_target_output (
// Default values
i_hselm = 1'b0;
HADDRM = {32{1'b0}};
- HAUSERM = {2{1'b0}};
i_htransm = 2'b00;
HWRITEM = 1'b0;
HSIZEM = 3'b000;
@@ -430,7 +395,6 @@ module nanosoc_ahb32_4x7_target_output (
begin
i_hselm = sel_op0;
HADDRM = addr_op0;
- HAUSERM = auser_op0;
i_htransm = trans_op0;
HWRITEM = write_op0;
HSIZEM = size_op0;
@@ -445,7 +409,6 @@ module nanosoc_ahb32_4x7_target_output (
begin
i_hselm = sel_op1;
HADDRM = addr_op1;
- HAUSERM = auser_op1;
i_htransm = trans_op1;
HWRITEM = write_op1;
HSIZEM = size_op1;
@@ -460,7 +423,6 @@ module nanosoc_ahb32_4x7_target_output (
begin
i_hselm = sel_op2;
HADDRM = addr_op2;
- HAUSERM = auser_op2;
i_htransm = trans_op2;
HWRITEM = write_op2;
HSIZEM = size_op2;
@@ -475,7 +437,6 @@ module nanosoc_ahb32_4x7_target_output (
begin
i_hselm = sel_op3;
HADDRM = addr_op3;
- HAUSERM = auser_op3;
i_htransm = trans_op3;
HWRITEM = write_op3;
HSIZEM = size_op3;
@@ -489,7 +450,6 @@ module nanosoc_ahb32_4x7_target_output (
begin
i_hselm = 1'bx;
HADDRM = {32{1'bx}};
- HAUSERM = {2{1'bx}};
i_htransm = 2'bxx;
HWRITEM = 1'bx;
HSIZEM = 3'bxxx;
@@ -575,29 +535,6 @@ module nanosoc_ahb32_4x7_target_output (
endcase // case(data_in_port)
end // block: p_data_mux
- // HWUSERM output decode
- always @ (
- wuser_op0 or
- wuser_op1 or
- wuser_op2 or
- wuser_op3 or
- data_in_port or wdata_phase
- )
- begin : p_wuser_mux
- // Default value
- HWUSERM = {2{1'b0}};
-
- // If interface active
- if (wdata_phase)
- // Decode selection
- case (data_in_port)
- 2'b00 : HWUSERM = wuser_op0;
- 2'b01 : HWUSERM = wuser_op1;
- 2'b10 : HWUSERM = wuser_op2;
- 2'b11 : HWUSERM = wuser_op3;
- default : HWUSERM = {2{1'bx}};
- endcase // case(data_in_port)
- end // block: p_wuser_mux
// ---------------------------------------------------------------------------
// HREADYMUXM generation
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_dmem.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_dmem.v
new file mode 100644
index 0000000000000000000000000000000000000000..99666f7b60d796dba210dab992227295aea4a0a9
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_dmem.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_dmem (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_dmem u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v
new file mode 100644
index 0000000000000000000000000000000000000000..799e0baf2f9e8b7e392c43dfedebf8802329e96f
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_exp.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_exp (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_exp u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_h.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_h.v
new file mode 100644
index 0000000000000000000000000000000000000000..2aee3e45ab62b2bcf445a45454b87ededf432443
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_h.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_expram_h (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_expram_h u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_l.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_l.v
new file mode 100644
index 0000000000000000000000000000000000000000..f973a67669f24bb619cb63335b5b85d4641367c9
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_expram_l.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_expram_l (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_expram_l u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_imem.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_imem.v
new file mode 100644
index 0000000000000000000000000000000000000000..cf2b4f8dac88429ff4f2dc3c57a246accb109425
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_imem.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_imem (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_imem u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_sysio.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_sysio.v
new file mode 100644
index 0000000000000000000000000000000000000000..609a2e81ee1ca368f4573fb9678b5736215752c7
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_sysio.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_sysio (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_sysio u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v
new file mode 100644
index 0000000000000000000000000000000000000000..0f46a25565d48cac638030b79575d10f02a554d5
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_systable.v
@@ -0,0 +1,429 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_systable (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_systable u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/system/src/nanosoc_busmatrix/xml/nanosoc.xml b/system/src/nanosoc_busmatrix/xml/nanosoc.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0df4b12d207ef9a52444b831d98562b09e778222
--- /dev/null
+++ b/system/src/nanosoc_busmatrix/xml/nanosoc.xml
@@ -0,0 +1,159 @@
+<?xml version="1.0" encoding="iso-8859-1" ?>
+
+<!--//----------------------------------------------------------------------------- -->
+<!--// customised interconnect specification for ADP/DMA/ Cortex-M0 controller -->
+<!--// -->
+<!--// Contributors -->
+<!--// -->
+<!--// David Flynn (d.w.flynn@soton.ac.uk) -->
+<!--// -->
+<!--// Copyright (C) 2023, SoC Labs (www.soclabs.org) -->
+<!--//----------------------------------------------------------------------------- -->
+
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file -->
+<!-- may only be used by a person authorised under and to the extent -->
+<!-- permitted by a subsisting licensing agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person -->
+<!-- is permitted to do so under the terms of a subsisting license -->
+<!-- agreement from Arm Limited or its affiliates. -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Version and Release Control Information: -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : based on Example XML file, defining an interconnect for -->
+<!-- (was 2 AHB Masters and 3 AHB Slaves.) -->
+<!-- 4 AHB Managers and 8 AHB Subordinates -->
+<!-- -->
+<!-- Note : This information will overwrite parameters -->
+<!-- specified on the command line -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<cfgfile>
+
+ <!-- - - - - *** DO NOT MODIFY ABOVE THIS LINE *** - - - - - - - - - - - -->
+
+ <!-- Global definitions -->
+
+ <architecture_version>ahb2</architecture_version>
+ <arbitration_scheme>burst</arbitration_scheme>
+ <routing_data_width>32</routing_data_width>
+ <routing_address_width>32</routing_address_width>
+ <user_signal_width>0</user_signal_width>
+ <bus_matrix_name>nanosoc_busmatrix</bus_matrix_name>
+ <input_stage_name>nanosoc_inititator_input</input_stage_name>
+ <matrix_decode_name>nanosoc_matrix_decode</matrix_decode_name>
+ <output_arbiter_name>nanosoc_arbiter</output_arbiter_name>
+ <output_stage_name>nanosoc_target_output< /output_stage_name>
+
+
+ <!-- Slave interface definitions -->
+
+ <slave_interface name="_socdebug">
+ <sparse_connect interface="_bootrom"/>
+ <sparse_connect interface="_imem"/>
+ <sparse_connect interface="_dmem"/>
+ <sparse_connect interface="_sysio"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_expram_l"/>
+ <sparse_connect interface="_expram_h"/>
+ <sparse_connect interface="_systable"/>
+ <address_region interface="_bootrom" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_bootrom" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_imem" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_dmem" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sysio" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_expram_l" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_expram_h" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ <address_region interface="_systable" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
+ <remap_region interface="_imem" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ </slave_interface>
+
+ <slave_interface name="_dma_0">
+ <sparse_connect interface="_bootrom"/>
+ <sparse_connect interface="_imem"/>
+ <sparse_connect interface="_dmem"/>
+ <sparse_connect interface="_sysio"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_expram_l"/>
+ <sparse_connect interface="_expram_h"/>
+ <address_region interface="_imem" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_bootrom" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_imem" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_dmem" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sysio" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_expram_l" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_expram_h" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
+ <slave_interface name="_dma_1">
+ <sparse_connect interface="_bootrom"/>
+ <sparse_connect interface="_imem"/>
+ <sparse_connect interface="_dmem"/>
+ <sparse_connect interface="_sysio"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_expram_l"/>
+ <sparse_connect interface="_expram_h"/>
+ <address_region interface="_imem" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_bootrom" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_imem" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_dmem" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sysio" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_expram_l" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_expram_h" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ </slave_interface>
+
+ <slave_interface name="_cpu">
+ <sparse_connect interface="_bootrom"/>
+ <sparse_connect interface="_imem"/>
+ <sparse_connect interface="_dmem"/>
+ <sparse_connect interface="_sysio"/>
+ <sparse_connect interface="_exp"/>
+ <sparse_connect interface="_expram_l"/>
+ <sparse_connect interface="_expram_h"/>
+ <sparse_connect interface="_systable"/>
+ <address_region interface="_bootrom" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_bootrom" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_imem" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_dmem" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_sysio" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
+ <address_region interface="_expram_l" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
+ <address_region interface="_expram_h" mem_lo='90000000' mem_hi='9fffffff' remapping='none'/>
+ <address_region interface="_exp" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
+ <address_region interface="_systable" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
+ <remap_region interface="_imem" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ </slave_interface>
+
+ <!-- Master interface definitions -->
+
+ <master_interface name="_bootrom"/>
+ <master_interface name="_imem"/>
+ <master_interface name="_dmem"/>
+ <master_interface name="_sysio"/>
+ <master_interface name="_expram_l"/>
+ <master_interface name="_expram_h"/>
+ <master_interface name="_exp"/>
+ <master_interface name="_systable"/>
+
+ <!-- - - - - *** DO NOT MODIFY BELOW THIS LINE *** - - - - - - - - - - - -->
+
+</cfgfile>
diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/nanosoc_chip/chip/verilog/nanosoc_chip.v
similarity index 58%
rename from system/src/verilog/nanosoc_chip.v
rename to system/src/nanosoc_chip/chip/verilog/nanosoc_chip.v
index a1e108ad4ddc822c7d3b9d3ba7a3303d42bf8d98..9f29474abce915348298915ee0cad6226ed32a2e 100644
--- a/system/src/verilog/nanosoc_chip.v
+++ b/system/src/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -45,40 +45,44 @@
//param ADDR_WIDTH_RAM = 15; // 32KB
//param ADDR_WIDTH_RAM = 16; // 64KB
-module nanosoc_chip
- #(parameter ADDR_WIDTH_RAM = 14)
- (
-`ifdef POWER_PINS
- inout wire VDDIO,
- inout wire VSSIO,
- inout wire VDD,
- inout wire VSS,
-`endif
- input wire xtal_clk_i,
- output wire xtal_clk_o,
- input wire nrst_i,
- input wire [15:0] p0_i, // level-shifted input from pad
- output wire [15:0] p0_o, // output port drive
- output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
- input wire [15:0] p1_i, // level-shifted input from pad
- output wire [15:0] p1_o, // output port drive
- output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
- output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
- input wire swdio_i,
- output wire swdio_o,
- output wire swdio_e,
- output wire swdio_z,
- input wire swdclk_i
+module nanosoc_chip #(
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 32,
+ parameter RAM_ADDR_W = 14,
+ parameter RAM_DATA_W = 32
+ )(
+ `ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+ `endif
+ input wire xtal_clk_i,
+ output wire xtal_clk_o,
+ input wire nrst_i,
+ input wire [15:0] p0_i, // level-shifted input from pad
+ output wire [15:0] p0_o, // output port drive
+ output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
+ input wire [15:0] p1_i, // level-shifted input from pad
+ output wire [15:0] p1_o, // output port drive
+ output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
+ input wire swdio_i,
+ output wire swdio_o,
+ output wire swdio_e,
+ output wire swdio_z,
+ input wire swdclk_i
);
-localparam CLKGATE_PRESENT = 0;
-localparam DMA_CHANNEL_NUM = 2;
-localparam INCLUDE_DMA = 1;
-localparam CORTEX_M0 = 1;
+ localparam CLKGATE_PRESENT = 0;
+ localparam DMA_CHANNEL_NUM = 2;
+ localparam INCLUDE_DMA = 1;
+ localparam CORTEX_M0 = 1;
//------------------------------------
// CMSDK internal wire naming preserved
+//------------------------------------
wire xtal_clk_in = xtal_clk_i;
wire xtal_clk_out;
@@ -168,66 +172,63 @@ localparam CORTEX_M0 = 1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
-
-
//----------------------------------------
-// SOC clock and reset management
+// SoC Clock and Reset Management
//----------------------------------------
-//
-
- wire PORESETn;// Power on reset
- wire HRESETn; // AHB reset
- wire PRESETn; // APB and peripheral reset
- wire DBGRESETn; // Debug system reset
- wire FCLK; // Free running system clock
- wire HCLK; // System clock from PMU
- wire DCLK;
- wire SCLK;
- wire PCLK; // Peripheral clock
- wire PCLKG; // Gated PCLK for APB
- wire PCLKEN; // Clock divider for AHB to APB bridge
- wire APBACTIVE;
+ wire PORESETn;// Power on reset
+ wire HRESETn; // AHB reset
+ wire PRESETn; // APB and peripheral reset
+ wire DBGRESETn; // Debug system reset
+ wire FCLK; // Free running system clock
+ wire HCLK; // System clock from PMU
+ wire DCLK;
+ wire SCLK;
+ wire PCLK; // Peripheral clock
+ wire PCLKG; // Gated PCLK for APB
+ wire PCLKEN; // Clock divider for AHB to APB bridge
+ wire APBACTIVE;
+
// event signals
- wire TXEV;
- wire RXEV;
- wire nTRST; // JTAG - Test reset (active low)
- wire SWDI; // JTAG/SWD - TMS / SWD data input
- wire SWCLK; // JTAG/SWD - TCK / SWCLK
- wire SWDO; // SWD - SWD data output
- wire SWDOEN; // SWD - SWD data output enable
- wire SYSRESETREQ; // processor system reset request
- wire WDOGRESETREQ; // watchdog system reset request
- wire HRESETREQ; // Combined system reset request
- wire NANOSOC_SYSRESETREQ; // Combined system reset request
- wire clk_ctrl_sys_reset_req;
- wire PMUHRESETREQ;
- wire PMUDBGRESETREQ;
- wire LOCKUP;
- wire LOCKUPRESET;
- wire SLEEPING;
- wire GATEHCLK; // Processor status - safe to gate HCLK
- wire WAKEUP; // Wake up request from WIC
- wire WICENREQ; // WIC enable request from PMU
- wire WICENACK; // WIC enable ack to PMU
- wire PMUENABLE;
- wire CDBGPWRUPREQ; // Debug Power Up request to PMU
- wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
- wire SLEEPHOLDREQn; // Sleep extension request from PMU
- wire SLEEPHOLDACKn; // Sleep extension request to PMU
- wire SYSPWRDOWNACK;
- wire DBGPWRDOWNACK;
- wire SYSPWRDOWN;
- wire DBGPWRDOWN;
- wire SYSISOLATEn;
- wire SYSRETAINn;
- wire DBGISOLATEn;
- wire SLEEPDEEP;
- wire ADPRESETREQ;
- // Scan test dummy signals; not connected until scan insertion
- wire TESTMODE; // Test mode enable signal (override synchronizers etc)
- wire SCANENABLE; // Scan enable signal
- wire SCANINHCLK; // HCLK scan input
- wire SCANOUTHCLK; // Scan Chain wire
+ wire TXEV;
+ wire RXEV;
+ wire nTRST; // JTAG - Test reset (active low)
+ wire SWDI; // JTAG/SWD - TMS / SWD data input
+ wire SWCLK; // JTAG/SWD - TCK / SWCLK
+ wire SWDO; // SWD - SWD data output
+ wire SWDOEN; // SWD - SWD data output enable
+ wire SYSRESETREQ; // processor system reset request
+ wire WDOGRESETREQ; // watchdog system reset request
+ wire HRESETREQ; // Combined system reset request
+ wire NANOSOC_SYSRESETREQ; // Combined system reset request
+ wire clk_ctrl_sys_reset_req;
+ wire PMUHRESETREQ;
+ wire PMUDBGRESETREQ;
+ wire LOCKUP;
+ wire LOCKUPRESET;
+ wire SLEEPING;
+ wire GATEHCLK; // Processor status - safe to gate HCLK
+ wire WAKEUP; // Wake up request from WIC
+ wire WICENREQ; // WIC enable request from PMU
+ wire WICENACK; // WIC enable ack to PMU
+ wire PMUENABLE;
+ wire CDBGPWRUPREQ; // Debug Power Up request to PMU
+ wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
+ wire SLEEPHOLDREQn; // Sleep extension request from PMU
+ wire SLEEPHOLDACKn; // Sleep extension request to PMU
+ wire SYSPWRDOWNACK;
+ wire DBGPWRDOWNACK;
+ wire SYSPWRDOWN;
+ wire DBGPWRDOWN;
+ wire SYSISOLATEn;
+ wire SYSRETAINn;
+ wire DBGISOLATEn;
+ wire SLEEPDEEP;
+ wire ADPRESETREQ;
+ // Scan test dummy signals; not connected until scan insertion
+ wire TESTMODE; // Test mode enable signal (override synchronizers etc)
+ wire SCANENABLE; // Scan enable signal
+ wire SCANINHCLK; // HCLK scan input
+ wire SCANOUTHCLK; // Scan Chain wire
// not required for FPGA
assign TESTMODE = 1'b0;
@@ -415,205 +416,205 @@ localparam CORTEX_M0 = 1;
wire ROM_MAP;
// Manager port SI0 (inputs from master 0)
- wire [31:0] HADDR_adp; // Address bus
- wire [1:0] HTRANS_adp; // Transfer type
- wire HWRITE_adp; // Transfer direction
- wire [2:0] HSIZE_adp; // Transfer size
- wire [2:0] HBURST_adp; // Burst type
- wire [3:0] HPROT_adp; // Protection control
- wire [31:0] HWDATA_adp; // Write data
- wire HMASTLOCK_adp; // Locked Sequence
- wire [1:0] HAUSER_adp; // Address USER signals
- wire [1:0] HWUSER_adp; // Write-data USER signals
+ wire [SYS_ADDR_W-1:0] HADDR_adp; // Address bus
+ wire [1:0] HTRANS_adp; // Transfer type
+ wire HWRITE_adp; // Transfer direction
+ wire [2:0] HSIZE_adp; // Transfer size
+ wire [2:0] HBURST_adp; // Burst type
+ wire [3:0] HPROT_adp; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_adp; // Write data
+ wire HMASTLOCK_adp; // Locked Sequence
+ wire [1:0] HAUSER_adp; // Address USER signals
+ wire [1:0] HWUSER_adp; // Write-data USER signals
// Manager port SI0 (outputs to master 0)
- wire [31:0] HRDATA_adp; // Read data bus
- wire HREADY_adp; // HREADY feedback
- wire HRESP_adp; // Transfer response
- wire [1:0] HRUSER_adp; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_adp; // Read data bus
+ wire HREADY_adp; // HREADY feedback
+ wire HRESP_adp; // Transfer response
+ wire [1:0] HRUSER_adp; // Read-data USER signals
// Manager port SI1 (inputs from master 1)
- wire [31:0] HADDR_dma; // Address bus
- wire [1:0] HTRANS_dma; // Transfer type
- wire HWRITE_dma; // Transfer direction
- wire [2:0] HSIZE_dma; // Transfer size
- wire [2:0] HBURST_dma; // Burst type
- wire [3:0] HPROT_dma; // Protection control
- wire [31:0] HWDATA_dma; // Write data
- wire HMASTLOCK_dma; // Locked Sequence
- wire [1:0] HAUSER_dma; // Address USER signals
- wire [1:0] HWUSER_dma; // Write-data USER signals
+ wire [SYS_ADDR_W-1:0] HADDR_dma; // Address bus
+ wire [1:0] HTRANS_dma; // Transfer type
+ wire HWRITE_dma; // Transfer direction
+ wire [2:0] HSIZE_dma; // Transfer size
+ wire [2:0] HBURST_dma; // Burst type
+ wire [3:0] HPROT_dma; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_dma; // Write data
+ wire HMASTLOCK_dma; // Locked Sequence
+ wire [1:0] HAUSER_dma; // Address USER signals
+ wire [1:0] HWUSER_dma; // Write-data USER signals
// Manager port SI1 (outputs to master 1)
- wire [31:0] HRDATA_dma; // Read data bus
- wire HREADY_dma; // HREADY feedback
- wire HRESP_dma; // Transfer response
- wire [1:0] HRUSER_dma; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_dma; // Read data bus
+ wire HREADY_dma; // HREADY feedback
+ wire HRESP_dma; // Transfer response
+ wire [1:0] HRUSER_dma; // Read-data USER signals
// Manager port SI2 (inputs from master 2)
- wire [31:0] HADDR_dma2; // Address bus
- wire [1:0] HTRANS_dma2; // Transfer type
- wire HWRITE_dma2; // Transfer direction
- wire [2:0] HSIZE_dma2; // Transfer size
- wire [2:0] HBURST_dma2; // Burst type
- wire [3:0] HPROT_dma2; // Protection control
- wire [31:0] HWDATA_dma2; // Write data
- wire HMASTLOCK_dma2; // Locked Sequence
- wire [1:0] HAUSER_dma2; // Address USER signals
- wire [1:0] HWUSER_dma2; // Write-data USER signals
+ wire [SYS_ADDR_W-1:0] HADDR_dma2; // Address bus
+ wire [1:0] HTRANS_dma2; // Transfer type
+ wire HWRITE_dma2; // Transfer direction
+ wire [2:0] HSIZE_dma2; // Transfer size
+ wire [2:0] HBURST_dma2; // Burst type
+ wire [3:0] HPROT_dma2; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_dma2; // Write data
+ wire HMASTLOCK_dma2; // Locked Sequence
+ wire [1:0] HAUSER_dma2; // Address USER signals
+ wire [1:0] HWUSER_dma2; // Write-data USER signals
// Manager port SI2 (outputs to master 2)
- wire [31:0] HRDATA_dma2; // Read data bus
- wire HREADY_dma2; // HREADY feedback
- wire HRESP_dma2; // Transfer response
- wire [1:0] HRUSER_dma2; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_dma2; // Read data bus
+ wire HREADY_dma2; // HREADY feedback
+ wire HRESP_dma2; // Transfer response
+ wire [1:0] HRUSER_dma2; // Read-data USER signals
// Manager port SI3 (inputs from master 3)
- wire [31:0] HADDR_cpu; // Address bus
- wire [1:0] HTRANS_cpu; // Transfer type
- wire HWRITE_cpu; // Transfer direction
- wire [2:0] HSIZE_cpu; // Transfer size
- wire [2:0] HBURST_cpu; // Burst type
- wire [3:0] HPROT_cpu; // Protection control
- wire [31:0] HWDATA_cpu; // Write data
- wire HMASTLOCK_cpu; // Locked Sequence
- wire [1:0] HAUSER_cpu; // Address USER signals
- wire [1:0] HWUSER_cpu; // Write-data USER signals
+ wire [SYS_ADDR_W-1:0] HADDR_cpu; // Address bus
+ wire [1:0] HTRANS_cpu; // Transfer type
+ wire HWRITE_cpu; // Transfer direction
+ wire [2:0] HSIZE_cpu; // Transfer size
+ wire [2:0] HBURST_cpu; // Burst type
+ wire [3:0] HPROT_cpu; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_cpu; // Write data
+ wire HMASTLOCK_cpu; // Locked Sequence
+ wire [1:0] HAUSER_cpu; // Address USER signals
+ wire [1:0] HWUSER_cpu; // Write-data USER signals
// Manager port SI3 (outputs to master 3)
- wire [31:0] HRDATA_cpu; // Read data bus
- wire HREADY_cpu; // HREADY feedback
- wire HRESP_cpu; // Transfer response
- wire [1:0] HRUSER_cpu; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_cpu; // Read data bus
+ wire HREADY_cpu; // HREADY feedback
+ wire HRESP_cpu; // Transfer response
+ wire [1:0] HRUSER_cpu; // Read-data USER signals
// Subordinate port MI0 (outputs to slave 0)
- wire HSEL_rom1; // Slave Select
- wire [31:0] HADDR_rom1; // Address bus
- wire [1:0] HTRANS_rom1; // Transfer type
- wire HWRITE_rom1; // Transfer direction
- wire [2:0] HSIZE_rom1; // Transfer size
- wire [2:0] HBURST_rom1; // Burst type
- wire [3:0] HPROT_rom1; // Protection control
- wire [31:0] HWDATA_rom1; // Write data
- wire HMASTLOCK_rom1; // Locked Sequence
- wire HREADYMUX_rom1; // Transfer done
- wire [1:0] HAUSER_rom1; // Address USER signals
- wire [1:0] HWUSER_rom1; // Write-data USER signals
+ wire HSEL_bootrom; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_bootrom; // Address bus
+ wire [1:0] HTRANS_bootrom; // Transfer type
+ wire HWRITE_bootrom; // Transfer direction
+ wire [2:0] HSIZE_bootrom; // Transfer size
+ wire [2:0] HBURST_bootrom; // Burst type
+ wire [3:0] HPROT_bootrom; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_bootrom; // Write data
+ wire HMASTLOCK_bootrom; // Locked Sequence
+ wire HREADYMUX_bootrom; // Transfer done
+ wire [1:0] HAUSER_bootrom; // Address USER signals
+ wire [1:0] HWUSER_bootrom; // Write-data USER signals
// Subordinate port MI0 (inputs from slave 0)
- wire [31:0] HRDATA_rom1; // Read data bus
- wire HREADYOUT_rom1; // HREADY feedback
- wire HRESP_rom1; // Transfer response
- wire [1:0] HRUSER_rom1; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_bootrom; // Read data bus
+ wire HREADYOUT_bootrom; // HREADY feedback
+ wire HRESP_bootrom; // Transfer response
+ wire [1:0] HRUSER_bootrom; // Read-data USER signals
// Subordinate port MI1 (outputs to slave 1)
- wire HSEL_ram2; // Slave Select
- wire [31:0] HADDR_ram2; // Address bus
- wire [1:0] HTRANS_ram2; // Transfer type
- wire HWRITE_ram2; // Transfer direction
- wire [2:0] HSIZE_ram2; // Transfer size
- wire [2:0] HBURST_ram2; // Burst type
- wire [3:0] HPROT_ram2; // Protection control
- wire [31:0] HWDATA_ram2; // Write data
- wire HMASTLOCK_ram2; // Locked Sequence
- wire HREADYMUX_ram2; // Transfer done
- wire [1:0] HAUSER_ram2; // Address USER signals
- wire [1:0] HWUSER_ram2; // Write-data USER signals
+ wire HSEL_imem; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_imem; // Address bus
+ wire [1:0] HTRANS_imem; // Transfer type
+ wire HWRITE_imem; // Transfer direction
+ wire [2:0] HSIZE_imem; // Transfer size
+ wire [2:0] HBURST_imem; // Burst type
+ wire [3:0] HPROT_imem; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_imem; // Write data
+ wire HMASTLOCK_imem; // Locked Sequence
+ wire HREADYMUX_imem; // Transfer done
+ wire [1:0] HAUSER_imem; // Address USER signals
+ wire [1:0] HWUSER_imem; // Write-data USER signals
// Subordinate port MI1 (inputs from slave 1)
- wire [31:0] HRDATA_ram2; // Read data bus
- wire HREADYOUT_ram2; // HREADY feedback
- wire HRESP_ram2; // Transfer response
- wire [1:0] HRUSER_ram2; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_imem; // Read data bus
+ wire HREADYOUT_imem; // HREADY feedback
+ wire HRESP_imem; // Transfer response
+ wire [1:0] HRUSER_imem; // Read-data USER signals
// Subordinate port MI2 (outputs to slave 2)
- wire HSEL_ram3; // Slave Select
- wire [31:0] HADDR_ram3; // Address bus
- wire [1:0] HTRANS_ram3; // Transfer type
- wire HWRITE_ram3; // Transfer direction
- wire [2:0] HSIZE_ram3; // Transfer size
- wire [2:0] HBURST_ram3; // Burst type
- wire [3:0] HPROT_ram3; // Protection control
- wire [31:0] HWDATA_ram3; // Write data
- wire HMASTLOCK_ram3; // Locked Sequence
- wire HREADYMUX_ram3; // Transfer done
- wire [1:0] HAUSER_ram3; // Address USER signals
- wire [1:0] HWUSER_ram3; // Write-data USER signals
+ wire HSEL_dmem; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_dmem; // Address bus
+ wire [1:0] HTRANS_dmem; // Transfer type
+ wire HWRITE_dmem; // Transfer direction
+ wire [2:0] HSIZE_dmem; // Transfer size
+ wire [2:0] HBURST_dmem; // Burst type
+ wire [3:0] HPROT_dmem; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_dmem; // Write data
+ wire HMASTLOCK_dmem; // Locked Sequence
+ wire HREADYMUX_dmem; // Transfer done
+ wire [1:0] HAUSER_dmem; // Address USER signals
+ wire [1:0] HWUSER_dmem; // Write-data USER signals
// Subordinate port MI2 (inputs from slave 2)
- wire [31:0] HRDATA_ram3; // Read data bus
- wire HREADYOUT_ram3; // HREADY feedback
- wire HRESP_ram3; // Transfer response
- wire [1:0] HRUSER_ram3; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_dmem; // Read data bus
+ wire HREADYOUT_dmem; // HREADY feedback
+ wire HRESP_dmem; // Transfer response
+ wire [1:0] HRUSER_dmem; // Read-data USER signals
// Subordinate port MI3 (outputs to slave 3)
- wire HSEL_sys; // Slave Select
- wire [31:0] HADDR_sys; // Address bus
- wire [1:0] HTRANS_sys; // Transfer type
- wire HWRITE_sys; // Transfer direction
- wire [2:0] HSIZE_sys; // Transfer size
- wire [2:0] HBURST_sys; // Burst type
- wire [3:0] HPROT_sys; // Protection control
- wire [31:0] HWDATA_sys; // Write data
- wire HMASTLOCK_sys; // Locked Sequence
- wire HREADYMUX_sys; // Transfer done
- wire [1:0] HAUSER_sys; // Address USER signals
- wire [1:0] HWUSER_sys; // Write-data USER signals
+ wire HSEL_sysio; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_sysio; // Address bus
+ wire [1:0] HTRANS_sysio; // Transfer type
+ wire HWRITE_sysio; // Transfer direction
+ wire [2:0] HSIZE_sysio; // Transfer size
+ wire [2:0] HBURST_sysio; // Burst type
+ wire [3:0] HPROT_sysio; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_sysio; // Write data
+ wire HMASTLOCK_sysio; // Locked Sequence
+ wire HREADYMUX_sysio; // Transfer done
+ wire [1:0] HAUSER_sysio; // Address USER signals
+ wire [1:0] HWUSER_sysio; // Write-data USER signals
// Subordinate port MI3 (inputs from slave 3)
- wire [31:0] HRDATA_sys; // Read data bus
- wire HREADYOUT_sys; // HREADY feedback
- wire HRESP_sys; // Transfer response
- wire [1:0] HRUSER_sys; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_sysio; // Read data bus
+ wire HREADYOUT_sysio; // HREADY feedback
+ wire HRESP_sysio; // Transfer response
+ wire [1:0] HRUSER_sysio; // Read-data USER signals
// Subordinate port MI4 (outputs to slave 4)
- wire HSEL_ram8; // Slave Select
- wire [31:0] HADDR_ram8; // Address bus
- wire [1:0] HTRANS_ram8; // Transfer type
- wire HWRITE_ram8; // Transfer direction
- wire [2:0] HSIZE_ram8; // Transfer size
- wire [2:0] HBURST_ram8; // Burst type
- wire [3:0] HPROT_ram8; // Protection control
- wire [31:0] HWDATA_ram8; // Write data
- wire HMASTLOCK_ram8; // Locked Sequence
- wire HREADYMUX_ram8; // Transfer done
- wire [1:0] HAUSER_ram8; // Address USER signals
- wire [1:0] HWUSER_ram8; // Write-data USER signals
+ wire HSEL_expram_l; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_expram_l; // Address bus
+ wire [1:0] HTRANS_expram_l; // Transfer type
+ wire HWRITE_expram_l; // Transfer direction
+ wire [2:0] HSIZE_expram_l; // Transfer size
+ wire [2:0] HBURST_expram_l; // Burst type
+ wire [3:0] HPROT_expram_l; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_expram_l; // Write data
+ wire HMASTLOCK_expram_l; // Locked Sequence
+ wire HREADYMUX_expram_l; // Transfer done
+ wire [1:0] HAUSER_expram_l; // Address USER signals
+ wire [1:0] HWUSER_expram_l; // Write-data USER signals
// Subordinate port MI4 (inputs from slave 4)
- wire [31:0] HRDATA_ram8; // Read data bus
- wire HREADYOUT_ram8; // HREADY feedback
- wire HRESP_ram8; // Transfer response
- wire [1:0] HRUSER_ram8; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_expram_l; // Read data bus
+ wire HREADYOUT_expram_l; // HREADY feedback
+ wire HRESP_expram_l; // Transfer response
+ wire [1:0] HRUSER_expram_l; // Read-data USER signals
// Subordinate port MI5 (outputs to slave 5)
- wire HSEL_ram9; // Slave Select
- wire [31:0] HADDR_ram9; // Address bus
- wire [1:0] HTRANS_ram9; // Transfer type
- wire HWRITE_ram9; // Transfer direction
- wire [2:0] HSIZE_ram9; // Transfer size
- wire [2:0] HBURST_ram9; // Burst type
- wire [3:0] HPROT_ram9; // Protection control
- wire [31:0] HWDATA_ram9; // Write data
- wire HMASTLOCK_ram9; // Locked Sequence
- wire HREADYMUX_ram9; // Transfer done
- wire [1:0] HAUSER_ram9; // Address USER signals
- wire [1:0] HWUSER_ram9; // Write-data USER signals
- // Subordinate port MI5 (inputs from slave 5)
- wire [31:0] HRDATA_ram9; // Read data bus
- wire HREADYOUT_ram9; // HREADY feedback
- wire HRESP_ram9; // Transfer response
- wire [1:0] HRUSER_ram9; // Read-data USER signals
-
- // Subordinate port MI6 (outputs to slave 6)
- wire HSEL_exp; // Slave Select
- wire [31:0] HADDR_exp; // Address bus
- wire [1:0] HTRANS_exp; // Transfer type
- wire HWRITE_exp; // Transfer direction
- wire [2:0] HSIZE_exp; // Transfer size
- wire [2:0] HBURST_exp; // Burst type
- wire [3:0] HPROT_exp; // Protection control
- wire [31:0] HWDATA_exp; // Write data
- wire HMASTLOCK_exp; // Locked Sequence
- wire HREADYMUX_exp; // Transfer done
- wire [1:0] HAUSER_exp; // Address USER signals
- wire [1:0] HWUSER_exp; // Write-data USER signals
+ wire HSEL_expram_h; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_expram_h; // Address bus
+ wire [1:0] HTRANS_expram_h; // Transfer type
+ wire HWRITE_expram_h; // Transfer direction
+ wire [2:0] HSIZE_expram_h; // Transfer size
+ wire [2:0] HBURST_expram_h; // Burst type
+ wire [3:0] HPROT_expram_h; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_expram_h; // Write data
+ wire HMASTLOCK_expram_h; // Locked Sequence
+ wire HREADYMUX_expram_h; // Transfer done
+ wire [1:0] HAUSER_expram_h; // Address USER signals
+ wire [1:0] HWUSER_expram_h; // Write-data USER signals
// Subordinate port MI5 (inputs from slave 5)
- wire [31:0] HRDATA_exp; // Read data bus
- wire HREADYOUT_exp; // HREADY feedback
- wire HRESP_exp; // Transfer response
- wire [1:0] HRUSER_exp; // Read-data USER signals
+ wire [SYS_DATA_W-1:0] HRDATA_expram_h; // Read data bus
+ wire HREADYOUT_expram_h; // HREADY feedback
+ wire HRESP_expram_h; // Transfer response
+ wire [1:0] HRUSER_expram_h; // Read-data USER signals
+
+ // Subordinate port MI6 (outputs to slave 6)
+ wire HSEL_exp; // Slave Select
+ wire [SYS_ADDR_W-1:0] HADDR_exp; // Address bus
+ wire [1:0] HTRANS_exp; // Transfer type
+ wire HWRITE_exp; // Transfer direction
+ wire [2:0] HSIZE_exp; // Transfer size
+ wire [2:0] HBURST_exp; // Burst type
+ wire [3:0] HPROT_exp; // Protection control
+ wire [SYS_DATA_W-1:0] HWDATA_exp; // Write data
+ wire HMASTLOCK_exp; // Locked Sequence
+ wire HREADYMUX_exp; // Transfer done
+ wire [1:0] HAUSER_exp; // Address USER signals
+ wire [1:0] HWUSER_exp; // Write-data USER signals
+ // Subordinate port MI5 (inputs from slave 6)
+ wire [SYS_DATA_W-1:0] HRDATA_exp; // Read data bus
+ wire HREADYOUT_exp; // HREADY feedback
+ wire HRESP_exp; // Transfer response
+ wire [1:0] HRUSER_exp; // Read-data USER signals
//------------------------------------------------------------------------------
@@ -623,8 +624,7 @@ localparam CORTEX_M0 = 1;
//------------------------------------------------------------------------------
// BusMatrix instance
- nanosoc_ahb32_4x7_busmatrix_lite
- u_nanosoc_ahb32_4x7_busmatrix_lite (
+ nanosoc_ahb32_4x7_busmatrix_lite u_nanosoc_ahb32_4x7_busmatrix_lite (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REMAP (REMAP),
@@ -694,112 +694,112 @@ localparam CORTEX_M0 = 1;
.HRUSER_cpu (HRUSER_cpu),
// Output port MI0 signals
- .HSEL_rom1 (HSEL_rom1),
- .HADDR_rom1 (HADDR_rom1),
- .HTRANS_rom1 (HTRANS_rom1),
- .HWRITE_rom1 (HWRITE_rom1),
- .HSIZE_rom1 (HSIZE_rom1),
- .HBURST_rom1 (HBURST_rom1),
- .HPROT_rom1 (HPROT_rom1),
- .HWDATA_rom1 (HWDATA_rom1),
- .HMASTLOCK_rom1 (HMASTLOCK_rom1),
- .HREADYMUX_rom1 (HREADYMUX_rom1),
- .HAUSER_rom1 (HAUSER_rom1),
- .HWUSER_rom1 (HWUSER_rom1),
- .HRDATA_rom1 (HRDATA_rom1),
- .HREADYOUT_rom1 (HREADYOUT_rom1),
- .HRESP_rom1 (HRESP_rom1),
- .HRUSER_rom1 (HRUSER_rom1),
+ .HSEL_bootrom (HSEL_bootrom),
+ .HADDR_bootrom (HADDR_bootrom),
+ .HTRANS_bootrom (HTRANS_bootrom),
+ .HWRITE_bootrom (HWRITE_bootrom),
+ .HSIZE_bootrom (HSIZE_bootrom),
+ .HBURST_bootrom (HBURST_bootrom),
+ .HPROT_bootrom (HPROT_bootrom),
+ .HWDATA_bootrom (HWDATA_bootrom),
+ .HMASTLOCK_bootrom (HMASTLOCK_bootrom),
+ .HREADYMUX_bootrom (HREADYMUX_bootrom),
+ .HAUSER_bootrom (HAUSER_bootrom),
+ .HWUSER_bootrom (HWUSER_bootrom),
+ .HRDATA_bootrom (HRDATA_bootrom),
+ .HREADYOUT_bootrom (HREADYOUT_bootrom),
+ .HRESP_bootrom (HRESP_bootrom),
+ .HRUSER_bootrom (HRUSER_bootrom),
// Output port MI1 signals
- .HSEL_ram2 (HSEL_ram2),
- .HADDR_ram2 (HADDR_ram2),
- .HTRANS_ram2 (HTRANS_ram2),
- .HWRITE_ram2 (HWRITE_ram2),
- .HSIZE_ram2 (HSIZE_ram2),
- .HBURST_ram2 (HBURST_ram2),
- .HPROT_ram2 (HPROT_ram2),
- .HWDATA_ram2 (HWDATA_ram2),
- .HMASTLOCK_ram2 (HMASTLOCK_ram2),
- .HREADYMUX_ram2 (HREADYMUX_ram2),
- .HAUSER_ram2 (HAUSER_ram2),
- .HWUSER_ram2 (HWUSER_ram2),
- .HRDATA_ram2 (HRDATA_ram2),
- .HREADYOUT_ram2 (HREADYOUT_ram2),
- .HRESP_ram2 (HRESP_ram2),
- .HRUSER_ram2 (HRUSER_ram2),
+ .HSEL_imem (HSEL_imem),
+ .HADDR_imem (HADDR_imem),
+ .HTRANS_imem (HTRANS_imem),
+ .HWRITE_imem (HWRITE_imem),
+ .HSIZE_imem (HSIZE_imem),
+ .HBURST_imem (HBURST_imem),
+ .HPROT_imem (HPROT_imem),
+ .HWDATA_imem (HWDATA_imem),
+ .HMASTLOCK_imem (HMASTLOCK_imem),
+ .HREADYMUX_imem (HREADYMUX_imem),
+ .HAUSER_imem (HAUSER_imem),
+ .HWUSER_imem (HWUSER_imem),
+ .HRDATA_imem (HRDATA_imem),
+ .HREADYOUT_imem (HREADYOUT_imem),
+ .HRESP_imem (HRESP_imem),
+ .HRUSER_imem (HRUSER_imem),
// Output port MI2 signals
- .HSEL_ram3 (HSEL_ram3),
- .HADDR_ram3 (HADDR_ram3),
- .HTRANS_ram3 (HTRANS_ram3),
- .HWRITE_ram3 (HWRITE_ram3),
- .HSIZE_ram3 (HSIZE_ram3),
- .HBURST_ram3 (HBURST_ram3),
- .HPROT_ram3 (HPROT_ram3),
- .HWDATA_ram3 (HWDATA_ram3),
- .HMASTLOCK_ram3 (HMASTLOCK_ram3),
- .HREADYMUX_ram3 (HREADYMUX_ram3),
- .HAUSER_ram3 (HAUSER_ram3),
- .HWUSER_ram3 (HWUSER_ram3),
- .HRDATA_ram3 (HRDATA_ram3),
- .HREADYOUT_ram3 (HREADYOUT_ram3),
- .HRESP_ram3 (HRESP_ram3),
- .HRUSER_ram3 (HRUSER_ram3),
+ .HSEL_dmem (HSEL_dmem),
+ .HADDR_dmem (HADDR_dmem),
+ .HTRANS_dmem (HTRANS_dmem),
+ .HWRITE_dmem (HWRITE_dmem),
+ .HSIZE_dmem (HSIZE_dmem),
+ .HBURST_dmem (HBURST_dmem),
+ .HPROT_dmem (HPROT_dmem),
+ .HWDATA_dmem (HWDATA_dmem),
+ .HMASTLOCK_dmem (HMASTLOCK_dmem),
+ .HREADYMUX_dmem (HREADYMUX_dmem),
+ .HAUSER_dmem (HAUSER_dmem),
+ .HWUSER_dmem (HWUSER_dmem),
+ .HRDATA_dmem (HRDATA_dmem),
+ .HREADYOUT_dmem (HREADYOUT_dmem),
+ .HRESP_dmem (HRESP_dmem),
+ .HRUSER_dmem (HRUSER_dmem),
// Output port MI3 signals
- .HSEL_sys (HSEL_sys),
- .HADDR_sys (HADDR_sys),
- .HTRANS_sys (HTRANS_sys),
- .HWRITE_sys (HWRITE_sys),
- .HSIZE_sys (HSIZE_sys),
- .HBURST_sys (HBURST_sys),
- .HPROT_sys (HPROT_sys),
- .HWDATA_sys (HWDATA_sys),
- .HMASTLOCK_sys (HMASTLOCK_sys),
- .HREADYMUX_sys (HREADYMUX_sys),
- .HAUSER_sys (HAUSER_sys),
- .HWUSER_sys (HWUSER_sys),
- .HRDATA_sys (HRDATA_sys),
- .HREADYOUT_sys (HREADYOUT_sys),
- .HRESP_sys (HRESP_sys),
- .HRUSER_sys (HRUSER_sys),
+ .HSEL_sysio (HSEL_sysio),
+ .HADDR_sysio (HADDR_sysio),
+ .HTRANS_sysio (HTRANS_sysio),
+ .HWRITE_sysio (HWRITE_sysio),
+ .HSIZE_sysio (HSIZE_sysio),
+ .HBURST_sysio (HBURST_sysio),
+ .HPROT_sysio (HPROT_sysio),
+ .HWDATA_sysio (HWDATA_sysio),
+ .HMASTLOCK_sysio (HMASTLOCK_sysio),
+ .HREADYMUX_sysio (HREADYMUX_sysio),
+ .HAUSER_sysio (HAUSER_sysio),
+ .HWUSER_sysio (HWUSER_sysio),
+ .HRDATA_sysio (HRDATA_sysio),
+ .HREADYOUT_sysio (HREADYOUT_sysio),
+ .HRESP_sysio (HRESP_sysio),
+ .HRUSER_sysio (HRUSER_sysio),
// Output port MI4 signals
- .HSEL_ram8 (HSEL_ram8),
- .HADDR_ram8 (HADDR_ram8),
- .HTRANS_ram8 (HTRANS_ram8),
- .HWRITE_ram8 (HWRITE_ram8),
- .HSIZE_ram8 (HSIZE_ram8),
- .HBURST_ram8 (HBURST_ram8),
- .HPROT_ram8 (HPROT_ram8),
- .HWDATA_ram8 (HWDATA_ram8),
- .HMASTLOCK_ram8 (HMASTLOCK_ram8),
- .HREADYMUX_ram8 (HREADYMUX_ram8),
- .HAUSER_ram8 (HAUSER_ram8),
- .HWUSER_ram8 (HWUSER_ram8),
- .HRDATA_ram8 (HRDATA_ram8),
- .HREADYOUT_ram8 (HREADYOUT_ram8),
- .HRESP_ram8 (HRESP_ram8),
- .HRUSER_ram8 (HRUSER_ram8),
+ .HSEL_expram_l (HSEL_expram_l),
+ .HADDR_expram_l (HADDR_expram_l),
+ .HTRANS_expram_l (HTRANS_expram_l),
+ .HWRITE_expram_l (HWRITE_expram_l),
+ .HSIZE_expram_l (HSIZE_expram_l),
+ .HBURST_expram_l (HBURST_expram_l),
+ .HPROT_expram_l (HPROT_expram_l),
+ .HWDATA_expram_l (HWDATA_expram_l),
+ .HMASTLOCK_expram_l (HMASTLOCK_expram_l),
+ .HREADYMUX_expram_l (HREADYMUX_expram_l),
+ .HAUSER_expram_l (HAUSER_expram_l),
+ .HWUSER_expram_l (HWUSER_expram_l),
+ .HRDATA_expram_l (HRDATA_expram_l),
+ .HREADYOUT_expram_l (HREADYOUT_expram_l),
+ .HRESP_expram_l (HRESP_expram_l),
+ .HRUSER_expram_l (HRUSER_expram_l),
// Output port MI5 signals
- .HSEL_ram9 (HSEL_ram9),
- .HADDR_ram9 (HADDR_ram9),
- .HTRANS_ram9 (HTRANS_ram9),
- .HWRITE_ram9 (HWRITE_ram9),
- .HSIZE_ram9 (HSIZE_ram9),
- .HBURST_ram9 (HBURST_ram9),
- .HPROT_ram9 (HPROT_ram9),
- .HWDATA_ram9 (HWDATA_ram9),
- .HMASTLOCK_ram9 (HMASTLOCK_ram9),
- .HREADYMUX_ram9 (HREADYMUX_ram9),
- .HAUSER_ram9 (HAUSER_ram9),
- .HWUSER_ram9 (HWUSER_ram9),
- .HRDATA_ram9 (HRDATA_ram9),
- .HREADYOUT_ram9 (HREADYOUT_ram9),
- .HRESP_ram9 (HRESP_ram9),
- .HRUSER_ram9 (HRUSER_ram9),
+ .HSEL_expram_h (HSEL_expram_h),
+ .HADDR_expram_h (HADDR_expram_h),
+ .HTRANS_expram_h (HTRANS_expram_h),
+ .HWRITE_expram_h (HWRITE_expram_h),
+ .HSIZE_expram_h (HSIZE_expram_h),
+ .HBURST_expram_h (HBURST_expram_h),
+ .HPROT_expram_h (HPROT_expram_h),
+ .HWDATA_expram_h (HWDATA_expram_h),
+ .HMASTLOCK_expram_h (HMASTLOCK_expram_h),
+ .HREADYMUX_expram_h (HREADYMUX_expram_h),
+ .HAUSER_expram_h (HAUSER_expram_h),
+ .HWUSER_expram_h (HWUSER_expram_h),
+ .HRDATA_expram_h (HRDATA_expram_h),
+ .HREADYOUT_expram_h (HREADYOUT_expram_h),
+ .HRESP_expram_h (HRESP_expram_h),
+ .HRUSER_expram_h (HRUSER_expram_h),
// Output port MI6 signals
.HSEL_exp (HSEL_exp),
@@ -825,6 +825,102 @@ localparam CORTEX_M0 = 1;
.SCANOUTHCLK (SCANOUTHCLK)
);
+//----------------------------------------
+// Bootrom Region (region_bootrom)
+//----------------------------------------
+
+ localparam BOOTROM_ADDR_W = 10;
+
+ nanosoc_region_bootrom #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .BOOTROM_ADDR_W (BOOTROM_ADDR_W)
+ ) u_nanosoc_region_bootrom (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_bootrom),
+ .HADDR (HADDR_bootrom),
+ .HTRANS (HTRANS_bootrom),
+ .HSIZE (HSIZE_bootrom),
+ .HPROT (HPROT_bootrom),
+ .HWRITE (HWRITE_bootrom),
+ .HREADY (HREADYMUX_bootrom),
+ .HWDATA (HWDATA_bootrom),
+ .HREADYOUT (HREADYOUTS_bootrom),
+ .HRESP (HRESPS_bootrom),
+ .HRDATA (HRDATA_bootrom)
+ );
+
+//----------------------------------------
+// Instruction Memory Region (region_imem)
+//----------------------------------------
+
+ localparam IMEM_RAM_ADDR_W = RAM_ADDR_W;
+ localparam IMEM_RAM_DATA_W = RAM_DATA_W;
+ localparam IMEM_RAM_FPGA_IMG = "image.hex";
+
+ nanosoc_region_imem #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .IMEM_RAM_ADDR_W (IMEM_RAM_ADDR_W),
+ .IMEM_RAM_DATA_W (IMEM_RAM_DATA_W),
+ .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG)
+ ) u_nanosoc_region_imem (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_imem),
+ .HADDR (HADDR_imem),
+ .HTRANS (HTRANS_imem),
+ .HSIZE (HSIZE_imem),
+ .HPROT (HPROT_imem),
+ .HWRITE (HWRITE_imem),
+ .HREADY (HREADYMUX_imem),
+ .HWDATA (HWDATA_imem),
+ .HREADYOUT (HREADYOUTS_imem),
+ .HRESP (HRESPS_imem),
+ .HRDATA (HRDATA_imem)
+ );
+
+//----------------------------------------
+// Data Memory Region (region_dmem)
+//----------------------------------------
+
+ localparam DMEM_RAM_ADDR_W = RAM_ADDR_W;
+ localparam DMEM_RAM_DATA_W = RAM_DATA_W;
+
+ nanosoc_region_dmem #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
+ .DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
+ ) u_nanosoc_region_dmem (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_dmem),
+ .HADDR (HADDR_dmem),
+ .HTRANS (HTRANS_dmem),
+ .HSIZE (HSIZE_dmem),
+ .HPROT (HPROT_dmem),
+ .HWRITE (HWRITE_dmem),
+ .HREADY (HREADYMUX_dmem),
+ .HWDATA (HWDATA_dmem),
+ .HREADYOUT (HREADYOUTS_dmem),
+ .HRESP (HRESPS_dmem),
+ .HRDATA (HRDATA_dmem)
+ );
+
+//----------------------------------------
+// System Peripheral Region (region_sysio)
+//----------------------------------------
+
+//---------------------------------------------
+// Expansion SRAM Low Region (region_expram_l)
+//---------------------------------------------
+
+//----------------------------------------------
+// Expansion SRAM High Region (region_expram_h)
+//----------------------------------------------
+
// ************************************************
// ************************************************
//
@@ -842,7 +938,7 @@ localparam CORTEX_M0 = 1;
assign exp_irq2 = exp_irq[2];
assign exp_irq3 = exp_irq[3];
- //----------------------------------------
+//----------------------------------------
// Expansion Region "exp" instance
//----------------------------------------
@@ -895,150 +991,16 @@ nanosoc_exp_wrapper #(
assign HRUSER_exp = 2'b00;
-// ************************************************
-
-//----------------------------------------
-// Boot ROM "rom1" firmware
-// mapped 0x10000000-0x1fffffff
-// and on REMAP[0]
-// mapped 0x00000000-0x0000ffff
-//----------------------------------------
-
-nanosoc_ahb_bootrom
-// #(.AW(10) ) // 1K bytes ROM
- u_ahb_bootloader (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_rom1),
- .HADDR (HADDR_rom1[ 9:0]),
- .HTRANS (HTRANS_rom1),
- .HSIZE (HSIZE_rom1),
- .HWRITE (HWRITE_rom1),
- .HWDATA (HWDATA_rom1),
- .HREADY (HREADYMUX_rom1),
- .HREADYOUT (HREADYOUT_rom1),
- .HRDATA (HRDATA_rom1),
- .HRESP (HRESP_rom1)
- );
-
-//----------------------------------------
-// CODE/DATA "ram2"
-// mapped 0x20000000-0x2fffffff
-//----------------------------------------
-
-localparam AWRAM2 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM2-3:0] addr_ram2;
- wire [31:0] wdata_ram2;
- wire [31:0] rdata_ram2;
- wire [3:0] wen_ram2;
- wire cs_ram2;
-
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(.AW(AWRAM2)) u_ahb_to_sram2
- (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_ram2), // AHB inputs
- .HADDR (HADDR_ram2[AWRAM2-1:0]),
- .HTRANS (HTRANS_ram2),
- .HSIZE (HSIZE_ram2),
- .HWRITE (HWRITE_ram2),
- .HWDATA (HWDATA_ram2),
- .HREADY (HREADYMUX_ram2),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT_ram2), // Outputs
- .HRDATA (HRDATA_ram2),
- .HRESP (HRESP_ram2),
-
- // SRAM input
- .SRAMRDATA (rdata_ram2),
- // SRAM Outputs
- .SRAMADDR (addr_ram2),
- .SRAMWDATA (wdata_ram2),
- .SRAMWEN (wen_ram2),
- .SRAMCS (cs_ram2)
- );
-
- // SRAM model
-// cmsdk_fpga_sram #(.AW(AWRAM2)) u_fpga_ram2
- cmsdk_fpga_rom #(.AW(AWRAM2), .filename("image.hex") ) u_fpga_ram2
- (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr_ram2),
- .WDATA (wdata_ram2),
- .WREN (wen_ram2),
- .CS (cs_ram2),
- // SRAM Output
- .RDATA (rdata_ram2)
- );
-
-
-//----------------------------------------
-// DATA "ram3"
-// mapped 0x30000000-0x3fffffff
-//----------------------------------------
-
-localparam AWRAM3 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM3-3:0] addr_ram3;
- wire [31:0] wdata_ram3;
- wire [31:0] rdata_ram3;
- wire [3:0] wen_ram3;
- wire cs_ram3;
-
- // AHB to SRAM bridge
- cmsdk_ahb_to_sram #(.AW(AWRAM3)) u_ahb_to_sram3
- (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL_ram3), // AHB inputs
- .HADDR (HADDR_ram3[AWRAM3-1:0]),
- .HTRANS (HTRANS_ram3),
- .HSIZE (HSIZE_ram3),
- .HWRITE (HWRITE_ram3),
- .HWDATA (HWDATA_ram3),
- .HREADY (HREADYMUX_ram3),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT_ram3), // Outputs
- .HRDATA (HRDATA_ram3),
- .HRESP (HRESP_ram3),
-
- // SRAM input
- .SRAMRDATA (rdata_ram3),
- // SRAM Outputs
- .SRAMADDR (addr_ram3),
- .SRAMWDATA (wdata_ram3),
- .SRAMWEN (wen_ram3),
- .SRAMCS (cs_ram3)
- );
-
- // SRAM model
- cmsdk_fpga_sram #(.AW(AWRAM3)) u_fpga_ram3
- (
- // SRAM Inputs
- .CLK (HCLK),
- .ADDR (addr_ram3),
- .WDATA (wdata_ram3),
- .WREN (wen_ram3),
- .CS (cs_ram3),
- // SRAM Output
- .RDATA (rdata_ram3)
- );
-
//----------------------------------------
// Expansion/DMA "ram8,ram9" RAM instances
//----------------------------------------
localparam AWRAM8 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM8-3:0] addr_ram8;
- wire [31:0] wdata_ram8;
- wire [31:0] rdata_ram8;
- wire [3:0] wen_ram8;
- wire cs_ram8;
+ wire [AWRAM8-3:0] addr_expram_l;
+ wire [31:0] wdata_expram_l;
+ wire [31:0] rdata_expram_l;
+ wire [3:0] wen_expram_l;
+ wire cs_expram_l;
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(.AW(AWRAM8)) u_ahb_to_sram8
@@ -1046,49 +1008,49 @@ localparam AWRAM8 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
- .HSEL (HSEL_ram8), // AHB inputs
- .HADDR (HADDR_ram8[AWRAM8-1:0]),
- .HTRANS (HTRANS_ram8),
- .HSIZE (HSIZE_ram8),
- .HWRITE (HWRITE_ram8),
- .HWDATA (HWDATA_ram8),
- .HREADY (HREADYMUX_ram8),
+ .HSEL (HSEL_expram_l), // AHB inputs
+ .HADDR (HADDR_expram_l[AWRAM8-1:0]),
+ .HTRANS (HTRANS_expram_l),
+ .HSIZE (HSIZE_expram_l),
+ .HWRITE (HWRITE_expram_l),
+ .HWDATA (HWDATA_expram_l),
+ .HREADY (HREADYMUX_expram_l),
// AHB Outputs
- .HREADYOUT (HREADYOUT_ram8), // Outputs
- .HRDATA (HRDATA_ram8),
- .HRESP (HRESP_ram8),
+ .HREADYOUT (HREADYOUT_expram_l), // Outputs
+ .HRDATA (HRDATA_expram_l),
+ .HRESP (HRESP_expram_l),
// SRAM input
- .SRAMRDATA (rdata_ram8),
+ .SRAMRDATA (rdata_expram_l),
// SRAM Outputs
- .SRAMADDR (addr_ram8),
- .SRAMWDATA (wdata_ram8),
- .SRAMWEN (wen_ram8),
- .SRAMCS (cs_ram8)
+ .SRAMADDR (addr_expram_l),
+ .SRAMWDATA (wdata_expram_l),
+ .SRAMWEN (wen_expram_l),
+ .SRAMCS (cs_expram_l)
);
// SRAM model
- cmsdk_fpga_sram #(.AW(AWRAM8)) u_fpga_ram8
+ cmsdk_fpga_sram #(.AW(AWRAM8)) u_fpga_expram_l
(
// SRAM Inputs
.CLK (HCLK),
- .ADDR (addr_ram8),
- .WDATA (wdata_ram8),
- .WREN (wen_ram8),
- .CS (cs_ram8),
+ .ADDR (addr_expram_l),
+ .WDATA (wdata_expram_l),
+ .WREN (wen_expram_l),
+ .CS (cs_expram_l),
// SRAM Output
- .RDATA (rdata_ram8)
+ .RDATA (rdata_expram_l)
);
// instandiate expansion RAM instance to appear at 0x90000000
-localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
- wire [AWRAM9-3:0] addr_ram9;
- wire [31:0] wdata_ram9;
- wire [31:0] rdata_ram9;
- wire [3:0] wen_ram9;
- wire cs_ram9;
+ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance size
+ wire [AWRAM9-3:0] addr_expram_h;
+ wire [31:0] wdata_expram_h;
+ wire [31:0] rdata_expram_h;
+ wire [3:0] wen_expram_h;
+ wire cs_expram_h;
// AHB to SRAM bridge
cmsdk_ahb_to_sram #(.AW(AWRAM9)) u_ahb_to_sram9
@@ -1096,50 +1058,50 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
- .HSEL (HSEL_ram9), // AHB inputs
- .HADDR (HADDR_ram9[AWRAM9-1:0]),
- .HTRANS (HTRANS_ram9),
- .HSIZE (HSIZE_ram9),
- .HWRITE (HWRITE_ram9),
- .HWDATA (HWDATA_ram9),
- .HREADY (HREADYMUX_ram9),
+ .HSEL (HSEL_expram_h), // AHB inputs
+ .HADDR (HADDR_expram_h[AWRAM9-1:0]),
+ .HTRANS (HTRANS_expram_h),
+ .HSIZE (HSIZE_expram_h),
+ .HWRITE (HWRITE_expram_h),
+ .HWDATA (HWDATA_expram_h),
+ .HREADY (HREADYMUX_expram_h),
// AHB Outputs
- .HREADYOUT (HREADYOUT_ram9), // Outputs
- .HRDATA (HRDATA_ram9),
- .HRESP (HRESP_ram9),
+ .HREADYOUT (HREADYOUT_expram_h), // Outputs
+ .HRDATA (HRDATA_expram_h),
+ .HRESP (HRESP_expram_h),
// SRAM input
- .SRAMRDATA (rdata_ram9),
+ .SRAMRDATA (rdata_expram_h),
// SRAM Outputs
- .SRAMADDR (addr_ram9),
- .SRAMWDATA (wdata_ram9),
- .SRAMWEN (wen_ram9),
- .SRAMCS (cs_ram9)
+ .SRAMADDR (addr_expram_h),
+ .SRAMWDATA (wdata_expram_h),
+ .SRAMWEN (wen_expram_h),
+ .SRAMCS (cs_expram_h)
);
// SRAM model
- cmsdk_fpga_sram #(.AW(AWRAM9)) u_fpga_ram9
+ cmsdk_fpga_sram #(.AW(AWRAM9)) u_fpga_expram_h
(
// SRAM Inputs
.CLK (HCLK),
- .ADDR (addr_ram9),
- .WDATA (wdata_ram9),
- .WREN (wen_ram9),
- .CS (cs_ram9),
+ .ADDR (addr_expram_h),
+ .WDATA (wdata_expram_h),
+ .WREN (wen_expram_h),
+ .CS (cs_expram_h),
// SRAM Output
- .RDATA (rdata_ram9)
+ .RDATA (rdata_expram_h)
);
-// assign [31:0] HRDATA_ram8 = 32'hdead8888; // Read data bus
-// assign HREADYOUT_ram8 = 1'b1; // HREADY feedback
-// assign HRESP_ram8 = 1'b0; // Transfer response
-// assign [1:0] HRUSER_ram8 = 00; // Read-data USER signals
+// assign [31:0] HRDATA_expram_l = 32'hdead8888; // Read data bus
+// assign HREADYOUT_expram_l = 1'b1; // HREADY feedback
+// assign HRESP_expram_l = 1'b0; // Transfer response
+// assign [1:0] HRUSER_expram_l = 00; // Read-data USER signals
//
-// assign [31:0] HRDATA_ram9 = 32'hdead9999; // Read data bus
-// assign HREADYOUT_ram9 = 1'b1; // HREADY feedback
-// assign HRESP_ram9 = 1'b0; // Transfer response
-// assign [1:0] HRUSER_ram9 = 00; // Read-data USER signals
+// assign [31:0] HRDATA_expram_h = 32'hdead9999; // Read data bus
+// assign HREADYOUT_expram_h = 1'b1; // HREADY feedback
+// assign HRESP_expram_h = 1'b0; // Transfer response
+// assign [1:0] HRUSER_expram_h = 00; // Read-data USER signals
//----------------------------------------
@@ -1243,10 +1205,10 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
wire [7:0] ft_clkdiv = 8'd03;
- nanosoc_ft1248_stream_io_v1_0 #
- (.FT1248_WIDTH (1),
- .FT1248_CLKON(0) )
- u_ftdio_com (
+ nanosoc_ft1248_stream_io_v1_0 #(
+ .FT1248_WIDTH (1),
+ .FT1248_CLKON (0)
+ ) u_ftdio_com (
.clk (HCLK),
.resetn (HRESETn),
.ft_clkdiv (ft_clkdiv ),
@@ -1289,10 +1251,11 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
///generate if (INCLUDE_DMA != 0) begin : gen_dma
// DMA controller present
pl230_udma u_pl230_udma (
- // Clock and Reset
+ // Clock and Reset
.hclk (HCLK),
.hresetn (HRESETn),
- // DMA Control
+
+ // DMA Control
.dma_req (dma230_req),
.dma_sreq (dma230_req),
.dma_waitonreq (dma230_tie0),
@@ -1300,7 +1263,8 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
.dma_active (),
.dma_done (dma230_done_ch),
.dma_err (dmac_err),
- // AHB-Lite Master Interface
+
+ // AHB-Lite Master Interface
.hready (HREADY_dma),
.hresp (HRESP_dma),
.hrdata (HRDATA_dma),
@@ -1312,7 +1276,8 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
.hmastlock (HMASTLOCK_dma),
.hprot (HPROT_dma),
.hwdata (HWDATA_dma),
- // APB Slave Interface
+
+ // APB Slave Interface
.pclken (PCLKEN),
.psel (exp15_psel),
.pen (exp_penable),
@@ -1404,8 +1369,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
// Cortex-M0 integration level
- nanosoc_cpu
- u_nanosoc_cpu (
+ nanosoc_cpu u_nanosoc_cpu (
.HCLK (gated_hclk), //HCLK),
.FCLK (FCLK),
.DCLK (DCLK),
@@ -1468,41 +1432,31 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
assign p0_out_nen = ~p0_out_en; //active low pad drive option
assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
-
-
- // Common AHB signals
- wire [31:0] HADDR;
- wire [1:0] HTRANS;
- wire [2:0] HSIZE;
- wire HWRITE;
- wire [31:0] HWDATA;
- wire HREADY;
localparam BASEADDR_GPIO0 = 32'h4001_0000;
localparam BASEADDR_GPIO1 = 32'h4001_1000;
localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
- nanosoc_sysio
- u_nanosoc_sysio (
+ nanosoc_sysio u_nanosoc_sysio (
.FCLK (FCLK ), // free-running clock
.PORESETn (PORESETn ), // Power-On-Reset (active-low)
.TESTMODE (TESTMODE ), // Test-mode override for testability
.HCLK (HCLK ), // AHB interconnect clock
.HRESETn (HRESETn ), // AHB interconnect reset (active-low)
// Common AHB signals
- .HSEL (HSEL_sys ),
- .HADDR (HADDR_sys ),
- .HBURST (HBURST_sys ),
- .HMASTLOCK (HMASTLOCK_sys),
- .HPROT (HPROT_sys ),
- .HSIZE (HSIZE_sys ),
- .HTRANS (HTRANS_sys ),
- .HWDATA (HWDATA_sys ),
- .HWRITE (HWRITE_sys ),
- .HREADY (HREADYMUX_sys),
- .HRDATA (HRDATA_sys ),
- .HRESP (HRESP_sys ),
- .HREADYOUT (HREADYOUT_sys),
+ .HSEL (HSEL_sysio ),
+ .HADDR (HADDR_sysio ),
+ .HBURST (HBURST_sysio ),
+ .HMASTLOCK (HMASTLOCK_sysio),
+ .HPROT (HPROT_sysio ),
+ .HSIZE (HSIZE_sysio ),
+ .HTRANS (HTRANS_sysio ),
+ .HWDATA (HWDATA_sysio ),
+ .HWRITE (HWRITE_sysio ),
+ .HREADY (HREADYMUX_sysio),
+ .HRDATA (HRDATA_sysio ),
+ .HRESP (HRESP_sysio ),
+ .HREADYOUT (HREADYOUT_sysio),
// APB clocking
.PCLK (PCLK ),
.PCLKG (PCLKG ),
@@ -1594,8 +1548,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
assign swdio_e = SWDOEN;
assign swdio_z = !SWDOEN;
- nanosoc_mcu_pin_mux
- u_pin_mux (
+ nanosoc_mcu_pin_mux u_pin_mux (
// UART
.uart0_rxd (uart0_rxd),
.uart0_txd (uart0_txd),
diff --git a/system/src/nanosoc_chip/chip/verilog/nanosoc_chip_new.v b/system/src/nanosoc_chip/chip/verilog/nanosoc_chip_new.v
new file mode 100644
index 0000000000000000000000000000000000000000..8e4958d7b5938257da5f140821b27f98e2ff9fc2
--- /dev/null
+++ b/system/src/nanosoc_chip/chip/verilog/nanosoc_chip_new.v
@@ -0,0 +1,835 @@
+module nanosoc_chip #(
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 32,
+ parameter RAM_ADDR_W = 14,
+ parameter RAM_DATA_W = 32,
+ parameter DMA_CHANNEL_NUM = 2,
+ parameter CLKGATE_PRESENT = 0
+ )(
+ `ifdef POWER_PINS
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+ `endif
+ input wire xtal_clk_i,
+ output wire xtal_clk_o,
+ input wire nrst_i,
+ input wire [15:0] p0_i, // level-shifted input from pad
+ output wire [15:0] p0_o, // output port drive
+ output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
+ input wire [15:0] p1_i, // level-shifted input from pad
+ output wire [15:0] p1_o, // output port drive
+ output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
+ output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
+ input wire swdio_i,
+ output wire swdio_o,
+ output wire swdio_e,
+ output wire swdio_z,
+ input wire swdclk_i
+ );
+
+ //------------------------------------
+ // CMSDK internal wire naming preserved
+ //------------------------------------
+
+ wire xtal_clk_in;
+ wire xtal_clk_out;
+ wire pll_clk;
+ wire CLK;
+
+ assign xtal_clk_in = xtal_clk_i;
+ assign xtal_clk_o = xtal_clk_out;
+ wire nrst_in = nrst_i;
+
+ wire [15:0] p0_in; // level-shifted input from pad
+ wire [15:0] p0_out; // output port drive
+ wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
+
+ wire [15:0] p1_in; // level-shifted input from pad
+ wire [15:0] p1_out; // output port drive
+ wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_in_mux; // level-shifted input from pad
+ wire [15:0] p1_out_mux; // output port drive
+ wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
+
+ wire swdio_in;
+ wire swdio_out;
+ wire swdio_out_en;
+ wire swdio_out_nen;
+ wire swdclk_in;
+
+ wire ft_clk_o;
+ wire ft_ssn_o;
+ wire ft_miso_i;
+ wire ft_miosio_o;
+ wire ft_miosio_e;
+ wire ft_miosio_z;
+ wire ft_miosio_i;
+
+ // --------------------------------------------------------------------------------
+ // Port-0 IO pad driver mapping
+ // --------------------------------------------------------------------------------
+
+ assign p0_in = p0_i; // level-shifted input from pad
+ assign p0_o = p0_out; // output port drive
+ assign p0_e = p0_out_en; // active high output drive enable (pad tech dependent)
+ assign p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)
+
+
+ // --------------------------------------------------------------------------------
+ // Port-1 IO pad driver mapping
+ // --------------------------------------------------------------------------------
+
+ assign ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
+ assign p1_in_mux[0] = p1_i[0];
+ assign p1_o[0] = 1'b0;
+ assign p1_e[0] = 1'b0;
+ assign p1_z[0] = 1'b1;
+
+ assign p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
+ assign p1_o[1] = ft_clk_o;
+ assign p1_e[1] = 1'b1;
+ assign p1_z[1] = 1'b0;
+
+ assign ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
+ assign p1_in_mux[2] = p1_i[2];
+ assign p1_o[2] = ft_miosio_o;
+ assign p1_e[2] = ft_miosio_e;
+ assign p1_z[2] = ft_miosio_z;
+
+ assign p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
+ assign p1_o[3] = ft_ssn_o;
+ assign p1_e[3] = 1'b1;
+ assign p1_z[3] = 1'b0;
+
+ assign p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
+ assign p1_o[15:4] = p1_out_mux[15:4];
+ assign p1_e[15:4] = p1_out_en_mux[15:4];
+ assign p1_z[15:4] = p1_out_nen_mux[15:4];
+
+
+ wire tiehi = 1'b1;
+ wire tielo = 1'b0;
+
+ //----------------------------------------
+ // SoC Clock and Reset Management
+ //----------------------------------------
+
+ wire PORESETn;// Power on reset
+ wire HRESETn; // AHB reset
+ wire PRESETn; // APB and peripheral reset
+ wire DBGRESETn; // Debug system reset
+ wire FCLK; // Free running system clock
+ wire HCLK; // System clock from PMU
+ wire DCLK;
+ wire SCLK;
+ wire PCLK; // Peripheral clock
+ wire PCLKG; // Gated PCLK for APB
+ wire PCLKEN; // Clock divider for AHB to APB bridge
+ wire APBACTIVE;
+
+ // event signals
+ wire TXEV;
+ wire RXEV;
+ wire nTRST; // JTAG - Test reset (active low)
+ wire SWDI; // JTAG/SWD - TMS / SWD data input
+ wire SWCLK; // JTAG/SWD - TCK / SWCLK
+ wire SWDO; // SWD - SWD data output
+ wire SWDOEN; // SWD - SWD data output enable
+ wire SYSRESETREQ; // processor system reset request
+ wire WDOGRESETREQ; // watchdog system reset request
+ wire HRESETREQ; // Combined system reset request
+ wire NANOSOC_SYSRESETREQ; // Combined system reset request
+ wire clk_ctrl_sys_reset_req;
+ wire PMUHRESETREQ;
+ wire PMUDBGRESETREQ;
+ wire LOCKUP;
+ wire LOCKUPRESET;
+ wire SLEEPING;
+ wire GATEHCLK; // Processor status - safe to gate HCLK
+ wire WAKEUP; // Wake up request from WIC
+ wire WICENREQ; // WIC enable request from PMU
+ wire WICENACK; // WIC enable ack to PMU
+ wire PMUENABLE;
+ wire CDBGPWRUPREQ; // Debug Power Up request to PMU
+ wire CDBGPWRUPACK; // Debug Power Up ACK from PMU
+ wire SLEEPHOLDREQn; // Sleep extension request from PMU
+ wire SLEEPHOLDACKn; // Sleep extension request to PMU
+ wire SYSPWRDOWNACK;
+ wire DBGPWRDOWNACK;
+ wire SYSPWRDOWN;
+ wire DBGPWRDOWN;
+ wire SYSISOLATEn;
+ wire SYSRETAINn;
+ wire DBGISOLATEn;
+ wire SLEEPDEEP;
+ wire ADPRESETREQ;
+ // Scan test dummy signals; not connected until scan insertion
+ wire TESTMODE; // Test mode enable signal (override synchronizers etc)
+ wire SCANENABLE; // Scan enable signal
+ wire SCANINHCLK; // HCLK scan input
+ wire SCANOUTHCLK; // Scan Chain wire
+
+// not required for FPGA
+ assign TESTMODE = 1'b0;
+ assign SCANENABLE = 1'b0;
+ assign SCANINHCLK = 1'b0;
+ assign SCANOUTHCLK = 1'b0;
+
+// Technology-specific PLL/Frequecy synthesizer would generate
+// CLK, FCLK (Free running system clock) from xtal_clk_in
+
+ assign pll_clk = xtal_clk_in; // default to no PLL
+ assign CLK = (TESTMODE) ? xtal_clk_in : pll_clk;
+ assign HCLK = FCLK;
+
+
+//? assign HCLKSYS = (INCLUDE_DMA!=0) ? SCLK : HCLK;
+
+ // System Reset request can be from processor or watchdog
+ // or when lockup happens and the control flag is set.
+ assign NANOSOC_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
+ ADPRESETREQ |
+ (LOCKUP & LOCKUPRESET);
+ assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
+
+ // Clock controller to generate reset and clock signals
+ nanosoc_mcu_clkctrl #(
+ .CLKGATE_PRESENT (CLKGATE_PRESENT)
+ ) u_nanosoc_mcu_clkctrl (
+ // inputs
+ .XTAL1 (CLK),
+ .NRST (nrst_in),
+
+ .APBACTIVE (APBACTIVE),
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP),
+ .LOCKUP (LOCKUP),
+ .LOCKUPRESET (LOCKUPRESET),
+ .SYSRESETREQ (clk_ctrl_sys_reset_req),
+ .DBGRESETREQ (PMUDBGRESETREQ),
+ .CGBYPASS (TESTMODE),
+ .RSTBYPASS (TESTMODE),
+
+ // outputs
+ .XTAL2 (xtal_clk_out),
+ .FCLK (FCLK),
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PCLKEN (PCLKEN),
+//?`ifdef CORTEX_M0DESIGNSTART
+//? .PORESETn (PORESETn), // for cm0 designstart
+//? .HRESETn (HRESETn), // for cm0 designstart
+//?`endif
+ .PRESETn (PRESETn)
+ );
+
+ wire gated_hclk;
+ wire gated_dclk;
+ wire gated_sclk;
+
+ cortexm0_rst_ctl u_rst_ctl (
+ // Inputs
+ .GLOBALRESETn (nrst_in),
+ .FCLK (FCLK),
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SYSRESETREQ (NANOSOC_SYSRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .RSTBYPASS (TESTMODE),
+ .SE (SCANENABLE),
+
+ // Outputs
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .HRESETREQ (HRESETREQ)
+ );
+
+
+ // Cortex-M0 Power management unit
+ cortexm0_pmu u_cortexm0_pmu ( // Inputs
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HRESETREQ (NANOSOC_SYSRESETREQ), // from processor / watchdog
+ .PMUENABLE (PMUENABLE), // from System Controller
+ .WICENACK (WICENACK), // from WIC in integration
+
+ .WAKEUP (WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .SLEEPDEEP (SLEEPDEEP),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .GATEHCLK (GATEHCLK),
+ .SYSPWRDOWNACK (SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (DBGPWRDOWNACK),
+ .CGBYPASS (TESTMODE),
+
+ // Outputs
+ .HCLK (gated_hclk),
+ .DCLK (gated_dclk),
+ .SCLK (gated_sclk),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SYSISOLATEn (SYSISOLATEn),
+ .SYSRETAINn (SYSRETAINn),
+ .SYSPWRDOWN (SYSPWRDOWN),
+ .DBGISOLATEn (DBGISOLATEn),
+ .DBGPWRDOWN (DBGPWRDOWN),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ)
+ );
+
+ // Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
+ assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
+ assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
+ assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
+
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign SYSPWRDOWNACK = SYSPWRDOWN;
+ assign DBGPWRDOWNACK = DBGPWRDOWN;
+
+ wire exp_penable;
+ wire exp_pwrite;
+ wire [11:0] exp_paddr;
+ wire [31:0] exp_pwdata;
+ wire exp12_psel;
+ wire exp12_pready;
+ wire exp12_pslverr;
+ wire [31:0] exp12_prdata;
+ wire exp13_psel;
+ wire exp13_pready;
+ wire exp13_pslverr;
+ wire [31:0] exp13_prdata;
+ wire exp14_psel;
+ wire exp14_pready;
+ wire exp14_pslverr;
+ wire [31:0] exp14_prdata;
+ wire exp15_psel;
+ wire exp15_pready;
+ wire exp15_pslverr;
+ wire [31:0] exp15_prdata;
+
+
+ // internal peripheral signals
+ wire uart0_rxd;
+ wire uart0_txd;
+ wire uart0_txen;
+ wire uart1_rxd;
+ wire uart1_txd;
+ wire uart1_txen;
+ wire uart2_rxd;
+ wire uart2_txd;
+ wire uart2_txen;
+ wire timer0_extin;
+ wire timer1_extin;
+
+ wire [15:0] p0_altfunc;
+
+ wire [15:0] p1_altfunc;
+
+ wire exp_irq0;
+ wire exp_irq1;
+ wire exp_irq2;
+ wire exp_irq3;
+ wire exp_irqB;
+ wire exp_irqC;
+ wire exp_irqD;
+
+
+//----------------------------------------
+// ADP ASCII DEBUG PROTOCOL controller
+// AHB MANAGER 0
+//----------------------------------------
+
+ // -------------------------------
+ // ADP engine stream and control interfaces
+ // -------------------------------
+
+ wire comio_tx_ready;
+ wire [7:0] comio_tx_data8;
+ wire comio_tx_valid;
+
+ wire comio_rx_ready;
+ wire [7:0] comio_rx_data8;
+ wire comio_rx_valid;
+
+ wire stdio_tx_ready;
+ wire [7:0] stdio_tx_data8;
+ wire stdio_tx_valid;
+
+ wire stdio_rx_ready;
+ wire [7:0] stdio_rx_data8;
+ wire stdio_rx_valid;
+
+ wire [7:0] adp_gpo8;
+ wire [7:0] adp_gpi8;
+
+ assign adp_gpi8 = adp_gpo8;
+ assign ADPRESETREQ = adp_gpo8[0];
+
+ // ADP debug controller present
+ nanosoc_adp_control_v1_0 u_adp_control (
+ // Clock and Reset
+ .ahb_hclk (HCLK),
+ .ahb_hresetn (HRESETn),
+ // DMA Control
+ .com_rx_tready (comio_rx_ready),
+ .com_rx_tdata (comio_rx_data8),
+ .com_rx_tvalid (comio_rx_valid),
+ .com_tx_tready (comio_tx_ready),
+ .com_tx_tdata (comio_tx_data8),
+ .com_tx_tvalid (comio_tx_valid),
+ .stdio_rx_tready (stdio_rx_ready),
+ .stdio_rx_tdata (stdio_rx_data8),
+ .stdio_rx_tvalid (stdio_rx_valid),
+ .stdio_tx_tready (stdio_tx_ready),
+ .stdio_tx_tdata (stdio_tx_data8),
+ .stdio_tx_tvalid (stdio_tx_valid),
+ .gpo8 (adp_gpo8),
+ .gpi8 (adp_gpi8),
+
+ // AHB-Lite Master Interface
+ .ahb_hready (HREADY_adp),
+ .ahb_hresp (HRESP_adp),
+ .ahb_hrdata (HRDATA_adp),
+ .ahb_htrans (HTRANS_adp),
+ .ahb_hwrite (HWRITE_adp),
+ .ahb_haddr (HADDR_adp),
+ .ahb_hsize (HSIZE_adp),
+ .ahb_hburst (HBURST_adp),
+ .ahb_hmastlock (HMASTLOCK_adp),
+ .ahb_hprot (HPROT_adp),
+ .ahb_hwdata (HWDATA_adp)
+ );
+ assign HAUSER_adp [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_adp [1:0] = 2'b00; // Write-data USER signals
+
+ nanosoc_apb_usrt u_apb_usrt_com (
+ .PCLK (PCLK), // Peripheral clock
+ .PCLKG (PCLKG), // Gated PCLK for bus
+ .PRESETn (PRESETn), // Reset
+
+ .PSEL (exp14_psel), // APB interface inputs
+ .PADDR (exp_paddr[11:2]),
+ .PENABLE (exp_penable),
+ .PWRITE (exp_pwrite),
+ .PWDATA (exp_pwdata),
+
+ .PRDATA (exp14_prdata), // APB interface outputs
+ .PREADY (exp14_pready),
+ .PSLVERR (exp14_pslverr),
+
+ .ECOREVNUM (4'h0),// Engineering-change-order revision bits
+
+ .TX_VALID_o (stdio_rx_valid),
+ .TX_DATA8_o (stdio_rx_data8),
+ .TX_READY_i (stdio_rx_ready),
+
+ .RX_VALID_i (stdio_tx_valid),
+ .RX_DATA8_i (stdio_tx_data8),
+ .RX_READY_o (stdio_tx_ready),
+
+ .TXINT ( ), // Transmit Interrupt
+ .RXINT ( ), // Receive Interrupt
+ .TXOVRINT ( ), // Transmit Overrun Interrupt
+ .RXOVRINT ( ), // Receive Overrun Interrupt
+ .UARTINT ( ) // Combined Interrupt
+ );
+
+ wire [7:0] ft_clkdiv = 8'd03;
+
+ nanosoc_ft1248_stream_io_v1_0 #(
+ .FT1248_WIDTH (1),
+ .FT1248_CLKON (0)
+ ) u_ftdio_com (
+ .clk (HCLK),
+ .resetn (HRESETn),
+ .ft_clkdiv (ft_clkdiv ),
+ .ft_clk_o (ft_clk_o ),
+ .ft_ssn_o (ft_ssn_o ),
+ .ft_miso_i (ft_miso_i ),
+ .ft_miosio_o (ft_miosio_o ),
+ .ft_miosio_e (ft_miosio_e ),
+ .ft_miosio_z (ft_miosio_z ),
+ .ft_miosio_i (ft_miosio_i ),
+ .rxd_tready (comio_tx_ready),
+ .rxd_tdata (comio_tx_data8),
+ .rxd_tvalid (comio_tx_valid),
+ .rxd_tlast (1'b0),
+ .txd_tready (comio_rx_ready),
+ .txd_tdata (comio_rx_data8),
+ .txd_tvalid (comio_rx_valid),
+ .txd_tlast ( )
+ );
+
+
+//----------------------------------------
+// DIRECT MEMORY ACCESS controller
+// AHB MANAGER 1
+//----------------------------------------
+
+ // DMA interface not used in this example system
+ wire [DMA_CHANNEL_NUM-1:0] dma230_req; // tie off signal.
+ wire [DMA_CHANNEL_NUM-1:0] dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
+
+ assign dma230_req[0] = exp_drq_ip;
+ assign dma230_req[1] = exp_drq_op;
+
+
+ // DMA done per channel
+ wire [DMA_CHANNEL_NUM-1:0] dma230_done_ch;
+ wire dmac_done;
+ wire dmac_err;
+
+ ///generate if (INCLUDE_DMA != 0) begin : gen_dma
+ // DMA controller present
+ pl230_udma u_pl230_udma (
+ // Clock and Reset
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // DMA Control
+ .dma_req (dma230_req),
+ .dma_sreq (dma230_req),
+ .dma_waitonreq (dma230_tie0),
+ .dma_stall (1'b0),
+ .dma_active (),
+ .dma_done (dma230_done_ch),
+ .dma_err (dmac_err),
+
+ // AHB-Lite Master Interface
+ .hready (HREADY_dma),
+ .hresp (HRESP_dma),
+ .hrdata (HRDATA_dma),
+ .htrans (HTRANS_dma),
+ .hwrite (HWRITE_dma),
+ .haddr (HADDR_dma),
+ .hsize (HSIZE_dma),
+ .hburst (HBURST_dma),
+ .hmastlock (HMASTLOCK_dma),
+ .hprot (HPROT_dma),
+ .hwdata (HWDATA_dma),
+
+ // APB Slave Interface
+ .pclken (PCLKEN),
+ .psel (exp15_psel),
+ .pen (exp_penable),
+ .pwrite (exp_pwrite),
+ .paddr (exp_paddr[11:0]),
+ .pwdata (exp_pwdata[31:0]),
+ .prdata (exp15_prdata)
+ );
+
+ assign exp15_pready = 1'b1;
+ assign exp15_pslverr = 1'b0;
+ assign dmac_done = |dma230_done_ch; // OR all the DMA done together
+
+/* end else begin : gen_no_pl230_udma
+ // DMA controller not present
+ assign HADDR_dma [31:0] = 32'ha2a2a2a2; // Address bus
+ assign HTRANS_dma [1:0] = 2'b00; // Transfer type
+ assign HWRITE_dma = 1'b0; // Transfer direction
+ assign HSIZE_dma [2:0] = 3'b010; // Transfer size
+ assign HBURST_dma [2:0] = 3'b001; // Burst type
+ assign HPROT_dma [3:0] = 4'b0010; // Protection control
+ assign HWDATA_dma [31:0] = 32'hd2d2d2d2; // Write data
+ assign HMASTLOCK_dma = 1'b0; // Locked Sequence
+ assign HAUSER_dma [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_dma [1:0] = 2'b00; // Write-data USER signals
+
+ assign dmac_done = 1'b0;
+ assign dmac_err = 1'b0;
+ assign exp15_pready = 1'b1;
+ assign exp15_pslverr = 1'b0;
+ assign exp15_prdata = 32'h00000000;
+ assign dma230_done_ch = {DMA_CHANNEL_NUM{1'b0}};
+
+ end endgenerate
+*/
+
+
+
+//----------------------------------------
+// CORTEX-M0 CPU controller
+// AHB MANAGER 3
+//----------------------------------------
+
+ wire SYS_NMI; // Watchdog nin-maskable interrupt
+ wire [31:0] SYS_APB_IRQ; // APB subsystem IRQs
+ wire [15:0] SYS_GPIO0_IRQ; // GPIO-0 IRQs
+ wire [15:0] SYS_GPIO1_IRQ; // GPIO-1 IRQs
+
+ wire gpio0_combintr;
+ wire gpio1_combintr;
+ assign gpio0_combintr = |SYS_GPIO0_IRQ[15:0];
+ assign gpio1_combintr = |SYS_GPIO1_IRQ[15:0];
+
+ wire intnmi_cm0;
+ wire [31:0] intisr_cm0;
+
+// match interrupts to CMSDK for validation code reuse
+
+ assign intnmi_cm0 = SYS_NMI;
+ //assign intisr_cm0[ 5: 0] = SYS_APB_IRQ[ 5: 0];
+ assign intisr_cm0[ 0] = exp_irq0;
+ assign intisr_cm0[ 1] = exp_irq1;
+ assign intisr_cm0[ 2] = exp_irq2;
+ assign intisr_cm0[ 3] = exp_irq3;
+ assign intisr_cm0[ 5: 4] = SYS_APB_IRQ[ 5: 4];
+ assign intisr_cm0[ 6] = SYS_APB_IRQ[ 6] | gpio0_combintr;
+ assign intisr_cm0[ 7] = SYS_APB_IRQ[ 7] | gpio1_combintr;
+ assign intisr_cm0[14: 8] = SYS_APB_IRQ[14: 8];
+ assign intisr_cm0[15] = SYS_APB_IRQ[15] | dmac_done | dmac_err;
+ assign intisr_cm0[31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
+
+ assign HAUSER_cpu [1:0] = 2'b00; // Address USER signals
+ assign HWUSER_cpu [1:0] = 2'b00; // Write-data USER signals
+
+
+ // Cortex-M0 integration level
+ nanosoc_cpu u_nanosoc_cpu (
+ .HCLK (gated_hclk), //HCLK),
+ .FCLK (FCLK),
+ .DCLK (DCLK),
+ .SCLK (SCLK),
+ .HRESETn (HRESETn),
+ .PORESETn (PORESETn),
+ .DBGRESETn (DBGRESETn),
+ .RSTBYPASS (TESTMODE),
+ .DFTSE (SCANENABLE),
+ // AHB port
+ .HADDR (HADDR_cpu),
+ .HTRANS (HTRANS_cpu),
+ .HWRITE (HWRITE_cpu),
+ .HSIZE (HSIZE_cpu),
+ .HBURST (HBURST_cpu),
+ .HPROT (HPROT_cpu),
+ .HWDATA (HWDATA_cpu),
+ .HMASTLOCK (HMASTLOCK_cpu),
+ .HREADY (HREADY_cpu),
+// .HAUSER (HAUSER_cpu),
+// .HWUSER (HWUSER_cpu),
+ .HRDATA (HRDATA_cpu),
+ .HRESP (HRESP_cpu),
+// .HRUSER (HRUSER_cpu),
+ // sideband signals
+ .NMI (intnmi_cm0), // Non-maskable interrupt input
+ .IRQ (intisr_cm0[31:0]), // Interrupt request inputs
+ .TXEV (TXEV), // Event output (SEV executed)
+ .RXEV (RXEV), // Event input
+ // MISCELLANEOUS ---------------------
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP),
+ .WAKEUP (WAKEUP ), // Wake up request from WIC
+ .WICENREQ (WICENREQ ), // WIC enable request from PMU
+ .WICENACK (WICENACK ), // WIC enable ack to PMU
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+ .LOCKUP (LOCKUP), // Core is locked-up
+ .GATEHCLK (GATEHCLK),
+ .SYSRESETREQ (SYSRESETREQ), // System reset request
+ .WDOGRESETREQ (WDOGRESETREQ), // Watchdog HW reset request
+ .ADPRESETREQ (ADPRESETREQ), // ADP debugger reset request
+
+ // Debug - JTAG or Serial wire
+ // inputs
+ .SWDI (SWDI),
+ .SWCLK (SWCLK),
+ // outputs
+ .SWDO (SWDO),
+ .SWDOEN (SWDOEN)
+ );
+
+ assign RXEV = dmac_done; // Generate event when a DMA operation completed.
+
+
+//------------------------------------
+// internal wires
+
+ assign p0_out_nen = ~p0_out_en; //active low pad drive option
+ assign p1_out_nen_mux = ~p1_out_en_mux; //active low pad drive option
+
+ localparam BASEADDR_GPIO0 = 32'h4001_0000;
+ localparam BASEADDR_GPIO1 = 32'h4001_1000;
+ localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
+
+ nanosoc_sysio u_nanosoc_sysio (
+ .FCLK (FCLK ), // free-running clock
+ .PORESETn (PORESETn ), // Power-On-Reset (active-low)
+ .TESTMODE (TESTMODE ), // Test-mode override for testability
+ .HCLK (HCLK ), // AHB interconnect clock
+ .HRESETn (HRESETn ), // AHB interconnect reset (active-low)
+ // Common AHB signals
+ .HSEL (HSEL_sysio ),
+ .HADDR (HADDR_sysio ),
+ .HBURST (HBURST_sysio ),
+ .HMASTLOCK (HMASTLOCK_sysio),
+ .HPROT (HPROT_sysio ),
+ .HSIZE (HSIZE_sysio ),
+ .HTRANS (HTRANS_sysio ),
+ .HWDATA (HWDATA_sysio ),
+ .HWRITE (HWRITE_sysio ),
+ .HREADY (HREADYMUX_sysio),
+ .HRDATA (HRDATA_sysio ),
+ .HRESP (HRESP_sysio ),
+ .HREADYOUT (HREADYOUT_sysio),
+ // APB clocking
+ .PCLK (PCLK ),
+ .PCLKG (PCLKG ),
+ .PRESETn (PRESETn ),
+ .PCLKEN (PCLKEN ),
+ // APB expansion select outputs
+ .exp12_psel (exp12_psel ),
+ .exp13_psel (exp13_psel ),
+ .exp14_psel (exp14_psel ),
+ .exp15_psel (exp15_psel ),
+ .exp_pwdata (exp_pwdata ),
+ .exp_paddr (exp_paddr ),
+ .exp_pwrite (exp_pwrite ),
+ .exp_penable (exp_penable ),
+ // APB expansion interface inputs
+ .exp12_prdata (exp12_prdata ),
+ .exp12_pready (exp12_pready ),
+ .exp12_pslverr (exp12_pslverr),
+ .exp13_prdata (exp13_prdata ),
+ .exp13_pready (exp13_pready ),
+ .exp13_pslverr (exp13_pslverr),
+ .exp14_prdata (exp14_prdata ),
+ .exp14_pready (exp14_pready ),
+ .exp14_pslverr (exp14_pslverr),
+ .exp15_prdata (exp15_prdata ),
+ .exp15_pready (exp15_pready ),
+ .exp15_pslverr (exp15_pslverr),
+ // CPU sideband signalling
+ .SYS_NMI (SYS_NMI ),
+ .SYS_APB_IRQ (SYS_APB_IRQ ),
+ // CPU specific power/reset control
+ .REMAP_CTRL (ROM_MAP ),
+ .APBACTIVE (APBACTIVE ),
+ .SYSRESETREQ (SYSRESETREQ ),
+ .WDOGRESETREQ (WDOGRESETREQ ),
+ .LOCKUP (LOCKUP ),
+ .LOCKUPRESET (LOCKUPRESET ),
+ .PMUENABLE (PMUENABLE ),
+ // chip IO
+ .SYS_GPIO0_IRQ (SYS_GPIO0_IRQ ),
+ .SYS_GPIO1_IRQ (SYS_GPIO1_IRQ ),
+ // IO signalling
+ .uart0_rxd (uart1_txd), //(uart0_rxd ), // crossover
+ .uart0_txd (uart0_txd ),
+ .uart0_txen (uart0_txen ),
+ .uart1_rxd (uart0_txd), //uart1_rxd ), // crossover
+ .uart1_txd (uart1_txd ),
+ .uart1_txen (uart1_txen ),
+ .uart2_rxd (uart2_rxd ),
+ .uart2_txd (uart2_txd ),
+ .uart2_txen (uart2_txen ),
+ .timer0_extin (timer0_extin ),
+ .timer1_extin (timer1_extin ),
+ // GPIO port signalling
+ .p0_in (p0_in ),
+ .p0_out (p0_out ),
+ .p0_outen (p0_out_en ),
+ .p0_altfunc (p0_altfunc ),
+
+ .p1_in (p1_in ),
+ .p1_out (p1_out ),
+ .p1_outen (p1_out_en ),
+ .p1_altfunc (p1_altfunc )
+ );
+
+ assign REMAP[3] = 1'b0;
+ assign REMAP[2] = 1'b0;
+ assign REMAP[1] = 1'b0;
+ assign REMAP[0] =!ROM_MAP;
+
+ assign exp12_pready = 1'b1;
+ assign exp13_pready = 1'b1;
+ assign exp12_pslverr = 1'b0;
+ assign exp13_pslverr = 1'b0;
+ assign exp12_prdata = 32'h0;
+ assign exp13_prdata = 32'h0;
+
+
+ // Serial wire debug is used. nTRST, TDI and TDO are not needed
+
+
+//----------------------------------------
+// I/O port pin muxing and tristate
+//----------------------------------------
+
+ assign SWCLK = swdclk_i;
+ assign SWDI = swdio_i;
+ assign swdio_o = SWDO;
+ assign swdio_e = SWDOEN;
+ assign swdio_z = !SWDOEN;
+
+ nanosoc_mcu_pin_mux u_pin_mux (
+ // UART
+ .uart0_rxd (uart0_rxd),
+ .uart0_txd (uart0_txd),
+ .uart0_txen (uart0_txen),
+ .uart1_rxd (uart1_rxd),
+ .uart1_txd (uart1_txd),
+ .uart1_txen (uart1_txen),
+ .uart2_rxd (uart2_rxd),
+ .uart2_txd (uart2_txd),
+ .uart2_txen (uart2_txen),
+
+ // Timer
+ .timer0_extin (timer0_extin),
+ .timer1_extin (timer1_extin),
+
+
+ // IO Ports
+ .p0_in ( ), // was (p0_in) now from pad inputs),
+ .p0_out (p0_out),
+ .p0_outen (p0_out_en),
+ .p0_altfunc (p0_altfunc),
+
+ .p1_in ( ), // was(p1_in) now from pad inputs),
+ .p1_out (p1_out),
+ .p1_outen (p1_out_en),
+ .p1_altfunc (p1_altfunc),
+
+ // Debug
+ .i_trst_n ( ),
+ .i_swditms ( ), //i_swditms),
+ .i_swclktck ( ), //i_swclktck),
+ .i_tdi ( ),
+ .i_tdo ( ),
+ .i_tdoen_n ( ),
+ .i_swdo ( ),
+ .i_swdoen ( ),
+
+ // IO pads
+ .p1_out_mux (p1_out_mux),
+ .p1_out_en_mux (p1_out_en_mux),
+ .P0 ( ), //P0),
+ .P1 ( ), //P1),
+
+ .nTRST (nTRST), // Not needed if serial-wire debug is used
+ .TDI (1'b0), // Not needed if serial-wire debug is used
+ .SWDIOTMS ( ), //SWDIOTMS),
+ .SWCLKTCK ( ), //SWCLKTCK),
+ .TDO ( ) // Not needed if serial-wire debug is used
+
+ );
+
+endmodule
+
+
+
diff --git a/system/src/verilog/nanosoc_mcu_clkctrl.v b/system/src/nanosoc_chip/control/verilog/nanosoc_clkctrl.v
similarity index 99%
rename from system/src/verilog/nanosoc_mcu_clkctrl.v
rename to system/src/nanosoc_chip/control/verilog/nanosoc_clkctrl.v
index 80be7812559e3186ad7a5d7b20220ae96991adfb..98d947856d6ccd496fad72549370f932f30fed17 100644
--- a/system/src/verilog/nanosoc_mcu_clkctrl.v
+++ b/system/src/nanosoc_chip/control/verilog/nanosoc_clkctrl.v
@@ -37,7 +37,7 @@
// Note : Most of the clock gating are handled by the example PMU provided
// in the Cortex-M0/Cortex-M0+ deliverable.
-module nanosoc_mcu_clkctrl #(
+module nanosoc_clkctrl #(
parameter CLKGATE_PRESENT = 0)
(
input wire XTAL1, // Clock source
diff --git a/system/src/verilog/nanosoc_mcu_pin_mux.v b/system/src/nanosoc_chip/control/verilog/nanosoc_pin_mux.v
similarity index 99%
rename from system/src/verilog/nanosoc_mcu_pin_mux.v
rename to system/src/nanosoc_chip/control/verilog/nanosoc_pin_mux.v
index 963807e1f57c6714cfcb567d1b1e06b17cd4d34d..c9e4e970b4d5407667ae8ba761fbc02b7f24d806 100644
--- a/system/src/verilog/nanosoc_mcu_pin_mux.v
+++ b/system/src/nanosoc_chip/control/verilog/nanosoc_pin_mux.v
@@ -36,7 +36,7 @@
// microcontroller
//-----------------------------------------------------------------------------
//
-module nanosoc_mcu_pin_mux (
+module nanosoc_pin_mux (
//-------------------------------------------
// I/O ports
//-------------------------------------------
diff --git a/system/src/verilog/nanosoc_chip_pads.v b/system/src/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
similarity index 100%
rename from system/src/verilog/nanosoc_chip_pads.v
rename to system/src/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
diff --git a/system/src/verilog/nanosoc_cpu.v b/system/src/nanosoc_managers/cpu/verilog/nanosoc_manager_cpu.v
similarity index 60%
rename from system/src/verilog/nanosoc_cpu.v
rename to system/src/nanosoc_managers/cpu/verilog/nanosoc_manager_cpu.v
index 281e242cd09d1aa98c5aef2cf75dd9771af8307d..c51e5c0a81fadce9ba97a9e092b915862f867297 100644
--- a/system/src/verilog/nanosoc_cpu.v
+++ b/system/src/nanosoc_managers/cpu/verilog/nanosoc_manager_cpu.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// NanoSoC Cortex-M0 AHB Manager
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -35,7 +35,7 @@
// Abstract : System level design for the example Cortex-M0 system
//-----------------------------------------------------------------------------
-module nanosoc_cpu #(
+module nanosoc_manager_cpu #(
parameter CLKGATE_PRESENT = 0,
parameter BE = 0, // 1: Big endian 0: little endian
parameter BKPT = 4, // Number of breakpoint comparators
@@ -48,17 +48,16 @@ module nanosoc_cpu #(
parameter WPT = 2, // Number of DWT comparators
parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
- )
- (
+)(
input wire HCLK, // (HCLK master)
- input wire FCLK, // Free running clock
- input wire SCLK, // System clock
- input wire HRESETn, // AHB and System reset
- input wire PORESETn, // Power on reset
- input wire DCLK, // Debug clock
- input wire DBGRESETn, // Debug reset
- input wire RSTBYPASS, // Reset by pass (for testing)
- input wire DFTSE, // Reset by pass (for testing)
+ input wire FCLK, // Free running clock
+ input wire SCLK, // System clock
+ input wire HRESETn, // AHB and System reset
+ input wire PORESETn, // Power on reset
+ input wire DCLK, // Debug clock
+ input wire DBGRESETn, // Debug reset
+ input wire RSTBYPASS, // Reset by pass (for testing)
+ input wire DFTSE, // Reset by pass (for testing)
// AHB Lite port
output wire [31:0] HADDR, // Address bus
@@ -69,12 +68,9 @@ module nanosoc_cpu #(
output wire [3:0] HPROT, // Protection control
output wire [31:0] HWDATA, // Write data
output wire HMASTLOCK, // Locked Sequence
-// output wire [1:0] HAUSER, // Address USER signals
-// output wire [1:0] HWUSER, // Write-data USER signals
input wire [31:0] HRDATA, // Read data bus
input wire HREADY, // HREADY feedback
input wire HRESP, // Transfer response
-// input wire [1:0] HRUSER, // Read-data USER signals
// Sideband CPU signalling
input wire NMI, // Non-Maskable Interrupt request
@@ -132,99 +128,98 @@ module nanosoc_cpu #(
wire SHAREABLE;
// Cortex-M0 integration level
- CORTEXM0INTEGRATION
- #(.ACG (CLKGATE_PRESENT), // Architectural clock gating
- .BE (BE), // Big-endian
- .BKPT (BKPT), // Number of breakpoint comparators
- .DBG (DBG), // Debug configuration
- .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
- .NUMIRQ (NUMIRQ), // Number of Interrupts
- .RAR (RESET_ALL_REGS), // Reset All Registers
- .SMUL (SMUL), // Multiplier configuration
- .SYST (SYST), // SysTick
- .WIC (WIC), // Wake-up interrupt controller support
- .WICLINES (WICLINES), // Supported WIC lines
- .WPT (WPT)) // Number of DWT comparators
-
- u_cortex_m0_integration (
- // System inputs
- .FCLK (FCLK), // FCLK
- .SCLK (SCLK), // SCLK generated from PMU
- .HCLK (HCLK), // HCLK generated from PMU
- .DCLK (DCLK), // DCLK generated from PMU
- .PORESETn (PORESETn),
- .HRESETn (HRESETn),
- .DBGRESETn (DBGRESETn),
- .RSTBYPASS (RSTBYPASS),
- .SE (DFTSE),
-
- // Power management inputs
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .WICENREQ (WICENREQ),
- .CDBGPWRUPACK (CDBGPWRUPACK),
-
- // Power management outputs
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .WICENACK (WICENACK),
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
-
- .WAKEUP (WAKEUP),
- .WICSENSE (WICSENSE),
- .GATEHCLK (GATEHCLK),
- .SYSRESETREQ (SYSRESETREQ),
-
- // System bus
- .HADDR (HADDR ),
- .HTRANS (HTRANS ),
- .HSIZE (HSIZE ),
- .HBURST (HBURST ),
- .HPROT (HPROT ),
- .HMASTLOCK (HMASTLOCK ),
- .HWRITE (HWRITE ),
- .HWDATA (HWDATA ),
- .HRDATA (HRDATA ),
- .HREADY (HREADY ),
- .HRESP (HRESP ),
- .HMASTER ( ),
-
- .CODEHINTDE (CODEHINTDE),
- .SPECHTRANS (SPECHTRANS),
- .CODENSEQ (CODENSEQ),
-
- // Interrupts
- .IRQ (IRQ[31:0]),
- .NMI (NMI),
- .IRQLATENCY (8'h00),
-
- .ECOREVNUM (28'h0),
- // Systick
- .STCLKEN (STCLKEN),
- .STCALIB (STCALIB),
-
- // Debug - JTAG or Serial wire
- // inputs
- .nTRST (1'b1),
- .SWDITMS (SWDI),
- .SWCLKTCK (SWCLK),
- .TDI (1'b0),
- // outputs
- .TDO ( ),
- .nTDOEN ( ),
- .SWDO (SWDO),
- .SWDOEN (SWDOEN),
-
- .DBGRESTART (DBGRESTART),
- .DBGRESTARTED (DBGRESTARTED),
-
- // Event communication
- .TXEV (TXEV),
- .RXEV (RXEV),
- .EDBGRQ (EDBGRQ),
- // Status output
- .HALTED (HALTED),
- .LOCKUP (LOCKUP),
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP)
+ CORTEXM0INTEGRATION #(
+ .ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT) // Number of DWT comparators
+ ) u_cortex_m0_integration (
+ // System inputs
+ .FCLK (FCLK), // FCLK
+ .SCLK (SCLK), // SCLK generated from PMU
+ .HCLK (HCLK), // HCLK generated from PMU
+ .DCLK (DCLK), // DCLK generated from PMU
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .RSTBYPASS (RSTBYPASS),
+ .SE (DFTSE),
+
+ // Power management inputs
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+
+ // Power management outputs
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .WICENACK (WICENACK),
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .WAKEUP (WAKEUP),
+ .WICSENSE (WICSENSE),
+ .GATEHCLK (GATEHCLK),
+ .SYSRESETREQ (SYSRESETREQ),
+
+ // System bus
+ .HADDR (HADDR ),
+ .HTRANS (HTRANS ),
+ .HSIZE (HSIZE ),
+ .HBURST (HBURST ),
+ .HPROT (HPROT ),
+ .HMASTLOCK (HMASTLOCK ),
+ .HWRITE (HWRITE ),
+ .HWDATA (HWDATA ),
+ .HRDATA (HRDATA ),
+ .HREADY (HREADY ),
+ .HRESP (HRESP ),
+ .HMASTER ( ),
+
+ .CODEHINTDE (CODEHINTDE),
+ .SPECHTRANS (SPECHTRANS),
+ .CODENSEQ (CODENSEQ),
+
+ // Interrupts
+ .IRQ (IRQ[31:0]),
+ .NMI (NMI),
+ .IRQLATENCY (8'h00),
+
+ .ECOREVNUM (28'h0),
+ // Systick
+ .STCLKEN (STCLKEN),
+ .STCALIB (STCALIB),
+
+ // Debug - JTAG or Serial wire
+ // inputs
+ .nTRST (1'b1),
+ .SWDITMS (SWDI),
+ .SWCLKTCK (SWCLK),
+ .TDI (1'b0),
+ // outputs
+ .TDO ( ),
+ .nTDOEN ( ),
+ .SWDO (SWDO),
+ .SWDOEN (SWDOEN),
+
+ .DBGRESTART (DBGRESTART),
+ .DBGRESTARTED (DBGRESTARTED),
+
+ // Event communication
+ .TXEV (TXEV),
+ .RXEV (RXEV),
+ .EDBGRQ (EDBGRQ),
+ // Status output
+ .HALTED (HALTED),
+ .LOCKUP (LOCKUP),
+ .SLEEPING (SLEEPING),
+ .SLEEPDEEP (SLEEPDEEP)
);
// Unused debug feature
@@ -234,15 +229,15 @@ module nanosoc_cpu #(
// -------------------------------
// SysTick signals
// -------------------------------
- nanosoc_mcu_stclkctrl
- #(.DIV_RATIO (18'd01000))
- u_nanosoc_mcu_stclkctrl (
+ nanosoc_stclkctrl #(
+ .DIV_RATIO (18'd01000)
+ ) u_nanosoc_mcu_stclkctrl (
.FCLK (FCLK),
.SYSRESETn (HRESETn),
.STCLKEN (STCLKEN),
.STCALIB (STCALIB)
- );
+ );
endmodule
diff --git a/system/src/verilog/nanosoc_mcu_stclkctrl.v b/system/src/nanosoc_managers/cpu/verilog/nanosoc_stclkctrl.v
similarity index 90%
rename from system/src/verilog/nanosoc_mcu_stclkctrl.v
rename to system/src/nanosoc_managers/cpu/verilog/nanosoc_stclkctrl.v
index b4ea23cad824aeaa73c5a8b8711e546b5fc9fa10..ca006495ef5441ce0aacfa189471846f316fbebc 100644
--- a/system/src/verilog/nanosoc_mcu_stclkctrl.v
+++ b/system/src/nanosoc_managers/cpu/verilog/nanosoc_stclkctrl.v
@@ -35,19 +35,17 @@
// Abstract : Simple control for SysTick signals for Cortex-M processor
//-----------------------------------------------------------------------------
-module nanosoc_mcu_stclkctrl #(
+module nanosoc_stclkctrl #(
// Ratio between FCLK and SysTck reference clock
parameter DIV_RATIO = 18'd01000,
// Divide by half for each phase
parameter DIVIDER_RELOAD = (DIV_RATIO>>1)-1
- )
- (
- input wire FCLK, // Free running clock
- input wire SYSRESETn, // System reset
-
- output wire STCLKEN, // SysTick clock
- output wire [25:0] STCALIB // SysTick calibration
+ )(
+ input wire FCLK, // Free running clock
+ input wire SYSRESETn, // System reset
+ output wire STCLKEN, // SysTick clock
+ output wire [25:0] STCALIB // SysTick calibration
);
reg [17:0] reg_clk_divider;
@@ -58,7 +56,7 @@ module nanosoc_mcu_stclkctrl #(
assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value set to 0, indicate this value is not used
// Divider
- wire [17:0] reg_clk_div_min1 = reg_clk_divider -1;
+ wire [17:0] reg_clk_div_min1 = reg_clk_divider - 1;
always @(posedge FCLK or negedge SYSRESETn)
begin
if (~SYSRESETn)
diff --git a/system/src/nanosoc_managers/socdebug/verilog/nanosoc_manager_socdebug.v b/system/src/nanosoc_managers/socdebug/verilog/nanosoc_manager_socdebug.v
new file mode 100644
index 0000000000000000000000000000000000000000..cd0b5edb871ee655d501bbec1ab90e6b179ba5ad
--- /dev/null
+++ b/system/src/nanosoc_managers/socdebug/verilog/nanosoc_manager_socdebug.v
@@ -0,0 +1,106 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Wrapper for SoCDebug Chip Debug Manager
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_manager_socdebug #(
+ parameter PROMPT_CHAR = "]",
+ parameter integer FT1248_WIDTH = 1, // FTDI Interface 1,2,4 width supported
+ parameter integer FT1248_CLKON = 0 // FTDI clock always on - else quiet when no access
+)(
+ // AHB-lite Master Interface - ADP
+ input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR32_o,
+ output wire [ 2:0] HBURST3_o,
+ output wire HMASTLOCK_o,
+ output wire [ 3:0] HPROT4_o,
+ output wire [ 2:0] HSIZE3_o,
+ output wire [ 1:0] HTRANS2_o,
+ output wire [31:0] HWDATA32_o,
+ output wire HWRITE_o,
+ input wire [31:0] HRDATA32_i,
+ input wire HREADY_i,
+ input wire HRESP_i,
+
+ // APB Slave Interface - USRT
+ input wire PCLK, // Clock
+ input wire PCLKG, // Gated Clock
+ input wire PRESETn, // Reset
+
+ input wire PSEL_i, // Device select
+ input wire [11:2] PADDR_i, // Address
+ input wire PENABLE_i, // Transfer control
+ input wire PWRITE_i, // Write control
+ input wire [31:0] PWDATA_i, // Write data
+
+ output wire [31:0] PRDATA_o, // Read data
+ output wire PREADY_o, // Device ready
+ output wire PSLVERR_o, // Device error response
+
+ // FT1248 Interace - FT1248
+ output wire FT_CLK_O, // SCLK
+ output wire FT_SSN_O, // SS_N
+ input wire FT_MISO_I, // MISO
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_O, // MIOSIO tristate output when enabled
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
+ output wire [FT1248_WIDTH-1:0] FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
+ input wire [FT1248_WIDTH-1:0] FT_MIOSIO_I, // MIOSIO tristate input
+ input wire [7:0] FT_CLKDIV, // divider prescaler to ensure SCLK <1MHz
+
+ // GPIO interface
+ output wire [7:0] GPO8_o,
+ input wire [7:0] GPI8_i
+);
+
+ // Instantiate SoCDebug Controller
+ socdebug_ahb u_socdebug (
+ // AHB-lite Master Interface - ADP
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HADDR32_o (HADDR32_o),
+ .HBURST3_o (HBURST3_o),
+ .HMASTLOCK_o (HMASTLOCK_o),
+ .HPROT4_o (HPROT4_o),
+ .HSIZE3_o (HSIZE3_o),
+ .HTRANS2_o (HTRANS2_o),
+ .HWDATA32_o (HWDATA32_o),
+ .HWRITE_o (HWRITE_o),
+ .HRDATA32_i (HRDATA32_i),
+ .HREADY_i (HREADY_i),
+ .HRESP_i (HRESP_i),
+
+ // APB Slave Interface - USRT
+ .PCLK (PCLK),
+ .PCLKG (PCLKG),
+ .PRESETn (PRESETn),
+ .PSEL_i (PSEL_i),
+ .PADDR_i (PADDR_i),
+ .PENABLE_i (PENABLE_i),
+ .PWRITE_i (PWRITE_i),
+ .PWDATA_i (PWDATA_i),
+ .PRDATA_o (PRDATA_o),
+ .PREADY_o (PREADY_o),
+ .PSLVERR_o (PSLVERR_o),
+
+ // FT1248 Interace - FT1248
+ .FT_CLK_O (FT_CLK_O),
+ .FT_SSN_O (FT_SSN_O),
+ .FT_MISO_I (FT_MISO_I),
+ .FT_MIOSIO_O (FT_MIOSIO_O),
+ .FT_MIOSIO_E (FT_MIOSIO_E),
+ .FT_MIOSIO_Z (FT_MIOSIO_Z),
+ .FT_MIOSIO_I (FT_MIOSIO_I),
+ .FT_CLKDIV (FT_CLKDIV),
+
+ // GPIO interface
+ .GPO8_o (GPO8_o),
+ .GPI8_i (GPI8_i)
+ );
+endmodule
\ No newline at end of file
diff --git a/system/src/verilog/nanosoc_ahb_bootrom.v b/system/src/nanosoc_regions/bootrom/verilog/nanosoc_ahb_bootrom.v
similarity index 100%
rename from system/src/verilog/nanosoc_ahb_bootrom.v
rename to system/src/nanosoc_regions/bootrom/verilog/nanosoc_ahb_bootrom.v
diff --git a/system/src/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v b/system/src/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v
new file mode 100644
index 0000000000000000000000000000000000000000..94ce02faf33658abbd0c384f3eee81a6f6448cbe
--- /dev/null
+++ b/system/src/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v
@@ -0,0 +1,54 @@
+//-----------------------------------------------------------------------------
+// Nanosoc Bootrom Region
+// Region Mapped to: 0x10000000-0x1fffffff
+// and Remapped to: 0x00000000-0x0000ffff
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_bootrom #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter BOOTROM_ADDR_W = 10 // Size of Bootrom (Based on Address Width) - Default 1KB
+ )(
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+ );
+
+ nanosoc_ahb_bootrom #(
+ .AW (BOOTROM_ADDR_W)
+ ) u_ahb_bootloader (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL),
+ .HADDR (HADDR[9:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+ .HREADYOUT (HREADYOUT),
+ .HRDATA (HRDATA),
+ .HRESP (HRESP)
+ );
+
+endmodule
diff --git a/system/src/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v b/system/src/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v
new file mode 100644
index 0000000000000000000000000000000000000000..95b106e45f50c7252bcb1572c9a440fc110d3b0b
--- /dev/null
+++ b/system/src/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v
@@ -0,0 +1,87 @@
+//-----------------------------------------------------------------------------
+// Nanosoc CPU Data Memory Region (DMEM)
+// - Region Mapped to: 0x30000000-0x3fffffff
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_dmem #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter DMEM_RAM_ADDR_W = 14, // Width of DMEM RAM Address - Default 16KB
+ parameter DMEM_RAM_DATA_W = 32 // Width of DMEM RAM Data Bus - Default 32 bits
+ )(
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+ );
+
+ wire [DMEM_RAM_ADDR_W-3:0] addr_dmem;
+ wire [DMEM_RAM_DATA_W-1:0] wdata_dmem;
+ wire [DMEM_RAM_DATA_W-1:0] rdata_dmem;
+ wire [3:0] wen_dmem;
+ wire cs_dmem;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(
+ .AW (DMEM_RAM_ADDR_W)
+ ) u_ahb_to_sdmem (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_dmem),
+ .HADDR (HADDR_dmem [DMEM_RAM_ADDR_W-1:0]),
+ .HTRANS (HTRANS_dmem),
+ .HSIZE (HSIZE_dmem),
+ .HWRITE (HWRITE_dmem),
+ .HWDATA (HWDATA_dmem),
+ .HREADY (HREADYMUX_dmem),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_dmem),
+ .HRDATA (HRDATA_dmem),
+ .HRESP (HRESP_dmem),
+
+ // SRAM input
+ .SRAMRDATA (rdata_dmem),
+
+ // SRAM Outputs
+ .SRAMADDR (addr_dmem),
+ .SRAMWDATA (wdata_dmem),
+ .SRAMWEN (wen_dmem),
+ .SRAMCS (cs_dmem)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(
+ .AW (DMEM_RAM_ADDR_W)
+ ) u_fpga_dmem (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_dmem),
+ .WDATA (wdata_dmem),
+ .WREN (wen_dmem),
+ .CS (cs_dmem),
+
+ // SRAM Output
+ .RDATA (rdata_dmem)
+ );
+endmodule
\ No newline at end of file
diff --git a/system/src/nanosoc_regions/exp/verilog/nanosoc_region_exp.v b/system/src/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/src/nanosoc_regions/expram_h/verilog/nanosoc_region_expram__h b/system/src/nanosoc_regions/expram_h/verilog/nanosoc_region_expram__h
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/src/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v b/system/src/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
new file mode 100644
index 0000000000000000000000000000000000000000..979b68230f92c22ec91e99db3be23fc1da0c2e62
--- /dev/null
+++ b/system/src/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
@@ -0,0 +1,89 @@
+//-----------------------------------------------------------------------------
+// Nanosoc Expansion SRAM Low Region (expram_l)
+// - Region Mapped to: 0x30000000-0x3fffffff
+// - Memory Exhibits Wrapping Behaviour
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_expram_l #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter EXPRAM_L_RAM_ADDR_W = 14, // Width of RAM Address - Default 16KB
+ parameter EXPRAM_L_RAM_DATA_W = 32 // Width of RAM Data Bus - Default 32 bits
+ )(
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+ );
+
+ wire [EXPRAM_L_RAM_ADDR_W-3:0] addr_expram_l;
+ wire [EXPRAM_L_RAM_DATA_W-1:0] wdata_expram_l;
+ wire [EXPRAM_L_RAM_DATA_W-1:0] rdata_expram_l;
+ wire [3:0] wen_expram_l;
+ wire cs_expram_l;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(
+ .AW (EXPRAM_L_RAM_ADDR_W)
+ ) u_ahb_to_sram8 (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_expram_l),
+ .HADDR (HADDR_expram_l[EXPRAM_L_RAM_ADDR_W-1:0]),
+ .HTRANS (HTRANS_expram_l),
+ .HSIZE (HSIZE_expram_l),
+ .HWRITE (HWRITE_expram_l),
+ .HWDATA (HWDATA_expram_l),
+ .HREADY (HREADYMUX_expram_l),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_expram_l),
+ .HRDATA (HRDATA_expram_l),
+ .HRESP (HRESP_expram_l),
+
+ // SRAM input
+ .SRAMRDATA (rdata_expram_l),
+
+ // SRAM Outputs
+ .SRAMADDR (addr_expram_l),
+ .SRAMWDATA (wdata_expram_l),
+ .SRAMWEN (wen_expram_l),
+ .SRAMCS (cs_expram_l)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(
+ .AW (EXPRAM_L_RAM_ADDR_W)
+ ) u_fpga_expram_l (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_expram_l),
+ .WDATA (wdata_expram_l),
+ .WREN (wen_expram_l),
+ .CS (cs_expram_l),
+
+ // SRAM Output
+ .RDATA (rdata_expram_l)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/system/src/nanosoc_regions/imem/verilog/nanosoc_region_imem.v b/system/src/nanosoc_regions/imem/verilog/nanosoc_region_imem.v
new file mode 100644
index 0000000000000000000000000000000000000000..11ce6a6125778ed76c800c6630e747d21376a293
--- /dev/null
+++ b/system/src/nanosoc_regions/imem/verilog/nanosoc_region_imem.v
@@ -0,0 +1,91 @@
+//-----------------------------------------------------------------------------
+// Nanosoc CPU Instruction Memory Region (IMEM)
+// - Region Mapped to: 0x20000000-0x2fffffff
+// - Memory Exhibits Wrapping Behaviour
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_imem #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
+ parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
+ parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
+ )(
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+ );
+
+ wire [IMEM_RAM_ADDR_W-3:0] addr_imem;
+ wire [IMEM_RAM_DATA_W-1:0] wdata_imem;
+ wire [IMEM_RAM_DATA_W-1:0] rdata_imem;
+ wire [3:0] wen_imem;
+ wire cs_imem;
+
+ // AHB to SRAM bridge
+ cmsdk_ahb_to_sram #(
+ .AW (IMEM_RAM_ADDR_W)
+ ) u_ahb_to_simem (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL_imem),
+ .HADDR (HADDR_imem [IMEM_RAM_ADDR_W-1:0]),
+ .HTRANS (HTRANS_imem),
+ .HSIZE (HSIZE_imem),
+ .HWRITE (HWRITE_imem),
+ .HWDATA (HWDATA_imem),
+ .HREADY (HREADYMUX_imem),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT_imem),
+ .HRDATA (HRDATA_imem),
+ .HRESP (HRESP_imem),
+
+ // SRAM input
+ .SRAMRDATA (rdata_imem),
+
+ // SRAM Outputs
+ .SRAMADDR (addr_imem),
+ .SRAMWDATA (wdata_imem),
+ .SRAMWEN (wen_imem),
+ .SRAMCS (cs_imem)
+ );
+
+ // SRAM model
+ cmsdk_fpga_sram #(
+ .AW (IMEM_RAM_ADDR_W),
+ .filename(IMEM_RAM_FPGA_IMG)
+ ) u_fpga_imem (
+ // SRAM Inputs
+ .CLK (HCLK),
+ .ADDR (addr_imem),
+ .WDATA (wdata_imem),
+ .WREN (wen_imem),
+ .CS (cs_imem),
+
+ // SRAM Output
+ .RDATA (rdata_imem)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/system/src/verilog/nanosoc_apb_subsystem.v b/system/src/nanosoc_regions/sysio/verilog/nanosoc_apb_subsystem.v
similarity index 100%
rename from system/src/verilog/nanosoc_apb_subsystem.v
rename to system/src/nanosoc_regions/sysio/verilog/nanosoc_apb_subsystem.v
diff --git a/system/src/verilog/nanosoc_sysio.v b/system/src/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
similarity index 59%
rename from system/src/verilog/nanosoc_sysio.v
rename to system/src/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 46395dba5082f22418fd8ace7a261d7cffa68abf..2c484541bf8a348be1c68d136f02bc2cb7aaf09b 100644
--- a/system/src/verilog/nanosoc_sysio.v
+++ b/system/src/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -1,167 +1,150 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// Nanosoc System Peripheral Region (SYSIO)
+// - Region Mapped to: 0x40000000-0x4fffffff
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
-// David Flynn (d.w.flynn@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : System level design for the example Cortex-M0 system
-//-----------------------------------------------------------------------------
+module nanosoc_region_sysio #(
+ parameter SYS_ADDR_W=32, // System Address Width
+ parameter SYS_DATA_W=32, // System Data Width
+ parameter APB_ADDR_W=12, // APB Peripheral Address Width
+ parameter APB_DATA_W=32 // APB Peripheral Data Width
+ )(
+ input wire FCLK, // Free-running system clock
+ input wire PORESETn, // Power-On-Reset reset (active-low)
+ input wire TESTMODE, // Reset bypass in scan test
+
+ // AHB interface
+ input wire HCLK, // AHB clock
+ input wire HRESETn, // AHB reset (active-low)
+ input wire HSEL, // AHB region select
+ input wire [SYS_ADDR_W-1:0] HADDR, // AHB address
+ input wire [ 2:0] HBURST, // AHB burst
+ input wire HMASTLOCK, // AHB lock
+ input wire [ 3:0] HPROT, // AHB prot
+ input wire [ 2:0] HSIZE, // AHB size
+ input wire [ 1:0] HTRANS, // AHB transfer
+ input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data
+ input wire HWRITE, // AHB write
+ input wire HREADY, // AHB ready
+ output wire [SYS_DATA_W-1:0] HRDATA, // AHB read-data
+ output wire HRESP, // AHB response
+ output wire HREADYOUT, // AHB ready out
+
+ // APB clocking control
+ input wire PCLK, // Peripheral clock
+ input wire PCLKG, // Gated Peripheral bus clock
+ input wire PRESETn, // Peripheral system and APB reset
+ input wire PCLKEN, // Clock divide control for AHB to APB bridge
+
+ // APB external Slave Interface
+ output wire exp12_psel,
+ output wire exp13_psel,
+ output wire exp14_psel,
+ output wire exp15_psel,
+ output wire exp_penable,
+ output wire exp_pwrite,
+ output wire [APB_ADDR_W-1:0] exp_paddr,
+ output wire [APB_DATA_W-1:0] exp_pwdata,
+ input wire [APB_DATA_W-1:0] exp12_prdata,
+ input wire exp12_pready,
+ input wire exp12_pslverr,
+ input wire [APB_DATA_W-1:0] exp13_prdata,
+ input wire exp13_pready,
+ input wire exp13_pslverr,
+ input wire [APB_DATA_W-1:0] exp14_prdata,
+ input wire exp14_pready,
+ input wire exp14_pslverr,
+ input wire [APB_DATA_W-1:0] exp15_prdata,
+ input wire exp15_pready,
+ input wire exp15_pslverr,
+
+ // CPU sideband signalling
+ output wire SYS_NMI, // watchdog_interrupt;
+ output wire [31:0] SYS_APB_IRQ, // apbsubsys_interrupt;
+ output wire [15:0] SYS_GPIO0_IRQ, // GPIO 0 irqs
+ output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 irqs
+
+ // CPU power/reset control
+ output wire REMAP_CTRL, // REMAP control bit
+ output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
+ output wire SYSRESETREQ, // Processor control - system reset request
+ output wire WDOGRESETREQ, // Watchdog reset request
+ input wire LOCKUP, // Processor status - Locked up
+ output wire LOCKUPRESET, // System Controller cfg - reset if lockup
+ output wire PMUENABLE, // System Controller cfg - Enable PMU
+
+ // IO signalling
+ input wire uart0_rxd, // Uart 0 receive data
+ output wire uart0_txd, // Uart 0 transmit data
+ output wire uart0_txen, // Uart 0 transmit data enable
+ input wire uart1_rxd, // Uart 1 receive data
+ output wire uart1_txd, // Uart 1 transmit data
+ output wire uart1_txen, // Uart 1 transmit data enable
+ input wire uart2_rxd, // Uart 2 receive data
+ output wire uart2_txd, // Uart 2 transmit data
+ output wire uart2_txen, // Uart 2 transmit data enable
+ input wire timer0_extin, // Timer 0 external input
+ input wire timer1_extin, // Timer 1 external input
+
+ // GPIO
+ input wire [15:0] p0_in, // GPIO 0 inputs
+ output wire [15:0] p0_out, // GPIO 0 outputs
+ output wire [15:0] p0_outen, // GPIO 0 output enables
+ output wire [15:0] p0_altfunc, // GPIO 0 alternate function (pin mux)
+ input wire [15:0] p1_in, // GPIO 1 inputs
+ output wire [15:0] p1_out, // GPIO 1 outputs
+ output wire [15:0] p1_outen, // GPIO 1 output enables
+ output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux)
+ );
-module nanosoc_sysio
-(
- input wire FCLK, // Free-running system clock
- input wire PORESETn, // Power-On-Reset reset (active-low)
- input wire TESTMODE, // Reset bypass in scan test
-// AHB interface
- input wire HCLK, // AHB clock
- input wire HRESETn, // AHB reset (active-low)
- input wire HSEL, // AHB region select
- input wire [31:0] HADDR, // AHB address
- input wire [ 2:0] HBURST, // AHB burst
- input wire HMASTLOCK, // AHB lock
- input wire [ 3:0] HPROT, // AHB prot
- input wire [ 2:0] HSIZE, // AHB size
- input wire [ 1:0] HTRANS, // AHB transfer
- input wire [31:0] HWDATA, // AHB write data
- input wire HWRITE, // AHB write
- input wire HREADY, // AHB ready
- output wire [31:0] HRDATA, // AHB read-data
- output wire HRESP, // AHB response
- output wire HREADYOUT, // AHB ready out
- // APB clocking control
- input wire PCLK, // Peripheral clock
- input wire PCLKG, // Gated Peripheral bus clock
- input wire PRESETn, // Peripheral system and APB reset
- input wire PCLKEN, // Clock divide control for AHB to APB bridge
- // APB external Slave Interface
- output wire exp12_psel,
- output wire exp13_psel,
- output wire exp14_psel,
- output wire exp15_psel,
- output wire exp_penable,
- output wire exp_pwrite,
- output wire [11:0] exp_paddr,
- output wire [31:0] exp_pwdata,
- input wire [31:0] exp12_prdata,
- input wire exp12_pready,
- input wire exp12_pslverr,
- input wire [31:0] exp13_prdata,
- input wire exp13_pready,
- input wire exp13_pslverr,
- input wire [31:0] exp14_prdata,
- input wire exp14_pready,
- input wire exp14_pslverr,
- input wire [31:0] exp15_prdata,
- input wire exp15_pready,
- input wire exp15_pslverr,
-
- // CPU sideband signalling
- output wire SYS_NMI, // watchdog_interrupt;
- output wire [31:0] SYS_APB_IRQ, // apbsubsys_interrupt;
- output wire [15:0] SYS_GPIO0_IRQ, // GPIO 0 irqs
- output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 irqs
-
- // CPU power/reset control
- output wire REMAP_CTRL, // REMAP control bit
- output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
- output wire SYSRESETREQ, // Processor control - system reset request
- output wire WDOGRESETREQ, // Watchdog reset request
- input wire LOCKUP, // Processor status - Locked up
- output wire LOCKUPRESET, // System Controller cfg - reset if lockup
- output wire PMUENABLE, // System Controller cfg - Enable PMU
-
- // IO signalling
- input wire uart0_rxd, // Uart 0 receive data
- output wire uart0_txd, // Uart 0 transmit data
- output wire uart0_txen, // Uart 0 transmit data enable
- input wire uart1_rxd, // Uart 1 receive data
- output wire uart1_txd, // Uart 1 transmit data
- output wire uart1_txen, // Uart 1 transmit data enable
- input wire uart2_rxd, // Uart 2 receive data
- output wire uart2_txd, // Uart 2 transmit data
- output wire uart2_txen, // Uart 2 transmit data enable
- input wire timer0_extin, // Timer 0 external input
- input wire timer1_extin, // Timer 1 external input
-
- // GPIO
- input wire [15:0] p0_in, // GPIO 0 inputs
- output wire [15:0] p0_out, // GPIO 0 outputs
- output wire [15:0] p0_outen, // GPIO 0 output enables
- output wire [15:0] p0_altfunc, // GPIO 0 alternate function (pin mux)
- input wire [15:0] p1_in, // GPIO 1 inputs
- output wire [15:0] p1_out, // GPIO 1 outputs
- output wire [15:0] p1_outen, // GPIO 1 output enables
- output wire [15:0] p1_altfunc // GPIO 1 alternate function (pin mux)
-);
-
-
- localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
- localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
+
+ localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
+ localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
localparam BASEADDR_SYSROMTABLE = 32'hf000_0000;
- localparam BE = 0;
+ localparam BE = 0;
// ------------------------------------------------------------
// Local wires
// ------------------------------------------------------------
- wire defslv_hsel; // AHB default slave signals
- wire defslv_hreadyout;
- wire [31:0] defslv_hrdata;
- wire defslv_hresp;
+ wire defslv_hsel; // AHB default slave signals
+ wire defslv_hreadyout;
+ wire [SYS_DATA_W-1:0] defslv_hrdata;
+ wire defslv_hresp;
- wire apbsys_hsel; // APB subsystem AHB interface signals
- wire apbsys_hreadyout;
- wire [31:0] apbsys_hrdata;
- wire apbsys_hresp;
+ wire apbsys_hsel; // APB subsystem AHB interface signals
+ wire apbsys_hreadyout;
+ wire [SYS_DATA_W-1:0] apbsys_hrdata;
+ wire apbsys_hresp;
- wire gpio0_hsel; // AHB GPIO bus interface signals
- wire gpio0_hreadyout;
- wire [31:0] gpio0_hrdata;
- wire gpio0_hresp;
+ wire gpio0_hsel; // AHB GPIO bus interface signals
+ wire gpio0_hreadyout;
+ wire [SYS_DATA_W-1:0] gpio0_hrdata;
+ wire gpio0_hresp;
- wire gpio1_hsel; // AHB GPIO bus interface signals
- wire gpio1_hreadyout;
- wire [31:0] gpio1_hrdata;
- wire gpio1_hresp;
+ wire gpio1_hsel; // AHB GPIO bus interface signals
+ wire gpio1_hreadyout;
+ wire [SYS_DATA_W-1:0] gpio1_hrdata;
+ wire gpio1_hresp;
- wire sysctrl_hsel; // System control bus interface signals
- wire sysctrl_hreadyout;
- wire [31:0] sysctrl_hrdata;
- wire sysctrl_hresp;
+ wire sysctrl_hsel; // System control bus interface signals
+ wire sysctrl_hreadyout;
+ wire [SYS_DATA_W-1:0] sysctrl_hrdata;
+ wire sysctrl_hresp;
// System ROM Table
- wire sysrom_hsel; // AHB to System ROM Table - select
- wire sysrom_hreadyout;
- wire [31:0] sysrom_hrdata;
- wire sysrom_hresp;
+ wire sysrom_hsel; // AHB to System ROM Table - select
+ wire sysrom_hreadyout;
+ wire [SYS_DATA_W-1:0] sysrom_hrdata;
+ wire sysrom_hresp;
// AHB address decode
@@ -169,8 +152,7 @@ module nanosoc_sysio
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1),
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
- )
- u_addr_decode (
+ ) u_addr_decode (
// System Address
.hsel (HSEL),
.haddr (HADDR),
@@ -195,8 +177,7 @@ module nanosoc_sysio
.PORT8_ENABLE (0),
.PORT9_ENABLE (0),
.DW (32)
- )
- u_ahb_slave_mux_sys_bus (
+ ) u_ahb_slave_mux_sys_bus (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
@@ -297,9 +278,9 @@ module nanosoc_sysio
// Peripherals
// -------------------------------
- nanosoc_mcu_sysctrl #(.BE (BE))
- u_nanosoc_mcu_sysctrl
- (
+ nanosoc_mcu_sysctrl #(
+ .BE (BE)
+ ) u_nanosoc_mcu_sysctrl (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -359,7 +340,7 @@ module nanosoc_sysio
.PORTFUNC (p0_altfunc), // Alternate function control
.GPIOINT (SYS_GPIO0_IRQ[15:0]), // Interrupt outputs
- .COMBINT ( )
+ .COMBINT ()
);
@@ -367,8 +348,7 @@ module nanosoc_sysio
.ALTERNATE_FUNC_MASK (16'h002A), // pin muxing for Port #1
.ALTERNATE_FUNC_DEFAULT (16'h0000), // All pins default to GPIO
.BE (BE)
- )
- u_ahb_gpio_1 (
+ ) u_ahb_gpio_1 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -412,8 +392,7 @@ module nanosoc_sysio
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
- )
- u_nanosoc_apb_subsystem(
+ ) u_nanosoc_apb_subsystem (
// AHB interface for AHB to APB bridge
.HCLK (HCLK),
diff --git a/system/src/verilog/nanosoc_mcu_sysctrl.v b/system/src/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
similarity index 99%
rename from system/src/verilog/nanosoc_mcu_sysctrl.v
rename to system/src/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
index cfdf5d14ea1b10be9e4a49d55d64a9aa4aa9d01a..7ce66cb889d7e3e2a31582c64a8097082d0814e1 100644
--- a/system/src/verilog/nanosoc_mcu_sysctrl.v
+++ b/system/src/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
@@ -52,7 +52,7 @@
//
//-------------------------------------
-module nanosoc_mcu_sysctrl #(
+module nanosoc_sysctrl #(
parameter BE = 0 // By default use little endian
)
diff --git a/system/src/verilog/nanosoc_sys_ahb_decode.v b/system/src/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
similarity index 87%
rename from system/src/verilog/nanosoc_sys_ahb_decode.v
rename to system/src/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index 15d6d07ced7a86532c57de25f370183d21234143..36e86a9a6412a9c760b4f8eb4b3f2fea29e1d34c 100644
--- a/system/src/verilog/nanosoc_sys_ahb_decode.v
+++ b/system/src/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// NanoSoC AHB decoder adapted from Arm CMSDK AHB decoder
+// NanoSoC AHB decoder for System Peripheral Space adapted from Arm CMSDK AHB decoder
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -38,34 +38,31 @@
//-----------------------------------------------------------------------------
//
-module nanosoc_sys_ahb_decode #(
+module nanosoc_sysio_decode #(
+ parameter SYS_ADDR_W = 32,
// GPIO0 peripheral base address
parameter BASEADDR_GPIO0 = 32'h4001_0000,
// GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// GPIO1 peripheral base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000,
-
// Location of the System ROM Table.
parameter BASEADDR_SYSROMTABLE = 32'hf000_0000
- )
- (
+ )(
// System Address
- input wire hsel,
- input wire [31:0] haddr,
+ input wire hsel,
+ input wire [SYS_ADDR_W-1:0] haddr,
// Peripheral Selection
- output wire apbsys_hsel,
- output wire gpio0_hsel,
- output wire gpio1_hsel,
- output wire sysctrl_hsel,
- output wire sysrom_hsel,
+ output wire apbsys_hsel,
+ output wire gpio0_hsel,
+ output wire gpio1_hsel,
+ output wire sysctrl_hsel,
+ output wire sysrom_hsel,
// Default slave
- output wire defslv_hsel
- );
-
-
+ output wire defslv_hsel
+ );
// AHB address decode
// 0x40000000 - 0x4000FFFF : APB subsystem
diff --git a/system/src/verilog/nanosoc_ahb_cs_rom_table.v b/system/src/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v
similarity index 100%
rename from system/src/verilog/nanosoc_ahb_cs_rom_table.v
rename to system/src/nanosoc_regions/systable/verilog/nanosoc_ahb_cs_rom_table.v
diff --git a/system/src/nanosoc_regions/systable/verilog/nanosoc_region_systable.v b/system/src/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
new file mode 100644
index 0000000000000000000000000000000000000000..4c41134b52e55d3ff1ad81017cf7966c7d11a133
--- /dev/null
+++ b/system/src/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
@@ -0,0 +1,71 @@
+//-----------------------------------------------------------------------------
+// Nanosoc System ROM Table Region (SYSTABLE)
+// - Region Mapped to: 0xF0000000-0xF0003FFF
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_systable #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter SYSTABLE_BASE = 32'hf000_0000 // Base Address for System ROM Table
+ )(
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSEL, // AHB region select
+ input wire [SYS_ADDR_W-1:0] HADDR, // AHB address
+ input wire [ 2:0] HBURST, // AHB burst
+ input wire HMASTLOCK, // AHB lock
+ input wire [ 3:0] HPROT, // AHB prot
+ input wire [ 2:0] HSIZE, // AHB size
+ input wire [ 1:0] HTRANS, // AHB transfer
+ input wire [SYS_DATA_W-1:0] HWDATA, // AHB write data
+ input wire HWRITE, // AHB write
+ input wire HREADY, // AHB ready
+ output wire [SYS_DATA_W-1:0] HRDATA, // AHB read-data
+ output wire HRESP, // AHB response
+ output wire HREADYOUT // AHB ready out
+ );
+
+ // -------------------------------
+ // System ROM Table
+ // -------------------------------
+ nanosoc_ahb_cs_rom_table #(
+ .BASE (SYSTABLE_BASE),
+ // Entry 0 = Cortex-M0 Processor
+ .ENTRY0BASEADDR (32'hE00FF000),
+ .ENTRY0PRESENT (1'b1),
+ // Entry 1 = CoreSight MTB-M0
+ .ENTRY1BASEADDR (32'hF0200000),
+ .ENTRY1PRESENT (0)
+ ) u_system_rom_table (
+ // ECO Revision
+ .ECOREVNUM (4'h0),
+
+ //Inputs
+ .HCLK (HCLK),
+ .HSEL (HSEL),
+ .HADDR (HADDR),
+ .HBURST (HBURST),
+ .HMASTLOCK (HMASTLOCK),
+ .HPROT (HPROT),
+ .HSIZE (HSIZE),
+ .HTRANS (HTRANS),
+ .HWDATA (HWDATA),
+ .HWRITE (HWRITE),
+ .HREADY (HREADY),
+
+ //Outputs
+ .HRDATA (HRDATA),
+ .HREADYOUT (HREADYOUT),
+ .HRESP (HRESP)
+ );
+endmodule
\ No newline at end of file
diff --git a/system/src/nanosoc_sys/verilog/nanosoc_sys.v b/system/src/nanosoc_sys/verilog/nanosoc_sys.v
new file mode 100644
index 0000000000000000000000000000000000000000..9c4d9f6024bd02263a9ae7b3fda348fb8688fdab
--- /dev/null
+++ b/system/src/nanosoc_sys/verilog/nanosoc_sys.v
@@ -0,0 +1,2 @@
+module nanosoc_sys (
+
diff --git a/system/src/verilog/nanosoc_apb_usrt.v b/system/src/verilog/nanosoc_apb_usrt.v
deleted file mode 100644
index 8df136a6aaa944ef5f3b5dc0c5e1d94586117960..0000000000000000000000000000000000000000
--- a/system/src/verilog/nanosoc_apb_usrt.v
+++ /dev/null
@@ -1,1159 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC APB USRT adapted from Arm CMSDK APB UART
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Simple APB UART
-//-----------------------------------------------------------------------------
-//-------------------------------------
-// Programmer's model
-// 0x00 R RXD[7:0] Received Data
-// W TXD[7:0] Transmit data
-// 0x04 RW STAT[3:0]
-// [3] RX buffer overrun (write 1 to clear)
-// [2] TX buffer overrun (write 1 to clear)
-// [1] RX buffer full (Read only)
-// [0] TX buffer full (Read only)
-// 0x08 RW CTRL[3:0] TxIntEn, RxIntEn, TxEn, RxEn
-// [6] High speed test mode Enable
-// [5] RX overrun interrupt enable
-// [4] TX overrun interrupt enable
-// [3] RX Interrupt Enable
-// [2] TX Interrupt Enable
-// [1] RX Enable
-// [0] TX Enable
-// 0x0C R/Wc intr_status/INTCLEAR
-// [3] RX overrun interrupt
-// [2] TX overrun interrupt
-// [1] RX interrupt
-// [0] TX interrupt
-// 0x10 RW BAUDDIV[19:0] Baud divider
-// (minimum value is 16)
-// 0x3E0 - 0x3FC ID registers
-//-------------------------------------
-
-module nanosoc_apb_usrt (
-// --------------------------------------------------------------------------
-// Port Definitions
-// --------------------------------------------------------------------------
- input wire PCLK, // Clock
- input wire PCLKG, // Gated Clock
- input wire PRESETn, // Reset
-
- input wire PSEL, // Device select
- input wire [11:2] PADDR, // Address
- input wire PENABLE, // Transfer control
- input wire PWRITE, // Write control
- input wire [31:0] PWDATA, // Write data
-
- input wire [3:0] ECOREVNUM,// Engineering-change-order revision bits
-
- output wire [31:0] PRDATA, // Read data
- output wire PREADY, // Device ready
- output wire PSLVERR, // Device error response
-
- output wire TX_VALID_o,
- output wire [7:0] TX_DATA8_o,
- input wire TX_READY_i,
-
- input wire RX_VALID_i,
- input wire [7:0] RX_DATA8_i,
- output wire RX_READY_o,
-
- output wire TXINT, // Transmit Interrupt
- output wire RXINT, // Receive Interrupt
- output wire TXOVRINT, // Transmit overrun Interrupt
- output wire RXOVRINT, // Receive overrun Interrupt
- output wire UARTINT); // Combined interrupt
-
-// Local ID parameters, APB UART part number is 0x821
-localparam ARM_CMSDK_APB_UART_PID4 = 8'h04;
-localparam ARM_CMSDK_APB_UART_PID5 = 8'h00;
-localparam ARM_CMSDK_APB_UART_PID6 = 8'h00;
-localparam ARM_CMSDK_APB_UART_PID7 = 8'h00;
-localparam ARM_CMSDK_APB_UART_PID0 = 8'h21;
-localparam ARM_CMSDK_APB_UART_PID1 = 8'hB8;
-localparam ARM_CMSDK_APB_UART_PID2 = 8'h1B;
-localparam ARM_CMSDK_APB_UART_PID3 = 4'h0;
-localparam ARM_CMSDK_APB_UART_CID0 = 8'h0D;
-localparam ARM_CMSDK_APB_UART_CID1 = 8'hF0;
-localparam ARM_CMSDK_APB_UART_CID2 = 8'h05;
-localparam ARM_CMSDK_APB_UART_CID3 = 8'hB1;
-
-// original external IOs
-wire RXD = 1'b1; // Serial input
-wire TXD; // Transmit data output
-wire TXEN; // Transmit enabled
-wire BAUDTICK; // Baud rate (x16) Tick
-
-
- // --------------------------------------------------------------------------
- // Internal wires
- // --------------------------------------------------------------------------
-// Signals for read/write controls
-wire read_enable;
-wire write_enable;
-wire write_enable00; // Write enable for data register
-wire write_enable04; // Write enable for Status register
-wire write_enable08; // Write enable for control register
-wire write_enable0c; // Write enable for interrupt status register
-wire write_enable10; // Write enable for Baud rate divider
-reg [7:0] read_mux_byte0; // Read data multiplexer for lower 8-bit
-reg [7:0] read_mux_byte0_reg; // Register read data for lower 8-bit
-wire [31:0] read_mux_word; // Read data multiplexer for whole 32-bit
-wire [3:0] pid3_value; // constant value for lower 4-bit in perpherial ID3
-
-// Signals for Control registers
-reg [6:0] reg_ctrl; // Control register
-reg [7:0] reg_tx_buf; // Transmit data buffer
-reg [7:0] reg_rx_buf; // Receive data buffer
-reg [19:0] reg_baud_div; // Baud rate setting
-
-// Internal signals
- // Baud rate divider
-reg [15:0] reg_baud_cntr_i; // baud rate divider counter i (integer)
-wire [15:0] nxt_baud_cntr_i;
-reg [3:0] reg_baud_cntr_f; // baud rate divider counter f (fraction)
-wire [3:0] nxt_baud_cntr_f;
-wire [3:0] mapped_cntr_f; // remapped counter f value
-reg reg_baud_tick; // Register baud rate tick (16 times of baud rate)
-reg baud_updated; // baud rate value has bee updated from APB
-wire reload_i; // baud rate divider counter i reload
-wire reload_f; // baud rate divider counter f reload
-wire baud_div_en; // enable baud rate counter
-
- // Status
-wire [3:0] uart_status; // UART status
-reg reg_rx_overrun; // Receive overrun status register
-wire rx_overrun; // Receive overrun detection
-reg reg_tx_overrun; // Transmit overrun status register
-wire tx_overrun; // Transmit overrun detection
-wire nxt_rx_overrun; // next state for reg_rx_overrun
-wire nxt_tx_overrun; // next state for reg_tx_overrun
- // Interrupts
-reg reg_txintr; // Transmit interrupt register
-reg reg_rxintr; // Receive interrupt register
-wire tx_overflow_intr;// Transmit overrun/overflow interrupt
-wire rx_overflow_intr;// Receive overrun/overflow interrupt
-wire [3:0] intr_state; // UART interrupt status
-wire [1:0] intr_stat_set; // Set TX/RX interrupt
-wire [1:0] intr_stat_clear; // Clear TX/RX interrupt
-
- // transmit
-reg [3:0] tx_state; // Transmit FSM state
-reg [4:0] nxt_tx_state;
-wire tx_state_update;
-wire tx_state_inc; // Bit pulse
-reg [3:0] tx_tick_cnt; // Transmit Tick counter
-wire [4:0] nxt_tx_tick_cnt;
-reg [7:0] tx_shift_buf; // Transmit shift register
-wire [7:0] nxt_tx_shift_buf; // next state for tx_shift_buf
-wire tx_buf_ctrl_shift; // shift control for tx_shift_buf
-wire tx_buf_ctrl_load; // load control for tx_shift_buf
-reg tx_buf_full; // TX Buffer full
-reg reg_txd; // Tx Data
-wire nxt_txd; // next state of reg_txd
-wire update_reg_txd; // update reg_txd
-wire tx_buf_clear; // Clear buffer full status when data is load into TX shift register
-
- // Receive data sync and filter
-reg rxd_sync_1; // Double flip-flop syncrhoniser
-reg rxd_sync_2; // Double flip-flop syncrhoniser
-reg [2:0] rxd_lpf; // Averaging Low Pass Filter
-wire [2:0] nxt_rxd_lpf;
-wire rx_shift_in; // Shift Register Input
-
- // Receiver
-reg [3:0] rx_state; // Receiver FSM state
-reg [4:0] nxt_rx_state;
-wire rx_state_update;
-reg [3:0] rx_tick_cnt; // Receiver Tick counter
-wire [4:0] nxt_rx_tick_cnt;
-wire update_rx_tick_cnt;
-wire rx_state_inc;// Bit pulse
-reg [6:0] rx_shift_buf;// Receiver shift data register
-wire [6:0] nxt_rx_shift_buf;
-reg rx_buf_full; // Receive buffer full status
-wire nxt_rx_buf_full;
-wire rxbuf_sample; // Sample received data into receive data buffer
-wire rx_data_read; // Receive data buffer read by APB interface
-wire [7:0] nxt_rx_buf;
-
-// Start of main code
-// Read and write control signals
-assign read_enable = PSEL & (~PWRITE); // assert for whole APB read transfer
-assign write_enable = PSEL & (~PENABLE) & PWRITE; // assert for 1st cycle of write transfer
-assign write_enable00 = write_enable & (PADDR[11:2] == 10'h000);
-assign write_enable04 = write_enable & (PADDR[11:2] == 10'h001);
-assign write_enable08 = write_enable & (PADDR[11:2] == 10'h002);
-assign write_enable0c = write_enable & (PADDR[11:2] == 10'h003);
-assign write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
-
-// Write operations
- // Transmit data register
- always @(posedge PCLKG or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_tx_buf <= {8{1'b0}};
- else if (write_enable00)
- reg_tx_buf <= PWDATA[7:0];
- end
-
- assign TX_DATA8_o = reg_tx_buf[7:0];
-
- // Status register overrun registers
- assign nxt_rx_overrun = (reg_rx_overrun & (~((write_enable04|write_enable0c) & PWDATA[3]))) | rx_overrun;
- assign nxt_tx_overrun = (reg_tx_overrun & (~((write_enable04|write_enable0c) & PWDATA[2]))) | tx_overrun;
-
- // RX OverRun status
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_rx_overrun <= 1'b0;
- else if (rx_overrun | write_enable04 | write_enable0c)
- reg_rx_overrun <= nxt_rx_overrun;
- end
-
- // TX OverRun status
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_tx_overrun <= 1'b0;
- else if (tx_overrun | write_enable04 | write_enable0c)
- reg_tx_overrun <= nxt_tx_overrun;
- end
-
- // Control register
- always @(posedge PCLKG or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_ctrl <= {7{1'b0}};
- else if (write_enable08)
- reg_ctrl <= PWDATA[6:0];
- end
-
- // Baud rate divider - integer
- always @(posedge PCLKG or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_baud_div <= {20{1'b0}};
- else if (write_enable10)
- reg_baud_div <= PWDATA[19:0];
- end
-
-// Read operation
- assign uart_status = {reg_rx_overrun, reg_tx_overrun, rx_buf_full, tx_buf_full};
-
- assign pid3_value = ARM_CMSDK_APB_UART_PID3;
-
- // First level of read mux
- always @(PADDR or reg_rx_buf or uart_status or reg_ctrl or intr_state or reg_baud_div
- or ECOREVNUM or pid3_value)
- begin
- if (PADDR[11:5] == 7'h00) begin
- case (PADDR[4:2])
- 3'h0: read_mux_byte0 = reg_rx_buf;
- 3'h1: read_mux_byte0 = {{4{1'b0}},uart_status};
- 3'h2: read_mux_byte0 = {{1{1'b0}},reg_ctrl};
- 3'h3: read_mux_byte0 = {{4{1'b0}},intr_state};
- 3'h4: read_mux_byte0 = reg_baud_div[7:0];
- 3'h5, 3'h6, 3'h7: read_mux_byte0 = {8{1'b0}}; //default read out value
- default: read_mux_byte0 = {8{1'bx}};// x propogation
- endcase
- end
- else if (PADDR[11:6] == 6'h3F) begin
- case (PADDR[5:2])
- 4'h0, 4'h1,4'h2,4'h3: read_mux_byte0 = {8{1'b0}}; //default read out value
- // ID register - constant values
- 4'h4: read_mux_byte0 = ARM_CMSDK_APB_UART_PID4; // 0xFD0 : PID 4
- 4'h5: read_mux_byte0 = ARM_CMSDK_APB_UART_PID5; // 0xFD4 : PID 5
- 4'h6: read_mux_byte0 = ARM_CMSDK_APB_UART_PID6; // 0xFD8 : PID 6
- 4'h7: read_mux_byte0 = ARM_CMSDK_APB_UART_PID7; // 0xFDC : PID 7
- 4'h8: read_mux_byte0 = ARM_CMSDK_APB_UART_PID0; // 0xFE0 : PID 0 APB UART part number[7:0]
- 4'h9: read_mux_byte0 = ARM_CMSDK_APB_UART_PID1; // 0xFE0 : PID 1 [7:4] jep106_id_3_0. [3:0] part number [11:8]
- 4'hA: read_mux_byte0 = ARM_CMSDK_APB_UART_PID2; // 0xFE0 : PID 2 [7:4] revision, [3] jedec_used. [2:0] jep106_id_6_4
- 4'hB: read_mux_byte0 = {ECOREVNUM[3:0],pid3_value[3:0]};
- // 0xFE0 : PID 3 [7:4] ECO revision, [3:0] modification number
- 4'hC: read_mux_byte0 = ARM_CMSDK_APB_UART_CID0; // 0xFF0 : CID 0
- 4'hD: read_mux_byte0 = ARM_CMSDK_APB_UART_CID1; // 0xFF4 : CID 1 PrimeCell class
- 4'hE: read_mux_byte0 = ARM_CMSDK_APB_UART_CID2; // 0xFF8 : CID 2
- 4'hF: read_mux_byte0 = ARM_CMSDK_APB_UART_CID3; // 0xFFC : CID 3
- default : read_mux_byte0 = {8{1'bx}}; // x propogation
- endcase
- end
- else begin
- read_mux_byte0 = {8{1'b0}}; //default read out value
- end
- end
-
-
-
- // Register read data
- always @(posedge PCLKG or negedge PRESETn)
- begin
- if (~PRESETn)
- read_mux_byte0_reg <= {8{1'b0}};
- else if (read_enable)
- read_mux_byte0_reg <= read_mux_byte0;
- end
-
- // Second level of read mux
- assign read_mux_word[ 7: 0] = read_mux_byte0_reg;
- assign read_mux_word[19: 8] = (PADDR[11:2]==10'h004) ? reg_baud_div[19:8] : {12{1'b0}};
- assign read_mux_word[31:20] = {12{1'b0}};
-
-
- // Output read data to APB
- assign PRDATA[31: 0] = (read_enable) ? read_mux_word : {32{1'b0}};
- assign PREADY = 1'b1; // Always ready
- assign PSLVERR = 1'b0; // Always okay
-
-// --------------------------------------------
-// Baud rate generator
- // Baud rate generator enable
- assign baud_div_en = (reg_ctrl[1:0] != 2'b00);
- assign mapped_cntr_f = {reg_baud_cntr_f[0],reg_baud_cntr_f[1],
- reg_baud_cntr_f[2],reg_baud_cntr_f[3]};
- // Reload Integer divider
- // when UART enabled and (reg_baud_cntr_f < reg_baud_div[3:0])
- // then count to 1, or
- // when UART enabled then count to 0
- assign reload_i = (baud_div_en &
- (((mapped_cntr_f >= reg_baud_div[3:0]) &
- (reg_baud_cntr_i[15:1] == {15{1'b0}})) |
- (reg_baud_cntr_i[15:0] == {16{1'b0}})));
-
- // Next state for Baud rate divider
- assign nxt_baud_cntr_i = (baud_updated | reload_i) ? reg_baud_div[19:4] :
- (reg_baud_cntr_i - 16'h0001);
- // Update at reload or decrement
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_baud_cntr_i <= {16{1'b0}};
- else if (baud_updated | baud_div_en)
- reg_baud_cntr_i <= nxt_baud_cntr_i;
- end
-
- // Reload fraction divider
- assign reload_f = baud_div_en & (reg_baud_cntr_f==4'h0) &
- reload_i;
- // Next state for fraction part of Baud rate divider
- assign nxt_baud_cntr_f =
- (reload_f|baud_updated) ? 4'hF :
- (reg_baud_cntr_f - 4'h1);
-
- // Update at reload or decrement
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_baud_cntr_f <= {4{1'b0}};
- else if (baud_updated | reload_f | reload_i)
- reg_baud_cntr_f <= nxt_baud_cntr_f;
- end
-
- // Generate control signal to update baud rate counters
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- baud_updated <= 1'b0;
- else if (write_enable10 | baud_updated)
- // Baud rate updated - to load new value to counters
- baud_updated <= write_enable10;
- end
-
- // Generate Tick signal for external logic
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_baud_tick <= 1'b0;
- else if (reload_i | reg_baud_tick)
- reg_baud_tick <= reload_i;
- end
-
- // Connect to external
- assign BAUDTICK = reg_baud_tick;
-
-// --------------------------------------------
-// Transmit
-
- // Buffer full status
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- tx_buf_full <= 1'b0;
- else if (write_enable00) // | tx_buf_clear)
- tx_buf_full <= write_enable00;
- else if (tx_buf_full & TX_READY_i) // AXI stream ack
- tx_buf_full <= 0;
- end
-
- assign TX_VALID_o = tx_buf_full;
-
- // Increment TickCounter
- assign nxt_tx_tick_cnt = ((tx_state==4'h1) & reg_baud_tick) ? {5{1'b0}} :
- tx_tick_cnt + {{3{1'b0}},reg_baud_tick};
-
- // Registering TickCounter
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- tx_tick_cnt <= {4{1'b0}};
- else if (reg_baud_tick)
- tx_tick_cnt <= nxt_tx_tick_cnt[3:0];
- end
-
- // Increment state (except Idle(0) and Wait for Tick(1))
- assign tx_state_inc = (((&tx_tick_cnt)|(tx_state==4'h1)) & reg_baud_tick)|reg_ctrl[6];
- // state increment every cycle of high speed test mode is enabled
- // Clear buffer full status when data is load into shift register
- assign tx_buf_clear = ((tx_state==4'h0) & tx_buf_full) |
- ((tx_state==4'hB) & tx_buf_full & tx_state_inc);
-
- // tx_state machine
- // 0 = Idle, 1 = Wait for Tick,
- // 2 = Start bit, 3 = D0 .... 10 = D7
- // 11 = Stop bit
- always @(tx_state or tx_buf_full or tx_state_inc or reg_ctrl)
- begin
- case (tx_state)
- 0: begin
- nxt_tx_state = (tx_buf_full & reg_ctrl[0]) ? 5'h01 : 5'h00; // New data is written to buffer
- end
- 1, // State 1 : Wait for next Tick
- 2,3,4,5,6,7,8,9,10: begin // State 2-10: Start bit, D0 - D7
- nxt_tx_state = tx_state + {3'b000,tx_state_inc};
- end
- 11: begin // Stop bit , goto next start bit or Idle
- nxt_tx_state = (tx_state_inc) ? ( tx_buf_full ? 5'h02:5'h00) : {1'b0, tx_state};
- end
- default:
- nxt_tx_state = {5{1'bx}};
- endcase
- end
-
- assign tx_state_update = tx_state_inc | ((tx_state==4'h0) & tx_buf_full & reg_ctrl[0]) | (tx_state>4'd11);
-
- // Registering outputs
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- tx_state <= {4{1'b0}};
- else if (tx_state_update)
- tx_state <= nxt_tx_state[3:0];
- end
-
- // Load/shift TX register
- assign tx_buf_ctrl_load = (((tx_state==4'h0) & tx_buf_full) |
- ((tx_state==4'hB) & tx_buf_full & tx_state_inc));
- assign tx_buf_ctrl_shift = ((tx_state>4'h2) & tx_state_inc);
-
- assign nxt_tx_shift_buf = tx_buf_ctrl_load ? reg_tx_buf[7:0] : {1'b1,tx_shift_buf[7:1]};
-
- // Registering TX shift register
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- tx_shift_buf <= {8{1'b0}};
- else if (tx_buf_ctrl_shift | tx_buf_ctrl_load)
- tx_shift_buf <= nxt_tx_shift_buf;
- end
-
- // Data output
- assign nxt_txd = (tx_state==4'h2) ? 1'b0 :
- (tx_state>4'h2) ? tx_shift_buf[0] : 1'b1;
-
- assign update_reg_txd = (nxt_txd != reg_txd);
-
- // Registering outputs
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_txd <= 1'b1;
- else if (update_reg_txd)
- reg_txd <= nxt_txd;
- end
-
- // Generate TX overrun error status
- assign tx_overrun = tx_buf_full & (~tx_buf_clear) & write_enable00;
-
- // Connect to external
- assign TXD = reg_txd;
- assign TXEN = reg_ctrl[0];
-
-// --------------------------------------------
-// Receive synchronizer and low pass filter
-
- // Doubling Flip-flop synxt_rx_tick_cntnchroniser
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- begin
- rxd_sync_1 <= 1'b1;
- rxd_sync_2 <= 1'b1;
- end
- else if (reg_ctrl[1]) // Turn off synchronizer if receive is not enabled
- begin
- rxd_sync_1 <= RXD;
- rxd_sync_2 <= rxd_sync_1;
- end
- end
-
- // Averaging low pass filter
- assign nxt_rxd_lpf = {rxd_lpf[1:0], rxd_sync_2};
- // Registering stage for low pass filter
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- rxd_lpf <= 3'b111;
- else if (reg_baud_tick)
- rxd_lpf <= nxt_rxd_lpf;
- end
-
- // Averaging values
- assign rx_shift_in = (rxd_lpf[1] & rxd_lpf[0]) |
- (rxd_lpf[1] & rxd_lpf[2]) |
- (rxd_lpf[0] & rxd_lpf[2]);
-
-// --------------------------------------------
-// Receive
-
- // Increment TickCounter
- assign nxt_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) ? 5'h08 :
- rx_tick_cnt + {{3{1'b0}},reg_baud_tick};
-
- assign update_rx_tick_cnt = ((rx_state==4'h0) & (~rx_shift_in)) | reg_baud_tick;
-
- // Registering other register
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- rx_tick_cnt <= {4{1'b0}};
- else if (update_rx_tick_cnt)
- rx_tick_cnt <= nxt_rx_tick_cnt[3:0];
- end
-
- // Increment state
- assign rx_state_inc = ((&rx_tick_cnt) & reg_baud_tick);
- // Buffer full status
- assign nxt_rx_buf_full = rxbuf_sample | (rx_buf_full & (~rx_data_read));
-
- // Sample shift register when D7 is sampled
-/// assign rxbuf_sample = ((rx_state==4'h9) & rx_state_inc);
- assign rxbuf_sample = RX_VALID_i & !rx_buf_full;
-
- // Reading receive buffer (Set at 1st cycle of APB transfer
- // because read mux is registered before output)
- assign rx_data_read = (PSEL & (~PENABLE) & (PADDR[11:2]==10'h000) & (~PWRITE));
- // Generate RX overrun error status
- assign rx_overrun = rx_buf_full & rxbuf_sample & (~rx_data_read);
-
- // rx_state machine
- // 0 = Idle, 1 = Start of Start bit detected
- // 2 = Sample Start bit, 3 = D0 .... 10 = D7
- // 11 = Stop bit
- // 11, 12, 13, 14, 15: illegal/unused states
- always @(rx_state or rx_shift_in or rx_state_inc or reg_ctrl)
- begin
- case (rx_state)
- 0: begin
- nxt_rx_state = ((~rx_shift_in) & reg_ctrl[1]) ? 5'h01 : 5'h00; // Wait for Start bit
- end
- 1, // State 1 : Wait for middle of start bit
- 2,3,4,5,6,7,8,9: begin // State 2-9: D0 - D7
- nxt_rx_state = rx_state + {3'b000,rx_state_inc};
- end
- 10: begin // Stop bit , goto back to Idle
- nxt_rx_state = (rx_state_inc) ? 5'h00 : 5'h0A;
- end
- default:
- nxt_rx_state = {5{1'bx}};
- endcase
- end
-
- assign rx_state_update = rx_state_inc | ((~rx_shift_in) & reg_ctrl[1]);
-
- // Registering rx_state
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- rx_state <= {4{1'b0}};
- else if (rx_state_update)
- rx_state <= nxt_rx_state[3:0];
- end
-
- // Buffer full status
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- rx_buf_full <= 1'b0;
- else if (rxbuf_sample | rx_data_read)
- rx_buf_full <= nxt_rx_buf_full;
- end
-
- // Sample receive buffer
-/// assign nxt_rx_buf = {rx_shift_in, rx_shift_buf};
- assign nxt_rx_buf = RX_DATA8_i[7:0];
-
- // Registering receive data buffer
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_rx_buf <= {8{1'b0}};
- else if (rxbuf_sample)
- reg_rx_buf <= nxt_rx_buf;
- end
-
- // Shift register
- assign nxt_rx_shift_buf= {rx_shift_in, rx_shift_buf[6:1]};
- // Registering shift buffer
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- rx_shift_buf <= {7{1'b0}};
- else if (rx_state_inc)
- rx_shift_buf <= nxt_rx_shift_buf;
- end
-
-
-
-// --------------------------------------------
-// Interrupts
- // Set by event
- assign intr_stat_set[1] = reg_ctrl[3] & rxbuf_sample; // A new receive data is sampled
- assign intr_stat_set[0] = reg_ctrl[2] & reg_ctrl[0] & tx_buf_full & tx_buf_clear;
- // Falling edge of buffer full
- // Clear by write to IntClear register
- assign intr_stat_clear[1:0] = {2{write_enable0c}} & PWDATA[1:0];
-
- // Registering outputs
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_txintr <= 1'b0;
- else if (intr_stat_set[0] | intr_stat_clear[0])
- reg_txintr <= intr_stat_set[0];
- end
-
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- reg_rxintr <= 1'b0;
- else if (intr_stat_set[1] | intr_stat_clear[1])
- reg_rxintr <= intr_stat_set[1];
- end
-
- assign rx_overflow_intr = reg_rx_overrun & reg_ctrl[5];
- assign tx_overflow_intr = reg_tx_overrun & reg_ctrl[4];
-
- // Interrupt status for read back
- assign intr_state = {rx_overflow_intr, tx_overflow_intr, reg_rxintr, reg_txintr};
-
- // Connect to external
- assign TXINT = reg_txintr;
- assign RXINT = reg_rxintr;
- assign TXOVRINT = tx_overflow_intr;
- assign RXOVRINT = rx_overflow_intr;
- assign UARTINT = reg_txintr | reg_rxintr | tx_overflow_intr | rx_overflow_intr;
-
-
-`ifdef ARM_APB_ASSERT_ON
- // ------------------------------------------------------------
- // Assertions
- // ------------------------------------------------------------
-`include "std_ovl_defines.h"
-
- // Prepare signals for OVL checking
- reg [15:0] ovl_last_reg_baud_cntr_i;
- reg [3:0] ovl_last_reg_baud_cntr_f;
- reg ovl_last_baud_div_en;
- reg ovl_last_baud_updated;
- always @(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- begin
- ovl_last_reg_baud_cntr_i <= {16{1'b0}};
- ovl_last_reg_baud_cntr_f <= {4{1'b0}};
- ovl_last_baud_div_en <= 1'b0;
- ovl_last_baud_updated <= 1'b0;
- end
- else
- begin
- ovl_last_reg_baud_cntr_i <= reg_baud_cntr_i;
- ovl_last_reg_baud_cntr_f <= reg_baud_cntr_f;
- ovl_last_baud_div_en <= baud_div_en;
- ovl_last_baud_updated <= baud_updated;
- end
- end
-
- reg ovl_reg_hs_test_mode_triggered; // Indicate if HighSpeed testmode has been activated
- wire ovl_nxt_hs_test_mode_triggered;
- reg [7:0] ovl_reg_tx_tick_count; // For measuring width of TX state
- wire [7:0] ovl_nxt_tx_tick_count;
- reg [7:0] ovl_reg_rx_tick_count; // For measuring width of RX state
- wire [7:0] ovl_nxt_rx_tick_count;
- reg [3:0] ovl_reg_last_tx_state; // last state
- reg [3:0] ovl_reg_last_rx_state;
- reg [6:0] ovl_last_reg_ctrl;
-
- // Clear test mode indicator each time state is changed, set to 1 if high speed test mode is
- // enabled
- assign ovl_nxt_hs_test_mode_triggered =
- (tx_state!=ovl_reg_last_tx_state) ? reg_ctrl[6]: (reg_ctrl[6] | ovl_reg_hs_test_mode_triggered);
-
- // Counter clear at each state change, increasement at each reg_baud_tick
- assign ovl_nxt_tx_tick_count = (tx_state!=ovl_reg_last_tx_state) ? (8'h00) :
- (ovl_reg_tx_tick_count + {{7{1'b0}}, reg_baud_tick});
-
- // Counter clear at each state change, increasement at each reg_baud_tick
- assign ovl_nxt_rx_tick_count = (rx_state!=ovl_reg_last_rx_state) ? (8'h00) :
- (ovl_reg_rx_tick_count + {{7{1'b0}}, reg_baud_tick});
-
- always@(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- begin
- ovl_reg_hs_test_mode_triggered <= 1'b0;
- ovl_reg_last_tx_state <= 4'h0;
- ovl_reg_last_rx_state <= 4'h0;
- ovl_reg_tx_tick_count <= 8'h00;
- ovl_reg_rx_tick_count <= 8'h00;
- ovl_last_reg_ctrl <= 7'h00;
- end
- else
- begin
- ovl_reg_hs_test_mode_triggered <= ovl_nxt_hs_test_mode_triggered;
- ovl_reg_last_tx_state <= tx_state;
- ovl_reg_last_rx_state <= rx_state;
- ovl_reg_tx_tick_count <= ovl_nxt_tx_tick_count;
- ovl_reg_rx_tick_count <= ovl_nxt_rx_tick_count;
- ovl_last_reg_ctrl <= reg_ctrl;
- end
- end
-
- // Signals for checking clearing of interrupts
- reg ovl_last_txint;
- reg ovl_last_rxint;
- reg ovl_last_psel;
- reg ovl_last_penable;
- reg ovl_last_pwrite;
- reg [31:0] ovl_last_pwdata;
- reg [11:2] ovl_last_paddr;
- reg ovl_last_rx_buf_full;
- reg ovl_last_tx_shift_buf_0;
-
-
- always@(posedge PCLK or negedge PRESETn)
- begin
- if (~PRESETn)
- begin
- ovl_last_txint <= 1'b0;
- ovl_last_rxint <= 1'b0;
- ovl_last_psel <= 1'b0;
- ovl_last_penable <= 1'b0;
- ovl_last_pwrite <= 1'b0;
- ovl_last_paddr <= {10{1'b0}};
- ovl_last_pwdata <= {32{1'b0}};
- ovl_last_rx_buf_full <= 1'b0;
- ovl_last_tx_shift_buf_0 <= 1'b0;
- end
- else
- begin
- ovl_last_txint <= TXINT;
- ovl_last_rxint <= RXINT;
- ovl_last_psel <= PSEL;
- ovl_last_penable <= PENABLE;
- ovl_last_pwrite <= PWRITE;
- ovl_last_paddr <= PADDR;
- ovl_last_pwdata <= PWDATA;
- ovl_last_rx_buf_full <= rx_buf_full;
- ovl_last_tx_shift_buf_0 <= tx_shift_buf[0];
- end
- end
-
- // Ensure rx_state must not be 11, 12, 13, 14, 15
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "rx_state in illegal state")
- u_ovl_rx_state_illegal
- (.clk(PCLK), .reset_n(PRESETn),
- .test_expr((rx_state==4'hB)|(rx_state==4'hC)|(rx_state==4'hD)|
- (rx_state==4'hE)|(rx_state==4'hF)));
-
- // Ensure tx_state must not be 12, 13, 14, 15
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "tx_state in illegal state")
- u_ovl_tx_state_illegal
- (.clk(PCLK), .reset_n(PRESETn),
- .test_expr((tx_state==4'hC)|(tx_state==4'hD)|
- (tx_state==4'hE)|(tx_state==4'hF)));
-
- // Ensure reg_baud_cntr_i change only if UART is enabled
- // or if write to baud rate divider
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Unexpected baud rate divider change")
- u_ovl_reg_baud_cntr_i_change
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(ovl_last_reg_baud_cntr_i!=reg_baud_cntr_i),
- .consequent_expr(ovl_last_baud_div_en | ovl_last_baud_updated )
- );
-
- // Ensure reg_baud_div[19:4] >= reg_baud_cntr_i unless reg_baud_div just been programmed
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Unexpected baud rate divided change")
- u_ovl_reg_baud_cntr_i_range
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(reg_baud_cntr_i>reg_baud_div[19:4]),
- .consequent_expr(baud_updated)
- );
-
- // Ensure reg_baud_cntr_f change only if UART is enabled
- // or if write to baud rate divider
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Unexpected baud rate divider change")
- u_ovl_reg_baud_cntr_f_change
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(ovl_last_reg_baud_cntr_f!=reg_baud_cntr_f),
- .consequent_expr(ovl_last_baud_div_en | ovl_last_baud_updated )
- );
-
- // Ensure tx_buf_full is set to 1 after write to TX buffer (PADDR[11:2]==0)
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "tx_buf_full should be asserted after write to TX buffer")
- u_ovl_tx_buf_full
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event (PSEL & (~PENABLE) & PWRITE & (PADDR[11:2] == 10'h000)),
- .test_expr (tx_buf_full)
- );
-
- // If last tx_state=0 (idle) or 1 (wait for tick), TXD = 1.
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXD should be 1 when idle or just before data transmission")
- u_ovl_txd_state_0_1
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event ((tx_state==4'd0)|(tx_state==4'd1)),
- .test_expr (TXD==1'b1)
- );
-
- // If last tx_state=2 (start bit), TXD = 0.
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXD should be 0 when output start bit")
- u_ovl_txd_state_2
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event (tx_state==4'd2),
- .test_expr (TXD==1'b0)
- );
-
- // If last tx_state=3-10 (D0 to D7), TXD = anything (tx_shift_buf[0]).
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXD should be same as first bit of shift register during transfer")
- u_ovl_txd_state_3_to_10
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event ((tx_state>4'd2) & (tx_state<4'd11)),
- .test_expr (TXD==ovl_last_tx_shift_buf_0)
- );
-
- // If last tx_state=11 (stop bit), TXD = 1.
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXD should be 1 when output stop bit")
- u_ovl_txd_state_11
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event (tx_state==4'd11),
- .test_expr (TXD==1'b1)
- );
-
- // Duration of tx_state in 2 to 11 must have 16 reg_baud_tick
- // (unless high speed test mode has been active)
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Duration of tx_state when in state 2 to state 11 should have 16 ticks")
- u_ovl_width_of_tx_state
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr((tx_state!=ovl_reg_last_tx_state) & // at state change
- (ovl_reg_last_tx_state>4'd1)&(ovl_reg_last_tx_state<4'd12) & // from state 2 to 11
- (ovl_reg_hs_test_mode_triggered==1'b0)), // high speed test mode not triggered
- .consequent_expr((ovl_reg_tx_tick_count==8'd15) | (ovl_reg_tx_tick_count==8'd16))
- // count from 0 to 15 (16 ticks)
- );
-
-
- // In high speed test mode, tx_state must change if it is in range of 2 to 11
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "Duration of tx_state should be 1 cycle if high speed test mode is enabled")
- u_ovl_width_of_tx_state_in_high_speed_test_mode
- (.clk(PCLK), .reset_n(PRESETn),
- .start_event((tx_state>4'd1)&(tx_state<4'd12) & reg_ctrl[6]),
- .test_expr (tx_state != ovl_reg_last_tx_state)
- );
-
- // Duration of rx_state in 1 must have 8 reg_baud_tick
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Duration of rx_state when state 1 should have 8 ticks")
- u_ovl_width_of_rx_state_1
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr((rx_state!=ovl_reg_last_rx_state) & // at state change
- (ovl_reg_last_rx_state==4'd1)), // last state was state 1
- .consequent_expr((ovl_reg_rx_tick_count==8'd7)|(ovl_reg_rx_tick_count==8'd8))
- // count from 0 to 7 (8 ticks)
- );
-
- // Duration of rx_state in 2 to 10 must have 16 reg_baud_tick
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "Duration of rx_state when in state 2 to state 10 should have 16 ticks")
- u_ovl_width_of_rx_state_data
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr((rx_state!=ovl_reg_last_rx_state) & // at state change
- (ovl_reg_last_rx_state>4'd1)&(ovl_reg_last_rx_state<4'd11)), // from state 2 to 9
- .consequent_expr((ovl_reg_rx_tick_count==8'd15)|(ovl_reg_rx_tick_count==8'd16))
- // count from 0 to 15 (16 ticks)
- );
-
- // UARTINT must be 0 if TXINT, RXINT, TXOVRINT and RXOVRINT are all 0
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "UARTINT must be 0 if TXINT, RXINT, TXOVRINT and RXOVRINT are all 0")
- u_ovl_uartint_mismatch
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr((TXINT | RXINT | TXOVRINT | RXOVRINT) == 1'b0), // No interrupt
- .consequent_expr(UARTINT==1'b0) // Combined interrupt = 0
- );
-
- // TXINT should be asserted when TX interrupt enabled and transmit buffer is available
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXINT should be triggered when enabled")
- u_ovl_txint_enable
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (reg_ctrl[0] & reg_ctrl[2] & tx_buf_full & tx_buf_clear),
- .test_expr (TXINT == 1'b1)
- );
-
- // There should be no rising edge of TXINT if transmit is disabled or transmit interrupt is disabled
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "TXINT should not be triggered when disabled")
- u_ovl_txint_disable
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (((reg_ctrl[0]==1'b0) | (reg_ctrl[2]==1'b0)) & (TXINT == 1'b0)),
- .test_expr (TXINT == 1'b0)
- );
-
- // if TXINT falling edge, there must has been a write to INTCLEAR register with bit[0]=1
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "When there is a falling edge of TXINT, there must has been a write to INTCLEAR")
- u_ovl_txint_clear
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(ovl_last_txint & (~TXINT)), // Falling edge of TXINT
- .consequent_expr(ovl_last_psel & ovl_last_pwrite &
- (ovl_last_paddr==10'h003) & (ovl_last_pwdata[0]) ) // There must has been a write to INTCLEAR
- );
-
- // RXINT should be asserted when RX interrupt enabled and a new data is received
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "RXINT should be triggered when enabled")
- u_ovl_rxint_enable
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (reg_ctrl[3] & (rx_state==9) & (nxt_rx_state==10)),
- .test_expr (RXINT == 1'b1)
- );
-
- // There should be no rising edge of RXINT if receive interrupt is disabled
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "RXINT should not be triggered when disabled")
- u_ovl_rxint_disable
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event ((reg_ctrl[3]==1'b0) & (RXINT == 1'b0)),
- .test_expr (RXINT == 1'b0)
- );
-
- // if RXINT falling edge, there must has been a write to INTCLEAR register with bit[1]=1
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
- u_ovl_rxint_clear
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(ovl_last_rxint & (~RXINT)), // Falling edge of TXINT
- .consequent_expr(ovl_last_psel & ovl_last_pwrite &
- (ovl_last_paddr==10'h003) & (ovl_last_pwdata[1]) ) // There must has been a write to INTCLEAR
- );
-
- // rx_buf_full should rise if rx_state change from 9 to 10
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "rx_buf_full should be asserted when a new character is received")
- u_ovl_rx_buf_full
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event ((rx_state==9) & (nxt_rx_state==10)),
- .test_expr (rx_buf_full == 1'b1)
- );
-
- // if rx_buf_full falling edge, there must has been a read to the receive buffer
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "When there is a falling edge of RXINT, there must has been a read to receive buffer")
- u_ovl_rx_buf_full_clear
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr((~rx_buf_full) & ovl_last_rx_buf_full), // Falling edge of rx_buf_full
- .consequent_expr(ovl_last_psel & (~ovl_last_pwrite) &
- (ovl_last_paddr==10'h000) ) // There must has been a read to rx data
- );
-
- // TXOVRINT must be 0 if reg_ctrl[4]=0
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
- u_ovl_txovrint_disable
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(~reg_ctrl[4]),
- .consequent_expr(~TXOVRINT)
- );
-
- // RXOVRINT must be 0 if reg_ctrl[5]=0
- assert_implication
- #(`OVL_ERROR,`OVL_ASSERT,
- "When there is a falling edge of RXINT, there must has been a write to INTCLEAR")
- u_ovl_rxovrint_disable
- (.clk(PCLK), .reset_n(PRESETn),
- .antecedent_expr(~reg_ctrl[5]),
- .consequent_expr(~RXOVRINT)
- );
-
- // if a write take place to TX data buffer and tx_buf_full was 1, reg_tx_overrun will be set
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "tx buffer overrun should be asserted when a new character is write to buffer and buffer is already full")
- u_ovl_tx_buffer_overrun
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (write_enable00 & tx_buf_full & (~tx_buf_clear)),
- .test_expr (reg_tx_overrun == 1'b1)
- );
-
- // if rx_buf_full is high and rx_state change from 9 to 10, reg_rx_overrun will be set
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "rx buffer overrun should be asserted when a new character is received and rx buffer is already full")
- u_ovl_rx_buffer_overrun
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (rx_buf_full & (~rx_data_read) & (rx_state==9) & (nxt_rx_state==10)),
- .test_expr (reg_rx_overrun == 1'b1)
- );
-
- // if write to INTCLEAR with bit[2]=1, reg_tx_overrun will be cleared,
- // Cannot have new overrun at the same time because the APB can only do onething at a time
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "tx buffer overrun should be clear when write to INTCLEAR")
- u_ovl_tx_buffer_overrun_clear_a
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (write_enable0c & (PWDATA[2])),
- .test_expr (reg_tx_overrun==1'b0)
- );
-
- // if write to STATUS with bit[2]=1, reg_tx_overrun will be cleared,
- // Cannot have new overrun at the same time because the APB can only do onething at a time
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "tx buffer overrun should be clear when write to INTCLEAR")
- u_ovl_tx_buffer_overrun_clear_b
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (write_enable04 & (PWDATA[2])),
- .test_expr (reg_tx_overrun==1'b0)
- );
-
- // if write to INTCLEAR with bit[3]=1, reg_rx_overrun will be cleared, unless a new overrun take place
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "rx buffer overrun should be clear when write to INTCLEAR, unless new overrun")
- u_ovl_rx_buffer_overrun_clear_a
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (write_enable0c & (PWDATA[3]) & (~(rx_buf_full & (rx_state==9) & (nxt_rx_state==10)))),
- .test_expr (reg_rx_overrun==1'b0)
- );
-
- // If rx buffer is not full, it cannot have new overrun
- assert_next
- #(`OVL_ERROR, 1,1,0, `OVL_ASSERT,
- "rx buffer overrun should be clear when write to INTCLEAR, unless new overrun")
- u_ovl_rx_buffer_overrun_when_empty
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event ((~rx_buf_full) & (reg_rx_overrun==1'b0)),
- .test_expr (reg_rx_overrun==1'b0)
- );
-
-
- // Reading of reg_baud_div (worth checking due to two stage read mux)
- assert_next
- #(`OVL_ERROR, 1, 1, 0, `OVL_ASSERT,
- "Reading of baud rate divider value")
- u_ovl_read_baud_rate_divide_cfg
- (.clk(PCLK ), .reset_n (PRESETn),
- .start_event (PSEL & (~PENABLE) & (~PWRITE) & (PADDR[11:2]==10'h004)),
- .test_expr (PRDATA=={{12{1'b0}}, reg_baud_div})
- );
-
- // Recommended Baud Rate divider value is at least 16
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "UART enabled with baud rate less than 16")
- u_ovl_baud_rate_divider_illegal
- (.clk(PCLK), .reset_n(PRESETn),
- .test_expr(((reg_ctrl[0]) & (reg_ctrl[6]==1'b0) & (reg_baud_div[19:4]=={16{1'b0}}) ) |
- ((reg_ctrl[1]) & (reg_baud_div[19:4]=={16{1'b0}}) ) )
- );
-
- // Test mode never changes from hi-speed to normal speed unless TX is idle
- assert_never
- #(`OVL_ERROR,`OVL_ASSERT,
- "High speed test mode has been changed when TX was not idle")
- u_ovl_change_speed_tx_illegal
- (.clk(PCLK), .reset_n(PRESETn),
- .test_expr((tx_state != 4'd00) & (reg_ctrl[6] != ovl_last_reg_ctrl[6]))
- );
-
-`endif
-
-endmodule
diff --git a/system/test_io/verilog/axi_stream_io_v1_0.v b/system/test_io/verilog/axi_stream_io_v1_0.v
deleted file mode 100755
index 0c52be8420c4f63ab7eab0db84cc185a5073bcc6..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/axi_stream_io_v1_0.v
+++ /dev/null
@@ -1,114 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module axi_stream_io_v1_0 #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
-
- // Parameters of Axi Slave Bus Interface axi
- parameter integer C_axi_DATA_WIDTH = 32,
- parameter integer C_axi_ADDR_WIDTH = 4,
-
- // Parameters of Axi Master Bus Interface tx
- parameter integer C_tx_TDATA_WIDTH = 8,
- parameter integer C_tx_START_COUNT = 3,
-
- // Parameters of Axi Slave Bus Interface rx
- parameter integer C_rx_TDATA_WIDTH = 8
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
-
- // Ports of Axi Slave Bus Interface axi
- input wire axi_aclk,
- input wire axi_aresetn,
- input wire [C_axi_ADDR_WIDTH-1 : 0] axi_awaddr,
- input wire [2 : 0] axi_awprot,
- input wire axi_awvalid,
- output wire axi_awready,
- input wire [C_axi_DATA_WIDTH-1 : 0] axi_wdata,
- input wire [(C_axi_DATA_WIDTH/8)-1 : 0] axi_wstrb,
- input wire axi_wvalid,
- output wire axi_wready,
- output wire [1 : 0] axi_bresp,
- output wire axi_bvalid,
- input wire axi_bready,
- input wire [C_axi_ADDR_WIDTH-1 : 0] axi_araddr,
- input wire [2 : 0] axi_arprot,
- input wire axi_arvalid,
- output wire axi_arready,
- output wire [C_axi_DATA_WIDTH-1 : 0] axi_rdata,
- output wire [1 : 0] axi_rresp,
- output wire axi_rvalid,
- input wire axi_rready,
-
- output wire interrupt,
- // Ports of Axi Master Bus Interface tx
- output wire tx_tvalid,
- output wire [C_tx_TDATA_WIDTH-1 : 0] tx_tdata,
- output wire [(C_tx_TDATA_WIDTH/8)-1 : 0] tx_tstrb,
- output wire tx_tlast,
- input wire tx_tready,
-
- // Ports of Axi Slave Bus Interface rx
- output wire rx_tready,
- input wire [C_rx_TDATA_WIDTH-1 : 0] rx_tdata,
- input wire [(C_rx_TDATA_WIDTH/8)-1 : 0] rx_tstrb,
- input wire rx_tlast,
- input wire rx_tvalid
- );
-// Instantiation of Axi Bus Interface axi
- iostream_v1_0_axi # (
- .C_S_AXI_DATA_WIDTH(C_axi_DATA_WIDTH),
- .C_S_AXI_ADDR_WIDTH(C_axi_ADDR_WIDTH)
- ) iostream_v1_0_axi_inst (
- .S_AXI_ACLK(axi_aclk),
- .S_AXI_ARESETN(axi_aresetn),
- .tx_tvalid(tx_tvalid),
- .tx_tdata(tx_tdata),
-// output wire [0 : 0] tx_tstrb,
-// output wire tx_tlast,
- .tx_tready(tx_tready),
- .rx_tvalid(rx_tvalid),
- .rx_tdata(rx_tdata),
-// input wire [0 : 0] tx_tstrb,
-// input wire tx_tlast,
- .tx_tready(rx_tready),
- .interrupt(interrupt),
- .S_AXI_AWADDR(axi_awaddr),
- .S_AXI_AWPROT(axi_awprot),
- .S_AXI_AWVALID(axi_awvalid),
- .S_AXI_AWREADY(axi_awready),
- .S_AXI_WDATA(axi_wdata),
- .S_AXI_WSTRB(axi_wstrb),
- .S_AXI_WVALID(axi_wvalid),
- .S_AXI_WREADY(axi_wready),
- .S_AXI_BRESP(axi_bresp),
- .S_AXI_BVALID(axi_bvalid),
- .S_AXI_BREADY(axi_bready),
- .S_AXI_ARADDR(axi_araddr),
- .S_AXI_ARPROT(axi_arprot),
- .S_AXI_ARVALID(axi_arvalid),
- .S_AXI_ARREADY(axi_arready),
- .S_AXI_RDATA(axi_rdata),
- .S_AXI_RRESP(axi_rresp),
- .S_AXI_RVALID(axi_rvalid),
- .S_AXI_RREADY(axi_rready)
- );
-
-assign tx_tstrb[0:0] = tx_tvalid;
-assign tx_tlast = 1'b0;
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v b/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
deleted file mode 100755
index 303780efefce184c1f353751c71280794b5348bd..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/axi_stream_io_v1_0_axi_s.v
+++ /dev/null
@@ -1,424 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module axi_stream_io_v1_0_axi_s #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- // Width of S_AXI data bus
- parameter integer C_S_AXI_DATA_WIDTH = 32,
- // Width of S_AXI address bus
- parameter integer C_S_AXI_ADDR_WIDTH = 4
- )
- (
- // Users to add ports here
- output wire interrupt,
-
- // Ports of Axi Master Bus Interface tx
-// input wire tx_aclk,
-// input wire tx_aresetn,
- output wire tx_tvalid,
- output wire [7 : 0] tx_tdata,
-// output wire [0 : 0] tx_tstrb,
-// output wire tx_tlast,
- input wire tx_tready,
-
- // Ports of Axi Slave Bus Interface rx
-// input wire rx_aclk,
-// input wire rx_aresetn,
- output wire rx_tready,
- input wire [7 : 0] rx_tdata,
-// input wire [0 : 0] rx_tstrb,
-// input wire rx_tlast,
- input wire rx_tvalid,
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // Global Clock Signal
- input wire S_AXI_ACLK,
- // Global Reset Signal. This Signal is Active LOW
- input wire S_AXI_ARESETN,
- // Write address (issued by master, acceped by Slave)
- input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
- // Write channel Protection type. This signal indicates the
- // privilege and security level of the transaction, and whether
- // the transaction is a data access or an instruction access.
- input wire [2 : 0] S_AXI_AWPROT,
- // Write address valid. This signal indicates that the master signaling
- // valid write address and control information.
- input wire S_AXI_AWVALID,
- // Write address ready. This signal indicates that the slave is ready
- // to accept an address and associated control signals.
- output wire S_AXI_AWREADY,
- // Write data (issued by master, acceped by Slave)
- input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
- // Write strobes. This signal indicates which byte lanes hold
- // valid data. There is one write strobe bit for each eight
- // bits of the write data bus.
- input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
- // Write valid. This signal indicates that valid write
- // data and strobes are available.
- input wire S_AXI_WVALID,
- // Write ready. This signal indicates that the slave
- // can accept the write data.
- output wire S_AXI_WREADY,
- // Write response. This signal indicates the status
- // of the write transaction.
- output wire [1 : 0] S_AXI_BRESP,
- // Write response valid. This signal indicates that the channel
- // is signaling a valid write response.
- output wire S_AXI_BVALID,
- // Response ready. This signal indicates that the master
- // can accept a write response.
- input wire S_AXI_BREADY,
- // Read address (issued by master, acceped by Slave)
- input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
- // Protection type. This signal indicates the privilege
- // and security level of the transaction, and whether the
- // transaction is a data access or an instruction access.
- input wire [2 : 0] S_AXI_ARPROT,
- // Read address valid. This signal indicates that the channel
- // is signaling valid read address and control information.
- input wire S_AXI_ARVALID,
- // Read address ready. This signal indicates that the slave is
- // ready to accept an address and associated control signals.
- output wire S_AXI_ARREADY,
- // Read data (issued by slave)
- output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
- // Read response. This signal indicates the status of the
- // read transfer.
- output wire [1 : 0] S_AXI_RRESP,
- // Read valid. This signal indicates that the channel is
- // signaling the required read data.
- output wire S_AXI_RVALID,
- // Read ready. This signal indicates that the master can
- // accept the read data and response information.
- input wire S_AXI_RREADY
- );
-
- // AXI4LITE signals
- reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
- reg axi_awready;
- reg axi_wready;
- reg [1 : 0] axi_bresp;
- reg axi_bvalid;
- reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
- reg axi_arready;
- reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
- reg [1 : 0] axi_rresp;
- reg axi_rvalid;
-
- // Example-specific design signals
- // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
- // ADDR_LSB is used for addressing 32/64 bit registers/memories
- // ADDR_LSB = 2 for 32 bits (n downto 2)
- // ADDR_LSB = 3 for 64 bits (n downto 3)
- localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
- localparam integer OPT_MEM_ADDR_BITS = 1;
-
- //----------------------------------------------
- //-- Signals for user logic register space example
- //------------------------------------------------
- //-- Number of Slave Registers 4
- reg [8:0] tx_reg; // TX data
- reg [8:0] rx_reg; // RX data
- reg [7:0] ctrl_reg; // ctrl
- wire slv_reg_rden;
- wire slv_reg_wren;
- reg [7:0] reg_data_out;
- integer byte_index;
- reg aw_en;
-
- wire tx_req = tx_reg[8]; // request to transmit
- wire tx_ack = tx_tready; // acknowledge when stream ready
- wire tx_rdy = !tx_reg[8];
- wire rx_req = rx_tvalid; // request to receive
- wire rx_ack = !rx_reg[8];
- wire rx_rdy = rx_reg[8];
-
- //assign rx_reg[7:0] <= rx_tdata;
-
- // I/O Connections assignments
-
- assign interrupt = ctrl_reg[4] & (!tx_req | rx_req);
-
- // TX stream interface
- assign tx_tdata = tx_reg[7:0];
- assign tx_tvalid = tx_req;
-
- // RX stream interface
- assign rx_tready = rx_ack;
-
- //AXI Slave
- assign S_AXI_AWREADY = axi_awready;
- assign S_AXI_WREADY = axi_wready;
- assign S_AXI_BRESP = axi_bresp;
- assign S_AXI_BVALID = axi_bvalid;
- assign S_AXI_ARREADY = axi_arready;
- assign S_AXI_RDATA = axi_rdata;
- assign S_AXI_RRESP = axi_rresp;
- assign S_AXI_RVALID = axi_rvalid;
- // Implement axi_awready generation
- // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
- // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
- // de-asserted when reset is low.
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_awready <= 1'b0;
- aw_en <= 1'b1;
- end
- else
- begin
- if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
- begin
- // slave is ready to accept write address when
- // there is a valid write address and write data
- // on the write address and data bus. This design
- // expects no outstanding transactions.
- axi_awready <= 1'b1;
- aw_en <= 1'b0;
- end
- else if (S_AXI_BREADY && axi_bvalid)
- begin
- aw_en <= 1'b1;
- axi_awready <= 1'b0;
- end
- else
- begin
- axi_awready <= 1'b0;
- end
- end
- end
-
- // Implement axi_awaddr latching
- // This process is used to latch the address when both
- // S_AXI_AWVALID and S_AXI_WVALID are valid.
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_awaddr <= 0;
- end
- else
- begin
- if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
- begin
- // Write Address latching
- axi_awaddr <= S_AXI_AWADDR;
- end
- end
- end
-
- // Implement axi_wready generation
- // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
- // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
- // de-asserted when reset is low.
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_wready <= 1'b0;
- end
- else
- begin
- if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
- begin
- // slave is ready to accept write data when
- // there is a valid write address and write data
- // on the write address and data bus. This design
- // expects no outstanding transactions.
- axi_wready <= 1'b1;
- end
- else
- begin
- axi_wready <= 1'b0;
- end
- end
- end
-
- // Implement memory mapped register select and write logic generation
- // The write data is accepted and written to memory mapped registers when
- // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
- // select byte enables of slave registers while writing.
- // These registers are cleared when reset (active low) is applied.
- // Slave register write enable is asserted when valid address and data are available
- // and the slave is ready to accept the write address and write data.
- assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- rx_reg <= 0;
- else if ((ctrl_reg[1] == 1'b1))
- rx_reg <= 0;
- else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
- rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
- else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0))
- rx_reg[8] <= 1'b0;
- else if (rx_req & rx_ack) // check precedence (rx_req)
- rx_reg[8:0] <= {1'b1, rx_tdata[7:0]};
- end
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- tx_reg <= 0;
- else if ((ctrl_reg[0] == 1'b1))
- tx_reg <= 0;
- else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1))
- tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
- else if (tx_req & tx_ack)
- tx_reg[8] <= 1'b0;
- end
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- ctrl_reg <= 8'b00000100;
- else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3))
- ctrl_reg[7:0] <= S_AXI_WDATA[7:0];
- end
-
- // Implement write response logic generation
- // The write response and response valid signals are asserted by the slave
- // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
- // This marks the acceptance of address and indicates the status of
- // write transaction.
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_bvalid <= 0;
- axi_bresp <= 2'b0;
- end
- else
- begin
- if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
- begin
- // indicates a valid write response is available
- axi_bvalid <= 1'b1;
- axi_bresp <= 2'b0; // 'OKAY' response
- end // work error responses in future
- else
- begin
- if (S_AXI_BREADY && axi_bvalid)
- //check if bready is asserted while bvalid is high)
- //(there is a possibility that bready is always asserted high)
- begin
- axi_bvalid <= 1'b0;
- end
- end
- end
- end
-
- // Implement axi_arready generation
- // axi_arready is asserted for one S_AXI_ACLK clock cycle when
- // S_AXI_ARVALID is asserted. axi_awready is
- // de-asserted when reset (active low) is asserted.
- // The read address is also latched when S_AXI_ARVALID is
- // asserted. axi_araddr is reset to zero on reset assertion.
-
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_arready <= 1'b0;
- axi_araddr <= 32'b0;
- end
- else
- begin
- if (~axi_arready && S_AXI_ARVALID)
- begin
- // indicates that the slave has acceped the valid read address
- axi_arready <= 1'b1;
- // Read address latching
- axi_araddr <= S_AXI_ARADDR;
- end
- else
- begin
- axi_arready <= 1'b0;
- end
- end
- end
-
- // Implement axi_arvalid generation
- // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
- // S_AXI_ARVALID and axi_arready are asserted. The slave registers
- // data are available on the axi_rdata bus at this instance. The
- // assertion of axi_rvalid marks the validity of read data on the
- // bus and axi_rresp indicates the status of read transaction.axi_rvalid
- // is deasserted on reset (active low). axi_rresp and axi_rdata are
- // cleared to zero on reset (active low).
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_rvalid <= 0;
- axi_rresp <= 0;
- end
- else
- begin
- if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
- begin
- // Valid read data is available at the read data bus
- axi_rvalid <= 1'b1;
- axi_rresp <= 2'b0; // 'OKAY' response
- end
- else if (axi_rvalid && S_AXI_RREADY)
- begin
- // Read data is accepted by the master
- axi_rvalid <= 1'b0;
- end
- end
- end
-
- // Implement memory mapped register select and read logic generation
- // Slave register read enable is asserted when valid address is available
- // and the slave is ready to accept the read address.
- assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
- always @(*)
- begin
- // Address decoding for reading registers
- case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
- 2'h0 : reg_data_out <= rx_reg[7:0];
- 2'h1 : reg_data_out <= tx_reg[7:0];
- 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_rdy, tx_rdy, rx_rdy, rx_rdy};
- 2'h3 : reg_data_out <= ctrl_reg;
- default : reg_data_out <= 0;
- endcase
- end
-
- // Output register or memory read data
- always @( posedge S_AXI_ACLK )
- begin
- if ( S_AXI_ARESETN == 1'b0 )
- begin
- axi_rdata <= 0;
- end
- else
- begin
- // When there is a valid read address (S_AXI_ARVALID) with
- // acceptance of read address by the slave (axi_arready),
- // output the read dada
- if (slv_reg_rden)
- begin
- axi_rdata <= {24'h000000, reg_data_out}; // register read data
- end
- end
- end
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/system/test_io/verilog/nanosoc_adp_control_v1_0.v b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
deleted file mode 100755
index 81a3da2304f66717dcaf31307999ebde7bdda120..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/nanosoc_adp_control_v1_0.v
+++ /dev/null
@@ -1,103 +0,0 @@
-//-----------------------------------------------------------------------------
-// top-level soclabs ASCII Debug Protocol controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021-2, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-
- module nanosoc_adp_control_v1_0 #
- (
- // Users to add parameters here
- parameter PROMPT_CHAR = "]"
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // Ports of Axi Slave Bus Interface com_rx
- input wire ahb_hclk,
- input wire ahb_hresetn,
-
- output wire com_rx_tready,
- input wire [7 : 0] com_rx_tdata,
- input wire com_rx_tvalid,
-
- // Ports of Axi Master Bus Interface com_tx
- output wire com_tx_tvalid,
- output wire [7 : 0] com_tx_tdata,
- input wire com_tx_tready,
-
- // Ports of Axi Slave Bus Interface stdio_rx
- output wire stdio_rx_tready,
- input wire [7 : 0] stdio_rx_tdata,
- input wire stdio_rx_tvalid,
-
- // Ports of Axi Master Bus Interface stdio_tx
- output wire stdio_tx_tvalid,
- output wire [7 : 0] stdio_tx_tdata,
- input wire stdio_tx_tready,
-
- output wire [7 : 0] gpo8,
- input wire [7 : 0] gpi8,
-
- output wire [31:0] ahb_haddr ,
- output wire [ 2:0] ahb_hburst ,
- output wire ahb_hmastlock,
- output wire [ 3:0] ahb_hprot ,
- output wire [ 2:0] ahb_hsize ,
- output wire [ 1:0] ahb_htrans ,
- output wire [31:0] ahb_hwdata ,
- output wire ahb_hwrite ,
- input wire [31:0] ahb_hrdata ,
- input wire ahb_hready ,
- input wire ahb_hresp
- );
-
- // Add user logic here
-
-nanosoc_adp_manager
- #(.PROMPT_CHAR (PROMPT_CHAR))
- u_adp_manager(
- .HCLK (ahb_hclk ),
- .HRESETn (ahb_hresetn ),
- .HADDR32_o (ahb_haddr ),
- .HBURST3_o (ahb_hburst ),
- .HMASTLOCK_o (ahb_hmastlock ),
- .HPROT4_o (ahb_hprot ),
- .HSIZE3_o (ahb_hsize ),
- .HTRANS2_o (ahb_htrans ),
- .HWDATA32_o (ahb_hwdata ),
- .HWRITE_o (ahb_hwrite ),
- .HRDATA32_i (ahb_hrdata ),
- .HREADY_i (ahb_hready ),
- .HRESP_i (ahb_hresp ),
- .GPO8_o (gpo8 ),
- .GPI8_i (gpi8 ),
- .COMRX_TREADY_o(com_rx_tready),
- .COMRX_TDATA_i(com_rx_tdata),
- .COMRX_TVALID_i(com_rx_tvalid),
- .STDRX_TREADY_o(stdio_rx_tready),
- .STDRX_TDATA_i(stdio_rx_tdata),
- .STDRX_TVALID_i(stdio_rx_tvalid),
- .COMTX_TVALID_o(com_tx_tvalid),
- .COMTX_TDATA_o(com_tx_tdata),
- .COMTX_TREADY_i(com_tx_tready),
- .STDTX_TVALID_o(stdio_tx_tvalid),
- .STDTX_TDATA_o(stdio_tx_tdata),
- .STDTX_TREADY_i(stdio_tx_tready)
-
- );
-
-
-endmodule
diff --git a/system/test_io/verilog/nanosoc_adp_manager.v b/system/test_io/verilog/nanosoc_adp_manager.v
deleted file mode 100755
index cf6c0d850b0f50781599a489030b5b37761179e1..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/nanosoc_adp_manager.v
+++ /dev/null
@@ -1,778 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoCLabs ASCII Debug Protocol controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-
-//`define ADPBASIC 1
-
-`define ADPFSMDESIGN 1
-
-module nanosoc_adp_manager // AHB initiator interface
- #(parameter PROMPT_CHAR = "]"
- )
- ( input wire HCLK,
- input wire HRESETn,
- output wire [31:0] HADDR32_o,
- output wire [ 2:0] HBURST3_o,
- output wire HMASTLOCK_o,
- output wire [ 3:0] HPROT4_o,
- output wire [ 2:0] HSIZE3_o,
- output wire [ 1:0] HTRANS2_o,
- output wire [31:0] HWDATA32_o,
- output wire HWRITE_o,
- input wire [31:0] HRDATA32_i,
- input wire HREADY_i,
- input wire HRESP_i,
-// COMIO interface
- output wire [ 7:0] GPO8_o,
- input wire [ 7:0] GPI8_i,
- input wire [ 7:0] COMRX_TDATA_i,
- input wire COMRX_TVALID_i,
- output wire COMRX_TREADY_o,
- output wire [ 7:0] COMTX_TDATA_o,
- output wire COMTX_TVALID_o,
- input wire COMTX_TREADY_i,
-// STDIO interface
- input wire [ 7:0] STDRX_TDATA_i,
- input wire STDRX_TVALID_i,
- output wire STDRX_TREADY_o,
- output wire [ 7:0] STDTX_TDATA_o,
- output wire STDTX_TVALID_o,
- input wire STDTX_TREADY_i
-);
-
-wire COM_RXE_i = !COMRX_TVALID_i;
-wire COM_TXF_i = !COMTX_TREADY_i;
-
-//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o;
-//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o;
-
-
-wire STD_TXF_i = !STDTX_TREADY_i;
-wire STD_RXE_i = !STDRX_TVALID_i;
-
-`ifdef ADPBASIC
- localparam BANNERHEX = 32'h50c1ab01;
-`else
- localparam BANNERHEX = 32'h50c1ab04;
-`endif
-
-localparam CMD_bad = 4'b0000;
-localparam CMD_A = 4'b0001; // set Address
-localparam CMD_C = 4'b0010; // Control
-localparam CMD_R = 4'b0011; // Read word, addr++
-localparam CMD_S = 4'b0100; // Status/STDIN
-localparam CMD_W = 4'b0101; // Write word, addr++
-localparam CMD_X = 4'b0110; // eXit
-`ifndef ADPBASIC
-localparam CMD_F = 4'b1000; // Fill (wordocunt) from addr++
-localparam CMD_M = 4'b1001; // set read Mask
-localparam CMD_P = 4'b1010; // Poll hardware (count)
-localparam CMD_U = 4'b1011; // (Binary) Upload (wordocunt) from addr++
-localparam CMD_V = 4'b1100; // match Value
-`endif
-
-
-function FNvalid_adp_entry; // Escape char
-input [7:0] char8;
- FNvalid_adp_entry = (char8[7:0] == 8'h1b);
-endfunction
-
-function [3:0] FNvalid_cmd;
-input [7:0] char8;
-case (char8[7:0])
-"A": FNvalid_cmd = CMD_A;
-"a": FNvalid_cmd = CMD_A;
-"C": FNvalid_cmd = CMD_C;
-"c": FNvalid_cmd = CMD_C;
-"R": FNvalid_cmd = CMD_R;
-"r": FNvalid_cmd = CMD_R;
-"S": FNvalid_cmd = CMD_S;
-"s": FNvalid_cmd = CMD_S;
-"W": FNvalid_cmd = CMD_W;
-"w": FNvalid_cmd = CMD_W;
-"X": FNvalid_cmd = CMD_X;
-"x": FNvalid_cmd = CMD_X;
-`ifndef ADPBASIC
-"F": FNvalid_cmd = CMD_F;
-"f": FNvalid_cmd = CMD_F;
-"M": FNvalid_cmd = CMD_M;
-"m": FNvalid_cmd = CMD_M;
-"P": FNvalid_cmd = CMD_P;
-"p": FNvalid_cmd = CMD_P;
-"U": FNvalid_cmd = CMD_U;
-"u": FNvalid_cmd = CMD_U;
-"V": FNvalid_cmd = CMD_V;
-"v": FNvalid_cmd = CMD_V;
-`endif
-default:
- FNvalid_cmd = 0;
-endcase
-endfunction
-
-function FNvalid_space; // space or tab char
-input [7:0] char8;
- FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09));
-endfunction
-
-function FNnull; // space or tab char
-input [7:0] char8;
- FNnull = (char8[7:0] == 8'h00);
-endfunction
-
-function FNexit; // EOF
-input [7:0] char8;
- FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00));
-endfunction
-
-function FNvalid_EOL; // CR or LF
-input [7:0] char8;
- FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d));
-endfunction
-
-function FNuppercase;
-input [7:0] char8;
- FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8);
-endfunction
-
-
-function [2:0] FNsize_inc;
-// top 2 bits encode 01 (byte), 10 (halfword), 11 (word) 00 - no parameter
-input [2:0] cnt8;
-case (cnt8[2:0])
-3'b000: FNsize_inc = 3'b010;
-3'b010: FNsize_inc = 3'b011;
-3'b011: FNsize_inc = 3'b100;
-3'b100: FNsize_inc = 3'b101;
-default:
- FNsize_inc = 3'b111;
-endcase
-endfunction
-
-function [1:0] FNparam2size;
-// top 2 bits encode 01 (byte), 10 (halfword), 11 (word) 00 - no parameter
-input [1:0] parm2;
-case (parm2[1:0])
-2'b01: FNparam2size = 2'b00; // 8-bit
-2'b10: FNparam2size = 2'b01; // 16-bit
-2'b11: FNparam2size = 2'b10; // 32-bit
-default:
- FNparam2size = 2'b10;// default to 32-bit
-endcase
-endfunction
-
-function [34:0] FNBuild_size3_param32_hexdigit;
-input [34:0] param32;
-input [7:0] char8;
-case (char8[7:0])
-"\t":FNBuild_size3_param32_hexdigit = 35'b0; // tab starts new (zeroed) param32
-" ": FNBuild_size3_param32_hexdigit = 35'b0; // space starts new (zeroed) param32
-"x": FNBuild_size3_param32_hexdigit = 35'b0; // hex prefix starts new (zeroed) param32
-"X": FNBuild_size3_param32_hexdigit = 35'b0; // hex prefix starts new (zeroed) param32
-"0": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0000};
-"1": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0001};
-"2": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0010};
-"3": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0011};
-"4": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0100};
-"5": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0101};
-"6": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0110};
-"7": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b0111};
-"8": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1000};
-"9": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1001};
-"A": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1010};
-"B": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1011};
-"C": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1100};
-"D": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1101};
-"E": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1110};
-"F": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1111};
-"a": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1010};
-"b": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1011};
-"c": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1100};
-"d": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1101};
-"e": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1110};
-"f": FNBuild_size3_param32_hexdigit = {FNsize_inc(param32[34:32]),param32[27:0],4'b1111};
-default: FNBuild_size3_param32_hexdigit = param32; // EOL etc returns param32 unchanged
-endcase
-endfunction
-
-
-function [7:0] FNmap_hex_digit;
-input [3:0] nibble;
-case (nibble[3:0])
-4'b0000: FNmap_hex_digit = "0";
-4'b0001: FNmap_hex_digit = "1";
-4'b0010: FNmap_hex_digit = "2";
-4'b0011: FNmap_hex_digit = "3";
-4'b0100: FNmap_hex_digit = "4";
-4'b0101: FNmap_hex_digit = "5";
-4'b0110: FNmap_hex_digit = "6";
-4'b0111: FNmap_hex_digit = "7";
-4'b1000: FNmap_hex_digit = "8";
-4'b1001: FNmap_hex_digit = "9";
-4'b1010: FNmap_hex_digit = "a";
-4'b1011: FNmap_hex_digit = "b";
-4'b1100: FNmap_hex_digit = "c";
-4'b1101: FNmap_hex_digit = "d";
-4'b1110: FNmap_hex_digit = "e";
-4'b1111: FNmap_hex_digit = "f";
-default: FNmap_hex_digit = "0";
-endcase
-endfunction
-
-// as per Vivado synthesis mapping
-`ifdef ADPFSMDESIGN
-localparam ADP_WRITEHEX = 6'b000000 ;
-localparam ADP_WRITEHEXS = 6'b000001 ;
-localparam ADP_WRITEHEX9 = 6'b000010 ;
-localparam ADP_WRITEHEX8 = 6'b000011 ;
-localparam ADP_WRITEHEX7 = 6'b000100 ;
-localparam ADP_WRITEHEX6 = 6'b000101 ;
-localparam ADP_WRITEHEX5 = 6'b000110 ;
-localparam ADP_WRITEHEX4 = 6'b000111 ;
-localparam ADP_WRITEHEX3 = 6'b001000 ;
-localparam ADP_WRITEHEX2 = 6'b001001 ;
-localparam ADP_WRITEHEX1 = 6'b001010 ;
-localparam ADP_WRITEHEX0 = 6'b001011 ;
-localparam ADP_LINEACK = 6'b001100 ;
-localparam ADP_LINEACK2 = 6'b001101 ;
-localparam ADP_PROMPT = 6'b001110 ;
-localparam ADP_IOCHK = 6'b001111 ;
-localparam ADP_STDOUT = 6'b010000 ;
-localparam ADP_STDOUT1 = 6'b010001 ;
-localparam ADP_STDOUT2 = 6'b010010 ;
-localparam ADP_STDOUT3 = 6'b010011 ;
-localparam ADP_RXCMD = 6'b010100 ;
-localparam ADP_RXPARAM = 6'b010101 ;
-localparam ADP_ACTION = 6'b010110 ;
-localparam ADP_SYSCTL = 6'b010111 ;
-localparam ADP_READ = 6'b011000 ;
-localparam ADP_SYSCHK = 6'b011001 ;
-localparam ADP_STDIN = 6'b011010 ;
-localparam ADP_WRITE = 6'b011011 ;
-localparam ADP_EXIT = 6'b011100 ;
-localparam STD_IOCHK = 6'b011101 ;
-localparam STD_RXD1 = 6'b011110 ;
-localparam STD_RXD2 = 6'b011111 ;
-localparam STD_TXD1 = 6'b100000 ;
-localparam STD_TXD2 = 6'b100001 ;
-localparam ADP_UCTRL = 6'b100010 ;
-localparam ADP_UREADB = 6'b100011 ;
-localparam ADP_UWRITE = 6'b100100 ;
-localparam ADP_POLL = 6'b100101 ;
-localparam ADP_POLL1 = 6'b100110 ;
-localparam ADP_POLL2 = 6'b100111 ;
-localparam ADP_FCTRL = 6'b101000 ;
-localparam ADP_FWRITE = 6'b101001 ;
-localparam ADP_ECHOCMD = 6'b101010 ;
-localparam ADP_ECHOBUS = 6'b101011 ;
-localparam ADP_UNKNOWN = 6'b101100 ;
-reg [5:0] adp_state ;
-`else
-// one-hot encoded explicitly
-localparam ADP_WRITEHEX = 45'b000000000000000000000000000000000000000000001 ; // = 6'b000000 ;
-localparam ADP_WRITEHEXS = 45'b000000000000000000000000000000000000000000010 ; // = 6'b000001 ;
-localparam ADP_WRITEHEX9 = 45'b000000000000000000000000000000000000000000100 ; // = 6'b000010 ;
-localparam ADP_WRITEHEX8 = 45'b000000000000000000000000000000000000000001000 ; // = 6'b000011 ;
-localparam ADP_WRITEHEX7 = 45'b000000000000000000000000000000000000000010000 ; // = 6'b000100 ;
-localparam ADP_WRITEHEX6 = 45'b000000000000000000000000000000000000000100000 ; // = 6'b000101 ;
-localparam ADP_WRITEHEX5 = 45'b000000000000000000000000000000000000001000000 ; // = 6'b000110 ;
-localparam ADP_WRITEHEX4 = 45'b000000000000000000000000000000000000010000000 ; // = 6'b000111 ;
-localparam ADP_WRITEHEX3 = 45'b000000000000000000000000000000000000100000000 ; // = 6'b001000 ;
-localparam ADP_WRITEHEX2 = 45'b000000000000000000000000000000000001000000000 ; // = 6'b001001 ;
-localparam ADP_WRITEHEX1 = 45'b000000000000000000000000000000000010000000000 ; // = 6'b001010 ;
-localparam ADP_WRITEHEX0 = 45'b000000000000000000000000000000000100000000000 ; // = 6'b001011 ;
-localparam ADP_LINEACK = 45'b000000000000000000000000000000001000000000000 ; // = 6'b001100 ;
-localparam ADP_LINEACK2 = 45'b000000000000000000000000000000010000000000000 ; // = 6'b001101 ;
-localparam ADP_PROMPT = 45'b000000000000000000000000000000100000000000000 ; // = 6'b001110 ;
-localparam ADP_IOCHK = 45'b000000000000000000000000000001000000000000000 ; // = 6'b001111 ;
-localparam ADP_STDOUT = 45'b000000000000000000000000000010000000000000000 ; // = 6'b010000 ;
-localparam ADP_STDOUT1 = 45'b000000000000000000000000000100000000000000000 ; // = 6'b010001 ;
-localparam ADP_STDOUT2 = 45'b000000000000000000000000001000000000000000000 ; // = 6'b010010 ;
-localparam ADP_STDOUT3 = 45'b000000000000000000000000010000000000000000000 ; // = 6'b010011 ;
-localparam ADP_RXCMD = 45'b000000000000000000000000100000000000000000000 ; // = 6'b010100 ;
-localparam ADP_RXPARAM = 45'b000000000000000000000001000000000000000000000 ; // = 6'b010101 ;
-localparam ADP_ACTION = 45'b000000000000000000000010000000000000000000000 ; // = 6'b010110 ;
-localparam ADP_SYSCTL = 45'b000000000000000000000100000000000000000000000 ; // = 6'b010111 ;
-localparam ADP_READ = 45'b000000000000000000001000000000000000000000000 ; // = 6'b011000 ;
-localparam ADP_SYSCHK = 45'b000000000000000000010000000000000000000000000 ; // = 6'b011001 ;
-localparam ADP_STDIN = 45'b000000000000000000100000000000000000000000000 ; // = 6'b011010 ;
-localparam ADP_WRITE = 45'b000000000000000001000000000000000000000000000 ; // = 6'b011011 ;
-localparam ADP_EXIT = 45'b000000000000000010000000000000000000000000000 ; // = 6'b011100 ;
-localparam STD_IOCHK = 45'b000000000000000100000000000000000000000000000 ; // = 6'b011101 ;
-localparam STD_RXD1 = 45'b000000000000001000000000000000000000000000000 ; // = 6'b011110 ;
-localparam STD_RXD2 = 45'b000000000000010000000000000000000000000000000 ; // = 6'b011111 ;
-localparam STD_TXD1 = 45'b000000000000100000000000000000000000000000000 ; // = 6'b100000 ;
-localparam STD_TXD2 = 45'b000000000001000000000000000000000000000000000 ; // = 6'b100001 ;
-localparam ADP_UCTRL = 45'b000000000010000000000000000000000000000000000 ; // = 6'b100010 ;
-localparam ADP_UREADB = 45'b000000000100000000000000000000000000000000000 ; // = 6'b100011 ;
-localparam ADP_UWRITE = 45'b000000001000000000000000000000000000000000000 ; // = 6'b100100 ;
-localparam ADP_POLL = 45'b000000010000000000000000000000000000000000000 ; // = 6'b100101 ;
-localparam ADP_POLL1 = 45'b000000100000000000000000000000000000000000000 ; // = 6'b100110 ;
-localparam ADP_POLL2 = 45'b000001000000000000000000000000000000000000000 ; // = 6'b100111 ;
-localparam ADP_FCTRL = 45'b000010000000000000000000000000000000000000000 ; // = 6'b101000 ;
-localparam ADP_FWRITE = 45'b000100000000000000000000000000000000000000000 ; // = 6'b101001 ;
-localparam ADP_ECHOCMD = 45'b001000000000000000000000000000000000000000000 ; // = 6'b101010 ;
-localparam ADP_ECHOBUS = 45'b010000000000000000000000000000000000000000000 ; // = 6'b101011 ;
-localparam ADP_UNKNOWN = 45'b100000000000000000000000000000000000000000000 ; // = 6'b101100 ;
-reg [44:0] adp_state ;
-`endif
-
-reg [31:0] adp_bus_data;
-reg banner ;
-reg com_tx_req ;
-reg [7:0] com_tx_byte ;
-reg com_rx_ack ;
-reg std_tx_req ;
-reg [ 7:0] std_tx_byte;
-reg std_rx_ack ;
-reg adp_bus_req ;
-reg adp_bus_write ;
-reg adp_bus_err ;
-reg [7:0] adp_cmd ;
-reg [7:0] adp_cmdwid ;
-reg [34:0] adp_param ;
-reg [31:0] adp_addr ;
-reg [1:0] adp_size ;
-reg adp_addr_inc;
-reg [31:0] adp_sys ;
-
-assign GPO8_o = adp_sys[7:0];
-
-// ADP RX stream
-wire com_rx_req = COMRX_TVALID_i;
-wire [ 7:0] com_rx_byte = COMRX_TDATA_i;
-assign COMRX_TREADY_o = com_rx_ack;
-// ADP TX stream
-wire com_tx_ack = COMTX_TREADY_i;
-assign COMTX_TDATA_o = com_tx_byte;
-assign COMTX_TVALID_o = com_tx_req;
-// STD RX stream (from STDOUT)
-wire std_rx_req = STDRX_TVALID_i;
-wire [ 7:0] std_rx_byte = STDRX_TDATA_i;
-assign STDRX_TREADY_o = std_rx_ack;
-// STD TX stream (to STDIN)
-wire std_tx_ack = STDTX_TREADY_i;
-assign STDTX_TDATA_o = std_tx_byte;
-assign STDTX_TVALID_o = std_tx_req;
-
-//AMBA AHB master as "stream" interface
-reg ahb_dphase;
-wire ahb_aphase = adp_bus_req & !ahb_dphase;
-wire adp_bus_ack = ahb_dphase & HREADY_i;
-// control pipe
-always @(posedge HCLK or negedge HRESETn)
- if(!HRESETn)
- ahb_dphase <= 0;
- else if (HREADY_i)
- ahb_dphase <= (ahb_aphase);
-
-wire [1:0] byteaddr;
-
-assign byteaddr = (adp_size[1]) ? 2'b00 : (adp_size[0]) ? {adp_addr[1], 1'b0} : adp_addr[1:0];
-
-assign HADDR32_o[31:2] = adp_addr[31:2];
-assign HADDR32_o[ 1:0] = byteaddr[1:0];
-assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer;
-assign HMASTLOCK_o = 1'b0;
-assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1};
-assign HSIZE3_o[2:0] = {1'b0, adp_size};
-assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq
-assign HWDATA32_o = (adp_size[1]) ? adp_bus_data
- : (adp_size[0]) ? {2{adp_bus_data[15:0]}}
- : {4{adp_bus_data[7:0]}} ;
-assign HWRITE_o = adp_bus_write;
-
-
-`ifndef ADPBASIC
-reg [34:0] adp_val;
-reg [31:0] adp_mask;
-reg [31:0] adp_poll;
-reg [31:0] adp_count;
-reg adp_count_dec ;
-wire adp_delay_done;
-wire poll2_loop_next;
-`endif
-
-// ADP_control flags in the 'C' control field
-wire adp_disable;
-wire adp_stdin_wait;
-
-// commnon interface handshake terms
-wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o;
-wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i;
-wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o;
-wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i;
-wire adp_bus_done = (adp_bus_req & adp_bus_ack);
-
-// common task to set up for next state
-task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner)
-// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end
- begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
-endtask
-task ADP_PROMPT_next; // prepare prompt TX
- begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end
-endtask
-task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion
- begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end
-endtask
-task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion
- begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end
-endtask
-
-task ADP_hexdigit_next; // output nibble
-input [3:0] nibble;
- begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
-endtask
-task ADP_txchar_next; // output char
-input [7:0] octet;
- begin com_tx_req<= 1; com_tx_byte <= octet; end
-endtask
-
-task com_rx_nxt; com_rx_ack <=1; endtask
-
-function FNcount_down_zero_next; // param about to be zero
-input [31:0] counter;
- FNcount_down_zero_next = !(|counter[31:1]);
-endfunction
-
-always @(posedge HCLK or negedge HRESETn)
- if(!HRESETn) begin
- adp_state <= ADP_WRITEHEX ;
- adp_bus_data <= BANNERHEX;
- banner <= 1; // start-up HEX message
- com_tx_req <= 0; // default no TX req
- com_rx_ack <= 0; // default no RX ack
- std_tx_req <= 0; // default no TX req
- std_rx_ack <= 0; // default no RX ack
- adp_bus_req <= 0; // default no bus transaction
- adp_bus_err <= 0; // default no bus error
- adp_cmd <= 0;
- adp_param <= 0;
- adp_size <= 2'b10; // default to 32-bit word size
- adp_addr <= 0;
- adp_addr_inc <= 0;
- adp_bus_write<= 0;
-`ifndef ADPBASIC
- adp_count <= 0;
- adp_count_dec<= 0;
- adp_val <= 0;
- adp_mask <= 0;
- adp_sys <= 0;
-`endif
- end else begin // default states
- adp_state <= adp_state; // default to hold current state
- com_tx_req <= 0; // default no TX req
- com_rx_ack <= 0; // default no RX ack
- std_tx_req <= 0; // default no TX req
- std_rx_ack <= 0; // default no RX ack
- adp_bus_req <= 0; // default no bus transaction
- adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + (1 << adp_size) : adp_addr; // address++
- adp_addr_inc <= 0;
-`ifndef ADPBASIC
- adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param--
- adp_count_dec<= 0;
-`endif
- case (adp_state)
-// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>>
- STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
- if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN
-// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
- else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending
- STD_TXD1: // get STD out char
- if (std_rx_done)
- begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end
- else std_rx_ack <= 1; // extend
- STD_TXD2: // output char to ADP channel
- if (com_tx_done) begin adp_state <= STD_IOCHK; end
- else com_tx_req <= 1; // extend
- STD_RXD1: // read rx char and check for ADP entry else STDIN **
- if (com_rx_done) begin
- if (FNvalid_adp_entry(com_rx_byte))
- begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt
- else if (std_tx_ack)
- begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end
- else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked
- end else com_rx_ack <= 1; // extend
- STD_RXD2: // get STD in char
- if (std_tx_done) begin adp_state <= STD_IOCHK; end
- else std_tx_req <= 1; // extend
-
-// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>>
- ADP_PROMPT: // transition after reset deassertion
- if (com_tx_done) begin adp_state <= ADP_IOCHK; end
- else com_tx_req <= 1; // extend
-
- ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
- if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
- else if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
-
-// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>>
- ADP_STDOUT: // output "<"
- if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end
- else com_tx_req <= 1; // extend stream request if not ready
- ADP_STDOUT1: // get STD out char
- if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end
- else std_rx_ack <= 1; // else extend
- ADP_STDOUT2: // output char
- if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end
- else com_tx_req <= 1; // else extend
- ADP_STDOUT3: // output ">"
- if (com_tx_done) begin if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end else adp_state <= ADP_IOCHK; end
- else com_tx_req <= 1; // else extend
-
-// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>>
- ADP_RXCMD: // read and save ADP command
- if (com_rx_done) begin
- if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit
- else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command
- else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_LINEACK; end // no command, skip param
- else begin adp_cmd <= com_rx_byte; adp_param <= 35'h0_00000000; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter
- end
- else com_rx_ack <= 1; // extend stream request if not ready
- ADP_RXPARAM: // read and build hex parameter
- if (com_rx_done) begin // RX byte
- if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit
- else if (FNvalid_EOL(com_rx_byte))
-`ifndef ADPBASIC
- begin adp_count <= adp_param[31:0]; adp_state <= ADP_ACTION;
- adp_size <= FNparam2size(adp_param[34:33]); end // parameter complete on EOL
-`else
- begin adp_state <= ADP_ACTION;
- adp_size <= FNparam2size(adp_param[34:33]); end // parameter complete on EOL
-`endif
- else
- begin adp_param <= FNBuild_size3_param32_hexdigit(adp_param[34:0], com_rx_byte); com_rx_ack <= 1; end // build parameter
- end
- else com_rx_ack <= 1;
-
- ADP_ACTION: // parse command and action with parameter
- if (FNexit(com_rx_byte))
- adp_state <= STD_IOCHK;
- else if (FNvalid_cmd(adp_cmd) == CMD_A)
- begin if (|adp_param[34:32]) adp_addr <= adp_param[31:0]; else adp_param <= {3'b111, adp_addr} ;
- adp_state <= ADP_ECHOCMD; end
- else if (FNvalid_cmd(adp_cmd) == CMD_C) begin
- if (|adp_param[34:32] == 1'b0) // report GPO
- begin adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 1) // clear selected bits in GPO
- begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 2) // set selected bits in GPO
- begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end
- else if (adp_param[31:8] == 3) // overwrite bits in GPO
- begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end
- else // 4 etc, report GPO
- begin adp_state <= ADP_SYSCTL; end
- end
- else if (FNvalid_cmd(adp_cmd) == CMD_R)
- begin adp_size <= FNparam2size(adp_param[34:33]); ADP_BUSREADINC_next; adp_state <= ADP_READ;
-`ifndef ADPBASIC
- adp_count_dec <= 1'b1; // optional loop param
-`endif
- end // no param required
- else if (FNvalid_cmd(adp_cmd) == CMD_S)
- begin adp_state <= ADP_SYSCHK; end
- else if (FNvalid_cmd(adp_cmd) == CMD_W)
- begin adp_size <= FNparam2size(adp_param[34:33]); adp_bus_data <= adp_param[31:0]; ADP_BUSWRITEINC_next; adp_state <= ADP_WRITE; end
- else if (FNvalid_cmd(adp_cmd) == CMD_X)
- begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end
-`ifndef ADPBASIC
- else if (FNvalid_cmd(adp_cmd) == CMD_U)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_UCTRL; // non-zero count
- else if (FNvalid_cmd(adp_cmd) == CMD_M)
- begin if (|adp_param[34:32]) adp_mask <= adp_param[31:0]; else adp_param <= {3'b111,adp_mask};
- adp_state <= ADP_ECHOCMD; end
- else if (FNvalid_cmd(adp_cmd) == CMD_P)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count
- else if (FNvalid_cmd(adp_cmd) == CMD_V)
- begin if (|adp_param[34:32]) begin adp_size <= FNparam2size(adp_param[34:33]); adp_val <= adp_param[34:0]; end
- else adp_param <= adp_val;
- adp_state <= ADP_ECHOCMD; end
- else if (FNvalid_cmd(adp_cmd) == CMD_F)
- if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_FCTRL; // non-zero count
-`endif
- else
- begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald
-
-// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>>
-
- ADP_WRITE: // perform bus write at current address pointer (and auto increment)
- if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= HRESP_i; end
- else begin ADP_BUSWRITEINC_next; end // extend request
-
- ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex
- if (adp_bus_done) begin adp_bus_data <= (byteaddr[1:0] == 2'b01) ? {HRDATA32_i[ 7: 0],HRDATA32_i[31: 8]}
- : (byteaddr[1:0] == 2'b10) ? {HRDATA32_i[15: 0],HRDATA32_i[31:16]}
- : (byteaddr[1:0] == 2'b11) ? {HRDATA32_i[23: 0],HRDATA32_i[31:24]}
- : HRDATA32_i;
- adp_bus_err <= HRESP_i; ADP_txchar_next("R"); adp_state <= ADP_ECHOBUS;
- end
- else begin
- ADP_BUSREADINC_next;
-`ifndef ADPBASIC
- adp_count_dec<= 1'b1;
-`endif
- end // extend request
-
-`ifndef ADPBASIC
-
-// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>>
- ADP_UCTRL: // set control value
- begin com_rx_ack <= 1; adp_size = 2'b00; adp_state <= ADP_UREADB; end // read next byte
- ADP_UREADB: // read raw binary byte
- if (com_rx_done)
- begin adp_bus_data[31:0] <= {4{com_rx_byte}}; ADP_BUSWRITEINC_next; adp_count_dec <= 1; adp_state <= ADP_UWRITE; end
- else com_rx_ack <= 1; // extend stream request if not ready
- ADP_UWRITE: // Write word to Addr++
- if (adp_bus_done) begin // auto address++, count--
- if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_UREADB; adp_bus_err <= adp_bus_err | HRESP_i; end
- end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1; end // extend request
-
-// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>>
- ADP_POLL: // set poll value
- begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end
- ADP_POLL1: // wait for read data, no addr++
- if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; adp_bus_err <= adp_bus_err | HRESP_i; end
- else begin adp_bus_req <= 1; adp_count_dec <=1; end
- ADP_POLL2:
- if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= 1'b1; end // timeout
- else if (((adp_bus_data & adp_mask) ^ adp_val[31:0]) == 0) begin adp_state <= ADP_ECHOCMD; adp_param <= {1'b0, (adp_param[31:0] - adp_count)}; end // exact match
- else adp_state <= ADP_POLL;
-
-// >>>>>>>>>>>>>>>> ADP (ZERO) FILL MEMORY >>>>>>>>>>>>>>>>>>>>>>
- ADP_FCTRL: // set control value
- begin adp_size <= FNparam2size(adp_val[34:33]); adp_bus_data <= adp_val[31:0]; ADP_BUSWRITEINC_next; adp_count_dec <= 1; adp_state <= ADP_FWRITE; end
- ADP_FWRITE: // Write word to Addr++
- if (adp_bus_done) begin // auto address++, count--
- if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_FCTRL; adp_bus_err <= adp_bus_err | HRESP_i; end
- end else begin ADP_BUSWRITEINC_next; adp_count_dec <= 1; end // extend request
-`endif
-
- // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>>
-
- ADP_UNKNOWN: // output "?"
- if (com_tx_done) begin ADP_LINEACK_next; end
- else com_tx_req <= 1; // extend stream request if not ready
-
- ADP_EXIT: // exit ADP mode
- if (com_tx_done) adp_state <= STD_IOCHK;
- else com_tx_req <= 1; // extend stream request if not ready
-
- ADP_SYSCHK: // check STDIN fifo
- begin // no upper flags so STDIN char
- if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
- else begin adp_bus_err <= 1'b1; adp_state <= ADP_ECHOCMD; end // signal error then echo comand
- end
- ADP_STDIN: // push char into STDIN
- if (std_tx_done) begin adp_bus_data <= {24'b0,adp_param[7:0]}; ADP_txchar_next("S"); adp_state <= ADP_ECHOBUS; end
- else std_tx_req <= 1; // extend
-
- ADP_SYSCTL: // read current status - and report in hex
- begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); adp_state <= ADP_ECHOBUS; end
-
- ADP_ECHOCMD: // output command and (param) data
- begin ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param[31:0]; adp_state <= ADP_ECHOBUS; end // output command char
- ADP_ECHOBUS: // output command space and (bus) data
- if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
- else com_tx_req <= 1; // extend
-
- ADP_WRITEHEX: // output hex word with prefix
- begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
-
- ADP_WRITEHEXS:
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX9:
- if (com_tx_done & adp_size[1]) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix
- else if (com_tx_done & adp_size[0]) begin adp_state <= ADP_WRITEHEX4; ADP_txchar_next("x"); end // output "x" hex prefix
- else if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_txchar_next("x"); end // output "x" hex prefix
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX8:
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX7: // output hex nibble 7
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX6: // output hex nibble 6
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX5: // output hex nibble 5
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX4: // output hex nibble 4
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX3: // output hex nibble 3
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX2: // output hex nibble 2
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX1: // output hex nibble 1
- if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0
- else com_tx_req <= 1; // extend
- ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack
- if (com_tx_done) begin
- adp_bus_err <= 1'b0; // clear sticky bus error flag
- if (banner) begin ADP_LINEACK_next; end
- else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
- end else com_tx_req <= 1; // extend
-
- ADP_LINEACK: // write EOLN
- if (com_tx_done) begin
- begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end
- end else com_tx_req <= 1; // extend
- ADP_LINEACK2: // CR
- if (com_tx_done) begin
- if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end
-`ifndef ADPBASIC
- else if ((FNvalid_cmd(adp_cmd) == CMD_R) & |adp_count) //// non-zero count
- begin ADP_BUSREADINC_next; adp_count_dec <= 1'b1; adp_state <= ADP_READ; end //
-`endif
- else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end
- end else com_tx_req <= 1; // extend
- default:
- begin ADP_txchar_next("#"); adp_state <= ADP_UNKNOWN; end // default error
- endcase
- end
-
-endmodule
-
-////AHBLITE_ADPMASTER instancing
-//adp_manager
-// #(.PROMPT_CHAR ("]"))
-// ADPmanager(
-// .HCLK (ahb_hclk ),
-// .HRESETn (ahb_hrestn ),
-// .HADDR32_o (ahb_haddr ),
-// .HBURST3_o (ahb_hburst ),
-// .HMASTLOCK_o (ahb_hmastlock ),
-// .HPROT4_o (ahb_hprot ),
-// .HSIZE3_o (ahb_hsize ),
-// .HTRANS2_o (ahb_htrans ),
-// .HWDATA32_o (ahb_hwdata ),
-// .HWRITE_o (ahb_hwrite ),
-// .HRDATA32_i (ahb_hrdata ),
-// .HREADY_i (ahb_hready ),
-// .HRESP_i (ahb_hresp ),
-// .GPO8_o (gpio8 ),
-// .GPI8_i (gpio8 ),
-// .COMRX_TREADY_o(com_rx_tready),
-// .COMRX_TDATA_i(com_rx_tdata),
-// .COMRX_TVALID_i(com_rx_tvalid),
-// .STDRX_TREADY_o(std_rx_tready),
-// .STDRX_TDATA_i(std_rx_tdata),
-// .STDRX_TVALID_i(std_rx_tvalid),
-// .COMTX_TVALID_o(com_tx_tvalid),
-// .COMTX_TDATA_o(com_tx_tdata),
-// .COMTX_TREADY_i(com_tx_tready),
-// .STDTX_TVALID_o(std_tx_tvalid),
-// .STDTX_TDATA_o(std_tx_tdata),
-// .STDTX_TREADY_i(std_tx_tready)
-// );
diff --git a/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v b/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
deleted file mode 100755
index 21b14bc7923dcadcbd85c628c777319e1f831a66..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
+++ /dev/null
@@ -1,305 +0,0 @@
-//-----------------------------------------------------------------------------
-// soclabs on-chip AXI stream to FTDI FT1248 controller
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_ft1248_stream_io_v1_0 #
- (
- // Users to add parameters here
- // FTDI Interface 1,2,4 width supported
- parameter integer FT1248_WIDTH = 1,
- // FTDI clock always on - else quiet when no access
- parameter integer FT1248_CLKON = 1
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- // Parameters of Axi Stream Master Bus Interface TXD
- // Parameters of Axi Stream Slave Bus Interface RXD
- )
- (
- // IO pad interface - to FT232R configured in 1/2/4/8 mode
- output wire ft_clk_o, // SCLK
- output wire ft_ssn_o, // SS_N
- input wire ft_miso_i, // MISO
- output wire [FT1248_WIDTH-1:0] ft_miosio_o, // MIOSIO tristate output when enabled
- output wire [FT1248_WIDTH-1:0] ft_miosio_e, // MIOSIO tristate output enable (active hi)
- output wire [FT1248_WIDTH-1:0] ft_miosio_z, // MIOSIO tristate output enable (active lo)
- input wire [FT1248_WIDTH-1:0] ft_miosio_i, // MIOSIO tristate input
-
- input wire [7:0] ft_clkdiv, // divider prescaler to ensure SCLK <1MHz
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // initially clocked from aclk
- // asynch
- input wire clk,
- input wire resetn,
-
- // Ports of Axi Master Bus Interface TXD
- output wire txd_tvalid,
- output wire [7 : 0] txd_tdata,
- output wire txd_tlast,
- input wire txd_tready,
-
- // Ports of Axi Slave Bus Interface RXD
- output wire rxd_tready,
- input wire [7 : 0] rxd_tdata,
- input wire rxd_tlast,
- input wire rxd_tvalid
- );
-
- //----------------------------------------------
- //-- State Machine encoding
- //----------------------------------------------
-
-// Explicit FSM state bit assignment
-// bit [0] SCLK
-// bit [1] MIO_OE
-// bit [2] CMD/W
-// bit [3] DAT/R
-// bit [4] SSEL
-
-localparam FT_0_IDLE = 5'b00000;
-localparam FT_1_IDLE = 5'b00001;
-localparam FT_ZCMD_CLKLO = 5'b10100;
-localparam FT_CMD_CLKHI = 5'b10111;
-localparam FT_CMD_CLKLO = 5'b10110;
-localparam FT_ZBT_CLKHI = 5'b10001;
-localparam FT_ZBT_CLKLO = 5'b10000;
-localparam FT_WD_CLKHI = 5'b11111;
-localparam FT_WD_CLKLO = 5'b11110;
-localparam FT_ZWD_CLKLO = 5'b11100;
-localparam FT_RD_CLKHI = 5'b11001;
-localparam FT_RD_CLKLO = 5'b11000;
-
-reg [4:0] ft_state;
-// 9- bit shift register to support 8-bit data + 1 sequence control flag
-// write data uses bits[7:0], with bit[8] set to flag length for serialized transfers
-// read data uses bits[8:1], with bit[0] set to flag continuation for serialized transfers
-reg [8:0] ft_reg;
-
- //----------------------------------------------
- //-- IO PAD control, parameterized on WIDTH param
- //----------------------------------------------
-
-wire bwid8 = (FT1248_WIDTH==8);
-wire bwid4 = (FT1248_WIDTH==4);
-wire bwid2 = (FT1248_WIDTH==2);
-wire bwid1 = (FT1248_WIDTH==1);
-
-wire [7:0] ft_rdmasked;
-
-generate if (FT1248_WIDTH == 8) begin
-assign ft_rdmasked[7:1] = ft_miosio_i[7:1];
-assign ft_miosio_o[7:1] = ft_reg[7:1];
-assign ft_miosio_e[7:1] = {7{ft_state[1]}};
-assign ft_miosio_z[7:1] = ~{7{ft_state[1]}};
-end
-endgenerate
-
-generate if (FT1248_WIDTH == 4) begin
-assign ft_rdmasked[7:1] = {4'b1111, ft_miosio_i[3:1]};
-assign ft_miosio_o[3:1] = ft_reg[3:1];
-assign ft_miosio_e[3:1] = {3{ft_state[1]}};
-assign ft_miosio_z[3:1] = ~{3{ft_state[1]}};
-end
-endgenerate
-
-generate if (FT1248_WIDTH == 2) begin
-assign ft_rdmasked[7:1] = {6'b111111, ft_miosio_i[1]};
-assign ft_miosio_o[1] = ft_reg[1];
-assign ft_miosio_e[1] = ft_state[1];
-assign ft_miosio_z[1] = ~ft_state[1];
-end
-endgenerate
-
-generate if (FT1248_WIDTH == 1)
-assign ft_rdmasked[7:1] = 7'b1111111;
-endgenerate
-
-assign ft_rdmasked[0] = ft_miosio_i[0];
-assign ft_miosio_o[0] = ft_reg[0];
-assign ft_miosio_e[0] = ft_state[1];
-assign ft_miosio_z[0] = ~ft_state[1];
-
-assign ft_clk_o = ft_state[0];
-assign ft_ssn_o = !ft_state[4];
-
-// diagnostic decodes
-//wire ft_cmd = !ft_state[3] & ft_state[2];
-//wire ft_dwr = ft_state[3] & ft_state[2];
-//wire ft_drd = ft_state[3] & !ft_state[2];
-
-
- //----------------------------------------------
- //-- Internal clock prescaler
- //----------------------------------------------
-
- // clock prescaler, ft_clken enables serial IO engine clocking
- reg [7:0] ft_clkcnt_r;
- reg ft_clken;
-
- always @(posedge clk or negedge resetn )
- begin
- if (!resetn) begin
- ft_clkcnt_r <= 0;
- ft_clken <= 0;
- end
- else begin
- ft_clken <= (ft_clkcnt_r == ft_clkdiv);
- ft_clkcnt_r <= (ft_clkcnt_r == ft_clkdiv) ? 0 : (ft_clkcnt_r +1);
- end
- end
-
- //----------------------------------------------
- //-- Internal "synchronizers" (dual stage)
- //----------------------------------------------
- // synchronizers for channel ready flags when idle
- // (treat these signals as synchronous during transfer sequencing)
- reg ft_miso_i_sync;
- reg ft_miosio_i0_sync;
- reg ft_miso_i_sync_1;
- reg ft_miosio_i0_sync_1;
-
- always @(posedge clk or negedge resetn )
- begin
- if (!resetn) begin
- ft_miso_i_sync_1 <= 1;
- ft_miosio_i0_sync_1 <= 1;
- ft_miso_i_sync <= 1;
- ft_miosio_i0_sync <= 1;
- end
- else begin
- ft_miso_i_sync_1 <= ft_miso_i;
- ft_miosio_i0_sync_1 <= ft_miosio_i[0];
- ft_miso_i_sync <= ft_miso_i_sync_1;
- ft_miosio_i0_sync <= ft_miosio_i0_sync_1;
- end
- end
-
- //----------------------------------------------
- //-- AXI Stream interface handshakes
- //----------------------------------------------
-
-reg ft_txf; // FTDI Transmit channel Full
-reg ft_rxe; // FTDO Receive channel Empty
-reg ft_wcyc; // read access committed
-reg ft_nak; // check for NAK terminate
-
-// TX stream delivers valid FT1248 read data transfer
-// 8-bit write port with extra top-bit used as valid qualifer
-reg [8:0] txdata;
-assign txd_tdata = txdata[7:0];
-assign txd_tvalid = txdata[8];
-
-// activate if RX channel data and the stream buffer is not full
-wire ft_rxreq = !ft_rxe & !txdata[8];
-
-
-// RX stream handshakes on valid FT1248 write data transfer
-reg rxdone;
-reg rxrdy;
-assign rxd_tready = rxdone;
-
-// activate if TX channel not full and and the stream buffer data valid
-wire ft_txreq = !ft_txf & rxd_tvalid; // & !rxdone; // FTDI TX data ready and rxstream ready
-
-// FTDI1248 commands
-wire [3:0] wcmd = 4'b0000; // write request
-wire [3:0] rcmd = 4'b0001; // read request
-wire [3:0] fcmd = 4'b0100; // write flush request
-//wire [3:0] rcmd = 4'b1000; // read request BE bit-pattern
-//wire [3:0] fcmd = 4'b0010; // write flush request BE bit-pattern
-// and full FT1248 command bit patterns (using top-bits for shift sequencing)
-wire [8:0] wcmdpatt = {2'b11, wcmd[0], wcmd[1], 1'b0, wcmd[2], 1'b0, 1'b0, wcmd[3]};
-wire [8:0] rcmdpatt = {2'b11, rcmd[0], rcmd[1], 1'b0, rcmd[2], 1'b0, 1'b0, rcmd[3]};
-
-reg ssn_del;
-always @(posedge clk or negedge resetn)
- if (!resetn)
- ssn_del <= 1'b1;
- else if (ft_clken)
- ssn_del <= ft_ssn_o;
-wire ssn_start = ft_ssn_o & ssn_del;
-
-// FTDI1248 state machine
-
-always @(posedge clk or negedge resetn)
- if (!resetn) begin
- ft_state <= FT_0_IDLE;
- ft_reg <= 0;
- txdata <= 0;
- rxdone <= 0;
- ft_wcyc <= 0;
- ft_txf <= 1; // ftdi channel TXE# ('1' full)
- ft_rxe <= 1; // ftdi channel RXF# ('1' empty)
- ft_nak <= 0;
- end
- else begin
- ft_txf <= (ft_state==FT_0_IDLE) ? (ft_miosio_i[0] | ft_miosio_i0_sync) : 1'b1; //ft_txf & !( ft_wcyc &(ft_state==FT_ZBT_CLKHI) & ft_miso_i);
- ft_rxe <= (ft_state==FT_0_IDLE) ? (ft_miso_i | ft_miso_i_sync) : 1'b1; //ft_rxe & !(!ft_wcyc & (ft_state==FT_ZBT_CLKHI) & ft_miso_i);
- txdata[8] <= txdata[8] & !txd_tready; // tx_valid handshake
- rxdone <= (ft_clken & (ft_state==FT_ZWD_CLKLO) & !ft_nak) | (rxdone & !rxd_tvalid); // hold until acknowledged
- if (ft_clken)
- case (ft_state)
- FT_0_IDLE: begin // RX req priority
- if (ssn_start & ft_rxreq) begin ft_reg <= rcmdpatt; ft_state <= FT_ZCMD_CLKLO; end
- else if (ssn_start & ft_txreq) begin ft_reg <= wcmdpatt; ft_state <= FT_ZCMD_CLKLO; ft_wcyc <= 1; end
- else ft_state <= (!ft_txf | !ft_rxe | (FT1248_CLKON!=0)) ? FT_1_IDLE : FT_0_IDLE;
- end
- FT_1_IDLE:
- ft_state <= FT_0_IDLE;
- FT_ZCMD_CLKLO:
- ft_state <= FT_CMD_CLKHI;
- FT_CMD_CLKHI:
- ft_state <= FT_CMD_CLKLO;
- FT_CMD_CLKLO: // 2, 4 or 7 shifts
- if (bwid8) begin ft_reg <= FT_ZBT_CLKHI; end
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= (|ft_reg[8:5]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= (|ft_reg[8:3]) ? FT_CMD_CLKHI : FT_ZBT_CLKHI; end
- FT_ZBT_CLKHI:
- ft_state <= FT_ZBT_CLKLO;
- FT_ZBT_CLKLO:
- if (ft_wcyc) begin ft_reg <= {1'b1,rxd_tdata}; ft_state <= FT_WD_CLKHI; end
- else begin ft_reg <= 9'b011111111; ft_state <= FT_RD_CLKHI; end
- FT_WD_CLKHI:
- if (ft_miso_i & ft_reg[8]) begin ft_nak <= 1'b1; ft_state <= FT_ZWD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) ft_state <= (ft_reg[8]) ? FT_WD_CLKLO : FT_ZWD_CLKLO; // special case repeat on write data
- else if (bwid4) ft_state <= (|ft_reg[8:5]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else if (bwid2) ft_state <= (|ft_reg[8:3]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- else ft_state <= (|ft_reg[8:2]) ? FT_WD_CLKLO : FT_ZWD_CLKLO;
- FT_WD_CLKLO:
- if (bwid8) begin ft_reg <= { 1'b0,ft_reg[7:0]}; ft_state <= FT_WD_CLKHI; end // clear top flag
- else if (bwid4) begin ft_reg <= {4'b0000,ft_reg[8:4]}; ft_state <= FT_WD_CLKHI; end // shift 4 bits right
- else if (bwid2) begin ft_reg <= { 2'b00,ft_reg[8:2]}; ft_state <= FT_WD_CLKHI; end // shift 2 bits right
- else begin ft_reg <= { 1'b0,ft_reg[8:1]}; ft_state <= FT_WD_CLKHI; end // shift 1 bit right
- FT_ZWD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end // terminate without TX handshake
- else begin ft_state <= FT_0_IDLE; ft_wcyc <= 1'b0; end
- FT_RD_CLKHI: // capture iodata pins end of CLKHI phase
- if (ft_miso_i & (&ft_reg[7:0])) begin ft_nak <= 1'b1; ft_state <= FT_RD_CLKLO; end // NAK terminate on first cycle
- else if (bwid8) begin ft_reg <= (ft_reg[0]) ? {ft_rdmasked[7:0],1'b1} : {ft_reg[8:1],1'b0}; ft_state <= FT_RD_CLKLO; end // 8-bit read twice
- else if (bwid4) begin ft_reg <= {ft_rdmasked[3:0],ft_reg[8:4]}; ft_state <= FT_RD_CLKLO; end
- else if (bwid2) begin ft_reg <= {ft_rdmasked[1:0],ft_reg[8:2]}; ft_state <= FT_RD_CLKLO; end
- else begin ft_reg <= {ft_rdmasked[ 0],ft_reg[8:1]}; ft_state <= FT_RD_CLKLO; end
- FT_RD_CLKLO:
- if (ft_nak) begin ft_nak<= 1'b0; ft_state <= FT_0_IDLE; txdata <= 9'b0; end // terminate without TX handshake
- else if (ft_reg[0]) begin ft_state <= FT_RD_CLKHI; ft_reg[0] <= !(bwid8); end // loop until all 8 bits shifted in (or 8-bit read repeated)
- else begin ft_state <= FT_0_IDLE; txdata <= {1'b1,ft_reg[8:1]}; end
- default:
- ft_state <= FT_0_IDLE;
- endcase
- end
-
- // User logic ends
-
-endmodule
diff --git a/system/test_io/verilog/nanosoc_ft1248x1_adpio.v b/system/test_io/verilog/nanosoc_ft1248x1_adpio.v
deleted file mode 100644
index 766afa1a5eb3c024a8739625711fd9300455444f..0000000000000000000000000000000000000000
--- a/system/test_io/verilog/nanosoc_ft1248x1_adpio.v
+++ /dev/null
@@ -1,157 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC FT1248 ADP UART file logging
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
-// and allows cmsdk_uart_capture testbench models to log ADP ip, op streams
-//-----------------------------------------------------------------------------
-
-
-module nanosoc_ft1248x1_adpio
- #(parameter ADPFILENAME = "adp.cmd",
- parameter VERBOSE = 0)
- (
- input wire ft_clk_i, // SCLK
- input wire ft_ssn_i, // SS_N
- output wire ft_miso_o, // MISO
- inout wire ft_miosio_io, // MIOSIO tristate output when enabled
-
- output wire FTDI_CLK2UART_o, // Clock (baud rate)
- output wire FTDI_OP2UART_o, // Received data to UART capture
- output wire FTDI_IP2UART_o // Transmitted data to UART capture
- );
-
-
- //----------------------------------------------
- //-- File I/O
- //----------------------------------------------
-
-
- integer fdcmd; // channel descriptor for cmd file input
- integer ch;
-`define EOF -1
-
- reg ft_rxreq;
- wire ft_rxack;
- reg [7:0] ft_adpbyte;
-
- initial
- begin
- ft_rxreq <= 0;
- $timeformat(-9, 0, " ns", 14);
- fdcmd= $fopen(ADPFILENAME,"r");
- if (fdcmd == 0)
- $write("** FT1248x1 : no command file **\n");
- else begin
- ch = $fgetc(fdcmd);
- while (ch != `EOF) begin
- ft_adpbyte <= (ch & 8'hff);
- ft_rxreq <= 1'b1;
- while (ft_ssn_i == 1'b0)
- @(posedge ft_ssn_i);
- @(posedge ft_rxack);
- ft_rxreq <=0;
- @(negedge ft_rxack);
- ch = $fgetc(fdcmd);
- end
- end
- $fclose(fdcmd);
- ft_rxreq <= 0;
- end
-
-
-//----------------------------------------------
-//-- State Machine
-//----------------------------------------------
-
-wire ft_miosio_i;
-wire ft_miosio_o;
-wire ft_miosio_z;
-
-// tri-state pad control for MIOSIO
-assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-// add notinal delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
-assign #1 ft_miosio_i = ft_miosio_io;
-
-reg [4:0] ft_state; // 17-state for bit-serial
-wire [5:0] ft_nextstate = ft_state + 5'b00001;
-
-always @(posedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_state <= 5'b11111;
- else // loop if multi-data
-// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
- ft_state <= ft_nextstate;
-
-// 16: bus turnaround (or bit[5])
-// 0 for CMD3
-// 3 for CMD2
-// 5 for CMD1
-// 6 for CMD0
-// 7 for cmd turnaround
-// 8 for data bit0
-// 9 for data bit1
-// 10 for data bit2
-// 11 for data bit3
-// 12 for data bit4
-// 13 for data bit5
-// 14 for data bit6
-// 15 for data bit7
-
-// ft_miso_o reflects RXE when deselected
-assign ft_miso_o = (ft_ssn_i) ? !ft_rxreq : (ft_state == 5'b00111);
-
-// capture CMD on falling edge of clock (mid-data)
-// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
-reg [7:0] ft_cmd;
-always @(negedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_cmd <= 8'b00000001;
- else // shift in data
- ft_cmd <= (!ft_state[3] & !ft_nextstate[3]) ? {ft_cmd[6:0],ft_miosio_i} : ft_cmd;
-
-wire ft_cmd_valid = ft_cmd[7];
-wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
-wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
-
-// tristate enable for miosio (deselected status or serialized data for read command)
-wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
-assign ft_miosio_z = !ft_miosio_e;
-
-// serial data formatted with start bit for UART capture (on rising uart-clock)
-assign FTDI_CLK2UART_o = !ft_clk_i;
-// suitable for CMSDK UART capture IO
-// inject a start bit low else mark high
-assign FTDI_OP2UART_o = (ft_cmd_txd & (ft_state[4:3]) == 2'b01) ? ft_miosio_i : !(ft_cmd_txd & (ft_state == 5'b00111));
-assign FTDI_IP2UART_o = (ft_cmd_rxd & (ft_state[4:3]) == 2'b01) ? ft_miosio_io : !(ft_cmd_rxd & (ft_state == 5'b00111));
-
-// capture RXD on falling edge of clock
-reg [8:0] ft_rxd;
-always @(negedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_rxd <= 9'b111111111;
- else if (ft_cmd_txd & !(ft_miosio_i & (&ft_rxd[8:0]))) //only on valid start-bit
- ft_rxd <= {ft_miosio_i, ft_rxd[8:1]};
-
-// shift TXD on rising edge of clock
-reg [8:0] ft_txd;
-always @(posedge ft_clk_i or posedge ft_ssn_i)
- if (ft_ssn_i)
- ft_txd <= {1'b1,ft_adpbyte};
- else if (ft_rxreq & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //valid TX shift
- ft_txd <= {1'b0,ft_txd[8:1]};
-
-assign ft_rxack = (ft_cmd_rxd & (ft_state==5'b01111));
-
-// ft_miso_o reflects TXF when deselected (never full for simulation output)
-assign ft_miosio_o = (ft_ssn_i) ? 1'b0 : ft_txd[0];
-
-endmodule