diff --git a/hal/nanosoc_ip.waive b/hal/nanosoc_ip.waive
index 71b33273d4ff7fc18208675bf5327206cd8a4e3d..ce19aa126ec5f6f53ee4cf29f6beb287e4939070 100644
--- a/hal/nanosoc_ip.waive
+++ b/hal/nanosoc_ip.waive
@@ -84,6 +84,35 @@ lint_checking designunit = nanosoc_ss_expansion
USEPRT {"DEBUG_PADDR"} off;
}
+lint_checking designunit = nanosoc_ss_systemctrl
+{
+ // Not Top-level in design_info
+ IOCOMB off;
+ TPOUNR off;
+
+ // Doesn't recognise XTAL as Clock
+ CLKUCL {"XTAL"} off;
+
+ // Resets have different names in Arm IP
+ DIFRST {"SYS_"} off;
+
+ // Clocks have different names in Arm IP
+ DIFCLK {"SYS_"} off;
+
+ // APB Write tied low
+ EXPIPC {"APB_DATA_W"} off;
+
+ // APB Reset driven from SystemReset
+ RSTUCL off;
+
+ // Unconnected Ports on Pin Mux and other peripherals
+ UNCONN {"p0_in|p1_in|P0|P1|_psel"} off;
+
+ // TODO: UART Cross Over wiring Needs looking at
+ UNCONO {"p0_in|p1_in|uart|_psel"} off;
+ URDWIR {"uart0_rxd|uart1_rxd"} off;
+}
+
lint_checking designunit = nanosoc_region_exp
{
// In Case of Default Slave, Read Data and IRQS and DRQs constant Assigned
@@ -122,6 +151,19 @@ lint_checking designunit = nanosoc_region_expram_h
USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
}
+lint_checking designunit = nanosoc_region_sysio
+{
+ // Multiple Clock Domains in Module
+ MCKDMN off;
+
+ // Combined Interrupts not connected
+ UNCONO {"COMBINT"} off;
+ UNCONN {"COMBINT"} off;
+
+ // AHB signals unused
+ USEPRT {"HBURST|HMASTLOCK"} off;
+}
+
lint_checking designunit = nanosoc_bootrom_cpu_0
{
// Bootrom Clock name different to HCLK
@@ -153,22 +195,164 @@ lint_checking designunit = nanosoc_clkctrl
{
// Based Off of Arm IP
CBPAHI off;
+ NBGEND off;
+
+ // Clocks Aliased (Clock control module)
+ DALIAS off;
+ DIFCLK off;
+ FDTHRU {"CLK"} off;
+
+ // Reset Bypass select
+ GLTASR off;
+
+ // Synchronous Reset
+ FRSTDF {"sync"} off;
+ RSTGNP off;
+ RSTINP {"prst"} off;
+
+ // Bitwise Not Intended
+ LOGNEG {"reset|RST|RESET"} off;
+
+ // Contains Synchronous and Asynchronous logic
+ SYNASN off;
+
+ // Clock Gating Disable
+ TIELOG {"CLKEN"} off;
+
+ // SYSRESETREQ crosses clock domain
+ CLKDMN {"nxt_prst"} off;
+
+ // Combined Interrupts not connected
+ UNCONO {"COMBINT"} off;
+
+ // pclkgen not used
+ URDWIR {"pclkgen"} off;
+
+ // Some Ports Unused (Arm IP)
+ USEPRT off;
+}
+
+lint_checking designunit = nanosoc_pin_mux
+{
+ // Arm IP Feedthrough on Pins
+ FDTHRU off;
+ IOCPIO off;
+
+ // Inout Ports used
+ IOPNTA off;
+
+ // Tristate Enable not driven by primary input
+ SLNOTP off;
+
+ // Synopsys pragmas in RTL
+ TPRUSD off;
+
+ // Inferred Tristate Correctly
+ TSBINF {"P0|P1"} off;
+
+ // Contains logic other than Tri-States
+ TSMHOL off;
+
+ // Some Ports Unused (Arm IP)
+ USEPRT {"altfunc"} off;
+
}
lint_checking designunit = nanosoc_sysctrl
{
- // Based off of Arm IP
+ // Based off of Arm IP - bad pratice
CBPAHI off;
+ BOUINC off;
+ NBGEND off;
+ REVROP off;
+
+ // Default Case still useful
+ CDEFCV off;
+
+ // Parameters used in conditional Assignments
+ CONSTC {"BE"} off;
+
+ // Bitwise Not Intended
+ LOGNEG {"reset|RST|RESET"} off;
+
+ // Multiple Clocks
+ MULMCK off;
+
+ // Contains Synchronous and Asynchronous logic
+ SYNASN off;
+
+ // Some AHB Response Signals tied off
+ TIELOG {"HREADYOUT|HRESP"} off;
+
+ // SYSRESETREQ crosses clock domain
+ CLKDMN {"reg_resetinfo"} off;
+
+ // Not all Byte Strobes used and little endian data unused
+ URDREG {"byte_strobe|HWDATALE"} off;
+
+ // Some AHB Signals unused
+ USEPRT {"HTRANS|HSIZE"} off;
}
lint_checking designunit = nanosoc_sysio_apb_ss
{
- // Based off of Arm IP
+ // Based off of Arm IP with bad lint rules
CBPAHI off;
+ NBGEND off;
+
+ // Parameters used in conditional Assignments
+ CONSTC {"BE"} off;
+
+ // Bitwise And Intended
+ LOGAND {"endian"} off;
+
+ // Bitwise Not Intended
+ LOGNEG {"RESET"} off;
+
+ // Contains Synchronous and Asynchronous logic
+ SYNASN off;
+
+ // Some Peripheral Signals Tied off
+ TIELOG {"uart|interrupt"} off;
+
+ // BaudTick not connected
+ UNCONN {"BAUDTICK"} off;
+
+ // APB Peripherals and interrupts tied off
+ UNCONO {"PPROT|PSEL|INT|BAUD"} off;
+
+ // Some APB and Interrupts unused
+ URDWIR {"pprot|psel|int"} off;
+
+ // TODO: Uart Crossover needs looking at
+ USEPRT {"uart0_rxd|uart1_rxd"} off;
}
-lint_checking designunit = nanosoc_clkctrl
+lint_checking designunit = nanosoc_coresight_systable
{
- // Reset Bypass select
- GLTASR off;
+ // Based off of Arm IP with bad lint rules
+ FFWNSR off; // No reset
+ NBGEND off; // No begin/end
+
+ // Contains Synchronous and Asynchronous logic
+ SYNASN off;
+
+ // Some AHB Response Signals tied off
+ TIELOG {"HREADYOUT|HRESP"} off;
+
+ // Unequal Operands in assignment (Can't fix Arm IP)
+ ULCMPE {"PRESENT"} off;
+
+ // Unused wire is unused
+ URDWIR {"unused"} off;
+
+ // TODO: Uart Crossover needs looking at
+ USEPRT {"uart0_rxd|uart1_rxd"} off;
+}
+
+lint_checking designunit = nanosoc_sysio_decode
+{
+ // Some of AHB Address Unused
+ USEPRT {"haddr"} off;
+
}
\ No newline at end of file
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 9d0750de01e92c0c77e7def60cef0b2cdea8943d..42784a780fbfaf339a7694f0962b58f2d264cd7f 100644
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -19,7 +19,6 @@ module nanosoc_region_sysio #(
)(
input wire FCLK, // Free-running system clock
input wire PORESETn, // Power-On-Reset reset (active-low)
- input wire TESTMODE, // Reset bypass in scan test
// AHB interface
input wire HCLK, // AHB clock
@@ -75,7 +74,7 @@ module nanosoc_region_sysio #(
// CPU power/reset control
output wire REMAP_CTRL, // REMAP control bit
output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
- output wire SYSRESETREQ, // Processor control - system reset request
+ input wire SYSRESETREQ, // Processor control - system reset request
output wire WDOGRESETREQ, // Watchdog reset request
input wire LOCKUP, // Processor status - Locked up
output wire LOCKUPRESET, // System Controller cfg - reset if lockup
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v b/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
index 7ce66cb889d7e3e2a31582c64a8097082d0814e1..8cf8a1cd639a66edddec05663c2c55d9b081509c 100644
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
@@ -236,23 +236,20 @@ localparam ARM_CMSDK_CM0_SYSCTRL_CID3 = {32'h000000B1}; // 0xFFC : CID 3
// endian conversion
always @(bigendian or reg_hsize or read_mux_le or HWDATA)
begin
- if ((bigendian)&(reg_hsize==2'b10))
- begin
+ if ((bigendian)&&(reg_hsize==2'b10)) begin
read_mux = {read_mux_le[ 7: 0],read_mux_le[15: 8],
read_mux_le[23:16],read_mux_le[31:24]};
HWDATALE = {HWDATA[ 7: 0],HWDATA[15: 8],HWDATA[23:16],HWDATA[ 31:24]};
+ end else begin
+ if ((bigendian)&&(reg_hsize==2'b01)) begin
+ read_mux = {read_mux_le[23:16],read_mux_le[31:24],
+ read_mux_le[ 7: 0],read_mux_le[15: 8]};
+ HWDATALE = {HWDATA[23:16],HWDATA[ 31:24],HWDATA[ 7: 0],HWDATA[15: 8]};
+ end else begin
+ read_mux = read_mux_le;
+ HWDATALE = HWDATA;
end
- else if ((bigendian)&(reg_hsize==2'b01))
- begin
- read_mux = {read_mux_le[23:16],read_mux_le[31:24],
- read_mux_le[ 7: 0],read_mux_le[15: 8]};
- HWDATALE = {HWDATA[23:16],HWDATA[ 31:24],HWDATA[ 7: 0],HWDATA[15: 8]};
- end
- else
- begin
- read_mux = read_mux_le;
- HWDATALE = HWDATA;
- end
+ end
end
// ----------------------------------------------------------
// Remap register
diff --git a/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v b/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
index 900136be273af4a46f123e6b23f50eeb084dd7ee..a13a6e75d6dbae1caee6ade124b21243e3726848 100644
--- a/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
+++ b/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
@@ -84,7 +84,7 @@ module nanosoc_coresight_systable
// ------------------------------------------------------------
// ROM Table Manufacturer, Part Number and Revision
// ------------------------------------------------------------
- parameter [6:0] JEPID = 7'b0000000, // JEP106 identity code
+ parameter [6:0] JEPID = 7'd0000000, // JEP106 identity code
parameter [3:0] JEPCONTINUATION = 4'h0, // number of JEP106
// continuation codes
parameter [11:0] PARTNUMBER = 12'h000, // part number
@@ -155,10 +155,10 @@ module nanosoc_coresight_systable
localparam [19:0] ENTRY3OFFSET = ENTRY3BASEADDR[31:12] - BASE[31:12];
// Construct entries
- localparam [31:0] ENTRY0 = { ENTRY0OFFSET, 10'b0, 1'b1, ENTRY0PRESENT!=0 };
- localparam [31:0] ENTRY1 = { ENTRY1OFFSET, 10'b0, 1'b1, ENTRY1PRESENT!=0 };
- localparam [31:0] ENTRY2 = { ENTRY2OFFSET, 10'b0, 1'b1, ENTRY2PRESENT!=0 };
- localparam [31:0] ENTRY3 = { ENTRY3OFFSET, 10'b0, 1'b1, ENTRY3PRESENT!=0 };
+ localparam [31:0] ENTRY0 = { ENTRY0OFFSET, 10'd0, 1'b1, ENTRY0PRESENT!=0 };
+ localparam [31:0] ENTRY1 = { ENTRY1OFFSET, 10'd0, 1'b1, ENTRY1PRESENT!=0 };
+ localparam [31:0] ENTRY2 = { ENTRY2OFFSET, 10'd0, 1'b1, ENTRY2PRESENT!=0 };
+ localparam [31:0] ENTRY3 = { ENTRY3OFFSET, 10'd0, 1'b1, ENTRY3PRESENT!=0 };
// ------------------------------------------------------------
diff --git a/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v b/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
index 9fe8ae723ecf339c78141cb890edfb5cb73e3228..34277c553cc1e60742151ea8e3ad5a15f9bd5c67 100644
--- a/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+++ b/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
@@ -17,7 +17,6 @@ module nanosoc_region_systable #(
parameter SYSTABLE_BASE = 32'hf000_0000 // Base Address for System ROM Table
)(
input wire HCLK, // Clock
- input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSEL, // AHB region select
diff --git a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 3e4a7c59b3451d86893ab1e47ded8fa5c51ab823..a68b5a28d8bb6ed7c2613d7bda8ffd1ab7ce540e 100644
--- a/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -101,7 +101,7 @@ module nanosoc_ss_systemctrl #(
output wire SYS_LOCKUPRESET, // System Controller cfg - reset if lockup
// System Reset Request Signals
- output wire SYS_SYSRESETREQ, // System Request from System Managers
+ input wire SYS_SYSRESETREQ, // System Request from System Managers
input wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
// Power Management Control and Status
@@ -238,7 +238,6 @@ module nanosoc_ss_systemctrl #(
// Clock and Reset
.FCLK(SYS_FCLK),
.PORESETn(SYS_PORESETn),
- .TESTMODE(SYS_TESTMODE),
// AHB interface
.HCLK(SYS_HCLK),
@@ -332,9 +331,8 @@ module nanosoc_ss_systemctrl #(
.SYS_DATA_W(SYS_DATA_W),
.SYSTABLE_BASE(SYSTABLE_BASE)
) u_region_systable (
- // Clock and Reset
+ // Clock
.HCLK(SYS_HCLK),
- .HRESETn(SYS_HRESETn),
// AHB connection to Initiator
.HSEL(SYSTABLE_HSEL),