From ee8726a3ab60c395b26dda6134286e9b2a9363c7 Mon Sep 17 00:00:00 2001 From: Daniel Newbrook <dwn1c21@soton.ac.uk> Date: Mon, 3 Jul 2023 14:26:24 +0100 Subject: [PATCH] Update fpga tcl scripts --- fpga_imp/scripts/build_mcu_fpga_ip.tcl | 70 +------------------ .../scripts/build_mcu_fpga_pynq_zcu104.tcl | 23 +++--- 2 files changed, 17 insertions(+), 76 deletions(-) diff --git a/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/fpga_imp/scripts/build_mcu_fpga_ip.tcl index 3931947..21455b4 100644 --- a/fpga_imp/scripts/build_mcu_fpga_ip.tcl +++ b/fpga_imp/scripts/build_mcu_fpga_ip.tcl @@ -23,75 +23,11 @@ file mkdir $outputDir # # STEP#1: setup design sources and constraints # +source scripts/top_flist.tcl -# local search path for configurations -set search_path ../verilog -set cortexm0_vlog $::env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical -source scripts/rtl_source_cm0.tcl - -set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ] -read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ] -read_verilog [ glob $cortexm0_vlog/models/cells/*.v ] - -# Arm unmodified CMSDK RTL -set cmsdk_vlog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101 -source scripts/rtl_source_cmsdk.tcl - -set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ] -read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v -read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v -read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v -read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v -read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v - -# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path) -set search_path [ concat $search_path ../verilog ] -set dma230_vlog $env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/src/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog -source scripts/rtl_source_dma230.tcl - -# ADP, FT1248 and streamio IP -source scripts/rtl_source_soclabs_ip.tcl - -## FPGA-specific pads -#source scripts/rtl_source_fpga_ip.tcl - -# soclabs modified mcu system - -set soc_vlog ../src -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v -read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v -read_verilog $soc_vlog/verilog/nanosoc_ahb_bootrom.v -read_verilog $soc_vlog/verilog/nanosoc_apb_subsystem.v -read_verilog $soc_vlog/bootrom/verilog/bootrom.v -read_verilog $soc_vlog/verilog/nanosoc_ahb_cs_rom_table.v -read_verilog $soc_vlog/verilog/nanosoc_apb_usrt.v -##read_verilog $soc_vlog/cmsdk_clkreset.v -read_verilog ../test_io/verilog/nanosoc_ft1248x1_adpio.v -read_verilog $soc_vlog/verilog/nanosoc_mcu_clkctrl.v -read_verilog $soc_vlog/verilog/nanosoc_mcu_pin_mux.v -read_verilog $soc_vlog/verilog/nanosoc_mcu_stclkctrl.v -read_verilog $soc_vlog/verilog/nanosoc_mcu_sysctrl.v -##read_verilog $soc_vlog/cmsdk_uart_capture.v -read_verilog $soc_vlog/verilog/nanosoc_cpu.v -read_verilog $soc_vlog/verilog/nanosoc_sys_ahb_decode.v -read_verilog $soc_vlog/verilog/nanosoc_sysio.v -read_verilog ../aes/src/nanosoc_acc_wrapper.v -read_verilog $soc_vlog/verilog/nanosoc_chip.v -read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v -set search_path [ concat $search_path ../../../secworks-aes/src/rtl ] -read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v - -#set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset] -set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset] +set_property generic {ACCELERATOR_SUBSYSTEM=1} [current_fileset] +set_property verilog_define {ACCELERATOR_SUBSYSTEM=1} [current_fileset] set_property top nanosoc_chip [current_fileset] # FPGA specific timing constraints diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl index 167d4be..a2643a2 100644 --- a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl +++ b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl @@ -62,15 +62,20 @@ read_verilog $importDir/design_1_wrapper.v source $importDir/design_1.tcl create_root_design "" -set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest -add_files -norecurse -scan_for_includes "$arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../defines/pl230_defs.v" -set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] -set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] -set_property is_global_include true [get_files ../defines/pl230_defs.v] - -set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] -set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] -set_property file_type {Verilog Header} [get_files ../defines/pl230_defs.v] +#set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest +#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v +#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v + +#add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v +#set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] +#set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] +#set_property is_global_include true [get_files ../system/sldma230_tech/src/defines/pl230_defs.v] + +#set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] +#set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] +#set_property file_type {Verilog Header} [get_files ../system/sldma230_tech/src/defines/pl230_defs.v] + +#add_files -norecurse -scan_for_includes add_files $importDir/fpga_pinmap.xdc -- GitLab