diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..adb53875ffe7496c66088618f1c876ecb4338702
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,18 @@
+# Exclude Simulation Files
+/Cortex-M0/nanosoc/systems/mcu/rtl_sim*
+/Cortex-M0/nanosoc/systems/mcu/testcodes/*/*
+
+# Exclude Compiled Binaries
+/Cortex-M0/nanosoc/software/*/*.elf
+/Cortex-M0/nanosoc/software/*/*.hex
+/Cortex-M0/nanosoc/software/*/*.lst
+/Cortex-M0/nanosoc/software/*/*.o
+
+/Cortex-M0/nanosoc/systems/mcu/testcodes/*.elf
+/Cortex-M0/nanosoc/systems/mcu/testcodes/*.hex
+/Cortex-M0/nanosoc/systems/mcu/testcodes/*.lst
+/Cortex-M0/nanosoc/systems/mcu/testcodes/*.o
+
+!/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
+!/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
+!/Cortex-M0/nanosoc/systems/mcu/rtl_sim/*.py
diff --git a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
index bafff8790d0ca4524cd0d9d091bbc5d68c2bed49..ac25da9bfa2013c1126f16acc316f8eaf8ffdc4a 100644
--- a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
@@ -6,7 +6,7 @@
#
# David Flynn (d.w.flynn@soton.ac.uk)
#
-# Copyright � 2021-3, SoC Labs (www.soclabs.org)
+# Copyright � 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
@@ -46,7 +46,7 @@ TEST_LIST = hello dhry sleep_demo interrupt_demo dualtimer_demo \
self_reset_demo watchdog_demo rtx_demo gpio_tests timer_tests \
uart_tests debug_tests default_slaves_tests dma_tests \
gpio_driver_tests uart_driver_tests timer_driver_tests apb_mux_tests \
- memory_tests romtable_tests aes128_tests
+ memory_tests romtable_tests
# Default to DS-5 tool-chain
TOOL_CHAIN = ds5
@@ -66,6 +66,7 @@ TOOL_CHAIN = ds5
# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h
#DF#CPU_PRODUCT = CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
+DMA_PRODUCT = DMA_230
# Select Verilog Command File based on CPU type
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
@@ -76,7 +77,8 @@ endif
# Select Verilog Command File based on CPU type
ifeq ($(CPU_PRODUCT),CORTEX_M0)
# For Cortex-M0 product users
- TBENCH_VC = ../verilog/tbench_M0.vc
+ TBENCH_VC += -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
+ DEFINES_VC = +define+CORTEX_M0 +define+USE_TARMAC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0_DS)
@@ -84,31 +86,49 @@ ifeq ($(CPU_PRODUCT),CORTEX_M0_DS)
TBENCH_VC = ../verilog/tbench_M0_DS.vc
endif
+ifeq ($(DMA_PRODUCT),DMA_230)
+ # For Cortex-M0 product users
+ TBENCH_VC += -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
+endif
+
+ACCELERATOR_VC =
+# ACCELERATOR_IP = SHA_2
-# Simulator type (mti/vcs/nc)
-SIMULATOR = mti
+# ifeq ($(ACCELERATOR_IP),SHA_2)
+# # For SHA2 Accelerator IP
+# ACCELERATOR_VC = -sv -f $(SOC_TOP_DIR)/sha-2-accelerator/flist/sha-2-accelerator_src.flist
+# ACCELERATOR_VC += -f $(SOC_TOP_DIR)/accelerator-wrapper/flist/accelerator-wrapper_src.flist
+# endif
+
+#ADP command File
+# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd
+ADP_FILE ?= $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/rtl_sim/
+ADP_PATH := $(shell realpath $(ADP_FILE))
+ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
+
+# Simulator type (mti/vcs/xm)
+SIMULATOR = xm
# MTI option
#DF#MTI_OPTIONS = -novopt
MTI_OPTIONS = -suppress 2892
-MTI_VC_OPTIONS = -f $(TBENCH_VC)
+MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
# VCS option
VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
-VCS_VC_OPTIONS = -f $(TBENCH_VC)
+VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
-# NC verilog option
-NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
-NC_VC_OPTIONS = -f $(TBENCH_VC)
+# XM verilog option
+XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
+XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# Boot Loader image
BOOTLOADER = bootloader
# Debug Tester image
DEBUGTESTER = debugtester
-
# Software make options
# - Pass onto the software makefile to define targetted CPU type
# You can append additional make options for testcode here
@@ -164,32 +184,36 @@ all_vcs : compile_vcs bootrom debugtester
fi ; \
done
-# ------- NC -----------
+# ------- XM -----------
# Compile RTL
-compile_nc :
- ncprep +overwrite $(NC_VC_OPTIONS) +debug | tee compile_nc.log
- ncvlog -work worklib -f ncvlog.args | tee -a compile_nc.log
- ncelab -mess -f ncelab.args -access +r | tee -a compile_nc.log
+compile_xm :
+ @echo ADP_FILE
+ @echo $(ADP_OPTIONS)
+ xmprep +overwrite $(DEFINES_VC) $(XM_VC_OPTIONS) +debug | tee compile_xm.log
+ xmvlog -work worklib -f xmvlog.args | tee -a compile_xm.log
+ xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
-# Note : If coverage is required, you can add -coverage all to ncelab
+# Note : If coverage is required, you can add -coverage all to xmelab
# Run simulation in batch mode
-run_nc : code
+run_xm : code
@if [ ! -d logs ] ; then \
mkdir logs; \
fi
@echo run > run.tcl.tmp
@echo exit >> run.tcl.tmp
@mv run.tcl.tmp run.tcl
- ncsim $(NCSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
+ xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
+ @make verify
# Run simulation in interactive mode
-sim_nc : code
- ncsim -gui $(NCSIM_OPTIONS)
+sim_xm : code
+ xmsim -gui $(XMSIM_OPTIONS)
+ @make verify
# Compile RTL, and run all tests in batch mode
-all_nc : compile_nc bootrom debugtester
+all_xm : compile_xm bootrom debugtester
@if [ ! -d logs ] ; then \
mkdir logs; \
fi
@@ -201,12 +225,13 @@ all_nc : compile_nc bootrom debugtester
echo $$thistest ; \
make testcode TESTNAME=$$thistest ;\
if [ -e image.hex ] ; then \
- ncsim $(NCSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
+ xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\
else \
echo Cannot read image.hex ;\
exit 1; \
fi ; \
done
+ @make verify
# ------- MTI -----------
@@ -408,6 +433,10 @@ clean_code:
@(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; )
@(cd ../testcodes/$(TESTNAME) ; make clean; cd ../../rtl_sim; )
+# ----- verification ------
+verify:
+ @python3 $(PROJECT_DIR)/flow/adp_verify.py
+
# ------- clean -----------
# Remove RTL compile files, log files, software compile files
@@ -430,15 +459,6 @@ clean : clean_all_code
@if [ -e ft1248_op.log ] ; then \
rm ft1248_op.log ; \
fi
- @if [ -e ft1248_out.log ] ; then \
- rm ft1248_out.log ; \
- fi
- @if [ -e dma230.log ] ; then \
- rm dma230.log ; \
- fi
- @if [ -e aes128.log ] ; then \
- rm aes128.log ; \
- fi
@if [ -e uart.log ] ; then \
rm uart.log ; \
fi
@@ -487,8 +507,8 @@ clean : clean_all_code
@if [ -e compile_vcs.log ] ; then \
rm compile_vcs.log ; \
fi
- @if [ -e compile_nc.log ] ; then \
- rm compile_nc.log ; \
+ @if [ -e compile_xm.log ] ; then \
+ rm compile_xm.log ; \
fi
@if [ -e transcript ] ; then \
rm transcript ; \
@@ -505,9 +525,6 @@ clean : clean_all_code
@if [ -e inter.vpd ] ; then \
rm -rf inter.vpd ; \
fi
- @if [ -e vsim.cmd ] ; then \
- rm -rf vsim.cmd ; \
- fi
@if [ -e quit.do ] ; then \
rm -rf quit.do ; \
fi
@@ -526,35 +543,35 @@ clean : clean_all_code
@if [ -e hdl.var ] ; then \
rm -rf hdl.var ; \
fi
- @if [ -e ncelab.args ] ; then \
- rm -rf ncelab.args ; \
+ @if [ -e xmelab.args ] ; then \
+ rm -rf xmelab.args ; \
fi
- @if [ -e ncvlog.args ] ; then \
- rm -rf ncvlog.args ; \
+ @if [ -e xmvlog.args ] ; then \
+ rm -rf xmvlog.args ; \
fi
- @if [ -e ncsim.args ] ; then \
- rm -rf ncsim.args ; \
+ @if [ -e xmsim.args ] ; then \
+ rm -rf xmsim.args ; \
fi
- @if [ -e ncprep.log ] ; then \
- rm -rf ncprep.log ; \
+ @if [ -e xmprep.log ] ; then \
+ rm -rf xmprep.log ; \
fi
- @if [ -e ncelab.log ] ; then \
- rm -rf ncelab.log ; \
+ @if [ -e xmelab.log ] ; then \
+ rm -rf xmelab.log ; \
fi
- @if [ -e ncvlog.log ] ; then \
- rm -rf ncvlog.log ; \
+ @if [ -e xmvlog.log ] ; then \
+ rm -rf xmvlog.log ; \
fi
- @if [ -e ncsim.log ] ; then \
- rm -rf ncsim.log ; \
+ @if [ -e xmsim.log ] ; then \
+ rm -rf xmsim.log ; \
fi
@if [ -e run.tcl ] ; then \
rm -rf run.tcl ; \
fi
- @if [ -e RUN_NC ] ; then \
- rm -rf RUN_NC ; \
+ @if [ -e RUN_XM ] ; then \
+ rm -rf RUN_XM ; \
fi
- @if [ -e ncsim.key ] ; then \
- rm -rf ncsim.key ; \
+ @if [ -e xmsim.key ] ; then \
+ rm -rf xmsim.key ; \
fi
@if [ -e cds.lib ] ; then \
rm -rf cds.lib ; \
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
index 11126d04a91d53c1ddbc7654fb3f0148e55cc28e..d1991c97c983d14fa7444a8acd1fd660128527f9 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -833,36 +833,62 @@ localparam CORTEX_M0 = 1;
//
// ************************************************
- wire aes128_ip_req;
- wire aes128_op_req;
- wire aes128_irq;
-
- soclabs_ahb_aes128_ctrl u_exp_aes128 (
- .ahb_hclk (HCLK),
- .ahb_hresetn (HRESETn),
- .ahb_hsel (HSEL_exp),
- .ahb_haddr16 (HADDR_exp[15:0]),
- .ahb_htrans (HTRANS_exp),
- .ahb_hwrite (HWRITE_exp),
- .ahb_hsize (HSIZE_exp),
-// .ahb_hburst (HBURST_exp),
- .ahb_hprot (HPROT_exp),
- .ahb_hwdata (HWDATA_exp),
-// .ahb_hmastlock (HMASTLOCK_exp),
- .ahb_hready (HREADYMUX_exp),
- .ahb_hrdata (HRDATA_exp),
- .ahb_hreadyout (HREADYOUT_exp),
- .ahb_hresp (HRESP_exp),
- .drq_ipdma128 (aes128_ip_req),
- .dlast_ipdma128 (1'b0),
- .drq_opdma128 (aes128_op_req),
- .dlast_opdma128 (1'b0),
- .irq_key128 (exp_irq0),
- .irq_ip128 (exp_irq1),
- .irq_op128 (exp_irq2),
- .irq_error (exp_irq3),
- .irq_merged (aes128_irq)
- );
+ wire exp_ip_req;
+ wire exp_op_req;
+ wire exp_irq;
+
+//----------------------------------------
+// Expansion Region "exp" instance
+//----------------------------------------
+
+nanosoc_exp #(.ADDRWIDTH(29)
+) u_nanosoc_exp (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input slave port: 32 bit data bus interface
+ .HSELS (HSEL_exp),
+ .HADDRS (HADDR_exp[28:0]),
+ .HTRANSS (HTRANS_exp),
+ .HSIZES (HSIZE_exp),
+ .HPROTS (HPROTS_exp),
+ .HWRITES (HWRITE_exp),
+ .HREADYS (HREADYMUX_exp),
+ .HWDATAS (HWDATA_exp),
+
+ .HREADYOUTS (HREADYOUT_exp),
+ .HRESPS (HRESP_exp),
+ .HRDATAS (HRDATA_exp),
+ .ip_data_req (exp_ip_req),
+ .op_data_req (exp_op_req)
+);
+
+// soclabs_ahb_aes128_ctrl u_exp_aes128 (
+// .ahb_hclk (HCLK),
+// .ahb_hresetn (HRESETn),
+// .ahb_hsel (HSEL_exp),
+// .ahb_haddr16 (HADDR_exp[15:0]),
+// .ahb_htrans (HTRANS_exp),
+// .ahb_hwrite (HWRITE_exp),
+// .ahb_hsize (HSIZE_exp),
+// // .ahb_hburst (HBURST_exp),
+// .ahb_hprot (HPROT_exp),
+// .ahb_hwdata (HWDATA_exp),
+// // .ahb_hmastlock (HMASTLOCK_exp),
+// .ahb_hready (HREADYMUX_exp),
+// .ahb_hrdata (HRDATA_exp),
+// .ahb_hreadyout (HREADYOUT_exp),
+// .ahb_hresp (HRESP_exp),
+// .drq_ipdma128 (aes128_ip_req),
+// .dlast_ipdma128 (1'b0),
+// .drq_opdma128 (aes128_op_req),
+// .dlast_opdma128 (1'b0),
+// .irq_key128 (exp_irq0),
+// .irq_ip128 (exp_irq1),
+// .irq_op128 (exp_irq2),
+// .irq_error (exp_irq3),
+// .irq_merged (aes128_irq)
+// );
// // Default slave
// cmsdk_ahb_default_slave u_ahb_exp (
@@ -1260,8 +1286,8 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
wire [DMA_CHANNEL_NUM-1:0] dma230_req; // tie off signal.
wire [DMA_CHANNEL_NUM-1:0] dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
- assign dma230_req[0] = aes128_ip_req;
- assign dma230_req[1] = aes128_op_req;
+ assign dma230_req[0] = exp_ip_req;
+ assign dma230_req[1] = exp_op_req;
// DMA done per channel