From e5d443b8cf27728462a36fea60cde2a7191e44ba Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 6 Jul 2023 17:03:19 +0100
Subject: [PATCH] Created Basic Cocotb ADP Read Test
---
verif/cocotb/test_adp.py | 79 ++++++++++++++++++++++++++++++++
verif/cocotb/test_chip.py | 47 -------------------
verif/tb/verilog/nanosoc_tb.v | 42 ++++++++---------
verif/tb/verilog/nanosoc_tb_qs.v | 42 ++++++++---------
4 files changed, 121 insertions(+), 89 deletions(-)
create mode 100644 verif/cocotb/test_adp.py
delete mode 100644 verif/cocotb/test_chip.py
diff --git a/verif/cocotb/test_adp.py b/verif/cocotb/test_adp.py
new file mode 100644
index 0000000..64f2857
--- /dev/null
+++ b/verif/cocotb/test_adp.py
@@ -0,0 +1,79 @@
+from random import randint, randrange, getrandbits, shuffle
+from collections.abc import Iterable
+
+import logging
+import cocotb
+from cocotb.clock import Clock
+from cocotb.regression import TestFactory
+from cocotb.result import TestFailure
+from cocotb.triggers import ClockCycles, Combine, Join, RisingEdge
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor
+
+CLK_PERIOD = (10, "ns")
+
+# Class for ADP AXI Stream Interface
+class ADPDriver ():
+ def __init__(self, send, recieve):
+ # Send Stream to NanoSoC
+ self.send = send
+ # Send Recieve to NanoSoC
+ self.recieve = recieve
+
+# Control ADP AXI Stream bus and create ADP Driver Object
+def setup_adp(dut):
+ adp_sender = AxiStreamSource(AxiStreamBus.from_prefix(dut, "txd8"), dut.XTAL1, dut.NRST)
+ adp_reciever = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rxd8"), dut.XTAL1, dut.NRST)
+ driver = ADPDriver(adp_sender, adp_reciever)
+ return driver
+
+# Start Clocks and Reset System
+@cocotb.coroutine
+async def setup_dut(dut):
+ cocotb.start_soon(Clock(dut.XTAL1, *CLK_PERIOD).start())
+ dut.NRST.value = 0
+ await ClockCycles(dut.XTAL1, 2)
+ dut.NRST.value = 1
+ await ClockCycles(dut.XTAL1, 2)
+
+@cocotb.coroutine
+async def write(driver, buf):
+ wr_count = 0
+ for i in buf:
+ print(i)
+ await driver.tx.send(str(ord(i)))
+ return wr_count
+
+# Basic Test Clocks Test
+@cocotb.test()
+async def test_clocks(dut):
+ """Tests Clocks and Resets in Cocotb"""
+ log = logging.getLogger(f"cocotb.test")
+ await setup_dut(dut)
+ log.info("Setup Complete")
+
+# Basic Test Reading from ADP
+@cocotb.test()
+async def test_driver(dut):
+ """Tests ADP Driver"""
+ log = logging.getLogger(f"cocotb.test")
+ await setup_dut(dut)
+ adp_driver = setup_adp(dut)
+ logging.getLogger("cocotb.nanosoc_tb.rxd8").setLevel(logging.WARNING)
+ log.info("Setup Complete")
+ log.info("Starting Test")
+ temp_str = ""
+ while True:
+ # Read Bytes from ADP AXI Stream
+ data = await adp_driver.recieve.read()
+ curr_char = chr(data[0])
+ # Combine Bytes into Strings and Print Out
+ if (curr_char == '\n'):
+ log.info(temp_str)
+ # Exit Test on Last String
+ if temp_str == "** Remap->IMEM0":
+ break
+ temp_str = ""
+ else:
+ temp_str += curr_char
+ log.info("Driver Test Complete")
diff --git a/verif/cocotb/test_chip.py b/verif/cocotb/test_chip.py
deleted file mode 100644
index 766ee50..0000000
--- a/verif/cocotb/test_chip.py
+++ /dev/null
@@ -1,47 +0,0 @@
-from random import randint, randrange, getrandbits, shuffle
-from collections.abc import Iterable
-
-import logging
-import cocotb
-from cocotb.clock import Clock
-from cocotb.regression import TestFactory
-from cocotb.result import TestFailure
-from cocotb.triggers import ClockCycles, Combine, Join, RisingEdge
-
-from cocotbext.axi import AxiBus, AxiMaster
-
-CLK_PERIOD = (10, "ns")
-AXI_PREFIX = "S_AXI"
-
-async def setup_dut(dut):
- cocotb.start_soon(Clock(dut.XTAL1, *CLK_PERIOD).start())
- dut.NRST.value = 0
- await ClockCycles(dut.XTAL1, 2)
- dut.NRST.value = 1
- await ClockCycles(dut.XTAL1, 2)
-
-def binatodeci(binary):
- return sum(val*(2**idx) for idx, val in enumerate(reversed(binary)))
-
-@cocotb.coroutine
-async def reg_write(manager, register, data):
- print("Writing address: "+str(register.address))
- await manager.write(register.address, data)
-
-@cocotb.coroutine
-async def reg_read(manager, register, length = 1):
- event = manager.init_read(register.address, length)
- await event.wait()
- return event.data.data
-
-@cocotb.coroutine
-async def field_read(manager, register, field, length = 1):
- reg_read_val = await reg_read(manager, register, length)
- return getattr(register, field).decode_read_value(binatodeci(reg_read_val))
-
-
-@cocotb.test()
-async def test_clocks(dut):
- """Tests Clocks and Resets in Cocotb"""
- await setup_dut(dut)
- print("Setup Complete")
\ No newline at end of file
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index c7be34f..adf6e25 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -261,13 +261,13 @@ reg baud_clk_del;
// AXI stream io testing
//
- wire txd8_ready;
- wire txd8_valid;
- wire [7:0] txd8_data ;
+ wire txd8_tready;
+ wire txd8_tvalid;
+ wire [7:0] txd8_tdata ;
- wire rxd8_ready;
- wire rxd8_valid;
- wire [7:0] rxd8_data ;
+ wire rxd8_tready;
+ wire rxd8_tvalid;
+ wire [7:0] rxd8_tdata ;
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
@@ -275,9 +275,9 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (XTAL1),
.aresetn (NRST),
- .txd8_ready (txd8_ready),
- .txd8_valid (txd8_valid),
- .txd8_data (txd8_data)
+ .txd8_ready (txd8_tready),
+ .txd8_valid (txd8_tvalid),
+ .txd8_data (txd8_tdata)
);
`endif
@@ -296,12 +296,12 @@ reg baud_clk_del;
.ft_miosio_z (ft_miosio_z),
.aclk (XTAL1),
.aresetn (NRST),
- .rxd_tready_o (txd8_ready),
- .rxd_tvalid_i (txd8_valid),
- .rxd_tdata8_i (txd8_data),
- .txd_tready_i (rxd8_ready),
- .txd_tvalid_o (rxd8_valid),
- .txd_tdata8_o (rxd8_data)
+ .rxd_tready_o (txd8_tready),
+ .rxd_tvalid_i (txd8_tvalid),
+ .rxd_tdata8_i (txd8_tdata),
+ .txd_tready_i (rxd8_tready),
+ .txd_tvalid_o (rxd8_tvalid),
+ .txd_tdata8_o (rxd8_tdata)
);
`ifndef COCOTB_SIM
@@ -310,9 +310,9 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_rxd_to_file (
.aclk (XTAL1),
.aresetn (NRST),
- .rxd8_ready (rxd8_ready),
- .rxd8_valid (rxd8_valid),
- .rxd8_data (rxd8_data)
+ .rxd8_ready (rxd8_tready),
+ .rxd8_valid (rxd8_tvalid),
+ .rxd8_data (rxd8_tdata)
);
`endif
@@ -321,9 +321,9 @@ nanosoc_track_tb_iostream
(
.aclk (XTAL1),
.aresetn (NRST),
- .rxd8_ready (rxd8_ready),
- .rxd8_valid (rxd8_valid),
- .rxd8_data (rxd8_data),
+ .rxd8_ready (rxd8_tready),
+ .rxd8_valid (rxd8_tvalid),
+ .rxd8_data (rxd8_tdata),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.AUXCTRL ( ),
.SIMULATIONEND( )
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index d52dfde..e8aabe9 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -261,13 +261,13 @@ reg baud_clk_del;
// AXI stream io testing
//
- wire txd8_ready;
- wire txd8_valid;
- wire [7:0] txd8_data ;
+ wire txd8_tready;
+ wire txd8_tvalid;
+ wire [7:0] txd8_tdata ;
- wire rxd8_ready;
- wire rxd8_valid;
- wire [7:0] rxd8_data ;
+ wire rxd8_tready;
+ wire rxd8_tvalid;
+ wire [7:0] rxd8_tdata ;
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
@@ -275,9 +275,9 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (XTAL1),
.aresetn (NRST),
- .txd8_ready (txd8_ready),
- .txd8_valid (txd8_valid),
- .txd8_data (txd8_data)
+ .txd8_ready (txd8_tready),
+ .txd8_valid (txd8_tvalid),
+ .txd8_data (txd8_tdata)
);
`endif
@@ -296,12 +296,12 @@ reg baud_clk_del;
.ft_miosio_z (ft_miosio_z),
.aclk (XTAL1),
.aresetn (NRST),
- .rxd_tready_o (txd8_ready),
- .rxd_tvalid_i (txd8_valid),
- .rxd_tdata8_i (txd8_data),
- .txd_tready_i (rxd8_ready),
- .txd_tvalid_o (rxd8_valid),
- .txd_tdata8_o (rxd8_data)
+ .rxd_tready_o (txd8_tready),
+ .rxd_tvalid_i (txd8_tvalid),
+ .rxd_tdata8_i (txd8_tdata),
+ .txd_tready_i (rxd8_tready),
+ .txd_tvalid_o (rxd8_tvalid),
+ .txd_tdata8_o (rxd8_tdata)
);
`ifndef COCOTB_SIM
@@ -310,9 +310,9 @@ reg baud_clk_del;
) u_nanosoc_axi_stream_io_8_rxd_to_file (
.aclk (XTAL1),
.aresetn (NRST),
- .rxd8_ready (rxd8_ready),
- .rxd8_valid (rxd8_valid),
- .rxd8_data (rxd8_data)
+ .rxd8_ready (rxd8_tready),
+ .rxd8_valid (rxd8_tvalid),
+ .rxd8_data (rxd8_tdata)
);
`endif
@@ -321,9 +321,9 @@ nanosoc_track_tb_iostream
(
.aclk (XTAL1),
.aresetn (NRST),
- .rxd8_ready (rxd8_ready),
- .rxd8_valid (rxd8_valid),
- .rxd8_data (rxd8_data),
+ .rxd8_ready (rxd8_tready),
+ .rxd8_valid (rxd8_tvalid),
+ .rxd8_data (rxd8_tdata),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.AUXCTRL ( ),
.SIMULATIONEND( )
--
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