From d2f406db6909cf8d6627ad1ae7070dc12229b3a7 Mon Sep 17 00:00:00 2001 From: Daniel Newbrook <dwn1c21@soton.ac.uk> Date: Fri, 15 Dec 2023 09:03:22 +0000 Subject: [PATCH] Add sdf write out for synthesis --- ASIC/28pin/Cadence/scripts/genus.tcl | 2 ++ ASIC/44pin/Cadence/scripts/genus.tcl | 33 +++++++++++++++++++++++----- ASIC/60pin/Cadence/scripts/genus.tcl | 2 ++ 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/ASIC/28pin/Cadence/scripts/genus.tcl b/ASIC/28pin/Cadence/scripts/genus.tcl index ceef0ea..cdd5fa7 100644 --- a/ASIC/28pin/Cadence/scripts/genus.tcl +++ b/ASIC/28pin/Cadence/scripts/genus.tcl @@ -61,6 +61,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_ write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.v write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pins.vp +write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.sdf + #report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains.rep #report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup.rep #report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers.rep diff --git a/ASIC/44pin/Cadence/scripts/genus.tcl b/ASIC/44pin/Cadence/scripts/genus.tcl index a163ff8..0f76169 100644 --- a/ASIC/44pin/Cadence/scripts/genus.tcl +++ b/ASIC/44pin/Cadence/scripts/genus.tcl @@ -1,3 +1,18 @@ +#----------------------------------------------------------------------------- +# NanoSoC gate synthesis script for Cadence Genus +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# run: genus -f genus.tcl +# Contributors +# +# Daniel Newbrook (d.newbrook@soton.ac.uk) +# David Flynn (d.w.flynn@soton.ac.uk) +# Srimanth Tenneti +# +# Copyright (C) 2023, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +## -- Setup libraries -- ## set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/" set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib @@ -6,19 +21,25 @@ set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib create_library_domain domain1 set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER" +## -- Load power intent for top and accelerator power domains -- ## read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf +## -- Uncomment if you want to preserve hierarchy -- ## +#set_db auto_ungroup none + +## -- Read in RTL and elaborate top level source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl +read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v elaborate nanosoc_chip_pads +## -- Apply power intent and check library and CPF -- ## apply_power_intent -check_library > lib_check.log - -check_cpf - +check_library > syn_lib_check.log +check_cpf > syn_cpf_check.log commit_power_intent -check_power_structure -license lpgxl +check_power_structure -license lpgxl > syn_pow_check.log +## -- Read constraints -- ## read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc #set_db dft_scan_style muxed_scan @@ -60,6 +81,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_ write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp +write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.sdf + #report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep #report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep #report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep diff --git a/ASIC/60pin/Cadence/scripts/genus.tcl b/ASIC/60pin/Cadence/scripts/genus.tcl index 9ba96a2..f14ee75 100644 --- a/ASIC/60pin/Cadence/scripts/genus.tcl +++ b/ASIC/60pin/Cadence/scripts/genus.tcl @@ -60,6 +60,8 @@ report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_powe write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vm write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vp +write_sdf -timescale ns > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.sdf + report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_60pin.rep report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_60pin.rep report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_60pin.rep -- GitLab