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Commit cd36ea27 authored by dam1n19's avatar dam1n19
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SOC1-230: Wired in PL230 to DMA Subsystem

parent 9e7a5d1d
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+ 121
− 33
View file @ cd36ea27
......@@ -12,41 +12,129 @@
module nanosoc_ss_dma #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter DMA_0_CFG_ADDR_W = 12, // DMAC 0 Configuration Port Address Width
parameter DMA_1_CFG_ADDR_W = 0, // DMAC 1 Configuration Port Address Width
parameter DMA_0_CHANNEL_NUM = 2, // DMAC 0 Number of DMA Channels
parameter DMA_1_CHANNEL_NUM = 0 // DMAC 1 Number of DMA Channels
parameter DMAC_0_CFG_ADDR_W = 12, // DMAC 0 Configuration Port Address Width
parameter DMAC_1_CFG_ADDR_W = 12, // DMAC 1 Configuration Port Address Width
parameter DMAC_0_CHANNEL_NUM = 2, // DMAC 0 Number of DMA Channels
parameter DMAC_1_CHANNEL_NUM = 2 // DMAC 1 Number of DMA Channels
)(
// AHB Clocks and Resets
// System AHB Clocks and Resets
input wire SYS_HCLK,
input wire SYS_HRESETn,
// DMAC 0 AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMAC_0_HADDR, // Address bus
output wire [1:0] DMAC_0_HTRANS, // Transfer type
output wire DMAC_0_HWRITE, // Transfer direction
output wire [2:0] DMAC_0_HSIZE, // Transfer size
output wire [2:0] DMAC_0_HBURST, // Burst type
output wire [3:0] DMAC_0_HPROT, // Protection control
output wire [SYS_DATA_W-1:0] DMAC_0_HWDATA, // Write data
output wire DMAC_0_HMASTLOCK, // Locked Sequence
input wire [SYS_DATA_W-1:0] DMAC_0_HRDATA, // Read data bus
input wire DMAC_0_HREADY, // HREADY feedback
input wire DMAC_0_HRESP, // Transfer response
// DMAC 0 APB Configurtation Port
input wire DMAC_0_PCLKEN, // APB clock enable
input wire DMAC_0_PSEL, // APB peripheral select
input wire DMAC_0_PEN, // APB transfer enable
input wire DMAC_0_PWRITE, // APB transfer direction
input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data
// DMAC 0 DMA Request and Status Port
input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request
output wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_DONE, // DMA transfer done
output wire DMAC_0_DMA_ERR, // DMA slave response not OK
// DMAC 1 AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMAC_1_HADDR, // Address bus
output wire [1:0] DMAC_1_HTRANS, // Transfer type
output wire DMAC_1_HWRITE, // Transfer direction
output wire [2:0] DMAC_1_HSIZE, // Transfer size
output wire [2:0] DMAC_1_HBURST, // Burst type
output wire [3:0] DMAC_1_HPROT, // Protection control
output wire [SYS_DATA_W-1:0] DMAC_1_HWDATA, // Write data
output wire DMAC_1_HMASTLOCK, // Locked Sequence
input wire [SYS_DATA_W-1:0] DMAC_1_HRDATA, // Read data bus
input wire DMAC_1_HREADY, // HREADY feedback
input wire DMAC_1_HRESP, // Transfer response
// DMAC 1 APB Configurtation Port
input wire DMAC_1_PCLKEN, // APB clock enable
input wire DMAC_1_PSEL, // APB peripheral select
input wire DMAC_1_PEN, // APB transfer enable
input wire DMAC_1_PWRITE, // APB transfer direction
input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
// DMAC 1 DMA Request and Status Port
input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
output wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE, // DMA transfer done
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
// -------------------------------
// DMA Controller 0 Instantiation
// -------------------------------
sldmac230 #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
.CFG_ADDR_W (CFG_ADDR_W),
.CHANNEL_NUM (DMAC_0_CHANNEL_NUM)
) u_dmac_0 (
// AHB Clocks and Resets
.HCLK(DMAC_0_HCLK),
.HRESETn(DMAC_0_HRESETn),
// AHB Lite Port
output wire [SYS_ADDR_W-1:0] DMA_0_HADDR, // Address bus
output wire [1:0] DMA_0_HTRANS, // Transfer type
output wire DMA_0_HWRITE, // Transfer direction
output wire [2:0] DMA_0_HSIZE, // Transfer size
output wire [2:0] DMA_0_HBURST, // Burst type
output wire [3:0] DMA_0_HPROT, // Protection control
output wire [SYS_DATA_W-1:0] DMA_0_HWDATA, // Write data
output wire DMA_0_HMASTLOCK, // Locked Sequence
input wire [SYS_DATA_W-1:0] DMA_0_HRDATA, // Read data bus
input wire DMA_0_HREADY, // HREADY feedback
input wire DMA_0_HRESP, // Transfer response
// APB Configurtation Port
input wire DMA_0_PCLKEN, // APB clock enable
input wire DMA_0_PSEL, // APB peripheral select
input wire DMA_0_PEN, // APB transfer enable
input wire DMA_0_PWRITE, // APB transfer direction
input wire [DMA_0_CFG_ADDR_W-1:0] DMA_0_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMA_0_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMA_0_PRDATA, // APB read data
.HADDR(DMAC_0_HADDR),
.HTRANS(DMAC_0_HTRANS),
.HWRITE(DMAC_0_HWRITE),
.HSIZE(DMAC_0_HSIZE),
.HBURST(DMAC_0_HBURST),
.HPROT(DMAC_0_HPROT),
.HWDATA(DMAC_0_HWDATA),
.HMASTLOCK(DMAC_0_HMASTLOCK),
.HRDATA(DMAC_0_HRDATA),
.HREADY(DMAC_0_HREADY),
.HRESP(DMAC_0_HRESP),
// APB Configuration Port
.PCLKEN(DMAC_0_PCLKEN),
.PSEL(DMAC_0_PSEL),
.PEN(DMAC_0_PEN),
.PWRITE(DMAC_0_PWRITE),
.PADDR(DMAC_0_PADDR),
.PWDATA(DMAC_0_PWDATA),
.PRDATA(DMAC_0_PRDATA),
// DMA Request and Status Port
input wire [DMA_0_CHANNEL_NUM-1:0] DMA_0_DMA_REQ, // DMA transfer request
output wire [DMA_0_CHANNEL_NUM-1:0] DMA_0_DMA_DONE, // DMA transfer done
output wire DMA_0_DMA_ERR // DMA slave response not OK
.DMA_REQ(DMAC_0_DMA_REQ),
.DMA_DONE(DMAC_0_DMA_DONE),
.DMA_ERR(DMAC_0_DMA_ERR)
);
// -------------------------------
// DMA Controller 1 Instantiation - Not implemented
// -------------------------------
// AHB Tie-off signals
assign DMAC_1_HADDR = 32'b0;
assign DMAC_1_HTRANS = 2'b0;
assign DMAC_1_HWRITE = 1'b0;
assign DMAC_1_HSIZE = 3'b0;
assign DMAC_1_HBURST = 3'b0;
assign DMAC_1_HPROT = 4'0;
assign DMAC_1_HWDATA = 32'b0;
assign DMAC_1_HMASTLOCK = 1'b0;
// APB Tie-off signals
assign DMAC_1_PRDATA = 32'b0;
// DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = 0;
assign DMAC_1_DMA_ERR = 0;
endmodule
\ No newline at end of file
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