diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
index 5cb3abc76865723fb378458365bb5eb19069116c..fb2712d2cabcc05959b092c88c1f91bab9809612 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -192,12 +192,12 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Slave__DMA_0</spirit:name>
- <spirit:description>Slave port _DMA_0</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_0</spirit:name>
+ <spirit:description>Slave port _DMAC_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMA_0_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
@@ -233,7 +233,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_DMA_0</spirit:name>
+ <spirit:name>HSEL_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -241,7 +241,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMA_0</spirit:name>
+ <spirit:name>HADDR_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -249,7 +249,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMA_0</spirit:name>
+ <spirit:name>HTRANS_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -257,7 +257,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMA_0</spirit:name>
+ <spirit:name>HWRITE_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -265,7 +265,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMA_0</spirit:name>
+ <spirit:name>HSIZE_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -273,7 +273,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMA_0</spirit:name>
+ <spirit:name>HBURST_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -281,18 +281,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMA_0</spirit:name>
+ <spirit:name>HPROT_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_DMA_0 unmapped -->
+ <!-- HMASTER_DMAC_0 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMA_0</spirit:name>
+ <spirit:name>HWDATA_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -300,7 +300,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMA_0</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -308,7 +308,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_DMA_0</spirit:name>
+ <spirit:name>HREADY_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -318,7 +318,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMA_0</spirit:name>
+ <spirit:name>HRDATA_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -326,7 +326,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_DMA_0</spirit:name>
+ <spirit:name>HREADYOUT_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -334,7 +334,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMA_0</spirit:name>
+ <spirit:name>HRESP_DMAC_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -345,12 +345,12 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Slave__DMA_1</spirit:name>
- <spirit:description>Slave port _DMA_1</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_1</spirit:name>
+ <spirit:description>Slave port _DMAC_1</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMA_1_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_1_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
@@ -386,7 +386,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_DMA_1</spirit:name>
+ <spirit:name>HSEL_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -394,7 +394,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMA_1</spirit:name>
+ <spirit:name>HADDR_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -402,7 +402,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMA_1</spirit:name>
+ <spirit:name>HTRANS_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -410,7 +410,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMA_1</spirit:name>
+ <spirit:name>HWRITE_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -418,7 +418,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMA_1</spirit:name>
+ <spirit:name>HSIZE_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -426,7 +426,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMA_1</spirit:name>
+ <spirit:name>HBURST_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -434,18 +434,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMA_1</spirit:name>
+ <spirit:name>HPROT_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_DMA_1 unmapped -->
+ <!-- HMASTER_DMAC_1 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMA_1</spirit:name>
+ <spirit:name>HWDATA_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -453,7 +453,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMA_1</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -461,7 +461,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_DMA_1</spirit:name>
+ <spirit:name>HREADY_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -471,7 +471,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMA_1</spirit:name>
+ <spirit:name>HRDATA_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -479,7 +479,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_DMA_1</spirit:name>
+ <spirit:name>HREADYOUT_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -487,7 +487,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMA_1</spirit:name>
+ <spirit:name>HRESP_DMAC_1</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -2433,8 +2433,8 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__DMA_0_MM</spirit:name>
- <spirit:description>_DMA_0 memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_0_MM</spirit:name>
+ <spirit:description>_DMAC_0 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
@@ -2509,8 +2509,8 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteTarget_Slave__DMA_1_MM</spirit:name>
- <spirit:description>_DMA_1 memory map</spirit:description>
+ <spirit:name>AHBLiteTarget_Slave__DMAC_1_MM</spirit:name>
+ <spirit:description>_DMAC_1 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
@@ -2836,13 +2836,13 @@
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_DMA_0</spirit:name>
+ <spirit:name>HSEL_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMA_0</spirit:name>
+ <spirit:name>HADDR_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2852,7 +2852,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMA_0</spirit:name>
+ <spirit:name>HTRANS_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2862,13 +2862,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMA_0</spirit:name>
+ <spirit:name>HWRITE_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMA_0</spirit:name>
+ <spirit:name>HSIZE_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2878,7 +2878,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMA_0</spirit:name>
+ <spirit:name>HBURST_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2891,7 +2891,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMA_0</spirit:name>
+ <spirit:name>HPROT_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2901,7 +2901,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_DMA_0</spirit:name>
+ <spirit:name>HMASTER_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2914,7 +2914,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMA_0</spirit:name>
+ <spirit:name>HWDATA_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2924,26 +2924,26 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMA_0</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_DMA_0</spirit:name>
+ <spirit:name>HREADY_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_DMA_1</spirit:name>
+ <spirit:name>HSEL_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMA_1</spirit:name>
+ <spirit:name>HADDR_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2953,7 +2953,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMA_1</spirit:name>
+ <spirit:name>HTRANS_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2963,13 +2963,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMA_1</spirit:name>
+ <spirit:name>HWRITE_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMA_1</spirit:name>
+ <spirit:name>HSIZE_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2979,7 +2979,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMA_1</spirit:name>
+ <spirit:name>HBURST_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2992,7 +2992,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMA_1</spirit:name>
+ <spirit:name>HPROT_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3002,7 +3002,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_DMA_1</spirit:name>
+ <spirit:name>HMASTER_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3015,7 +3015,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMA_1</spirit:name>
+ <spirit:name>HWDATA_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3025,13 +3025,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMA_1</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_DMA_1</spirit:name>
+ <spirit:name>HREADY_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
@@ -4389,7 +4389,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMA_0</spirit:name>
+ <spirit:name>HRDATA_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4399,13 +4399,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_DMA_0</spirit:name>
+ <spirit:name>HREADYOUT_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMA_0</spirit:name>
+ <spirit:name>HRESP_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4415,7 +4415,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMA_1</spirit:name>
+ <spirit:name>HRDATA_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4425,13 +4425,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_DMA_1</spirit:name>
+ <spirit:name>HREADYOUT_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMA_1</spirit:name>
+ <spirit:name>HRESP_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4501,11 +4501,11 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
index 3f0251e5af9a5a54ff8c94572ebee15f145b4bc0..e2f7c6b2210615c3ec5eb2d2d4e853cb95735e58 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -169,12 +169,12 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteInitiator_Slave__DMA_0</spirit:name>
- <spirit:description>Slave port _DMA_0</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_0</spirit:name>
+ <spirit:description>Slave port _DMAC_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMA_0_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
@@ -210,7 +210,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMA_0</spirit:name>
+ <spirit:name>HADDR_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -218,7 +218,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMA_0</spirit:name>
+ <spirit:name>HTRANS_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -226,7 +226,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMA_0</spirit:name>
+ <spirit:name>HWRITE_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -234,7 +234,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMA_0</spirit:name>
+ <spirit:name>HSIZE_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -242,7 +242,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMA_0</spirit:name>
+ <spirit:name>HBURST_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -250,7 +250,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMA_0</spirit:name>
+ <spirit:name>HPROT_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -258,7 +258,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMA_0</spirit:name>
+ <spirit:name>HWDATA_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -266,7 +266,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMA_0</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -276,7 +276,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMA_0</spirit:name>
+ <spirit:name>HRDATA_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -284,7 +284,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_DMA_0</spirit:name>
+ <spirit:name>HREADY_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -292,19 +292,19 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMA_0</spirit:name>
+ <spirit:name>HRESP_DMAC_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteInitiator_Slave__DMA_1</spirit:name>
- <spirit:description>Slave port _DMA_1</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_1</spirit:name>
+ <spirit:description>Slave port _DMAC_1</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMA_1_MM"/>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_1_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
@@ -340,7 +340,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMA_1</spirit:name>
+ <spirit:name>HADDR_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -348,7 +348,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMA_1</spirit:name>
+ <spirit:name>HTRANS_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -356,7 +356,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMA_1</spirit:name>
+ <spirit:name>HWRITE_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -364,7 +364,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMA_1</spirit:name>
+ <spirit:name>HSIZE_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -372,7 +372,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMA_1</spirit:name>
+ <spirit:name>HBURST_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -380,7 +380,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMA_1</spirit:name>
+ <spirit:name>HPROT_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -388,7 +388,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMA_1</spirit:name>
+ <spirit:name>HWDATA_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -396,7 +396,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMA_1</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -406,7 +406,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMA_1</spirit:name>
+ <spirit:name>HRDATA_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -414,7 +414,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADY_DMA_1</spirit:name>
+ <spirit:name>HREADY_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -422,7 +422,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMA_1</spirit:name>
+ <spirit:name>HRESP_DMAC_1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -2271,8 +2271,8 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__DMA_0_MM</spirit:name>
- <spirit:description>_DMA_0 memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_0_MM</spirit:name>
+ <spirit:description>_DMAC_0 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
@@ -2347,8 +2347,8 @@
</spirit:memoryMap>
<spirit:memoryMap>
- <spirit:name>AHBLiteInitiator_Slave__DMA_1_MM</spirit:name>
- <spirit:description>_DMA_1 memory map</spirit:description>
+ <spirit:name>AHBLiteInitiator_Slave__DMAC_1_MM</spirit:name>
+ <spirit:description>_DMAC_1 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
@@ -2648,7 +2648,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMA_0</spirit:name>
+ <spirit:name>HADDR_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2658,7 +2658,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMA_0</spirit:name>
+ <spirit:name>HTRANS_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2668,13 +2668,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMA_0</spirit:name>
+ <spirit:name>HWRITE_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMA_0</spirit:name>
+ <spirit:name>HSIZE_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2684,7 +2684,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMA_0</spirit:name>
+ <spirit:name>HBURST_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2697,7 +2697,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMA_0</spirit:name>
+ <spirit:name>HPROT_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2707,7 +2707,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMA_0</spirit:name>
+ <spirit:name>HWDATA_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2717,13 +2717,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMA_0</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMA_1</spirit:name>
+ <spirit:name>HADDR_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2733,7 +2733,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMA_1</spirit:name>
+ <spirit:name>HTRANS_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2743,13 +2743,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMA_1</spirit:name>
+ <spirit:name>HWRITE_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMA_1</spirit:name>
+ <spirit:name>HSIZE_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2759,7 +2759,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMA_1</spirit:name>
+ <spirit:name>HBURST_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2772,7 +2772,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMA_1</spirit:name>
+ <spirit:name>HPROT_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2782,7 +2782,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMA_1</spirit:name>
+ <spirit:name>HWDATA_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2792,7 +2792,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMA_1</spirit:name>
+ <spirit:name>HMASTLOCK_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
@@ -3979,7 +3979,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMA_0</spirit:name>
+ <spirit:name>HRDATA_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3989,19 +3989,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_DMA_0</spirit:name>
+ <spirit:name>HREADY_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMA_0</spirit:name>
+ <spirit:name>HRESP_DMAC_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMA_1</spirit:name>
+ <spirit:name>HRDATA_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -4011,13 +4011,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADY_DMA_1</spirit:name>
+ <spirit:name>HREADY_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMA_1</spirit:name>
+ <spirit:name>HRESP_DMAC_1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
@@ -4083,11 +4083,11 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/logs/nanosoc.log b/system/nanosoc_busmatrix/logs/nanosoc.log
index dd5b2f7836d30cb7fd29059cb2ada60bab8d8e86..68f64e8cce3a5c2d8a55fc58e239ee5e542a3a66 100644
--- a/system/nanosoc_busmatrix/logs/nanosoc.log
+++ b/system/nanosoc_busmatrix/logs/nanosoc.log
@@ -14,7 +14,7 @@
=
= BuildBusMatrix.pl
=
-= Run Date : 04/06/2023 08:53:53
+= Run Date : 04/06/2023 13:16:41
==============================================================
Script accepted the following parameters:
@@ -27,8 +27,8 @@ Script accepted the following parameters:
- Arbitration scheme : 'burst'
- Address map : user defined
- Connectivity mapping : _SOCDEBUG -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
- _DMA_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
- _DMA_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
_CPU_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
- Connectivity type : sparse
- Routing data width : 32
@@ -55,7 +55,7 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v' file...
@@ -75,36 +75,36 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Creating the bus matrix variant...
- - Rendering 'nanosoc_busmatrix_lite.v'
- - Rendering 'nanosoc_busmatrix.v'
- - Rendering 'nanosoc_busmatrix.xml'
- - Rendering 'nanosoc_matrix_decode_DMA_0.v'
- - Rendering 'nanosoc_target_output_EXPRAM_H.v'
- - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_busmatrix_lite.xml'
+ - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_arbiter_IMEM.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_0.v'
+ - Rendering 'nanosoc_target_output_BOOTROM.v'
- Rendering 'nanosoc_arbiter_BOOTROM.v'
- - Rendering 'nanosoc_arbiter_EXP_1.v'
- - Rendering 'nanosoc_target_output_EXP_1.v'
- - Rendering 'nanosoc_target_output_IMEM.v'
- - Rendering 'nanosoc_inititator_input.v'
+ - Rendering 'nanosoc_target_output_SYSTABLE.v'
- Rendering 'nanosoc_target_output_EXP_2.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- - Rendering 'nanosoc_target_output_SYSIO.v'
+ - Rendering 'nanosoc_inititator_input.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
+ - Rendering 'nanosoc_target_output_IMEM.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_L.v'
+ - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_target_output_EXP_1.v'
+ - Rendering 'nanosoc_target_output_DMEM.v'
+ - Rendering 'nanosoc_target_output_EXP_0.v'
- Rendering 'nanosoc_matrix_decode_CPU_0.v'
- - Rendering 'nanosoc_target_output_BOOTROM.v'
- - Rendering 'nanosoc_arbiter_DMEM.v'
- - Rendering 'nanosoc_arbiter_IMEM.v'
- - Rendering 'nanosoc_busmatrix_default_slave.v'
- - Rendering 'nanosoc_target_output_SYSTABLE.v'
+ - Rendering 'nanosoc_matrix_decode_SOCDEBUG.v'
- Rendering 'nanosoc_arbiter_SYSIO.v'
- - Rendering 'nanosoc_busmatrix_lite.xml'
- - Rendering 'nanosoc_target_output_DMEM.v'
- Rendering 'nanosoc_arbiter_EXP_2.v'
- - Rendering 'nanosoc_target_output_EXP_0.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
- - Rendering 'nanosoc_target_output_EXPRAM_L.v'
- Rendering 'nanosoc_arbiter_EXP_0.v'
- - Rendering 'nanosoc_matrix_decode_DMA_1.v'
- - Rendering 'nanosoc_matrix_decode_SOCDEBUG.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
+ - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_target_output_EXPRAM_H.v'
+ - Rendering 'nanosoc_arbiter_EXP_1.v'
+ - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_busmatrix.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
+ - Rendering 'nanosoc_arbiter_DMEM.v'
+ - Rendering 'nanosoc_target_output_SYSIO.v'
Done!
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index 80980b19e22e9fbaa5c15febf32a3d09eafd54dd..baa99937bbaf742b3cc3a30787d8837be0753e51 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -36,8 +36,8 @@
// - Arbiter type 'burst',
// - Connectivity mapping:
// _SOCDEBUG -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
-// _DMA_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
-// _DMA_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
// _CPU_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// - Connectivity type 'sparse'.
//
@@ -68,30 +68,30 @@ module nanosoc_busmatrix (
HREADY_SOCDEBUG,
// Input port SI1 (inputs from master 1)
- HSEL_DMA_0,
- HADDR_DMA_0,
- HTRANS_DMA_0,
- HWRITE_DMA_0,
- HSIZE_DMA_0,
- HBURST_DMA_0,
- HPROT_DMA_0,
- HMASTER_DMA_0,
- HWDATA_DMA_0,
- HMASTLOCK_DMA_0,
- HREADY_DMA_0,
+ HSEL_DMAC_0,
+ HADDR_DMAC_0,
+ HTRANS_DMAC_0,
+ HWRITE_DMAC_0,
+ HSIZE_DMAC_0,
+ HBURST_DMAC_0,
+ HPROT_DMAC_0,
+ HMASTER_DMAC_0,
+ HWDATA_DMAC_0,
+ HMASTLOCK_DMAC_0,
+ HREADY_DMAC_0,
// Input port SI2 (inputs from master 2)
- HSEL_DMA_1,
- HADDR_DMA_1,
- HTRANS_DMA_1,
- HWRITE_DMA_1,
- HSIZE_DMA_1,
- HBURST_DMA_1,
- HPROT_DMA_1,
- HMASTER_DMA_1,
- HWDATA_DMA_1,
- HMASTLOCK_DMA_1,
- HREADY_DMA_1,
+ HSEL_DMAC_1,
+ HADDR_DMAC_1,
+ HTRANS_DMAC_1,
+ HWRITE_DMAC_1,
+ HSIZE_DMAC_1,
+ HBURST_DMAC_1,
+ HPROT_DMAC_1,
+ HMASTER_DMAC_1,
+ HWDATA_DMAC_1,
+ HMASTLOCK_DMAC_1,
+ HREADY_DMAC_1,
// Input port SI3 (inputs from master 3)
HSEL_CPU_0,
@@ -297,14 +297,14 @@ module nanosoc_busmatrix (
HRESP_SOCDEBUG,
// Input port SI1 (outputs to master 1)
- HRDATA_DMA_0,
- HREADYOUT_DMA_0,
- HRESP_DMA_0,
+ HRDATA_DMAC_0,
+ HREADYOUT_DMAC_0,
+ HRESP_DMAC_0,
// Input port SI2 (outputs to master 2)
- HRDATA_DMA_1,
- HREADYOUT_DMA_1,
- HRESP_DMA_1,
+ HRDATA_DMAC_1,
+ HREADYOUT_DMAC_1,
+ HRESP_DMAC_1,
// Input port SI3 (outputs to master 3)
HRDATA_CPU_0,
@@ -342,30 +342,30 @@ module nanosoc_busmatrix (
input HREADY_SOCDEBUG; // Transfer done
// Input port SI1 (inputs from master 1)
- input HSEL_DMA_0; // Slave Select
- input [31:0] HADDR_DMA_0; // Address bus
- input [1:0] HTRANS_DMA_0; // Transfer type
- input HWRITE_DMA_0; // Transfer direction
- input [2:0] HSIZE_DMA_0; // Transfer size
- input [2:0] HBURST_DMA_0; // Burst type
- input [3:0] HPROT_DMA_0; // Protection control
- input [3:0] HMASTER_DMA_0; // Master select
- input [31:0] HWDATA_DMA_0; // Write data
- input HMASTLOCK_DMA_0; // Locked Sequence
- input HREADY_DMA_0; // Transfer done
+ input HSEL_DMAC_0; // Slave Select
+ input [31:0] HADDR_DMAC_0; // Address bus
+ input [1:0] HTRANS_DMAC_0; // Transfer type
+ input HWRITE_DMAC_0; // Transfer direction
+ input [2:0] HSIZE_DMAC_0; // Transfer size
+ input [2:0] HBURST_DMAC_0; // Burst type
+ input [3:0] HPROT_DMAC_0; // Protection control
+ input [3:0] HMASTER_DMAC_0; // Master select
+ input [31:0] HWDATA_DMAC_0; // Write data
+ input HMASTLOCK_DMAC_0; // Locked Sequence
+ input HREADY_DMAC_0; // Transfer done
// Input port SI2 (inputs from master 2)
- input HSEL_DMA_1; // Slave Select
- input [31:0] HADDR_DMA_1; // Address bus
- input [1:0] HTRANS_DMA_1; // Transfer type
- input HWRITE_DMA_1; // Transfer direction
- input [2:0] HSIZE_DMA_1; // Transfer size
- input [2:0] HBURST_DMA_1; // Burst type
- input [3:0] HPROT_DMA_1; // Protection control
- input [3:0] HMASTER_DMA_1; // Master select
- input [31:0] HWDATA_DMA_1; // Write data
- input HMASTLOCK_DMA_1; // Locked Sequence
- input HREADY_DMA_1; // Transfer done
+ input HSEL_DMAC_1; // Slave Select
+ input [31:0] HADDR_DMAC_1; // Address bus
+ input [1:0] HTRANS_DMAC_1; // Transfer type
+ input HWRITE_DMAC_1; // Transfer direction
+ input [2:0] HSIZE_DMAC_1; // Transfer size
+ input [2:0] HBURST_DMAC_1; // Burst type
+ input [3:0] HPROT_DMAC_1; // Protection control
+ input [3:0] HMASTER_DMAC_1; // Master select
+ input [31:0] HWDATA_DMAC_1; // Write data
+ input HMASTLOCK_DMAC_1; // Locked Sequence
+ input HREADY_DMAC_1; // Transfer done
// Input port SI3 (inputs from master 3)
input HSEL_CPU_0; // Slave Select
@@ -571,14 +571,14 @@ module nanosoc_busmatrix (
output [1:0] HRESP_SOCDEBUG; // Transfer response
// Input port SI1 (outputs to master 1)
- output [31:0] HRDATA_DMA_0; // Read data bus
- output HREADYOUT_DMA_0; // HREADY feedback
- output [1:0] HRESP_DMA_0; // Transfer response
+ output [31:0] HRDATA_DMAC_0; // Read data bus
+ output HREADYOUT_DMAC_0; // HREADY feedback
+ output [1:0] HRESP_DMAC_0; // Transfer response
// Input port SI2 (outputs to master 2)
- output [31:0] HRDATA_DMA_1; // Read data bus
- output HREADYOUT_DMA_1; // HREADY feedback
- output [1:0] HRESP_DMA_1; // Transfer response
+ output [31:0] HRDATA_DMAC_1; // Read data bus
+ output HREADYOUT_DMAC_1; // HREADY feedback
+ output [1:0] HRESP_DMAC_1; // Transfer response
// Input port SI3 (outputs to master 3)
output [31:0] HRDATA_CPU_0; // Read data bus
@@ -618,38 +618,38 @@ module nanosoc_busmatrix (
wire [1:0] HRESP_SOCDEBUG; // Transfer response
// Input Port SI1
- wire HSEL_DMA_0; // Slave Select
- wire [31:0] HADDR_DMA_0; // Address bus
- wire [1:0] HTRANS_DMA_0; // Transfer type
- wire HWRITE_DMA_0; // Transfer direction
- wire [2:0] HSIZE_DMA_0; // Transfer size
- wire [2:0] HBURST_DMA_0; // Burst type
- wire [3:0] HPROT_DMA_0; // Protection control
- wire [3:0] HMASTER_DMA_0; // Master select
- wire [31:0] HWDATA_DMA_0; // Write data
- wire HMASTLOCK_DMA_0; // Locked Sequence
- wire HREADY_DMA_0; // Transfer done
-
- wire [31:0] HRDATA_DMA_0; // Read data bus
- wire HREADYOUT_DMA_0; // HREADY feedback
- wire [1:0] HRESP_DMA_0; // Transfer response
+ wire HSEL_DMAC_0; // Slave Select
+ wire [31:0] HADDR_DMAC_0; // Address bus
+ wire [1:0] HTRANS_DMAC_0; // Transfer type
+ wire HWRITE_DMAC_0; // Transfer direction
+ wire [2:0] HSIZE_DMAC_0; // Transfer size
+ wire [2:0] HBURST_DMAC_0; // Burst type
+ wire [3:0] HPROT_DMAC_0; // Protection control
+ wire [3:0] HMASTER_DMAC_0; // Master select
+ wire [31:0] HWDATA_DMAC_0; // Write data
+ wire HMASTLOCK_DMAC_0; // Locked Sequence
+ wire HREADY_DMAC_0; // Transfer done
+
+ wire [31:0] HRDATA_DMAC_0; // Read data bus
+ wire HREADYOUT_DMAC_0; // HREADY feedback
+ wire [1:0] HRESP_DMAC_0; // Transfer response
// Input Port SI2
- wire HSEL_DMA_1; // Slave Select
- wire [31:0] HADDR_DMA_1; // Address bus
- wire [1:0] HTRANS_DMA_1; // Transfer type
- wire HWRITE_DMA_1; // Transfer direction
- wire [2:0] HSIZE_DMA_1; // Transfer size
- wire [2:0] HBURST_DMA_1; // Burst type
- wire [3:0] HPROT_DMA_1; // Protection control
- wire [3:0] HMASTER_DMA_1; // Master select
- wire [31:0] HWDATA_DMA_1; // Write data
- wire HMASTLOCK_DMA_1; // Locked Sequence
- wire HREADY_DMA_1; // Transfer done
-
- wire [31:0] HRDATA_DMA_1; // Read data bus
- wire HREADYOUT_DMA_1; // HREADY feedback
- wire [1:0] HRESP_DMA_1; // Transfer response
+ wire HSEL_DMAC_1; // Slave Select
+ wire [31:0] HADDR_DMAC_1; // Address bus
+ wire [1:0] HTRANS_DMAC_1; // Transfer type
+ wire HWRITE_DMAC_1; // Transfer direction
+ wire [2:0] HSIZE_DMAC_1; // Transfer size
+ wire [2:0] HBURST_DMAC_1; // Burst type
+ wire [3:0] HPROT_DMAC_1; // Protection control
+ wire [3:0] HMASTER_DMAC_1; // Master select
+ wire [31:0] HWDATA_DMAC_1; // Write data
+ wire HMASTLOCK_DMAC_1; // Locked Sequence
+ wire HREADY_DMAC_1; // Transfer done
+
+ wire [31:0] HRDATA_DMAC_1; // Read data bus
+ wire HREADYOUT_DMAC_1; // HREADY feedback
+ wire [1:0] HRESP_DMAC_1; // Transfer response
// Input Port SI3
wire HSEL_CPU_0; // Slave Select
@@ -1122,16 +1122,16 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_DMA_0),
- .HADDRS (HADDR_DMA_0),
- .HTRANSS (HTRANS_DMA_0),
- .HWRITES (HWRITE_DMA_0),
- .HSIZES (HSIZE_DMA_0),
- .HBURSTS (HBURST_DMA_0),
- .HPROTS (HPROT_DMA_0),
- .HMASTERS (HMASTER_DMA_0),
- .HMASTLOCKS (HMASTLOCK_DMA_0),
- .HREADYS (HREADY_DMA_0),
+ .HSELS (HSEL_DMAC_0),
+ .HADDRS (HADDR_DMAC_0),
+ .HTRANSS (HTRANS_DMAC_0),
+ .HWRITES (HWRITE_DMAC_0),
+ .HSIZES (HSIZE_DMAC_0),
+ .HBURSTS (HBURST_DMAC_0),
+ .HPROTS (HPROT_DMAC_0),
+ .HMASTERS (HMASTER_DMAC_0),
+ .HMASTLOCKS (HMASTLOCK_DMAC_0),
+ .HREADYS (HREADY_DMAC_0),
// Internal Response
.active_ip (i_active1),
@@ -1139,8 +1139,8 @@ module nanosoc_busmatrix (
.resp_ip (i_resp1),
// Input Port Response
- .HREADYOUTS (HREADYOUT_DMA_0),
- .HRESPS (HRESP_DMA_0),
+ .HREADYOUTS (HREADYOUT_DMAC_0),
+ .HRESPS (HRESP_DMAC_0),
// Internal Address/Control Signals
.sel_ip (i_sel1),
@@ -1165,16 +1165,16 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Input Port Address/Control Signals
- .HSELS (HSEL_DMA_1),
- .HADDRS (HADDR_DMA_1),
- .HTRANSS (HTRANS_DMA_1),
- .HWRITES (HWRITE_DMA_1),
- .HSIZES (HSIZE_DMA_1),
- .HBURSTS (HBURST_DMA_1),
- .HPROTS (HPROT_DMA_1),
- .HMASTERS (HMASTER_DMA_1),
- .HMASTLOCKS (HMASTLOCK_DMA_1),
- .HREADYS (HREADY_DMA_1),
+ .HSELS (HSEL_DMAC_1),
+ .HADDRS (HADDR_DMAC_1),
+ .HTRANSS (HTRANS_DMAC_1),
+ .HWRITES (HWRITE_DMAC_1),
+ .HSIZES (HSIZE_DMAC_1),
+ .HBURSTS (HBURST_DMAC_1),
+ .HPROTS (HPROT_DMAC_1),
+ .HMASTERS (HMASTER_DMAC_1),
+ .HMASTLOCKS (HMASTLOCK_DMAC_1),
+ .HREADYS (HREADY_DMAC_1),
// Internal Response
.active_ip (i_active2),
@@ -1182,8 +1182,8 @@ module nanosoc_busmatrix (
.resp_ip (i_resp2),
// Input Port Response
- .HREADYOUTS (HREADYOUT_DMA_1),
- .HRESPS (HRESP_DMA_1),
+ .HREADYOUTS (HREADYOUT_DMAC_1),
+ .HRESPS (HRESP_DMAC_1),
// Internal Address/Control Signals
.sel_ip (i_sel2),
@@ -1339,14 +1339,14 @@ module nanosoc_busmatrix (
// Matrix decoder for SI1
- nanosoc_matrix_decode_DMA_0 u_nanosoc_matrix_decode_dma_0 (
+ nanosoc_matrix_decode_DMAC_0 u_nanosoc_matrix_decode_dmac_0 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI1
- .HREADYS (HREADY_DMA_0),
+ .HREADYS (HREADY_DMAC_0),
.sel_dec (i_sel1),
.decode_addr_dec (i_addr1[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans1),
@@ -1418,20 +1418,20 @@ module nanosoc_busmatrix (
.active_dec (i_active1),
.HREADYOUTS (i_readyout1),
.HRESPS (i_resp1),
- .HRDATAS (HRDATA_DMA_0)
+ .HRDATAS (HRDATA_DMAC_0)
);
// Matrix decoder for SI2
- nanosoc_matrix_decode_DMA_1 u_nanosoc_matrix_decode_dma_1 (
+ nanosoc_matrix_decode_DMAC_1 u_nanosoc_matrix_decode_dmac_1 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Signals from Input stage SI2
- .HREADYS (HREADY_DMA_1),
+ .HREADYS (HREADY_DMAC_1),
.sel_dec (i_sel2),
.decode_addr_dec (i_addr2[31:10]), // HADDR[9:0] is not decoded
.trans_dec (i_trans2),
@@ -1503,7 +1503,7 @@ module nanosoc_busmatrix (
.active_dec (i_active2),
.HREADYOUTS (i_readyout2),
.HRESPS (i_resp2),
- .HRDATAS (HRDATA_DMA_1)
+ .HRDATAS (HRDATA_DMAC_1)
);
@@ -1633,7 +1633,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -1646,7 +1646,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -1719,7 +1719,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -1732,7 +1732,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -1805,7 +1805,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -1818,7 +1818,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -1891,7 +1891,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -1904,7 +1904,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -1977,7 +1977,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -1990,7 +1990,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -2063,7 +2063,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -2076,7 +2076,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -2149,7 +2149,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -2162,7 +2162,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -2235,7 +2235,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -2248,7 +2248,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
@@ -2321,7 +2321,7 @@ module nanosoc_busmatrix (
.prot_op1 (i_prot1),
.master_op1 (i_master1),
.mastlock_op1 (i_mastlock1),
- .wdata_op1 (HWDATA_DMA_0),
+ .wdata_op1 (HWDATA_DMAC_0),
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
@@ -2334,7 +2334,7 @@ module nanosoc_busmatrix (
.prot_op2 (i_prot2),
.master_op2 (i_master2),
.mastlock_op2 (i_mastlock2),
- .wdata_op2 (HWDATA_DMA_1),
+ .wdata_op2 (HWDATA_DMAC_1),
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
index 4e5219adc04a4ea37f4e58bda9216691af14315d..1a00f814071f9a6452df7f78d39b10de221fa218 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -50,24 +50,24 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_SOCDEBUG,
// Input port SI1 (inputs from master 1)
- HADDR_DMA_0,
- HTRANS_DMA_0,
- HWRITE_DMA_0,
- HSIZE_DMA_0,
- HBURST_DMA_0,
- HPROT_DMA_0,
- HWDATA_DMA_0,
- HMASTLOCK_DMA_0,
+ HADDR_DMAC_0,
+ HTRANS_DMAC_0,
+ HWRITE_DMAC_0,
+ HSIZE_DMAC_0,
+ HBURST_DMAC_0,
+ HPROT_DMAC_0,
+ HWDATA_DMAC_0,
+ HMASTLOCK_DMAC_0,
// Input port SI2 (inputs from master 2)
- HADDR_DMA_1,
- HTRANS_DMA_1,
- HWRITE_DMA_1,
- HSIZE_DMA_1,
- HBURST_DMA_1,
- HPROT_DMA_1,
- HWDATA_DMA_1,
- HMASTLOCK_DMA_1,
+ HADDR_DMAC_1,
+ HTRANS_DMAC_1,
+ HWRITE_DMAC_1,
+ HSIZE_DMAC_1,
+ HBURST_DMAC_1,
+ HPROT_DMAC_1,
+ HWDATA_DMAC_1,
+ HMASTLOCK_DMAC_1,
// Input port SI3 (inputs from master 3)
HADDR_CPU_0,
@@ -260,14 +260,14 @@ module nanosoc_busmatrix_lite (
HRESP_SOCDEBUG,
// Input port SI1 (outputs to master 1)
- HRDATA_DMA_0,
- HREADY_DMA_0,
- HRESP_DMA_0,
+ HRDATA_DMAC_0,
+ HREADY_DMAC_0,
+ HRESP_DMAC_0,
// Input port SI2 (outputs to master 2)
- HRDATA_DMA_1,
- HREADY_DMA_1,
- HRESP_DMA_1,
+ HRDATA_DMAC_1,
+ HREADY_DMAC_1,
+ HRESP_DMAC_1,
// Input port SI3 (outputs to master 3)
HRDATA_CPU_0,
@@ -301,24 +301,24 @@ module nanosoc_busmatrix_lite (
input HMASTLOCK_SOCDEBUG; // Locked Sequence
// Input port SI1 (inputs from master 1)
- input [31:0] HADDR_DMA_0; // Address bus
- input [1:0] HTRANS_DMA_0; // Transfer type
- input HWRITE_DMA_0; // Transfer direction
- input [2:0] HSIZE_DMA_0; // Transfer size
- input [2:0] HBURST_DMA_0; // Burst type
- input [3:0] HPROT_DMA_0; // Protection control
- input [31:0] HWDATA_DMA_0; // Write data
- input HMASTLOCK_DMA_0; // Locked Sequence
+ input [31:0] HADDR_DMAC_0; // Address bus
+ input [1:0] HTRANS_DMAC_0; // Transfer type
+ input HWRITE_DMAC_0; // Transfer direction
+ input [2:0] HSIZE_DMAC_0; // Transfer size
+ input [2:0] HBURST_DMAC_0; // Burst type
+ input [3:0] HPROT_DMAC_0; // Protection control
+ input [31:0] HWDATA_DMAC_0; // Write data
+ input HMASTLOCK_DMAC_0; // Locked Sequence
// Input port SI2 (inputs from master 2)
- input [31:0] HADDR_DMA_1; // Address bus
- input [1:0] HTRANS_DMA_1; // Transfer type
- input HWRITE_DMA_1; // Transfer direction
- input [2:0] HSIZE_DMA_1; // Transfer size
- input [2:0] HBURST_DMA_1; // Burst type
- input [3:0] HPROT_DMA_1; // Protection control
- input [31:0] HWDATA_DMA_1; // Write data
- input HMASTLOCK_DMA_1; // Locked Sequence
+ input [31:0] HADDR_DMAC_1; // Address bus
+ input [1:0] HTRANS_DMAC_1; // Transfer type
+ input HWRITE_DMAC_1; // Transfer direction
+ input [2:0] HSIZE_DMAC_1; // Transfer size
+ input [2:0] HBURST_DMAC_1; // Burst type
+ input [3:0] HPROT_DMAC_1; // Protection control
+ input [31:0] HWDATA_DMAC_1; // Write data
+ input HMASTLOCK_DMAC_1; // Locked Sequence
// Input port SI3 (inputs from master 3)
input [31:0] HADDR_CPU_0; // Address bus
@@ -511,14 +511,14 @@ module nanosoc_busmatrix_lite (
output HRESP_SOCDEBUG; // Transfer response
// Input port SI1 (outputs to master 1)
- output [31:0] HRDATA_DMA_0; // Read data bus
- output HREADY_DMA_0; // HREADY feedback
- output HRESP_DMA_0; // Transfer response
+ output [31:0] HRDATA_DMAC_0; // Read data bus
+ output HREADY_DMAC_0; // HREADY feedback
+ output HRESP_DMAC_0; // Transfer response
// Input port SI2 (outputs to master 2)
- output [31:0] HRDATA_DMA_1; // Read data bus
- output HREADY_DMA_1; // HREADY feedback
- output HRESP_DMA_1; // Transfer response
+ output [31:0] HRDATA_DMAC_1; // Read data bus
+ output HREADY_DMAC_1; // HREADY feedback
+ output HRESP_DMAC_1; // Transfer response
// Input port SI3 (outputs to master 3)
output [31:0] HRDATA_CPU_0; // Read data bus
@@ -554,32 +554,32 @@ module nanosoc_busmatrix_lite (
wire HRESP_SOCDEBUG; // Transfer response
// Input Port SI1
- wire [31:0] HADDR_DMA_0; // Address bus
- wire [1:0] HTRANS_DMA_0; // Transfer type
- wire HWRITE_DMA_0; // Transfer direction
- wire [2:0] HSIZE_DMA_0; // Transfer size
- wire [2:0] HBURST_DMA_0; // Burst type
- wire [3:0] HPROT_DMA_0; // Protection control
- wire [31:0] HWDATA_DMA_0; // Write data
- wire HMASTLOCK_DMA_0; // Locked Sequence
-
- wire [31:0] HRDATA_DMA_0; // Read data bus
- wire HREADY_DMA_0; // HREADY feedback
- wire HRESP_DMA_0; // Transfer response
+ wire [31:0] HADDR_DMAC_0; // Address bus
+ wire [1:0] HTRANS_DMAC_0; // Transfer type
+ wire HWRITE_DMAC_0; // Transfer direction
+ wire [2:0] HSIZE_DMAC_0; // Transfer size
+ wire [2:0] HBURST_DMAC_0; // Burst type
+ wire [3:0] HPROT_DMAC_0; // Protection control
+ wire [31:0] HWDATA_DMAC_0; // Write data
+ wire HMASTLOCK_DMAC_0; // Locked Sequence
+
+ wire [31:0] HRDATA_DMAC_0; // Read data bus
+ wire HREADY_DMAC_0; // HREADY feedback
+ wire HRESP_DMAC_0; // Transfer response
// Input Port SI2
- wire [31:0] HADDR_DMA_1; // Address bus
- wire [1:0] HTRANS_DMA_1; // Transfer type
- wire HWRITE_DMA_1; // Transfer direction
- wire [2:0] HSIZE_DMA_1; // Transfer size
- wire [2:0] HBURST_DMA_1; // Burst type
- wire [3:0] HPROT_DMA_1; // Protection control
- wire [31:0] HWDATA_DMA_1; // Write data
- wire HMASTLOCK_DMA_1; // Locked Sequence
-
- wire [31:0] HRDATA_DMA_1; // Read data bus
- wire HREADY_DMA_1; // HREADY feedback
- wire HRESP_DMA_1; // Transfer response
+ wire [31:0] HADDR_DMAC_1; // Address bus
+ wire [1:0] HTRANS_DMAC_1; // Transfer type
+ wire HWRITE_DMAC_1; // Transfer direction
+ wire [2:0] HSIZE_DMAC_1; // Transfer size
+ wire [2:0] HBURST_DMAC_1; // Burst type
+ wire [3:0] HPROT_DMAC_1; // Protection control
+ wire [31:0] HWDATA_DMAC_1; // Write data
+ wire HMASTLOCK_DMAC_1; // Locked Sequence
+
+ wire [31:0] HRDATA_DMAC_1; // Read data bus
+ wire HREADY_DMAC_1; // HREADY feedback
+ wire HRESP_DMAC_1; // Transfer response
// Input Port SI3
wire [31:0] HADDR_CPU_0; // Address bus
@@ -763,8 +763,8 @@ module nanosoc_busmatrix_lite (
wire tie_hi;
wire tie_low;
wire [1:0] i_hresp_SOCDEBUG;
- wire [1:0] i_hresp_DMA_0;
- wire [1:0] i_hresp_DMA_1;
+ wire [1:0] i_hresp_DMAC_0;
+ wire [1:0] i_hresp_DMAC_1;
wire [1:0] i_hresp_CPU_0;
wire [3:0] i_hmaster_BOOTROM;
@@ -799,9 +799,9 @@ module nanosoc_busmatrix_lite (
assign HRESP_SOCDEBUG = i_hresp_SOCDEBUG[0];
- assign HRESP_DMA_0 = i_hresp_DMA_0[0];
+ assign HRESP_DMAC_0 = i_hresp_DMAC_0[0];
- assign HRESP_DMA_1 = i_hresp_DMA_1[0];
+ assign HRESP_DMAC_1 = i_hresp_DMAC_1[0];
assign HRESP_CPU_0 = i_hresp_CPU_0[0];
@@ -839,36 +839,36 @@ module nanosoc_busmatrix_lite (
.HRESP_SOCDEBUG (i_hresp_SOCDEBUG),
// Input port SI1 signals
- .HSEL_DMA_0 (tie_hi),
- .HADDR_DMA_0 (HADDR_DMA_0),
- .HTRANS_DMA_0 (HTRANS_DMA_0),
- .HWRITE_DMA_0 (HWRITE_DMA_0),
- .HSIZE_DMA_0 (HSIZE_DMA_0),
- .HBURST_DMA_0 (HBURST_DMA_0),
- .HPROT_DMA_0 (HPROT_DMA_0),
- .HWDATA_DMA_0 (HWDATA_DMA_0),
- .HMASTLOCK_DMA_0 (HMASTLOCK_DMA_0),
- .HMASTER_DMA_0 (tie_hi_4),
- .HREADY_DMA_0 (HREADY_DMA_0),
- .HRDATA_DMA_0 (HRDATA_DMA_0),
- .HREADYOUT_DMA_0 (HREADY_DMA_0),
- .HRESP_DMA_0 (i_hresp_DMA_0),
+ .HSEL_DMAC_0 (tie_hi),
+ .HADDR_DMAC_0 (HADDR_DMAC_0),
+ .HTRANS_DMAC_0 (HTRANS_DMAC_0),
+ .HWRITE_DMAC_0 (HWRITE_DMAC_0),
+ .HSIZE_DMAC_0 (HSIZE_DMAC_0),
+ .HBURST_DMAC_0 (HBURST_DMAC_0),
+ .HPROT_DMAC_0 (HPROT_DMAC_0),
+ .HWDATA_DMAC_0 (HWDATA_DMAC_0),
+ .HMASTLOCK_DMAC_0 (HMASTLOCK_DMAC_0),
+ .HMASTER_DMAC_0 (tie_hi_4),
+ .HREADY_DMAC_0 (HREADY_DMAC_0),
+ .HRDATA_DMAC_0 (HRDATA_DMAC_0),
+ .HREADYOUT_DMAC_0 (HREADY_DMAC_0),
+ .HRESP_DMAC_0 (i_hresp_DMAC_0),
// Input port SI2 signals
- .HSEL_DMA_1 (tie_hi),
- .HADDR_DMA_1 (HADDR_DMA_1),
- .HTRANS_DMA_1 (HTRANS_DMA_1),
- .HWRITE_DMA_1 (HWRITE_DMA_1),
- .HSIZE_DMA_1 (HSIZE_DMA_1),
- .HBURST_DMA_1 (HBURST_DMA_1),
- .HPROT_DMA_1 (HPROT_DMA_1),
- .HWDATA_DMA_1 (HWDATA_DMA_1),
- .HMASTLOCK_DMA_1 (HMASTLOCK_DMA_1),
- .HMASTER_DMA_1 (tie_hi_4),
- .HREADY_DMA_1 (HREADY_DMA_1),
- .HRDATA_DMA_1 (HRDATA_DMA_1),
- .HREADYOUT_DMA_1 (HREADY_DMA_1),
- .HRESP_DMA_1 (i_hresp_DMA_1),
+ .HSEL_DMAC_1 (tie_hi),
+ .HADDR_DMAC_1 (HADDR_DMAC_1),
+ .HTRANS_DMAC_1 (HTRANS_DMAC_1),
+ .HWRITE_DMAC_1 (HWRITE_DMAC_1),
+ .HSIZE_DMAC_1 (HSIZE_DMAC_1),
+ .HBURST_DMAC_1 (HBURST_DMAC_1),
+ .HPROT_DMAC_1 (HPROT_DMAC_1),
+ .HWDATA_DMAC_1 (HWDATA_DMAC_1),
+ .HMASTLOCK_DMAC_1 (HMASTLOCK_DMAC_1),
+ .HMASTER_DMAC_1 (tie_hi_4),
+ .HREADY_DMAC_1 (HREADY_DMAC_1),
+ .HRDATA_DMAC_1 (HRDATA_DMAC_1),
+ .HREADYOUT_DMAC_1 (HREADY_DMAC_1),
+ .HRESP_DMAC_1 (i_hresp_DMAC_1),
// Input port SI3 signals
.HSEL_CPU_0 (tie_hi),
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
index 4aab2f63ef4ea76b9673c7291a0c95d9208fcebf..9bc7a0de6b2bb14f329efe3517ae6294bf80153b 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
@@ -33,7 +33,7 @@
-module nanosoc_matrix_decode_DMA_0 (
+module nanosoc_matrix_decode_DMAC_0 (
// Common AHB signals
HCLK,
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
index b4e1ad6fb2b5a2a5cba2e4793d4e89b2f93bbf1c..eda0cb8d33e612de0625a452ace966183c7eecb5 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
@@ -33,7 +33,7 @@
-module nanosoc_matrix_decode_DMA_1 (
+module nanosoc_matrix_decode_DMAC_1 (
// Common AHB signals
HCLK,
diff --git a/system/nanosoc_busmatrix/xml/nanosoc.xml b/system/nanosoc_busmatrix/xml/nanosoc.xml
index 34786fd07f845d574fbf46635d6b86fa484aba11..b55e1f81e23a6049d356a133def753ef86791cde 100644
--- a/system/nanosoc_busmatrix/xml/nanosoc.xml
+++ b/system/nanosoc_busmatrix/xml/nanosoc.xml
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="iso-8859-1" ?>
<!--//----------------------------------------------------------------------------- -->
-<!--// customised interconnect specification for ADP/DMA/ Cortex-M0 controller -->
+<!--// Customised Bus Matrix Interconnect specification for SoC Labs NanoSoCer -->
<!--// -->
<!--// Contributors -->
<!--// -->
@@ -86,7 +86,7 @@
<remap_region interface="_IMEM" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
</slave_interface>
- <slave_interface name="_DMA_0">
+ <slave_interface name="_DMAC_0">
<sparse_connect interface="_BOOTROM"/>
<sparse_connect interface="_IMEM"/>
<sparse_connect interface="_DMEM"/>
@@ -108,7 +108,7 @@
<address_region interface="_EXP_2" mem_lo='c0000000' mem_hi='dfffffff' remapping='none'/>
</slave_interface>
- <slave_interface name="_DMA_1">
+ <slave_interface name="_DMAC_1">
<sparse_connect interface="_BOOTROM"/>
<sparse_connect interface="_IMEM"/>
<sparse_connect interface="_DMEM"/>
diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 9f29474abce915348298915ee0cad6226ed32a2e..1bb5c8a8fdc713c9ff2b238520808ad31861ab17 100644
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -200,7 +200,7 @@ module nanosoc_chip #(
wire WDOGRESETREQ; // watchdog system reset request
wire HRESETREQ; // Combined system reset request
wire NANOSOC_SYSRESETREQ; // Combined system reset request
- wire clk_ctrl_sys_reset_req;
+ wire CCTRLRESETREQ;
wire PMUHRESETREQ;
wire PMUDBGRESETREQ;
wire LOCKUP;
@@ -254,7 +254,7 @@ module nanosoc_chip #(
assign NANOSOC_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ |
ADPRESETREQ |
(LOCKUP & LOCKUPRESET);
- assign clk_ctrl_sys_reset_req = PMUHRESETREQ | HRESETREQ;
+ assign CCTRLRESETREQ = PMUHRESETREQ | HRESETREQ;
// Clock controller to generate reset and clock signals
nanosoc_mcu_clkctrl
@@ -269,7 +269,7 @@ module nanosoc_chip #(
.SLEEPDEEP (SLEEPDEEP),
.LOCKUP (LOCKUP),
.LOCKUPRESET (LOCKUPRESET),
- .SYSRESETREQ (clk_ctrl_sys_reset_req),
+ .SYSRESETREQ (CCTRLRESETREQ),
.DBGRESETREQ (PMUDBGRESETREQ),
.CGBYPASS (TESTMODE),
.RSTBYPASS (TESTMODE),
diff --git a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
index 01bb5b229667fa674526c73c91d25cb4b7bbde1f..03416193cc212f526c5ef7b501e236d40ecc6dd5 100644
--- a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+++ b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
@@ -1,12 +1,29 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Interconnect Level - Connects AHB Managers to Device Regions
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.masptone@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
module nanosoc_interconnect #(
+ // AHB System Parameters
parameter SYS_ADDR_W = 32,
parameter SYS_DATA_W = 32,
+
+ // Default RAM Instantiation Parameters
parameter RAM_ADDR_W = 14,
parameter RAM_DATA_W = 32,
- parameter DMA_CHANNEL_NUM = 2,
- parameter CLKGATE_PRESENT = 0,
- parameter integer FT1248_WIDTH = 1 // FTDI Interface 1,2,4 width supported
+
+ // System Manager Parameters
+ parameter DMA_CHANNEL_NUM = 2
)(
+ // Global Clocks and Reset
+ input wire GLOBALRESETn, // Global Reset
+
// Clocks, Gated-Clocks and Reset - AHB-lite
input wire HCLK, // Clock
input wire HCLKG, // Gated Clock
@@ -33,11 +50,23 @@ module nanosoc_interconnect #(
output wire SWO, // SWD data output
output wire SWDOEN, // SWD data output enable
- // CPU Reset Request Signals
+ // Manager Reset Request Signals
input wire NANOSOC_SYSRESETREQ,
- input wire SYSRESETREQ,
- input wire WDOGRESETREQ,
- input wire ADPRESETREQ,
+ output wire SYSRESETREQ,
+ output wire WDOGRESETREQ,
+ output wire ADPRESETREQ,
+
+ // CPU Power Control/Status Signals
+ input wire SLEEPING,
+ input wire SLEEPDEEP,
+ input wire WAKEUP,
+ input wire WICENREQ,
+ input wire WICENACK,
+ input wire SLEEPHOLDREQn,
+ input wire SLEEPHOLDACKn,
+ input wire CDBGPWRUPACK,
+ input wire CDBGPWRUPREQ,
+
// SoCDebug Controller AHB-lite Subordinate Interface
input wire [31:0] HADDR32_SOCDEBUG_o,
@@ -73,7 +102,7 @@ module nanosoc_interconnect #(
//--------------------------------
// CPU_0
//--------------------------------
- // Connectivity -AHB
+ // Connectivity - AHB
wire [31:0] HADDR_CPU_0;
wire [1:0] HTRANS_CPU_0;
wire HWRITE_CPU_0;
@@ -86,6 +115,10 @@ module nanosoc_interconnect #(
wire HRDATA_CPU_0;
wire HRESP_CPU_0;
+ // Connectivity - CPU Sidebank Signals
+ wire [31:0] SYS_NMI;
+ wire SYS_APB_IRQ;
+
// Instantiate Cortex-M0
nanosoc_manager_cortexm0 u_cpu_0 (
@@ -112,10 +145,10 @@ module nanosoc_interconnect #(
.HRDATA (HRDATA_CPU_0),
.HRESP (HRESP_CPU_0),
- // Sideband Signals - TODO: Rename, Reroute and Restructure
- .NMI (intnmi_cm0), // Non-maskable interrupt input
- .IRQ (intisr_cm0[31:0]), // Interrupt request inputs
- .TXEV (TXEV), // Event output (SEV executed)
+ // Sideband Signals
+ .NMI (SYS_NMI), // Non-maskable interrupt input
+ .IRQ (intisr_cm0[31:0]), // Interrupt request inputs - TODO: Need to generate this in own module/wrapper
+ .TXEV ( ), // Event output (SEV executed)
.RXEV (RXEV), // Event input
// CPU Control/Status Signals - TODO: Rename, Reroute and Restructure
@@ -140,7 +173,14 @@ module nanosoc_interconnect #(
.SWDO (SWDO),
.SWDOEN (SWDOEN)
);
-
+
+ //--------------------------------
+ // DMAC_0
+ //--------------------------------
+ // Connectivity - DMAC Interrupt Control
+ wire [DMA_CHANNEL_NUM-1:0] DMAC_0_CH_DONE;
+ wire DMAC_0_DONE;
+
// Instantiate DMA_0 - DMA230
// Instantiate DMA_1 - Not Implemented
@@ -161,7 +201,7 @@ module nanosoc_interconnect #(
.HCLK (HCLK),
.HRESETn (HRESETn),
- // System Address Remap COotrol
+ // System Address Remap Control
.REMAP ({3'b0, !ROM_REMAP}),
// Manager Input Signals for SoCDebug Controller - Instantiated at Chip Level
@@ -178,29 +218,29 @@ module nanosoc_interconnect #(
.HRESP_SOCDEBUG (HRESP_SOCDEBUG_i),
// Manager Input Signals for DMA Controller 0 - DMA230
- .HADDR_DMA_0 (HADDR_DMA_0),
- .HTRANS_DMA_0 (HTRANS_DMA_0),
- .HWRITE_DMA_0 (HWRITE_DMA_0),
- .HSIZE_DMA_0 (HSIZE_DMA_0),
- .HBURST_DMA_0 (HBURST_DMA_0),
- .HPROT_DMA_0 (HPROT_DMA_0),
- .HWDATA_DMA_0 (HWDATA_DMA_0),
- .HMASTLOCK_DMA_0 (HMASTLOCK_DMA_0),
- .HREADY_DMA_0 (HREADY_DMA_0),
- .HRDATA_DMA_0 (HRDATA_DMA_0),
- .HRESP_DMA_0 (HRESP_DMA_0),
+ .HADDR_DMAC_0 (HADDR_DMAC_0),
+ .HTRANS_DMAC_0 (HTRANS_DMAC_0),
+ .HWRITE_DMAC_0 (HWRITE_DMAC_0),
+ .HSIZE_DMAC_0 (HSIZE_DMAC_0),
+ .HBURST_DMAC_0 (HBURST_DMAC_0),
+ .HPROT_DMAC_0 (HPROT_DMAC_0),
+ .HWDATA_DMAC_0 (HWDATA_DMAC_0),
+ .HMASTLOCK_DMAC_0 (HMASTLOCK_DMAC_0),
+ .HREADY_DMAC_0 (HREADY_DMAC_0),
+ .HRDATA_DMAC_0 (HRDATA_DMAC_0),
+ .HRESP_DMAC_0 (HRESP_DMAC_0),
// Manager Input Signals for DMA Controller 1 - Not Initialised
- .HADDR_DMA_1 (HADDR_DMA_1),
- .HTRANS_DMA_1 (HTRANS_DMA_1),
- .HWRITE_DMA_1 (HWRITE_DMA_1),
- .HSIZE_DMA_1 (HSIZE_DMA_1),
- .HBURST_DMA_1 (HBURST_DMA_1),
- .HPROT_DMA_1 (HPROT_DMA_1),
- .HWDATA_DMA_1 (HWDATA_DMA_1),
- .HMASTLOCK_DMA_1 (HMASTLOCK_DMA_1),
- .HREADY_DMA_1 (HREADY_DMA_1),
- .HRESP_DMA_1 (HRESP_DMA_1),
+ .HADDR_DMAC_1 (HADDR_DMAC_1),
+ .HTRANS_DMAC_1 (HTRANS_DMAC_1),
+ .HWRITE_DMAC_1 (HWRITE_DMAC_1),
+ .HSIZE_DMAC_1 (HSIZE_DMAC_1),
+ .HBURST_DMAC_1 (HBURST_DMAC_1),
+ .HPROT_DMAC_1 (HPROT_DMAC_1),
+ .HWDATA_DMAC_1 (HWDATA_DMAC_1),
+ .HMASTLOCK_DMAC_1 (HMASTLOCK_DMAC_1),
+ .HREADY_DMAC_1 (HREADY_DMAC_1),
+ .HRESP_DMAC_1 (HRESP_DMAC_1),
// Manager Input Signals for CPU 0 - Cortex-M0
.HADDR_CPU_0 (HADDR_CPU_0),
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..b5e2b43253484f0f00a9b86e677918fe9805f54b
--- /dev/null
+++ b/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v
@@ -0,0 +1,144 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Cortex-M0 Reset and Power Control Module
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_cortexm0_control #(
+ parameter CLKGATE_PRESENT = 0
+)(
+ // Input Clocks and Resets
+ input wire FCLK, // Free running clock
+ input wire SYSRESETn, // System Reset
+ input wire SCANENABLE, // Scan Mode Enable
+ input wire TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // Generated Clocks and Resets
+ output wire SCLK, // System clock
+ output wire HCLK, // AHB Clock
+ output wire HRESETn, // AHB Reset
+ output wire PORESETn, // Power on reset
+ output wire DCLK, // Debug clock
+ output wire DBGRESETn, // Debug reset
+
+ // System Reset Request
+ input wire NANOSOC_RESETREQ, // System Reset Request
+
+ // Power Management Control Signals
+ input wire PMUENABLE, // PMU NEable from System Register
+ input wire WAKEUP, // Wakeup Signaling from Core
+ input wire SLEEPDEEP, // Debug Power Up Request
+ input wire GATEHCLK, // Control Signal from Core to Control Clock Gating of HCLK
+
+ // Power Management Request signals
+ input wire CDBGPWRUPREQ, // Core Debug Power Up Request
+ output wire WICENREQ, // WIC enable request from PMU
+ output wire SLEEPHOLDREQn, // Core Sleep Hold Request
+ output wire PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
+ output wire CCTRLRESETREQ, // Core Control System Reset Request
+
+ // Power Management Ackowledge signals
+ input wire WICENACK, // Wake-on-Interrupt Enable ACK from Core
+ input wire SLEEPHOLDACKn, // Sleep Hold Acknowledgement
+ output wire CDBGPWRUPACK // Core Debug Power Up Acknowledge
+);
+
+ // -------------------------------
+ // Cortex-M0 Control System Reset Req
+ // -------------------------------
+ wire HRESETREQ;
+ wire PMUHRESETREQ;
+
+ assign CCTRLRESETREQ = PMUHRESETREQ | HRESETREQ;
+
+ // -------------------------------
+ // NanoSoC Power Down Detection
+ // -------------------------------
+ // System Power Down Signals
+ wire SYSPWRDOWN;
+ wire SYSPWRDOWNACK;
+
+ // Debug Power Down Signals
+ wire DBGPWRDOWN;
+ wire DBGPWRDOWNACK;
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign SYSPWRDOWNACK = SYSPWRDOWN;
+ assign DBGPWRDOWNACK = DBGPWRDOWN;
+
+ // -------------------------------
+ // NanoSoC Power Management Unit
+ // -------------------------------
+ // Connectivity - Clock Generation
+ wire HCLKG; // Gated HCLK
+ wire DCLKG; // Gated DCLK
+ wire SCLKG; // Gated SCLK
+
+ assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : HCLKG;
+ assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : DCLKG;
+ assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : SCLKG;
+
+ // Power Management Unit Instantiation
+ cortexm0_pmu u_cortexm0_pmu (
+ // Power Management Unit Inputs
+ .FCLK (FCLK),
+ .PORESETn (PORESETn),
+ .HRESETREQ (NANOSOC_RESETREQ), // from Cores / Watchdog / Debug Controller
+ .PMUENABLE (PMUENABLE), // from System Controller
+ .WICENACK (WICENACK), // from WIC in integration
+
+ .WAKEUP (WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CDBGPWRUPREQ),
+
+ .SLEEPDEEP (SLEEPDEEP),
+ .SLEEPHOLDACKn (SLEEPHOLDACKn),
+ .GATEHCLK (GATEHCLK),
+ .SYSPWRDOWNACK (SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (DBGPWRDOWNACK),
+ .CGBYPASS (TESTMODE),
+
+ // Power Management Unit Outputs
+ .HCLK (HCLKG),
+ .DCLK (DCLKG),
+ .SCLK (SCLKG),
+ .WICENREQ (WICENREQ),
+ .CDBGPWRUPACK (CDBGPWRUPACK),
+ .SYSISOLATEn ( ),
+ .SYSRETAINn ( ),
+ .SYSPWRDOWN (SYSPWRDOWN),
+ .DBGISOLATEn ( ),
+ .DBGPWRDOWN (DBGPWRDOWN),
+ .SLEEPHOLDREQn (SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ)
+ );
+
+ // -------------------------------
+ // Reset Control
+ // -------------------------------
+ cortexm0_rst_ctl u_rst_ctl (
+ // Inputs
+ .GLOBALRESETn (SYSRESETn),
+ .FCLK (FCLK),
+ .HCLK (HCLKG), // TODO: Why are theses Gated?
+ .DCLK (DCLKG), // TODO: Why are theses Gated?
+ .SYSRESETREQ (NANOSOC_RESETREQ),
+ .PMUHRESETREQ (PMUHRESETREQ),
+ .PMUDBGRESETREQ (PMUDBGRESETREQ),
+ .RSTBYPASS (TESTMODE),
+ .SE (SCANENABLE),
+
+ // Outputs
+ .PORESETn (PORESETn),
+ .HRESETn (HRESETn),
+ .DBGRESETn (DBGRESETn),
+ .HRESETREQ (HRESETREQ)
+ );
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_stclkctrl.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_stclkctrl.v
similarity index 98%
rename from system/nanosoc_managers/cortexm0/verilog/nanosoc_stclkctrl.v
rename to system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_stclkctrl.v
index ca006495ef5441ce0aacfa189471846f316fbebc..2f1dc81413a3e671883ba8f722a8bf30a42339f3 100644
--- a/system/nanosoc_managers/cortexm0/verilog/nanosoc_stclkctrl.v
+++ b/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_stclkctrl.v
@@ -35,7 +35,7 @@
// Abstract : Simple control for SysTick signals for Cortex-M processor
//-----------------------------------------------------------------------------
-module nanosoc_stclkctrl #(
+module nanosoc_cortexm0_stclkctrl #(
// Ratio between FCLK and SysTck reference clock
parameter DIV_RATIO = 18'd01000,
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
index 94ee5c0c224950b3b76dbaf66d063c709f524e00..52512dac01d511f61eb419bdee6caf4b04a80144 100644
--- a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
+++ b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
@@ -4,7 +4,8 @@
//
// Contributors
//
-// David Flynn (d.w.flynn@soton.ac.uk)
+// David Flynn (d.w.flynn@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
@@ -49,15 +50,27 @@ module nanosoc_manager_cortexm0 #(
parameter RESET_ALL_REGS = 0, // Do not reset all registers
parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
)(
- input wire HCLK, // (HCLK master)
+ // Input Clocks and Resets
input wire FCLK, // Free running clock
- input wire SCLK, // System clock
- input wire HRESETn, // AHB and System reset
- input wire PORESETn, // Power on reset
- input wire DCLK, // Debug clock
- input wire DBGRESETn, // Debug reset
- input wire RSTBYPASS, // Reset by pass (for testing)
- input wire DFTSE, // Reset by pass (for testing)
+ input wire SYSRESETn, // System Reset
+ input wire SCANENABLE, // Scan Mode Enable
+ input wire TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // System Reset Request Signals
+ input wire NANOSOC_RESETREQ, // System Request from System Managers
+ output wire CCTRLRESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
+
+ // Generated Clocks and Resets
+ output wire HCLK, // (HCLK master)
+ output wire SCLK, // System clock
+ output wire HRESETn, // AHB and System reset
+ output wire PORESETn, // Power on reset
+ output wire DCLK, // Debug clock
+ output wire DBGRESETn, // Debug reset
+
+ // Power Management Signals
+ input wire PMUENABLE, // Power Management Enable
+ output wire PMUDBGRESETREQ, // Power Management Debug Reset Req
// AHB Lite port
output wire [31:0] HADDR, // Address bus
@@ -79,55 +92,97 @@ module nanosoc_manager_cortexm0 #(
input wire RXEV, // Receive Event input
output wire SLEEPING, // Processor status - sleeping
output wire SLEEPDEEP, // Processor status - deep sleep
- output wire GATEHCLK, // Wake up request from WIC
output wire LOCKUP, // Wake up request from WIC
- output wire WAKEUP, // Wake up request from WIC
- input wire WICENREQ, // WIC enable request from PMU
- output wire WICENACK, // WIC enable ack to PMU
- input wire SLEEPHOLDREQn, // Sleep extension request from PM
- output wire SLEEPHOLDACKn, // Sleep extension request to PMU
- input wire CDBGPWRUPREQ, // Sleep extension request from PM
- output wire CDBGPWRUPACK, // Sleep extension request to PMU
- input wire SYSRESETREQ, // System reset request
- input wire WDOGRESETREQ, // Watchdog reset request
- input wire ADPRESETREQ, // ADP Debug reset request
+ output wire SYSRESETREQ, // System reset request
// Serial-Wire Debug
input wire SWDI, // SWD data input
input wire SWCLK, // SWD clock
output wire SWDO, // SWD data output
- output wire SWDOEN); // SWD data output enable
+ output wire SWDOEN // SWD data output enable
+);
+
+ // ---------------------------------------------------
+ // Cortex-M0 Power Management and Reset Control Unit
+ // ---------------------------------------------------
+ // Cortex-M0 Control to Core Connectivity
+ wire GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
+ wire WAKEUP; // Wake-up Signaling from Core
+ wire CDBGPWRUPREQ; // Core Debug Power Up Request
+ wire CDBGPWRUPACK; // Core Debug Power Up Acknowledge
+ wire WICENREQ; // WIC enable request from PMU
+ wire WICENACK; // Wake-on-Interrupt Enable ACK from Core
+ wire SLEEPHOLDREQn; // Core Sleep Hold Request
+ wire SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
+
+ // Cortex-M0 Control Instantiation
+ nanosoc_cortexm0_control #(
+ .CLKGATE_PRESENT(CLKGATE_PRESENT)
+ ) u_cpu_control (
+ // Input Clocks and Resets
+ .FCLK (FCLK), // Free running clock
+ .SYSRESETn (SYSRESETn), // System Reset
+ .SCANENABLE (SCANENABLE), // Scan Mode Enable
+ .TESTMODE (TESTMODE), // Test Mode Enable (Override Synchronisers)
+ // Generated Clocks and Resets
+ .SCLK (SCLK), // System clock
+ .HCLK (HCLK), // AHB Clock
+ .HRESETn (HRESETn), // AHB Reset
+ .PORESETn (PORESETn), // Power on reset
+ .DCLK (DCLK), // Debug clock
+ .DBGRESETn (DBGRESETn), // Debug reset
- // -------------------------------
- // Internal signals
- // -------------------------------
+ // System Reset Request
+ .NANOSOC_RESETREQ (NANOSOC_RESETREQ), // System Reset Request
- // clock, reset, and power control
+ // Power Management Control Signals
+ .PMUENABLE (PMUENABLE), // PMU Enable from System Register
+ .WAKEUP (WAKEUP), // Wake-up Signaling from Core
+ .SLEEPDEEP (SLEEPDEEP), // Debug Power Up Request
+ .GATEHCLK (GATEHCLK), // Control Signal from Core to Control CLock Gating of HCLK
- wire [33:0] WICSENSE;
+ // Power Management Request signals
+ .CDBGPWRUPREQ (CDBGPWRUPREQ), // Core Debug Power Up Request
+ .WICENREQ (WICENREQ), // WIC enable request from PMU
+ .SLEEPHOLDREQn (SLEEPHOLDREQn), // Core Sleep Hold Request
+ .PMUDBGRESETREQ (PMUDBGRESETREQ), // Power Management Unit Debug Reset Request
+ .CCTRLRESETREQ (CCTRLRESETREQ), // Core Control System Reset Request
- wire APBACTIVE; // APB bus active (for clock gating of PCLKG)
- wire LOCKUPRESET; // System Controller cfg - reset if lockup
- wire PMUENABLE; // System Controller cfg - Enable PMU
-
- // SysTick timer signals
+ // Power Management Ackowledge signals
+ .WICENACK (WICENACK), // Wake-on-Interrupt Enable ACK from Core
+ .SLEEPHOLDACKn (SLEEPHOLDACKn), // Sleep Hold Acknowledgement
+ .CDBGPWRUPACK (CDBGPWRUPACK) // Core Debug Power Up Acknowledge
+ );
+
+ // -------------------------------
+ // SysTick signals
+ // -------------------------------
+ // SysTick Timer Signals
wire STCLKEN;
wire [25:0] STCALIB;
+
+ // SysTick Control Instantiation
+ nanosoc_cortexm0_stclkctrl #(
+ .DIV_RATIO (18'd01000)
+ ) u_stclkctrl (
+ .FCLK (FCLK),
+ .SYSRESETn (HRESETn),
- // Processor debug signals
- wire DBGRESTART;
- wire DBGRESTARTED;
- wire EDBGRQ;
+ .STCLKEN (STCLKEN),
+ .STCALIB (STCALIB)
+ );
+ // -------------------------------
+ // Cortex-M0 CPU Instantiation
+ // -------------------------------
// Processor status
- wire HALTED;
wire [2:0] CODEHINTDE;
wire SPECHTRANS;
wire CODENSEQ;
wire SHAREABLE;
-
- // Cortex-M0 integration level
+
+ // Cortex-M0 Logic Instantiation
CORTEXM0INTEGRATION #(
.ACG (CLKGATE_PRESENT), // Architectural clock gating
.BE (BE), // Big-endian
@@ -143,15 +198,15 @@ module nanosoc_manager_cortexm0 #(
.WPT (WPT) // Number of DWT comparators
) u_cortex_m0_integration (
// System inputs
- .FCLK (FCLK), // FCLK
- .SCLK (SCLK), // SCLK generated from PMU
- .HCLK (HCLK), // HCLK generated from PMU
- .DCLK (DCLK), // DCLK generated from PMU
+ .FCLK (FCLKG), // FCLK
+ .SCLK (SCLKG), // SCLK generated from PMU
+ .HCLK (HCLKG), // HCLK generated from PMU
+ .DCLK (DCLKG), // DCLK generated from PMU
.PORESETn (PORESETn),
.HRESETn (HRESETn),
.DBGRESETn (DBGRESETn),
.RSTBYPASS (RSTBYPASS),
- .SE (DFTSE),
+ .SE (SCANENABLE),
// Power management inputs
.SLEEPHOLDREQn (SLEEPHOLDREQn),
@@ -164,22 +219,22 @@ module nanosoc_manager_cortexm0 #(
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.WAKEUP (WAKEUP),
- .WICSENSE (WICSENSE),
+ .WICSENSE ( ),
.GATEHCLK (GATEHCLK),
.SYSRESETREQ (SYSRESETREQ),
// System bus
- .HADDR (HADDR ),
- .HTRANS (HTRANS ),
- .HSIZE (HSIZE ),
- .HBURST (HBURST ),
- .HPROT (HPROT ),
- .HMASTLOCK (HMASTLOCK ),
- .HWRITE (HWRITE ),
- .HWDATA (HWDATA ),
- .HRDATA (HRDATA ),
- .HREADY (HREADY ),
- .HRESP (HRESP ),
+ .HADDR (HADDR),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HBURST (HBURST),
+ .HPROT (HPROT),
+ .HMASTLOCK (HMASTLOCK),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HRDATA (HRDATA),
+ .HREADY (HREADY),
+ .HRESP (HRESP),
.HMASTER ( ),
.CODEHINTDE (CODEHINTDE),
@@ -197,47 +252,30 @@ module nanosoc_manager_cortexm0 #(
.STCALIB (STCALIB),
// Debug - JTAG or Serial wire
- // inputs
+ // inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
- // outputs
+ // outputs
.TDO ( ),
.nTDOEN ( ),
.SWDO (SWDO),
.SWDOEN (SWDOEN),
- .DBGRESTART (DBGRESTART),
- .DBGRESTARTED (DBGRESTARTED),
+ .DBGRESTART (1'b0), // Unused - Multi-Core synchronous restart from halt
+ .DBGRESTARTED ( ), // Unused - Multi-Core synchronous restart from halt
// Event communication
.TXEV (TXEV),
.RXEV (RXEV),
- .EDBGRQ (EDBGRQ),
+ .EDBGRQ (1'b0), // Unused - Multi-Core synchronous halt request
+
// Status output
- .HALTED (HALTED),
+ .HALTED ( ),
.LOCKUP (LOCKUP),
.SLEEPING (SLEEPING),
.SLEEPDEEP (SLEEPDEEP)
);
- // Unused debug feature
- assign DBGRESTART = 1'b0; // multi-core synchronous restart from halt
- assign EDBGRQ = 1'b0; // multi-core synchronous halt request
-
- // -------------------------------
- // SysTick signals
- // -------------------------------
- nanosoc_stclkctrl #(
- .DIV_RATIO (18'd01000)
- ) u_nanosoc_mcu_stclkctrl (
- .FCLK (FCLK),
- .SYSRESETn (HRESETn),
-
- .STCLKEN (STCLKEN),
- .STCALIB (STCALIB)
- );
-
-
endmodule