diff --git a/flist/nanosoc_busmatrix_ip.flist b/flist/nanosoc_busmatrix_ip.flist
index a328ec80bc1c5f12a437276ad11cdfa634dad363..945880c99c5edcfa398ba7f89cacafc12e525550 100644
--- a/flist/nanosoc_busmatrix_ip.flist
+++ b/flist/nanosoc_busmatrix_ip.flist
@@ -17,6 +17,7 @@
// ============= NanoSoC BusMatrix IP search path =============
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
@@ -33,10 +34,11 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
-$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
diff --git a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
index 64f94570763c7b9e260d9fd39fa352d35fdf70e0..8855828fce4e551d9a5206a8a329d29a78804397 100644
--- a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
+++ b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -45,6 +45,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DEBUG_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -197,6 +198,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -348,6 +350,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_1_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -499,6 +502,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__CPU_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -789,6 +793,150 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0</spirit:name>
+ <spirit:description>Master port _EXTROM_0</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__EXTROM_0_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_EXTROM_0 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_EXTROM_0</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<spirit:busInterface>
<spirit:name>AHBLiteTarget_Master__IMEM_0</spirit:name>
<spirit:description>Master port _IMEM_0</spirit:description>
@@ -1863,10 +2011,19 @@
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_n0_1</spirit:name>
+ <spirit:description>Remap state remap_n0_1</spirit:description>
<spirit:remapPorts>
<spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="1">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0_n1</spirit:name>
+ <spirit:description>Remap state remap_n0_n1</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="1">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -1886,10 +2043,30 @@
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_BOOTROM_0_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x10000000_0x17ffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x008000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_AS</spirit:name>
+ <spirit:description>_EXTROM_0 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_EXTROM_0_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
+ <spirit:segment>
+ <spirit:name>_EXTROM_0_0x18000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x18000000</spirit:addressOffset>
+ <spirit:range>0x008000000</spirit:range>
+ </spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
@@ -2018,12 +2195,19 @@
<spirit:description>_DEBUG memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2091,13 +2275,24 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
- <spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
- <spirit:description>_DEBUG remap_n0 remap</spirit:description>
+ <spirit:memoryRemap spirit:state="remap_n0_1">
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_n0_1_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0_1 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is n0_1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x00000000_0_state_remap_n0_1_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0_n1">
+ <spirit:name>AHBLiteTarget_Slave__DEBUG_remap_n0_n1_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0_n1 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
- <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <!-- Removable region, active only when REMAP bitcombination is n0_n1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_n1_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2116,12 +2311,19 @@
</spirit:subspaceMap>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2185,12 +2387,19 @@
</spirit:subspaceMap>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2247,12 +2456,19 @@
<spirit:description>_CPU_0 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2320,13 +2536,24 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
- <spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_n0 remap</spirit:description>
+ <spirit:memoryRemap spirit:state="remap_n0_1">
+ <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_1_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_n0_1 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is n0_1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x00000000_0_state_remap_n0_1_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0_n1">
+ <spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_n1_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_n0_n1 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
- <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <!-- Removable region, active only when REMAP bitcombination is n0_n1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_n1_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2818,6 +3045,32 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HRDATA_IMEM_0</spirit:name>
<spirit:wire>
@@ -3112,6 +3365,100 @@
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HSEL_IMEM_0</spirit:name>
<spirit:wire>
@@ -3927,6 +4274,10 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
@@ -3959,6 +4310,10 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
diff --git a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
index b0ec4cd05819bc7e1a25e70903bdf31cd0891041..043d22378007036b67ebd5bb9055f5816e5acb8b 100644
--- a/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
+++ b/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -45,6 +45,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DEBUG_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -174,6 +175,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -302,6 +304,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_1_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -430,6 +433,7 @@
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__CPU_0_MM"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXTROM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
@@ -690,6 +694,143 @@
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0</spirit:name>
+ <spirit:description>Master port _EXTROM_0</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__EXTROM_0_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_EXTROM_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
<spirit:busInterface>
<spirit:name>AHBLiteTarget_Master__IMEM_0</spirit:name>
<spirit:description>Master port _IMEM_0</spirit:description>
@@ -1715,10 +1856,19 @@
</spirit:remapPorts>
</spirit:remapState>
<spirit:remapState>
- <spirit:name>remap_n0</spirit:name>
- <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:name>remap_n0_1</spirit:name>
+ <spirit:description>Remap state remap_n0_1</spirit:description>
<spirit:remapPorts>
<spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="1">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0_n1</spirit:name>
+ <spirit:description>Remap state remap_n0_n1</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="1">0</spirit:remapPort>
</spirit:remapPorts>
</spirit:remapState>
@@ -1738,10 +1888,30 @@
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_BOOTROM_0_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x10000000_0x17ffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x008000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_AS</spirit:name>
+ <spirit:description>_EXTROM_0 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_EXTROM_0_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
+ <spirit:segment>
+ <spirit:name>_EXTROM_0_0x18000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x18000000</spirit:addressOffset>
+ <spirit:range>0x008000000</spirit:range>
+ </spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
@@ -1870,12 +2040,19 @@
<spirit:description>_DEBUG memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -1943,13 +2120,24 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
- <spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_remap_MM</spirit:name>
- <spirit:description>_DEBUG remap_n0 remap</spirit:description>
+ <spirit:memoryRemap spirit:state="remap_n0_1">
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_1_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0_1 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is n0_1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x00000000_0_state_remap_n0_1_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0_n1">
+ <spirit:name>AHBLiteInitiator_Slave__DEBUG_remap_n0_n1_remap_MM</spirit:name>
+ <spirit:description>_DEBUG remap_n0_n1 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
- <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <!-- Removable region, active only when REMAP bitcombination is n0_n1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_n1_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -1968,12 +2156,19 @@
</spirit:subspaceMap>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2037,12 +2232,19 @@
</spirit:subspaceMap>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2099,12 +2301,19 @@
<spirit:description>_CPU_0 memory map</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
- spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
- <!-- Address_region 0x10000000-0x1fffffff -->
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x17ffffff">
+ <!-- Address_region 0x10000000-0x17ffffff -->
<spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x18000000_0x1fffffff">
+ <!-- Address_region 0x18000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x18000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x18000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
@@ -2172,13 +2381,24 @@
</spirit:subspaceMap>
</spirit:memoryRemap>
- <spirit:memoryRemap spirit:state="remap_n0">
- <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
- <spirit:description>_CPU_0 remap_n0 remap</spirit:description>
+ <spirit:memoryRemap spirit:state="remap_n0_1">
+ <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_1_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_n0_1 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__EXTROM_0"
+ spirit:segmentRef="_EXTROM_0_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is n0_1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__EXTROM_0_0x00000000_0_state_remap_n0_1_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0_n1">
+ <spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_n1_remap_MM</spirit:name>
+ <spirit:description>_CPU_0 remap_n0_n1 remap</spirit:description>
<spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
- <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <!-- Removable region, active only when REMAP bitcombination is n0_n1 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_n1_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2562,6 +2782,28 @@
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HRDATA_IMEM_0</spirit:name>
<spirit:wire>
@@ -2818,6 +3060,90 @@
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_EXTROM_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
<spirit:port>
<spirit:name>HSEL_IMEM_0</spirit:name>
<spirit:wire>
@@ -3551,6 +3877,10 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
@@ -3583,6 +3913,10 @@
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
+ <spirit:file>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
<spirit:file>
<spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
diff --git a/nanosoc/nanosoc_busmatrix/logs/nanosoc.log b/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
index 038f8afe8758dffb63e4e2d6e3a6ce02e88e64e9..d9ad973952831f07f46529771673033d0916d7eb 100644
--- a/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
+++ b/nanosoc/nanosoc_busmatrix/logs/nanosoc.log
@@ -14,89 +14,93 @@
=
= BuildBusMatrix.pl
=
-= Run Date : 16/06/2023 08:53:15
+= Run Date : 06/03/2025 11:53:40
==============================================================
Script accepted the following parameters:
- - Configuration file : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/xml/nanosoc.xml'
+ - Configuration file : '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml'
- Top-level name : 'nanosoc_busmatrix'
- Slave interfaces : 4
- - Master interfaces : 8
+ - Master interfaces : 9
- Architecture type : 'ahb2'
- Arbitration scheme : 'burst'
- Address map : user defined
- - Connectivity mapping : _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
- _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
- _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
- _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
+ - Connectivity mapping : _DEBUG -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+ _DMAC_0 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_1 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+ _CPU_0 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
- Connectivity type : sparse
- Routing data width : 32
- Routing address width : 32
- User signal width : 0
- Timescales : no
- - Configuration directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog'
+ - Configuration directory : '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog'
- Source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/verilog/src'
- - IPXact target directory : '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact'
+ - IPXact target directory : '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact'
- IPXact source directory : '/research/AAA/ip_library/latest/Corstone-101/logical/cmsdk_ahb_busmatrix/ipxact/src'
- Overwrite mode : enabled
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPANSION.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPANSION.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml' file...
+Deleting the '/home/dwf1m12/work/dev/accelerator-project-qspi/nanosoc_tech/nanosoc/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml' file...
Creating the bus matrix variant...
- - Rendering 'nanosoc_busmatrix.xml'
- - Rendering 'nanosoc_busmatrix_lite.xml'
- Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- - Rendering 'nanosoc_target_output_BOOTROM_0.v'
- - Rendering 'nanosoc_arbiter_EXP.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
+ - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
+ - Rendering 'nanosoc_matrix_decode_CPU_0.v'
- Rendering 'nanosoc_target_output_IMEM_0.v'
- - Rendering 'nanosoc_target_output_DMEM_0.v'
- - Rendering 'nanosoc_target_output_EXPRAM_L.v'
- - Rendering 'nanosoc_arbiter_SYSIO.v'
+ - Rendering 'nanosoc_inititator_input.v'
+ - Rendering 'nanosoc_arbiter_DMEM_0.v'
- Rendering 'nanosoc_target_output_SYSIO.v'
- Rendering 'nanosoc_busmatrix.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- - Rendering 'nanosoc_inititator_input.v'
- - Rendering 'nanosoc_target_output_EXPRAM_H.v'
- - Rendering 'nanosoc_arbiter_BOOTROM_0.v'
- - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_target_output_EXTROM_0.v'
- Rendering 'nanosoc_arbiter_IMEM_0.v'
- - Rendering 'nanosoc_arbiter_DMEM_0.v'
- - Rendering 'nanosoc_arbiter_SYSTABLE.v'
- - Rendering 'nanosoc_matrix_decode_CPU_0.v'
+ - Rendering 'nanosoc_arbiter_EXTROM_0.v'
+ - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_busmatrix_lite.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_H.v'
+ - Rendering 'nanosoc_target_output_BOOTROM_0.v'
+ - Rendering 'nanosoc_target_output_DMEM_0.v'
+ - Rendering 'nanosoc_arbiter_BOOTROM_0.v'
- Rendering 'nanosoc_matrix_decode_DEBUG.v'
- - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- - Rendering 'nanosoc_target_output_SYSTABLE.v'
+ - Rendering 'nanosoc_arbiter_SYSIO.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_L.v'
+ - Rendering 'nanosoc_busmatrix_lite.xml'
+ - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- Rendering 'nanosoc_target_output_EXP.v'
- - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_arbiter_EXP.v'
+ - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_H.v'
+ - Rendering 'nanosoc_target_output_SYSTABLE.v'
Done!
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
index 850c0bccd60e389146d4d5d9ada76dd3ba8092f2..287bd2c92b65eb2120d53ad77cd30ce27a95dc2f 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
index e2559ef58dfb6eb30868b759eb77d350e435cbda..e8e1f7c1d6ea50e1cd10cf35cc3251fb4d2517db 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
index 42a514fe5dada28a6eeada2033c99e5406cc4b18..319d1d27d6b4c8b085af8143c2417bda69fe8030 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
index d49521d8b5f460400525106e60625a50eb972162..354be78b57d1d99879edd7b0e64bd23b9c51e448 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
index 03c9c2571c3966f567e129e62dc9ac40fbad2e6a..0fc77f8b12532556a160b6d2e57fc7c062bd85e9 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..ff3512ad5bab044b9b12ab32d21bff58da105844
--- /dev/null
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXTROM_0.v
@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+// Abstract : The Output Arbitration is used to determine which
+// of the input stages will be given access to the
+// shared slave.
+//
+// Notes : The bus matrix has sparse connectivity.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_arbiter_EXTROM_0 (
+
+ // Common AHB signals
+ HCLK ,
+ HRESETn,
+
+ // Input port request signals
+ req_port0,
+ req_port1,
+ req_port2,
+ req_port3,
+
+ HREADYM,
+ HSELM,
+ HTRANSM,
+ HBURSTM,
+ HMASTLOCKM,
+
+ // Arbiter outputs
+ addr_in_port,
+ no_port
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+ input req_port0; // Port 0 request signal
+ input req_port1; // Port 1 request signal
+ input req_port2; // Port 2 request signal
+ input req_port3; // Port 3 request signal
+ input HREADYM; // Transfer done
+ input HSELM; // Slave select line
+ input [1:0] HTRANSM; // Transfer type
+ input [2:0] HBURSTM; // Burst type
+ input HMASTLOCKM; // Locked transfer
+ output [1:0] addr_in_port; // Port address input
+ output no_port; // No port selected signal
+
+
+// -----------------------------------------------------------------------------
+// Constant declarations
+// -----------------------------------------------------------------------------
+
+// HTRANS transfer type signal encoding
+`define TRN_IDLE 2'b00 // Idle transfer
+`define TRN_BUSY 2'b01 // Busy transfer
+`define TRN_NONSEQ 2'b10 // NonSequential transfer
+`define TRN_SEQ 2'b11 // Sequential transfer
+
+// HBURST transfer type signal encoding
+`define BUR_SINGLE 3'b000 // Single
+`define BUR_INCR 3'b001 // Incremental
+`define BUR_WRAP4 3'b010 // 4-beat wrap
+`define BUR_INCR4 3'b011 // 4-beat Incr
+`define BUR_WRAP8 3'b100 // 8-beat wrap
+`define BUR_INCR8 3'b101 // 8-beat Incr
+`define BUR_WRAP16 3'b110 // 16-beat Wrap
+`define BUR_INCR16 3'b111 // 16-beat Incr
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+ wire HREADYM; // Transfer done
+ wire HSELM; // Slave select line
+ wire [1:0] HTRANSM; // Transfer type
+ wire [2:0] HBURSTM; // Burst type
+ wire HMASTLOCKM; // Locked transfer
+ wire [1:0] addr_in_port; // Address input port
+ reg no_port; // No port selected signal
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ reg [1:0] addr_in_port_next; // D-input of addr_in_port
+ reg [1:0] i_addr_in_port; // Internal version of addr_in_port
+ reg no_port_next; // D-input of no_port
+ reg [3:0] next_burst_count; // D-input of reg_burst_count
+ reg [3:0] reg_burst_count; // Burst counter
+ reg next_burst_hold; // D-input of reg_burst_hold
+ reg reg_burst_hold; // Burst hold signal
+
+ // Early burst termination logic
+ reg [1:0] reg_early_term_count; // Counts number of early terminated bursts
+ wire [1:0] next_early_term_count; // D-input for reg_early_term_count
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// BURST TRANSFER COUNTER
+// -----------------------------------------------------------------------------
+//
+// The Burst counter is used to count down from the number of transfers the
+// master should perform and when the counter reaches zero the bus may be
+// passed to another master.
+//
+// reg_burst_count indicates the number of transfers remaining in the
+// current fixed length burst.
+// reg_burst_hold is actually a decode of reg_burst_count=0 but is driven from a register
+// to improve timing
+
+ always @ (HTRANSM or HSELM or HBURSTM or reg_burst_count or reg_burst_hold or reg_early_term_count)
+ begin : p_next_burst_count_comb
+ // Force the Burst logic to reset if this port is de-selected. This can
+ // happen for two reasons:
+ // 1. The master performs 2 fixed-length bursts back-to-back, but the
+ // second is to an alternate output port
+ // 2. The master is performing a fixed-length burst but is de-granted mid-
+ // way by a local AHB Arbiter
+ if (!HSELM)
+ begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end
+
+ // Burst logic is initialised on a NONSEQ transfer (i.e. start of burst)
+ // IDLE transfers cause the logic to reset
+ // BUSY transfers pause the decrementer
+ // SEQ transfers decrement the counter
+ else
+ case (HTRANSM)
+
+ `TRN_NONSEQ : begin
+ case (HBURSTM)
+ `BUR_INCR16, `BUR_WRAP16 : begin
+ next_burst_count = 4'b1111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR16 | BUR_WRAP16
+
+ `BUR_INCR8, `BUR_WRAP8 : begin
+ next_burst_count = 4'b0111;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR8 | BUR_WRAP8
+
+ `BUR_INCR4, `BUR_WRAP4 : begin
+ next_burst_count = 4'b0011;
+ next_burst_hold = 1'b1;
+ end // case: BUR_INCR4 | BUR_WRAP4
+
+ `BUR_SINGLE, `BUR_INCR : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: BUR_SINGLE | BUR_INCR
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+ endcase // case(HBURSTM)
+
+ // Prevent early burst termination from keeping hold of the port
+ if (reg_early_term_count == 2'b10)
+ begin
+ next_burst_hold = 1'b0;
+ next_burst_count = 4'd0;
+ end
+
+
+ end // case: `TRN_NONSEQ
+
+ `TRN_SEQ : begin
+ next_burst_count = reg_burst_count - 4'b1;
+ if (reg_burst_count == 4'b0001)
+ next_burst_hold = 1'b0;
+ else
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_SEQ
+
+ `TRN_BUSY : begin
+ next_burst_count = reg_burst_count;
+ next_burst_hold = reg_burst_hold;
+ end // case: `TRN_BUSY
+
+ `TRN_IDLE : begin
+ next_burst_count = 4'b0000;
+ next_burst_hold = 1'b0;
+ end // case: `TRN_IDLE
+
+ default : begin
+ next_burst_count = 4'bxxxx;
+ next_burst_hold = 1'bx;
+ end // case: default
+
+ endcase // case(HTRANSM)
+ end // block: p_next_burst_countComb
+
+
+ assign next_early_term_count = (!next_burst_hold) ? 2'b00 :
+ (reg_burst_hold & (HTRANSM == `TRN_NONSEQ)) ?
+ reg_early_term_count + 2'b1 :
+ reg_early_term_count;
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_burst_seq
+ if (!HRESETn)
+ begin
+ reg_burst_count <= 4'b0000;
+ reg_burst_hold <= 1'b0;
+ reg_early_term_count <= 2'b00;
+ end // if (HRESETn == 1'b0)
+ else
+ if (HREADYM)
+ begin
+ reg_burst_count <= next_burst_count;
+ reg_burst_hold <= next_burst_hold;
+ reg_early_term_count <= next_early_term_count;
+ end
+ end // block: p_burst_seq
+
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+// The Output Arbitration function looks at all the requests to use the
+// output port and determines which is the highest priority request. This
+// version of the arbitration logic uses a fixed priority scheme that is
+// gated by a tracking function of the burst boundary. Input port 0 is the
+// highest priority, input port 1 is the second highest priority, etc.
+// If none of the input ports are requesting then the current port will
+// remain active if it is performing IDLE transfers to the selected slave. If
+// this is not the case then the no_port signal will be asserted which
+// indicates that no input port should be selected.
+
+ always @ (
+ req_port0 or
+ req_port1 or
+ req_port2 or
+ req_port3 or
+ HSELM or HTRANSM or HMASTLOCKM or next_burst_hold or i_addr_in_port
+ )
+ begin : p_sel_port_comb
+ // Default values are used for addr_in_port_next and no_port_next
+ no_port_next = 1'b0;
+ addr_in_port_next = i_addr_in_port;
+
+ if ( HMASTLOCKM | next_burst_hold )
+ addr_in_port_next = i_addr_in_port;
+ else if ( req_port0 | ( (i_addr_in_port == 2'b00) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b00;
+ else if ( req_port1 | ( (i_addr_in_port == 2'b01) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b01;
+ else if ( req_port2 | ( (i_addr_in_port == 2'b10) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b10;
+ else if ( req_port3 | ( (i_addr_in_port == 2'b11) & HSELM &
+ (HTRANSM != 2'b00) ) )
+ addr_in_port_next = 2'b11;
+ else if (HSELM)
+ addr_in_port_next = i_addr_in_port;
+ else
+ no_port_next = 1'b1;
+ end // block: p_sel_port_comb
+
+
+ // Sequential process
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_addr_in_port_reg
+ if (!HRESETn)
+ begin
+ no_port <= 1'b1;
+ i_addr_in_port <= {2{1'b0}};
+ end
+ else
+ if (HREADYM)
+ begin
+ no_port <= no_port_next;
+ i_addr_in_port <= addr_in_port_next;
+ end
+ end // block: p_addr_in_port_reg
+
+ // Drive output with internal version
+ assign addr_in_port = i_addr_in_port;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
index 7e3ec3846216af3a7076d6660ab27fc38e92184a..d97f0d49479737ec102220e8225ca9d35c0a0dc0 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
index ebbf33182df87673cdb9f6fd909b20fd192c794a..f6adaae7393e4bee1d7ddd02179c0f1046b27bd9 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
index b0e8bef703369190c81fae4682b56b3ff8a22df1..17c955198dcf8be0a04d3e453b5e0c745fbad9f3 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index 9defea1e4032b715b527c70e4dc83f6e95c4f8bc..6f775bf8ee1c18717fcd3200519d7cb51445e77a 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -30,15 +30,15 @@
//
// - Architecture type 'ahb2',
// - 4 slave ports (connecting to masters),
-// - 8 master ports (connecting to slaves),
+// - 9 master ports (connecting to slaves),
// - Routing address width of 32 bits,
// - Routing data width of 32 bits,
// - Arbiter type 'burst',
// - Connectivity mapping:
-// _DEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
-// _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
-// _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
-// _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+// _DEBUG -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+// _DMAC_0 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_1 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H,
+// _CPU_0 -> _BOOTROM_0, _EXTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// - Connectivity type 'sparse'.
//
//------------------------------------------------------------------------------
@@ -112,36 +112,41 @@ module nanosoc_busmatrix (
HRESP_BOOTROM_0,
// Output port MI1 (inputs from slave 1)
+ HRDATA_EXTROM_0,
+ HREADYOUT_EXTROM_0,
+ HRESP_EXTROM_0,
+
+ // Output port MI2 (inputs from slave 2)
HRDATA_IMEM_0,
HREADYOUT_IMEM_0,
HRESP_IMEM_0,
- // Output port MI2 (inputs from slave 2)
+ // Output port MI3 (inputs from slave 3)
HRDATA_DMEM_0,
HREADYOUT_DMEM_0,
HRESP_DMEM_0,
- // Output port MI3 (inputs from slave 3)
+ // Output port MI4 (inputs from slave 4)
HRDATA_SYSIO,
HREADYOUT_SYSIO,
HRESP_SYSIO,
- // Output port MI4 (inputs from slave 4)
+ // Output port MI5 (inputs from slave 5)
HRDATA_EXPRAM_L,
HREADYOUT_EXPRAM_L,
HRESP_EXPRAM_L,
- // Output port MI5 (inputs from slave 5)
+ // Output port MI6 (inputs from slave 6)
HRDATA_EXPRAM_H,
HREADYOUT_EXPRAM_H,
HRESP_EXPRAM_H,
- // Output port MI6 (inputs from slave 6)
+ // Output port MI7 (inputs from slave 7)
HRDATA_EXP,
HREADYOUT_EXP,
HRESP_EXP,
- // Output port MI7 (inputs from slave 7)
+ // Output port MI8 (inputs from slave 8)
HRDATA_SYSTABLE,
HREADYOUT_SYSTABLE,
HRESP_SYSTABLE,
@@ -165,6 +170,19 @@ module nanosoc_busmatrix (
HREADYMUX_BOOTROM_0,
// Output port MI1 (outputs to slave 1)
+ HSEL_EXTROM_0,
+ HADDR_EXTROM_0,
+ HTRANS_EXTROM_0,
+ HWRITE_EXTROM_0,
+ HSIZE_EXTROM_0,
+ HBURST_EXTROM_0,
+ HPROT_EXTROM_0,
+ HMASTER_EXTROM_0,
+ HWDATA_EXTROM_0,
+ HMASTLOCK_EXTROM_0,
+ HREADYMUX_EXTROM_0,
+
+ // Output port MI2 (outputs to slave 2)
HSEL_IMEM_0,
HADDR_IMEM_0,
HTRANS_IMEM_0,
@@ -177,7 +195,7 @@ module nanosoc_busmatrix (
HMASTLOCK_IMEM_0,
HREADYMUX_IMEM_0,
- // Output port MI2 (outputs to slave 2)
+ // Output port MI3 (outputs to slave 3)
HSEL_DMEM_0,
HADDR_DMEM_0,
HTRANS_DMEM_0,
@@ -190,7 +208,7 @@ module nanosoc_busmatrix (
HMASTLOCK_DMEM_0,
HREADYMUX_DMEM_0,
- // Output port MI3 (outputs to slave 3)
+ // Output port MI4 (outputs to slave 4)
HSEL_SYSIO,
HADDR_SYSIO,
HTRANS_SYSIO,
@@ -203,7 +221,7 @@ module nanosoc_busmatrix (
HMASTLOCK_SYSIO,
HREADYMUX_SYSIO,
- // Output port MI4 (outputs to slave 4)
+ // Output port MI5 (outputs to slave 5)
HSEL_EXPRAM_L,
HADDR_EXPRAM_L,
HTRANS_EXPRAM_L,
@@ -216,7 +234,7 @@ module nanosoc_busmatrix (
HMASTLOCK_EXPRAM_L,
HREADYMUX_EXPRAM_L,
- // Output port MI5 (outputs to slave 5)
+ // Output port MI6 (outputs to slave 6)
HSEL_EXPRAM_H,
HADDR_EXPRAM_H,
HTRANS_EXPRAM_H,
@@ -229,7 +247,7 @@ module nanosoc_busmatrix (
HMASTLOCK_EXPRAM_H,
HREADYMUX_EXPRAM_H,
- // Output port MI6 (outputs to slave 6)
+ // Output port MI7 (outputs to slave 7)
HSEL_EXP,
HADDR_EXP,
HTRANS_EXP,
@@ -242,7 +260,7 @@ module nanosoc_busmatrix (
HMASTLOCK_EXP,
HREADYMUX_EXP,
- // Output port MI7 (outputs to slave 7)
+ // Output port MI8 (outputs to slave 8)
HSEL_SYSTABLE,
HADDR_SYSTABLE,
HTRANS_SYSTABLE,
@@ -350,36 +368,41 @@ module nanosoc_busmatrix (
input [1:0] HRESP_BOOTROM_0; // Transfer response
// Output port MI1 (inputs from slave 1)
+ input [31:0] HRDATA_EXTROM_0; // Read data bus
+ input HREADYOUT_EXTROM_0; // HREADY feedback
+ input [1:0] HRESP_EXTROM_0; // Transfer response
+
+ // Output port MI2 (inputs from slave 2)
input [31:0] HRDATA_IMEM_0; // Read data bus
input HREADYOUT_IMEM_0; // HREADY feedback
input [1:0] HRESP_IMEM_0; // Transfer response
- // Output port MI2 (inputs from slave 2)
+ // Output port MI3 (inputs from slave 3)
input [31:0] HRDATA_DMEM_0; // Read data bus
input HREADYOUT_DMEM_0; // HREADY feedback
input [1:0] HRESP_DMEM_0; // Transfer response
- // Output port MI3 (inputs from slave 3)
+ // Output port MI4 (inputs from slave 4)
input [31:0] HRDATA_SYSIO; // Read data bus
input HREADYOUT_SYSIO; // HREADY feedback
input [1:0] HRESP_SYSIO; // Transfer response
- // Output port MI4 (inputs from slave 4)
+ // Output port MI5 (inputs from slave 5)
input [31:0] HRDATA_EXPRAM_L; // Read data bus
input HREADYOUT_EXPRAM_L; // HREADY feedback
input [1:0] HRESP_EXPRAM_L; // Transfer response
- // Output port MI5 (inputs from slave 5)
+ // Output port MI6 (inputs from slave 6)
input [31:0] HRDATA_EXPRAM_H; // Read data bus
input HREADYOUT_EXPRAM_H; // HREADY feedback
input [1:0] HRESP_EXPRAM_H; // Transfer response
- // Output port MI6 (inputs from slave 6)
+ // Output port MI7 (inputs from slave 7)
input [31:0] HRDATA_EXP; // Read data bus
input HREADYOUT_EXP; // HREADY feedback
input [1:0] HRESP_EXP; // Transfer response
- // Output port MI7 (inputs from slave 7)
+ // Output port MI8 (inputs from slave 8)
input [31:0] HRDATA_SYSTABLE; // Read data bus
input HREADYOUT_SYSTABLE; // HREADY feedback
input [1:0] HRESP_SYSTABLE; // Transfer response
@@ -403,6 +426,19 @@ module nanosoc_busmatrix (
output HREADYMUX_BOOTROM_0; // Transfer done
// Output port MI1 (outputs to slave 1)
+ output HSEL_EXTROM_0; // Slave Select
+ output [31:0] HADDR_EXTROM_0; // Address bus
+ output [1:0] HTRANS_EXTROM_0; // Transfer type
+ output HWRITE_EXTROM_0; // Transfer direction
+ output [2:0] HSIZE_EXTROM_0; // Transfer size
+ output [2:0] HBURST_EXTROM_0; // Burst type
+ output [3:0] HPROT_EXTROM_0; // Protection control
+ output [3:0] HMASTER_EXTROM_0; // Master select
+ output [31:0] HWDATA_EXTROM_0; // Write data
+ output HMASTLOCK_EXTROM_0; // Locked Sequence
+ output HREADYMUX_EXTROM_0; // Transfer done
+
+ // Output port MI2 (outputs to slave 2)
output HSEL_IMEM_0; // Slave Select
output [31:0] HADDR_IMEM_0; // Address bus
output [1:0] HTRANS_IMEM_0; // Transfer type
@@ -415,7 +451,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_IMEM_0; // Locked Sequence
output HREADYMUX_IMEM_0; // Transfer done
- // Output port MI2 (outputs to slave 2)
+ // Output port MI3 (outputs to slave 3)
output HSEL_DMEM_0; // Slave Select
output [31:0] HADDR_DMEM_0; // Address bus
output [1:0] HTRANS_DMEM_0; // Transfer type
@@ -428,7 +464,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_DMEM_0; // Locked Sequence
output HREADYMUX_DMEM_0; // Transfer done
- // Output port MI3 (outputs to slave 3)
+ // Output port MI4 (outputs to slave 4)
output HSEL_SYSIO; // Slave Select
output [31:0] HADDR_SYSIO; // Address bus
output [1:0] HTRANS_SYSIO; // Transfer type
@@ -441,7 +477,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_SYSIO; // Locked Sequence
output HREADYMUX_SYSIO; // Transfer done
- // Output port MI4 (outputs to slave 4)
+ // Output port MI5 (outputs to slave 5)
output HSEL_EXPRAM_L; // Slave Select
output [31:0] HADDR_EXPRAM_L; // Address bus
output [1:0] HTRANS_EXPRAM_L; // Transfer type
@@ -454,7 +490,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_EXPRAM_L; // Locked Sequence
output HREADYMUX_EXPRAM_L; // Transfer done
- // Output port MI5 (outputs to slave 5)
+ // Output port MI6 (outputs to slave 6)
output HSEL_EXPRAM_H; // Slave Select
output [31:0] HADDR_EXPRAM_H; // Address bus
output [1:0] HTRANS_EXPRAM_H; // Transfer type
@@ -467,7 +503,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_EXPRAM_H; // Locked Sequence
output HREADYMUX_EXPRAM_H; // Transfer done
- // Output port MI6 (outputs to slave 6)
+ // Output port MI7 (outputs to slave 7)
output HSEL_EXP; // Slave Select
output [31:0] HADDR_EXP; // Address bus
output [1:0] HTRANS_EXP; // Transfer type
@@ -480,7 +516,7 @@ module nanosoc_busmatrix (
output HMASTLOCK_EXP; // Locked Sequence
output HREADYMUX_EXP; // Transfer done
- // Output port MI7 (outputs to slave 7)
+ // Output port MI8 (outputs to slave 8)
output HSEL_SYSTABLE; // Slave Select
output [31:0] HADDR_SYSTABLE; // Address bus
output [1:0] HTRANS_SYSTABLE; // Transfer type
@@ -614,6 +650,23 @@ module nanosoc_busmatrix (
wire [1:0] HRESP_BOOTROM_0; // Transfer response
// Output Port MI1
+ wire HSEL_EXTROM_0; // Slave Select
+ wire [31:0] HADDR_EXTROM_0; // Address bus
+ wire [1:0] HTRANS_EXTROM_0; // Transfer type
+ wire HWRITE_EXTROM_0; // Transfer direction
+ wire [2:0] HSIZE_EXTROM_0; // Transfer size
+ wire [2:0] HBURST_EXTROM_0; // Burst type
+ wire [3:0] HPROT_EXTROM_0; // Protection control
+ wire [3:0] HMASTER_EXTROM_0; // Master select
+ wire [31:0] HWDATA_EXTROM_0; // Write data
+ wire HMASTLOCK_EXTROM_0; // Locked Sequence
+ wire HREADYMUX_EXTROM_0; // Transfer done
+
+ wire [31:0] HRDATA_EXTROM_0; // Read data bus
+ wire HREADYOUT_EXTROM_0; // HREADY feedback
+ wire [1:0] HRESP_EXTROM_0; // Transfer response
+
+ // Output Port MI2
wire HSEL_IMEM_0; // Slave Select
wire [31:0] HADDR_IMEM_0; // Address bus
wire [1:0] HTRANS_IMEM_0; // Transfer type
@@ -630,7 +683,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_IMEM_0; // HREADY feedback
wire [1:0] HRESP_IMEM_0; // Transfer response
- // Output Port MI2
+ // Output Port MI3
wire HSEL_DMEM_0; // Slave Select
wire [31:0] HADDR_DMEM_0; // Address bus
wire [1:0] HTRANS_DMEM_0; // Transfer type
@@ -647,7 +700,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_DMEM_0; // HREADY feedback
wire [1:0] HRESP_DMEM_0; // Transfer response
- // Output Port MI3
+ // Output Port MI4
wire HSEL_SYSIO; // Slave Select
wire [31:0] HADDR_SYSIO; // Address bus
wire [1:0] HTRANS_SYSIO; // Transfer type
@@ -664,7 +717,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_SYSIO; // HREADY feedback
wire [1:0] HRESP_SYSIO; // Transfer response
- // Output Port MI4
+ // Output Port MI5
wire HSEL_EXPRAM_L; // Slave Select
wire [31:0] HADDR_EXPRAM_L; // Address bus
wire [1:0] HTRANS_EXPRAM_L; // Transfer type
@@ -681,7 +734,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_EXPRAM_L; // HREADY feedback
wire [1:0] HRESP_EXPRAM_L; // Transfer response
- // Output Port MI5
+ // Output Port MI6
wire HSEL_EXPRAM_H; // Slave Select
wire [31:0] HADDR_EXPRAM_H; // Address bus
wire [1:0] HTRANS_EXPRAM_H; // Transfer type
@@ -698,7 +751,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_EXPRAM_H; // HREADY feedback
wire [1:0] HRESP_EXPRAM_H; // Transfer response
- // Output Port MI6
+ // Output Port MI7
wire HSEL_EXP; // Slave Select
wire [31:0] HADDR_EXP; // Address bus
wire [1:0] HTRANS_EXP; // Transfer type
@@ -715,7 +768,7 @@ module nanosoc_busmatrix (
wire HREADYOUT_EXP; // HREADY feedback
wire [1:0] HRESP_EXP; // Transfer response
- // Output Port MI7
+ // Output Port MI8
wire HSEL_SYSTABLE; // Slave Select
wire [31:0] HADDR_SYSTABLE; // Address bus
wire [1:0] HTRANS_SYSTABLE; // Transfer type
@@ -829,6 +882,10 @@ module nanosoc_busmatrix (
wire i_sel0to7; // Routing selection signal
wire i_active0to7; // Active signal
+ // Bus-switch SI0 to MI8 signals
+ wire i_sel0to8; // Routing selection signal
+ wire i_active0to8; // Active signal
+
// Bus-switch SI1 to MI0 signals
wire i_sel1to0; // Routing selection signal
wire i_active1to0; // Active signal
@@ -857,6 +914,10 @@ module nanosoc_busmatrix (
wire i_sel1to6; // Routing selection signal
wire i_active1to6; // Active signal
+ // Bus-switch SI1 to MI7 signals
+ wire i_sel1to7; // Routing selection signal
+ wire i_active1to7; // Active signal
+
// Bus-switch SI2 to MI0 signals
wire i_sel2to0; // Routing selection signal
wire i_active2to0; // Active signal
@@ -885,6 +946,10 @@ module nanosoc_busmatrix (
wire i_sel2to6; // Routing selection signal
wire i_active2to6; // Active signal
+ // Bus-switch SI2 to MI7 signals
+ wire i_sel2to7; // Routing selection signal
+ wire i_active2to7; // Active signal
+
// Bus-switch SI3 to MI0 signals
wire i_sel3to0; // Routing selection signal
wire i_active3to0; // Active signal
@@ -917,14 +982,19 @@ module nanosoc_busmatrix (
wire i_sel3to7; // Routing selection signal
wire i_active3to7; // Active signal
+ // Bus-switch SI3 to MI8 signals
+ wire i_sel3to8; // Routing selection signal
+ wire i_active3to8; // Active signal
+
wire i_hready_mux__bootrom_0; // Internal HREADYMUXM for MI0
- wire i_hready_mux__imem_0; // Internal HREADYMUXM for MI1
- wire i_hready_mux__dmem_0; // Internal HREADYMUXM for MI2
- wire i_hready_mux__sysio; // Internal HREADYMUXM for MI3
- wire i_hready_mux__expram_l; // Internal HREADYMUXM for MI4
- wire i_hready_mux__expram_h; // Internal HREADYMUXM for MI5
- wire i_hready_mux__exp; // Internal HREADYMUXM for MI6
- wire i_hready_mux__systable; // Internal HREADYMUXM for MI7
+ wire i_hready_mux__extrom_0; // Internal HREADYMUXM for MI1
+ wire i_hready_mux__imem_0; // Internal HREADYMUXM for MI2
+ wire i_hready_mux__dmem_0; // Internal HREADYMUXM for MI3
+ wire i_hready_mux__sysio; // Internal HREADYMUXM for MI4
+ wire i_hready_mux__expram_l; // Internal HREADYMUXM for MI5
+ wire i_hready_mux__expram_h; // Internal HREADYMUXM for MI6
+ wire i_hready_mux__exp; // Internal HREADYMUXM for MI7
+ wire i_hready_mux__systable; // Internal HREADYMUXM for MI8
// -----------------------------------------------------------------------------
@@ -1111,7 +1181,7 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Internal address remapping control
- .remapping_dec ( REMAP[0] ),
+ .remapping_dec ( { REMAP[1], REMAP[0] } ),
// Signals from Input stage SI0
.HREADYS (HREADY_DEBUG),
@@ -1127,45 +1197,51 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI1
.active_dec1 (i_active0to1),
- .readyout_dec1 (i_hready_mux__imem_0),
- .resp_dec1 (HRESP_IMEM_0),
- .rdata_dec1 (HRDATA_IMEM_0),
+ .readyout_dec1 (i_hready_mux__extrom_0),
+ .resp_dec1 (HRESP_EXTROM_0),
+ .rdata_dec1 (HRDATA_EXTROM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active0to2),
- .readyout_dec2 (i_hready_mux__dmem_0),
- .resp_dec2 (HRESP_DMEM_0),
- .rdata_dec2 (HRDATA_DMEM_0),
+ .readyout_dec2 (i_hready_mux__imem_0),
+ .resp_dec2 (HRESP_IMEM_0),
+ .rdata_dec2 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active0to3),
- .readyout_dec3 (i_hready_mux__sysio),
- .resp_dec3 (HRESP_SYSIO),
- .rdata_dec3 (HRDATA_SYSIO),
+ .readyout_dec3 (i_hready_mux__dmem_0),
+ .resp_dec3 (HRESP_DMEM_0),
+ .rdata_dec3 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI4
.active_dec4 (i_active0to4),
- .readyout_dec4 (i_hready_mux__expram_l),
- .resp_dec4 (HRESP_EXPRAM_L),
- .rdata_dec4 (HRDATA_EXPRAM_L),
+ .readyout_dec4 (i_hready_mux__sysio),
+ .resp_dec4 (HRESP_SYSIO),
+ .rdata_dec4 (HRDATA_SYSIO),
// Control/Response for Output Stage MI5
.active_dec5 (i_active0to5),
- .readyout_dec5 (i_hready_mux__expram_h),
- .resp_dec5 (HRESP_EXPRAM_H),
- .rdata_dec5 (HRDATA_EXPRAM_H),
+ .readyout_dec5 (i_hready_mux__expram_l),
+ .resp_dec5 (HRESP_EXPRAM_L),
+ .rdata_dec5 (HRDATA_EXPRAM_L),
// Control/Response for Output Stage MI6
.active_dec6 (i_active0to6),
- .readyout_dec6 (i_hready_mux__exp),
- .resp_dec6 (HRESP_EXP),
- .rdata_dec6 (HRDATA_EXP),
+ .readyout_dec6 (i_hready_mux__expram_h),
+ .resp_dec6 (HRESP_EXPRAM_H),
+ .rdata_dec6 (HRDATA_EXPRAM_H),
// Control/Response for Output Stage MI7
.active_dec7 (i_active0to7),
- .readyout_dec7 (i_hready_mux__systable),
- .resp_dec7 (HRESP_SYSTABLE),
- .rdata_dec7 (HRDATA_SYSTABLE),
+ .readyout_dec7 (i_hready_mux__exp),
+ .resp_dec7 (HRESP_EXP),
+ .rdata_dec7 (HRDATA_EXP),
+
+ // Control/Response for Output Stage MI8
+ .active_dec8 (i_active0to8),
+ .readyout_dec8 (i_hready_mux__systable),
+ .resp_dec8 (HRESP_SYSTABLE),
+ .rdata_dec8 (HRDATA_SYSTABLE),
.sel_dec0 (i_sel0to0),
.sel_dec1 (i_sel0to1),
@@ -1175,6 +1251,7 @@ module nanosoc_busmatrix (
.sel_dec5 (i_sel0to5),
.sel_dec6 (i_sel0to6),
.sel_dec7 (i_sel0to7),
+ .sel_dec8 (i_sel0to8),
.active_dec (i_active0),
.HREADYOUTS (i_readyout0),
@@ -1205,39 +1282,45 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI1
.active_dec1 (i_active1to1),
- .readyout_dec1 (i_hready_mux__imem_0),
- .resp_dec1 (HRESP_IMEM_0),
- .rdata_dec1 (HRDATA_IMEM_0),
+ .readyout_dec1 (i_hready_mux__extrom_0),
+ .resp_dec1 (HRESP_EXTROM_0),
+ .rdata_dec1 (HRDATA_EXTROM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active1to2),
- .readyout_dec2 (i_hready_mux__dmem_0),
- .resp_dec2 (HRESP_DMEM_0),
- .rdata_dec2 (HRDATA_DMEM_0),
+ .readyout_dec2 (i_hready_mux__imem_0),
+ .resp_dec2 (HRESP_IMEM_0),
+ .rdata_dec2 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active1to3),
- .readyout_dec3 (i_hready_mux__sysio),
- .resp_dec3 (HRESP_SYSIO),
- .rdata_dec3 (HRDATA_SYSIO),
+ .readyout_dec3 (i_hready_mux__dmem_0),
+ .resp_dec3 (HRESP_DMEM_0),
+ .rdata_dec3 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI4
.active_dec4 (i_active1to4),
- .readyout_dec4 (i_hready_mux__expram_l),
- .resp_dec4 (HRESP_EXPRAM_L),
- .rdata_dec4 (HRDATA_EXPRAM_L),
+ .readyout_dec4 (i_hready_mux__sysio),
+ .resp_dec4 (HRESP_SYSIO),
+ .rdata_dec4 (HRDATA_SYSIO),
// Control/Response for Output Stage MI5
.active_dec5 (i_active1to5),
- .readyout_dec5 (i_hready_mux__expram_h),
- .resp_dec5 (HRESP_EXPRAM_H),
- .rdata_dec5 (HRDATA_EXPRAM_H),
+ .readyout_dec5 (i_hready_mux__expram_l),
+ .resp_dec5 (HRESP_EXPRAM_L),
+ .rdata_dec5 (HRDATA_EXPRAM_L),
// Control/Response for Output Stage MI6
.active_dec6 (i_active1to6),
- .readyout_dec6 (i_hready_mux__exp),
- .resp_dec6 (HRESP_EXP),
- .rdata_dec6 (HRDATA_EXP),
+ .readyout_dec6 (i_hready_mux__expram_h),
+ .resp_dec6 (HRESP_EXPRAM_H),
+ .rdata_dec6 (HRDATA_EXPRAM_H),
+
+ // Control/Response for Output Stage MI7
+ .active_dec7 (i_active1to7),
+ .readyout_dec7 (i_hready_mux__exp),
+ .resp_dec7 (HRESP_EXP),
+ .rdata_dec7 (HRDATA_EXP),
.sel_dec0 (i_sel1to0),
.sel_dec1 (i_sel1to1),
@@ -1246,6 +1329,7 @@ module nanosoc_busmatrix (
.sel_dec4 (i_sel1to4),
.sel_dec5 (i_sel1to5),
.sel_dec6 (i_sel1to6),
+ .sel_dec7 (i_sel1to7),
.active_dec (i_active1),
.HREADYOUTS (i_readyout1),
@@ -1276,39 +1360,45 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI1
.active_dec1 (i_active2to1),
- .readyout_dec1 (i_hready_mux__imem_0),
- .resp_dec1 (HRESP_IMEM_0),
- .rdata_dec1 (HRDATA_IMEM_0),
+ .readyout_dec1 (i_hready_mux__extrom_0),
+ .resp_dec1 (HRESP_EXTROM_0),
+ .rdata_dec1 (HRDATA_EXTROM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active2to2),
- .readyout_dec2 (i_hready_mux__dmem_0),
- .resp_dec2 (HRESP_DMEM_0),
- .rdata_dec2 (HRDATA_DMEM_0),
+ .readyout_dec2 (i_hready_mux__imem_0),
+ .resp_dec2 (HRESP_IMEM_0),
+ .rdata_dec2 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active2to3),
- .readyout_dec3 (i_hready_mux__sysio),
- .resp_dec3 (HRESP_SYSIO),
- .rdata_dec3 (HRDATA_SYSIO),
+ .readyout_dec3 (i_hready_mux__dmem_0),
+ .resp_dec3 (HRESP_DMEM_0),
+ .rdata_dec3 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI4
.active_dec4 (i_active2to4),
- .readyout_dec4 (i_hready_mux__expram_l),
- .resp_dec4 (HRESP_EXPRAM_L),
- .rdata_dec4 (HRDATA_EXPRAM_L),
+ .readyout_dec4 (i_hready_mux__sysio),
+ .resp_dec4 (HRESP_SYSIO),
+ .rdata_dec4 (HRDATA_SYSIO),
// Control/Response for Output Stage MI5
.active_dec5 (i_active2to5),
- .readyout_dec5 (i_hready_mux__expram_h),
- .resp_dec5 (HRESP_EXPRAM_H),
- .rdata_dec5 (HRDATA_EXPRAM_H),
+ .readyout_dec5 (i_hready_mux__expram_l),
+ .resp_dec5 (HRESP_EXPRAM_L),
+ .rdata_dec5 (HRDATA_EXPRAM_L),
// Control/Response for Output Stage MI6
.active_dec6 (i_active2to6),
- .readyout_dec6 (i_hready_mux__exp),
- .resp_dec6 (HRESP_EXP),
- .rdata_dec6 (HRDATA_EXP),
+ .readyout_dec6 (i_hready_mux__expram_h),
+ .resp_dec6 (HRESP_EXPRAM_H),
+ .rdata_dec6 (HRDATA_EXPRAM_H),
+
+ // Control/Response for Output Stage MI7
+ .active_dec7 (i_active2to7),
+ .readyout_dec7 (i_hready_mux__exp),
+ .resp_dec7 (HRESP_EXP),
+ .rdata_dec7 (HRDATA_EXP),
.sel_dec0 (i_sel2to0),
.sel_dec1 (i_sel2to1),
@@ -1317,6 +1407,7 @@ module nanosoc_busmatrix (
.sel_dec4 (i_sel2to4),
.sel_dec5 (i_sel2to5),
.sel_dec6 (i_sel2to6),
+ .sel_dec7 (i_sel2to7),
.active_dec (i_active2),
.HREADYOUTS (i_readyout2),
@@ -1334,7 +1425,7 @@ module nanosoc_busmatrix (
.HRESETn (HRESETn),
// Internal address remapping control
- .remapping_dec ( REMAP[0] ),
+ .remapping_dec ( { REMAP[1], REMAP[0] } ),
// Signals from Input stage SI3
.HREADYS (HREADY_CPU_0),
@@ -1350,45 +1441,51 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI1
.active_dec1 (i_active3to1),
- .readyout_dec1 (i_hready_mux__imem_0),
- .resp_dec1 (HRESP_IMEM_0),
- .rdata_dec1 (HRDATA_IMEM_0),
+ .readyout_dec1 (i_hready_mux__extrom_0),
+ .resp_dec1 (HRESP_EXTROM_0),
+ .rdata_dec1 (HRDATA_EXTROM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active3to2),
- .readyout_dec2 (i_hready_mux__dmem_0),
- .resp_dec2 (HRESP_DMEM_0),
- .rdata_dec2 (HRDATA_DMEM_0),
+ .readyout_dec2 (i_hready_mux__imem_0),
+ .resp_dec2 (HRESP_IMEM_0),
+ .rdata_dec2 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active3to3),
- .readyout_dec3 (i_hready_mux__sysio),
- .resp_dec3 (HRESP_SYSIO),
- .rdata_dec3 (HRDATA_SYSIO),
+ .readyout_dec3 (i_hready_mux__dmem_0),
+ .resp_dec3 (HRESP_DMEM_0),
+ .rdata_dec3 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI4
.active_dec4 (i_active3to4),
- .readyout_dec4 (i_hready_mux__expram_l),
- .resp_dec4 (HRESP_EXPRAM_L),
- .rdata_dec4 (HRDATA_EXPRAM_L),
+ .readyout_dec4 (i_hready_mux__sysio),
+ .resp_dec4 (HRESP_SYSIO),
+ .rdata_dec4 (HRDATA_SYSIO),
// Control/Response for Output Stage MI5
.active_dec5 (i_active3to5),
- .readyout_dec5 (i_hready_mux__expram_h),
- .resp_dec5 (HRESP_EXPRAM_H),
- .rdata_dec5 (HRDATA_EXPRAM_H),
+ .readyout_dec5 (i_hready_mux__expram_l),
+ .resp_dec5 (HRESP_EXPRAM_L),
+ .rdata_dec5 (HRDATA_EXPRAM_L),
// Control/Response for Output Stage MI6
.active_dec6 (i_active3to6),
- .readyout_dec6 (i_hready_mux__exp),
- .resp_dec6 (HRESP_EXP),
- .rdata_dec6 (HRDATA_EXP),
+ .readyout_dec6 (i_hready_mux__expram_h),
+ .resp_dec6 (HRESP_EXPRAM_H),
+ .rdata_dec6 (HRDATA_EXPRAM_H),
// Control/Response for Output Stage MI7
.active_dec7 (i_active3to7),
- .readyout_dec7 (i_hready_mux__systable),
- .resp_dec7 (HRESP_SYSTABLE),
- .rdata_dec7 (HRDATA_SYSTABLE),
+ .readyout_dec7 (i_hready_mux__exp),
+ .resp_dec7 (HRESP_EXP),
+ .rdata_dec7 (HRDATA_EXP),
+
+ // Control/Response for Output Stage MI8
+ .active_dec8 (i_active3to8),
+ .readyout_dec8 (i_hready_mux__systable),
+ .resp_dec8 (HRESP_SYSTABLE),
+ .rdata_dec8 (HRDATA_SYSTABLE),
.sel_dec0 (i_sel3to0),
.sel_dec1 (i_sel3to1),
@@ -1398,6 +1495,7 @@ module nanosoc_busmatrix (
.sel_dec5 (i_sel3to5),
.sel_dec6 (i_sel3to6),
.sel_dec7 (i_sel3to7),
+ .sel_dec8 (i_sel3to8),
.active_dec (i_active3),
.HREADYOUTS (i_readyout3),
@@ -1494,7 +1592,7 @@ module nanosoc_busmatrix (
// Output stage for MI1
- nanosoc_target_output_IMEM_0 u_nanosoc_target_output_imem_0_1 (
+ nanosoc_target_output_EXTROM_0 u_nanosoc_target_output_extrom_0_1 (
// Common AHB signals
.HCLK (HCLK),
@@ -1553,13 +1651,99 @@ module nanosoc_busmatrix (
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_IMEM_0),
+ .HREADYOUTM (HREADYOUT_EXTROM_0),
.active_op0 (i_active0to1),
.active_op1 (i_active1to1),
.active_op2 (i_active2to1),
.active_op3 (i_active3to1),
+ // Slave Address/Control Signals
+ .HSELM (HSEL_EXTROM_0),
+ .HADDRM (HADDR_EXTROM_0),
+ .HTRANSM (HTRANS_EXTROM_0),
+ .HWRITEM (HWRITE_EXTROM_0),
+ .HSIZEM (HSIZE_EXTROM_0),
+ .HBURSTM (HBURST_EXTROM_0),
+ .HPROTM (HPROT_EXTROM_0),
+ .HMASTERM (HMASTER_EXTROM_0),
+ .HMASTLOCKM (HMASTLOCK_EXTROM_0),
+ .HREADYMUXM (i_hready_mux__extrom_0),
+ .HWDATAM (HWDATA_EXTROM_0)
+
+ );
+
+ // Drive output with internal version
+ assign HREADYMUX_EXTROM_0 = i_hready_mux__extrom_0;
+
+
+ // Output stage for MI2
+ nanosoc_target_output_IMEM_0 u_nanosoc_target_output_imem_0_2 (
+
+ // Common AHB signals
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Port 0 Signals
+ .sel_op0 (i_sel0to2),
+ .addr_op0 (i_addr0),
+ .trans_op0 (i_trans0),
+ .write_op0 (i_write0),
+ .size_op0 (i_size0),
+ .burst_op0 (i_burst0),
+ .prot_op0 (i_prot0),
+ .master_op0 (i_master0),
+ .mastlock_op0 (i_mastlock0),
+ .wdata_op0 (HWDATA_DEBUG),
+ .held_tran_op0 (i_held_tran0),
+
+ // Port 1 Signals
+ .sel_op1 (i_sel1to2),
+ .addr_op1 (i_addr1),
+ .trans_op1 (i_trans1),
+ .write_op1 (i_write1),
+ .size_op1 (i_size1),
+ .burst_op1 (i_burst1),
+ .prot_op1 (i_prot1),
+ .master_op1 (i_master1),
+ .mastlock_op1 (i_mastlock1),
+ .wdata_op1 (HWDATA_DMAC_0),
+ .held_tran_op1 (i_held_tran1),
+
+ // Port 2 Signals
+ .sel_op2 (i_sel2to2),
+ .addr_op2 (i_addr2),
+ .trans_op2 (i_trans2),
+ .write_op2 (i_write2),
+ .size_op2 (i_size2),
+ .burst_op2 (i_burst2),
+ .prot_op2 (i_prot2),
+ .master_op2 (i_master2),
+ .mastlock_op2 (i_mastlock2),
+ .wdata_op2 (HWDATA_DMAC_1),
+ .held_tran_op2 (i_held_tran2),
+
+ // Port 3 Signals
+ .sel_op3 (i_sel3to2),
+ .addr_op3 (i_addr3),
+ .trans_op3 (i_trans3),
+ .write_op3 (i_write3),
+ .size_op3 (i_size3),
+ .burst_op3 (i_burst3),
+ .prot_op3 (i_prot3),
+ .master_op3 (i_master3),
+ .mastlock_op3 (i_mastlock3),
+ .wdata_op3 (HWDATA_CPU_0),
+ .held_tran_op3 (i_held_tran3),
+
+ // Slave read data and response
+ .HREADYOUTM (HREADYOUT_IMEM_0),
+
+ .active_op0 (i_active0to2),
+ .active_op1 (i_active1to2),
+ .active_op2 (i_active2to2),
+ .active_op3 (i_active3to2),
+
// Slave Address/Control Signals
.HSELM (HSEL_IMEM_0),
.HADDRM (HADDR_IMEM_0),
@@ -1579,15 +1763,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_IMEM_0 = i_hready_mux__imem_0;
- // Output stage for MI2
- nanosoc_target_output_DMEM_0 u_nanosoc_target_output_dmem_0_2 (
+ // Output stage for MI3
+ nanosoc_target_output_DMEM_0 u_nanosoc_target_output_dmem_0_3 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to2),
+ .sel_op0 (i_sel0to3),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -1600,7 +1784,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
- .sel_op1 (i_sel1to2),
+ .sel_op1 (i_sel1to3),
.addr_op1 (i_addr1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
@@ -1613,7 +1797,7 @@ module nanosoc_busmatrix (
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
- .sel_op2 (i_sel2to2),
+ .sel_op2 (i_sel2to3),
.addr_op2 (i_addr2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
@@ -1626,7 +1810,7 @@ module nanosoc_busmatrix (
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
- .sel_op3 (i_sel3to2),
+ .sel_op3 (i_sel3to3),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -1641,10 +1825,10 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_DMEM_0),
- .active_op0 (i_active0to2),
- .active_op1 (i_active1to2),
- .active_op2 (i_active2to2),
- .active_op3 (i_active3to2),
+ .active_op0 (i_active0to3),
+ .active_op1 (i_active1to3),
+ .active_op2 (i_active2to3),
+ .active_op3 (i_active3to3),
// Slave Address/Control Signals
.HSELM (HSEL_DMEM_0),
@@ -1665,15 +1849,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_DMEM_0 = i_hready_mux__dmem_0;
- // Output stage for MI3
- nanosoc_target_output_SYSIO u_nanosoc_target_output_sysio_3 (
+ // Output stage for MI4
+ nanosoc_target_output_SYSIO u_nanosoc_target_output_sysio_4 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to3),
+ .sel_op0 (i_sel0to4),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -1686,7 +1870,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
- .sel_op1 (i_sel1to3),
+ .sel_op1 (i_sel1to4),
.addr_op1 (i_addr1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
@@ -1699,7 +1883,7 @@ module nanosoc_busmatrix (
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
- .sel_op2 (i_sel2to3),
+ .sel_op2 (i_sel2to4),
.addr_op2 (i_addr2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
@@ -1712,7 +1896,7 @@ module nanosoc_busmatrix (
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
- .sel_op3 (i_sel3to3),
+ .sel_op3 (i_sel3to4),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -1727,10 +1911,10 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_SYSIO),
- .active_op0 (i_active0to3),
- .active_op1 (i_active1to3),
- .active_op2 (i_active2to3),
- .active_op3 (i_active3to3),
+ .active_op0 (i_active0to4),
+ .active_op1 (i_active1to4),
+ .active_op2 (i_active2to4),
+ .active_op3 (i_active3to4),
// Slave Address/Control Signals
.HSELM (HSEL_SYSIO),
@@ -1751,15 +1935,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_SYSIO = i_hready_mux__sysio;
- // Output stage for MI4
- nanosoc_target_output_EXPRAM_L u_nanosoc_target_output_expram_l_4 (
+ // Output stage for MI5
+ nanosoc_target_output_EXPRAM_L u_nanosoc_target_output_expram_l_5 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to4),
+ .sel_op0 (i_sel0to5),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -1772,7 +1956,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
- .sel_op1 (i_sel1to4),
+ .sel_op1 (i_sel1to5),
.addr_op1 (i_addr1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
@@ -1785,7 +1969,7 @@ module nanosoc_busmatrix (
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
- .sel_op2 (i_sel2to4),
+ .sel_op2 (i_sel2to5),
.addr_op2 (i_addr2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
@@ -1798,7 +1982,7 @@ module nanosoc_busmatrix (
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
- .sel_op3 (i_sel3to4),
+ .sel_op3 (i_sel3to5),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -1813,10 +1997,10 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXPRAM_L),
- .active_op0 (i_active0to4),
- .active_op1 (i_active1to4),
- .active_op2 (i_active2to4),
- .active_op3 (i_active3to4),
+ .active_op0 (i_active0to5),
+ .active_op1 (i_active1to5),
+ .active_op2 (i_active2to5),
+ .active_op3 (i_active3to5),
// Slave Address/Control Signals
.HSELM (HSEL_EXPRAM_L),
@@ -1837,15 +2021,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_EXPRAM_L = i_hready_mux__expram_l;
- // Output stage for MI5
- nanosoc_target_output_EXPRAM_H u_nanosoc_target_output_expram_h_5 (
+ // Output stage for MI6
+ nanosoc_target_output_EXPRAM_H u_nanosoc_target_output_expram_h_6 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to5),
+ .sel_op0 (i_sel0to6),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -1858,7 +2042,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
- .sel_op1 (i_sel1to5),
+ .sel_op1 (i_sel1to6),
.addr_op1 (i_addr1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
@@ -1871,7 +2055,7 @@ module nanosoc_busmatrix (
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
- .sel_op2 (i_sel2to5),
+ .sel_op2 (i_sel2to6),
.addr_op2 (i_addr2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
@@ -1884,7 +2068,7 @@ module nanosoc_busmatrix (
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
- .sel_op3 (i_sel3to5),
+ .sel_op3 (i_sel3to6),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -1899,10 +2083,10 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXPRAM_H),
- .active_op0 (i_active0to5),
- .active_op1 (i_active1to5),
- .active_op2 (i_active2to5),
- .active_op3 (i_active3to5),
+ .active_op0 (i_active0to6),
+ .active_op1 (i_active1to6),
+ .active_op2 (i_active2to6),
+ .active_op3 (i_active3to6),
// Slave Address/Control Signals
.HSELM (HSEL_EXPRAM_H),
@@ -1923,15 +2107,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_EXPRAM_H = i_hready_mux__expram_h;
- // Output stage for MI6
- nanosoc_target_output_EXP u_nanosoc_target_output_exp_6 (
+ // Output stage for MI7
+ nanosoc_target_output_EXP u_nanosoc_target_output_exp_7 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to6),
+ .sel_op0 (i_sel0to7),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -1944,7 +2128,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 1 Signals
- .sel_op1 (i_sel1to6),
+ .sel_op1 (i_sel1to7),
.addr_op1 (i_addr1),
.trans_op1 (i_trans1),
.write_op1 (i_write1),
@@ -1957,7 +2141,7 @@ module nanosoc_busmatrix (
.held_tran_op1 (i_held_tran1),
// Port 2 Signals
- .sel_op2 (i_sel2to6),
+ .sel_op2 (i_sel2to7),
.addr_op2 (i_addr2),
.trans_op2 (i_trans2),
.write_op2 (i_write2),
@@ -1970,7 +2154,7 @@ module nanosoc_busmatrix (
.held_tran_op2 (i_held_tran2),
// Port 3 Signals
- .sel_op3 (i_sel3to6),
+ .sel_op3 (i_sel3to7),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -1985,10 +2169,10 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_EXP),
- .active_op0 (i_active0to6),
- .active_op1 (i_active1to6),
- .active_op2 (i_active2to6),
- .active_op3 (i_active3to6),
+ .active_op0 (i_active0to7),
+ .active_op1 (i_active1to7),
+ .active_op2 (i_active2to7),
+ .active_op3 (i_active3to7),
// Slave Address/Control Signals
.HSELM (HSEL_EXP),
@@ -2009,15 +2193,15 @@ module nanosoc_busmatrix (
assign HREADYMUX_EXP = i_hready_mux__exp;
- // Output stage for MI7
- nanosoc_target_output_SYSTABLE u_nanosoc_target_output_systable_7 (
+ // Output stage for MI8
+ nanosoc_target_output_SYSTABLE u_nanosoc_target_output_systable_8 (
// Common AHB signals
.HCLK (HCLK),
.HRESETn (HRESETn),
// Port 0 Signals
- .sel_op0 (i_sel0to7),
+ .sel_op0 (i_sel0to8),
.addr_op0 (i_addr0),
.trans_op0 (i_trans0),
.write_op0 (i_write0),
@@ -2030,7 +2214,7 @@ module nanosoc_busmatrix (
.held_tran_op0 (i_held_tran0),
// Port 3 Signals
- .sel_op3 (i_sel3to7),
+ .sel_op3 (i_sel3to8),
.addr_op3 (i_addr3),
.trans_op3 (i_trans3),
.write_op3 (i_write3),
@@ -2045,8 +2229,8 @@ module nanosoc_busmatrix (
// Slave read data and response
.HREADYOUTM (HREADYOUT_SYSTABLE),
- .active_op0 (i_active0to7),
- .active_op3 (i_active3to7),
+ .active_op0 (i_active0to8),
+ .active_op3 (i_active3to8),
// Slave Address/Control Signals
.HSELM (HSEL_SYSTABLE),
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
index f96bab0acd2ced0fbee9377e9549d669cf8d0f11..46af198dea1198977b03b61046fca81b2cb79192 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
index f10532b57d41779da310eb8beb08f555895c44fa..c317d484f3c5bd5372211927764203f1a01e798d 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -85,36 +85,41 @@ module nanosoc_busmatrix_lite (
HRESP_BOOTROM_0,
// Output port MI1 (inputs from slave 1)
+ HRDATA_EXTROM_0,
+ HREADYOUT_EXTROM_0,
+ HRESP_EXTROM_0,
+
+ // Output port MI2 (inputs from slave 2)
HRDATA_IMEM_0,
HREADYOUT_IMEM_0,
HRESP_IMEM_0,
- // Output port MI2 (inputs from slave 2)
+ // Output port MI3 (inputs from slave 3)
HRDATA_DMEM_0,
HREADYOUT_DMEM_0,
HRESP_DMEM_0,
- // Output port MI3 (inputs from slave 3)
+ // Output port MI4 (inputs from slave 4)
HRDATA_SYSIO,
HREADYOUT_SYSIO,
HRESP_SYSIO,
- // Output port MI4 (inputs from slave 4)
+ // Output port MI5 (inputs from slave 5)
HRDATA_EXPRAM_L,
HREADYOUT_EXPRAM_L,
HRESP_EXPRAM_L,
- // Output port MI5 (inputs from slave 5)
+ // Output port MI6 (inputs from slave 6)
HRDATA_EXPRAM_H,
HREADYOUT_EXPRAM_H,
HRESP_EXPRAM_H,
- // Output port MI6 (inputs from slave 6)
+ // Output port MI7 (inputs from slave 7)
HRDATA_EXP,
HREADYOUT_EXP,
HRESP_EXP,
- // Output port MI7 (inputs from slave 7)
+ // Output port MI8 (inputs from slave 8)
HRDATA_SYSTABLE,
HREADYOUT_SYSTABLE,
HRESP_SYSTABLE,
@@ -137,6 +142,18 @@ module nanosoc_busmatrix_lite (
HREADYMUX_BOOTROM_0,
// Output port MI1 (outputs to slave 1)
+ HSEL_EXTROM_0,
+ HADDR_EXTROM_0,
+ HTRANS_EXTROM_0,
+ HWRITE_EXTROM_0,
+ HSIZE_EXTROM_0,
+ HBURST_EXTROM_0,
+ HPROT_EXTROM_0,
+ HWDATA_EXTROM_0,
+ HMASTLOCK_EXTROM_0,
+ HREADYMUX_EXTROM_0,
+
+ // Output port MI2 (outputs to slave 2)
HSEL_IMEM_0,
HADDR_IMEM_0,
HTRANS_IMEM_0,
@@ -148,7 +165,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_IMEM_0,
HREADYMUX_IMEM_0,
- // Output port MI2 (outputs to slave 2)
+ // Output port MI3 (outputs to slave 3)
HSEL_DMEM_0,
HADDR_DMEM_0,
HTRANS_DMEM_0,
@@ -160,7 +177,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_DMEM_0,
HREADYMUX_DMEM_0,
- // Output port MI3 (outputs to slave 3)
+ // Output port MI4 (outputs to slave 4)
HSEL_SYSIO,
HADDR_SYSIO,
HTRANS_SYSIO,
@@ -172,7 +189,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_SYSIO,
HREADYMUX_SYSIO,
- // Output port MI4 (outputs to slave 4)
+ // Output port MI5 (outputs to slave 5)
HSEL_EXPRAM_L,
HADDR_EXPRAM_L,
HTRANS_EXPRAM_L,
@@ -184,7 +201,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_EXPRAM_L,
HREADYMUX_EXPRAM_L,
- // Output port MI5 (outputs to slave 5)
+ // Output port MI6 (outputs to slave 6)
HSEL_EXPRAM_H,
HADDR_EXPRAM_H,
HTRANS_EXPRAM_H,
@@ -196,7 +213,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_EXPRAM_H,
HREADYMUX_EXPRAM_H,
- // Output port MI6 (outputs to slave 6)
+ // Output port MI7 (outputs to slave 7)
HSEL_EXP,
HADDR_EXP,
HTRANS_EXP,
@@ -208,7 +225,7 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_EXP,
HREADYMUX_EXP,
- // Output port MI7 (outputs to slave 7)
+ // Output port MI8 (outputs to slave 8)
HSEL_SYSTABLE,
HADDR_SYSTABLE,
HTRANS_SYSTABLE,
@@ -302,36 +319,41 @@ module nanosoc_busmatrix_lite (
input HRESP_BOOTROM_0; // Transfer response
// Output port MI1 (inputs from slave 1)
+ input [31:0] HRDATA_EXTROM_0; // Read data bus
+ input HREADYOUT_EXTROM_0; // HREADY feedback
+ input HRESP_EXTROM_0; // Transfer response
+
+ // Output port MI2 (inputs from slave 2)
input [31:0] HRDATA_IMEM_0; // Read data bus
input HREADYOUT_IMEM_0; // HREADY feedback
input HRESP_IMEM_0; // Transfer response
- // Output port MI2 (inputs from slave 2)
+ // Output port MI3 (inputs from slave 3)
input [31:0] HRDATA_DMEM_0; // Read data bus
input HREADYOUT_DMEM_0; // HREADY feedback
input HRESP_DMEM_0; // Transfer response
- // Output port MI3 (inputs from slave 3)
+ // Output port MI4 (inputs from slave 4)
input [31:0] HRDATA_SYSIO; // Read data bus
input HREADYOUT_SYSIO; // HREADY feedback
input HRESP_SYSIO; // Transfer response
- // Output port MI4 (inputs from slave 4)
+ // Output port MI5 (inputs from slave 5)
input [31:0] HRDATA_EXPRAM_L; // Read data bus
input HREADYOUT_EXPRAM_L; // HREADY feedback
input HRESP_EXPRAM_L; // Transfer response
- // Output port MI5 (inputs from slave 5)
+ // Output port MI6 (inputs from slave 6)
input [31:0] HRDATA_EXPRAM_H; // Read data bus
input HREADYOUT_EXPRAM_H; // HREADY feedback
input HRESP_EXPRAM_H; // Transfer response
- // Output port MI6 (inputs from slave 6)
+ // Output port MI7 (inputs from slave 7)
input [31:0] HRDATA_EXP; // Read data bus
input HREADYOUT_EXP; // HREADY feedback
input HRESP_EXP; // Transfer response
- // Output port MI7 (inputs from slave 7)
+ // Output port MI8 (inputs from slave 8)
input [31:0] HRDATA_SYSTABLE; // Read data bus
input HREADYOUT_SYSTABLE; // HREADY feedback
input HRESP_SYSTABLE; // Transfer response
@@ -354,6 +376,18 @@ module nanosoc_busmatrix_lite (
output HREADYMUX_BOOTROM_0; // Transfer done
// Output port MI1 (outputs to slave 1)
+ output HSEL_EXTROM_0; // Slave Select
+ output [31:0] HADDR_EXTROM_0; // Address bus
+ output [1:0] HTRANS_EXTROM_0; // Transfer type
+ output HWRITE_EXTROM_0; // Transfer direction
+ output [2:0] HSIZE_EXTROM_0; // Transfer size
+ output [2:0] HBURST_EXTROM_0; // Burst type
+ output [3:0] HPROT_EXTROM_0; // Protection control
+ output [31:0] HWDATA_EXTROM_0; // Write data
+ output HMASTLOCK_EXTROM_0; // Locked Sequence
+ output HREADYMUX_EXTROM_0; // Transfer done
+
+ // Output port MI2 (outputs to slave 2)
output HSEL_IMEM_0; // Slave Select
output [31:0] HADDR_IMEM_0; // Address bus
output [1:0] HTRANS_IMEM_0; // Transfer type
@@ -365,7 +399,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_IMEM_0; // Locked Sequence
output HREADYMUX_IMEM_0; // Transfer done
- // Output port MI2 (outputs to slave 2)
+ // Output port MI3 (outputs to slave 3)
output HSEL_DMEM_0; // Slave Select
output [31:0] HADDR_DMEM_0; // Address bus
output [1:0] HTRANS_DMEM_0; // Transfer type
@@ -377,7 +411,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_DMEM_0; // Locked Sequence
output HREADYMUX_DMEM_0; // Transfer done
- // Output port MI3 (outputs to slave 3)
+ // Output port MI4 (outputs to slave 4)
output HSEL_SYSIO; // Slave Select
output [31:0] HADDR_SYSIO; // Address bus
output [1:0] HTRANS_SYSIO; // Transfer type
@@ -389,7 +423,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_SYSIO; // Locked Sequence
output HREADYMUX_SYSIO; // Transfer done
- // Output port MI4 (outputs to slave 4)
+ // Output port MI5 (outputs to slave 5)
output HSEL_EXPRAM_L; // Slave Select
output [31:0] HADDR_EXPRAM_L; // Address bus
output [1:0] HTRANS_EXPRAM_L; // Transfer type
@@ -401,7 +435,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_EXPRAM_L; // Locked Sequence
output HREADYMUX_EXPRAM_L; // Transfer done
- // Output port MI5 (outputs to slave 5)
+ // Output port MI6 (outputs to slave 6)
output HSEL_EXPRAM_H; // Slave Select
output [31:0] HADDR_EXPRAM_H; // Address bus
output [1:0] HTRANS_EXPRAM_H; // Transfer type
@@ -413,7 +447,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_EXPRAM_H; // Locked Sequence
output HREADYMUX_EXPRAM_H; // Transfer done
- // Output port MI6 (outputs to slave 6)
+ // Output port MI7 (outputs to slave 7)
output HSEL_EXP; // Slave Select
output [31:0] HADDR_EXP; // Address bus
output [1:0] HTRANS_EXP; // Transfer type
@@ -425,7 +459,7 @@ module nanosoc_busmatrix_lite (
output HMASTLOCK_EXP; // Locked Sequence
output HREADYMUX_EXP; // Transfer done
- // Output port MI7 (outputs to slave 7)
+ // Output port MI8 (outputs to slave 8)
output HSEL_SYSTABLE; // Slave Select
output [31:0] HADDR_SYSTABLE; // Address bus
output [1:0] HTRANS_SYSTABLE; // Transfer type
@@ -544,6 +578,22 @@ module nanosoc_busmatrix_lite (
wire HRESP_BOOTROM_0; // Transfer response
// Output Port MI1
+ wire HSEL_EXTROM_0; // Slave Select
+ wire [31:0] HADDR_EXTROM_0; // Address bus
+ wire [1:0] HTRANS_EXTROM_0; // Transfer type
+ wire HWRITE_EXTROM_0; // Transfer direction
+ wire [2:0] HSIZE_EXTROM_0; // Transfer size
+ wire [2:0] HBURST_EXTROM_0; // Burst type
+ wire [3:0] HPROT_EXTROM_0; // Protection control
+ wire [31:0] HWDATA_EXTROM_0; // Write data
+ wire HMASTLOCK_EXTROM_0; // Locked Sequence
+ wire HREADYMUX_EXTROM_0; // Transfer done
+
+ wire [31:0] HRDATA_EXTROM_0; // Read data bus
+ wire HREADYOUT_EXTROM_0; // HREADY feedback
+ wire HRESP_EXTROM_0; // Transfer response
+
+ // Output Port MI2
wire HSEL_IMEM_0; // Slave Select
wire [31:0] HADDR_IMEM_0; // Address bus
wire [1:0] HTRANS_IMEM_0; // Transfer type
@@ -559,7 +609,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_IMEM_0; // HREADY feedback
wire HRESP_IMEM_0; // Transfer response
- // Output Port MI2
+ // Output Port MI3
wire HSEL_DMEM_0; // Slave Select
wire [31:0] HADDR_DMEM_0; // Address bus
wire [1:0] HTRANS_DMEM_0; // Transfer type
@@ -575,7 +625,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_DMEM_0; // HREADY feedback
wire HRESP_DMEM_0; // Transfer response
- // Output Port MI3
+ // Output Port MI4
wire HSEL_SYSIO; // Slave Select
wire [31:0] HADDR_SYSIO; // Address bus
wire [1:0] HTRANS_SYSIO; // Transfer type
@@ -591,7 +641,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_SYSIO; // HREADY feedback
wire HRESP_SYSIO; // Transfer response
- // Output Port MI4
+ // Output Port MI5
wire HSEL_EXPRAM_L; // Slave Select
wire [31:0] HADDR_EXPRAM_L; // Address bus
wire [1:0] HTRANS_EXPRAM_L; // Transfer type
@@ -607,7 +657,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_EXPRAM_L; // HREADY feedback
wire HRESP_EXPRAM_L; // Transfer response
- // Output Port MI5
+ // Output Port MI6
wire HSEL_EXPRAM_H; // Slave Select
wire [31:0] HADDR_EXPRAM_H; // Address bus
wire [1:0] HTRANS_EXPRAM_H; // Transfer type
@@ -623,7 +673,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_EXPRAM_H; // HREADY feedback
wire HRESP_EXPRAM_H; // Transfer response
- // Output Port MI6
+ // Output Port MI7
wire HSEL_EXP; // Slave Select
wire [31:0] HADDR_EXP; // Address bus
wire [1:0] HTRANS_EXP; // Transfer type
@@ -639,7 +689,7 @@ module nanosoc_busmatrix_lite (
wire HREADYOUT_EXP; // HREADY feedback
wire HRESP_EXP; // Transfer response
- // Output Port MI7
+ // Output Port MI8
wire HSEL_SYSTABLE; // Slave Select
wire [31:0] HADDR_SYSTABLE; // Address bus
wire [1:0] HTRANS_SYSTABLE; // Transfer type
@@ -669,6 +719,8 @@ module nanosoc_busmatrix_lite (
wire [3:0] i_hmaster_BOOTROM_0;
wire [1:0] i_hresp_BOOTROM_0;
+ wire [3:0] i_hmaster_EXTROM_0;
+ wire [1:0] i_hresp_EXTROM_0;
wire [3:0] i_hmaster_IMEM_0;
wire [1:0] i_hresp_IMEM_0;
wire [3:0] i_hmaster_DMEM_0;
@@ -702,6 +754,7 @@ module nanosoc_busmatrix_lite (
assign HRESP_CPU_0 = i_hresp_CPU_0[0];
assign i_hresp_BOOTROM_0 = {{1{tie_low}}, HRESP_BOOTROM_0};
+ assign i_hresp_EXTROM_0 = {{1{tie_low}}, HRESP_EXTROM_0};
assign i_hresp_IMEM_0 = {{1{tie_low}}, HRESP_IMEM_0};
assign i_hresp_DMEM_0 = {{1{tie_low}}, HRESP_DMEM_0};
assign i_hresp_SYSIO = {{1{tie_low}}, HRESP_SYSIO};
@@ -798,6 +851,22 @@ module nanosoc_busmatrix_lite (
.HRESP_BOOTROM_0 (i_hresp_BOOTROM_0),
// Output port MI1 signals
+ .HSEL_EXTROM_0 (HSEL_EXTROM_0),
+ .HADDR_EXTROM_0 (HADDR_EXTROM_0),
+ .HTRANS_EXTROM_0 (HTRANS_EXTROM_0),
+ .HWRITE_EXTROM_0 (HWRITE_EXTROM_0),
+ .HSIZE_EXTROM_0 (HSIZE_EXTROM_0),
+ .HBURST_EXTROM_0 (HBURST_EXTROM_0),
+ .HPROT_EXTROM_0 (HPROT_EXTROM_0),
+ .HWDATA_EXTROM_0 (HWDATA_EXTROM_0),
+ .HMASTER_EXTROM_0 (i_hmaster_EXTROM_0),
+ .HMASTLOCK_EXTROM_0 (HMASTLOCK_EXTROM_0),
+ .HREADYMUX_EXTROM_0 (HREADYMUX_EXTROM_0),
+ .HRDATA_EXTROM_0 (HRDATA_EXTROM_0),
+ .HREADYOUT_EXTROM_0 (HREADYOUT_EXTROM_0),
+ .HRESP_EXTROM_0 (i_hresp_EXTROM_0),
+
+ // Output port MI2 signals
.HSEL_IMEM_0 (HSEL_IMEM_0),
.HADDR_IMEM_0 (HADDR_IMEM_0),
.HTRANS_IMEM_0 (HTRANS_IMEM_0),
@@ -813,7 +882,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_IMEM_0 (HREADYOUT_IMEM_0),
.HRESP_IMEM_0 (i_hresp_IMEM_0),
- // Output port MI2 signals
+ // Output port MI3 signals
.HSEL_DMEM_0 (HSEL_DMEM_0),
.HADDR_DMEM_0 (HADDR_DMEM_0),
.HTRANS_DMEM_0 (HTRANS_DMEM_0),
@@ -829,7 +898,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_DMEM_0 (HREADYOUT_DMEM_0),
.HRESP_DMEM_0 (i_hresp_DMEM_0),
- // Output port MI3 signals
+ // Output port MI4 signals
.HSEL_SYSIO (HSEL_SYSIO),
.HADDR_SYSIO (HADDR_SYSIO),
.HTRANS_SYSIO (HTRANS_SYSIO),
@@ -845,7 +914,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_SYSIO (HREADYOUT_SYSIO),
.HRESP_SYSIO (i_hresp_SYSIO),
- // Output port MI4 signals
+ // Output port MI5 signals
.HSEL_EXPRAM_L (HSEL_EXPRAM_L),
.HADDR_EXPRAM_L (HADDR_EXPRAM_L),
.HTRANS_EXPRAM_L (HTRANS_EXPRAM_L),
@@ -861,7 +930,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_EXPRAM_L (HREADYOUT_EXPRAM_L),
.HRESP_EXPRAM_L (i_hresp_EXPRAM_L),
- // Output port MI5 signals
+ // Output port MI6 signals
.HSEL_EXPRAM_H (HSEL_EXPRAM_H),
.HADDR_EXPRAM_H (HADDR_EXPRAM_H),
.HTRANS_EXPRAM_H (HTRANS_EXPRAM_H),
@@ -877,7 +946,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_EXPRAM_H (HREADYOUT_EXPRAM_H),
.HRESP_EXPRAM_H (i_hresp_EXPRAM_H),
- // Output port MI6 signals
+ // Output port MI7 signals
.HSEL_EXP (HSEL_EXP),
.HADDR_EXP (HADDR_EXP),
.HTRANS_EXP (HTRANS_EXP),
@@ -893,7 +962,7 @@ module nanosoc_busmatrix_lite (
.HREADYOUT_EXP (HREADYOUT_EXP),
.HRESP_EXP (i_hresp_EXP),
- // Output port MI7 signals
+ // Output port MI8 signals
.HSEL_SYSTABLE (HSEL_SYSTABLE),
.HADDR_SYSTABLE (HADDR_SYSTABLE),
.HTRANS_SYSTABLE (HTRANS_SYSTABLE),
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
index d770544cbae49d558bc2dc307f80a4a09ec16aa3..1407bda4967dc2464901e371ae1046a0c9d88de8 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
index 56ac92a2eb48f34a05e53fa1b48c3de459426ef7..9d6224826cf31ac922d3a2545afbaa1077785841 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -96,6 +96,12 @@ module nanosoc_matrix_decode_CPU_0 (
resp_dec7,
rdata_dec7,
+ // Bus-switch output 8
+ active_dec8,
+ readyout_dec8,
+ resp_dec8,
+ rdata_dec8,
+
// Output port selection signals
sel_dec0,
sel_dec1,
@@ -105,6 +111,7 @@ module nanosoc_matrix_decode_CPU_0 (
sel_dec5,
sel_dec6,
sel_dec7,
+ sel_dec8,
// Selected Output port data and control signals
active_dec,
@@ -124,7 +131,7 @@ module nanosoc_matrix_decode_CPU_0 (
input HRESETn; // AHB System Reset
// Internal address remapping control
- input [0:0] remapping_dec; // Internal remap signal
+ input [1:0] remapping_dec; // Internal remap signal
// Signals from the Input stage
input HREADYS; // Transfer done
@@ -180,6 +187,12 @@ module nanosoc_matrix_decode_CPU_0 (
input [1:0] resp_dec7; // HRESP input
input [31:0] rdata_dec7; // HRDATA input
+ // Bus-switch output MI8
+ input active_dec8; // Output stage MI8 active_dec signal
+ input readyout_dec8; // HREADYOUT input
+ input [1:0] resp_dec8; // HRESP input
+ input [31:0] rdata_dec8; // HRDATA input
+
// Output port selection signals
output sel_dec0; // HSEL output
output sel_dec1; // HSEL output
@@ -189,6 +202,7 @@ module nanosoc_matrix_decode_CPU_0 (
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
output sel_dec7; // HSEL output
+ output sel_dec8; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
@@ -205,7 +219,7 @@ module nanosoc_matrix_decode_CPU_0 (
wire HCLK; // AHB System Clock
wire HRESETn; // AHB System Reset
// Internal address remapping control
- wire [0:0] remapping_dec; // Internal remap signal
+ wire [1:0] remapping_dec; // Internal remap signal
// Signals from the Input stage
wire HREADYS; // Transfer done
@@ -269,6 +283,13 @@ module nanosoc_matrix_decode_CPU_0 (
wire [31:0] rdata_dec7; // HRDATA input
reg sel_dec7; // HSEL output
+ // Bus-switch output MI8
+ wire active_dec8; // active_dec signal
+ wire readyout_dec8; // HREADYOUT input
+ wire [1:0] resp_dec8; // HRESP input
+ wire [31:0] rdata_dec8; // HRDATA input
+ reg sel_dec8; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -280,8 +301,8 @@ module nanosoc_matrix_decode_CPU_0 (
reg [1:0] HRESPS; // Combinatorial HRESPS signal
reg [31:0] HRDATAS; // Read data bus
- reg [3:0] addr_out_port; // Address output ports
- reg [3:0] data_out_port; // Data output ports
+ reg [4:0] addr_out_port; // Address output ports
+ reg [4:0] data_out_port; // Data output ports
// Default slave signals
reg sel_dft_slv; // HSEL signal
@@ -334,98 +355,212 @@ module nanosoc_matrix_decode_CPU_0 (
if (trans_dec != 2'b00)
begin
- case (remapping_dec) // Composition: REMAP[0]
- 1'b0 : begin
+ case (remapping_dec) // Composition: { REMAP[1], REMAP[0] }
+ 2'b00 : begin
+ // Static address region 0x00000000-0x0fffffff
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 5'b00011; // Select Output port MI3
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 5'b00100; // Select Output port MI4
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 5'b00101; // Select Output port MI5
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 5'b00110; // Select Output port MI6
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 5'b01000; // Select Output port MI8
+
+ else
+ addr_out_port = 5'b10000; // Select the default slave
+ end
+
+ 2'b01 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
// Static address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 5'b00011; // Select Output port MI3
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 5'b00100; // Select Output port MI4
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 5'b00101; // Select Output port MI5
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 5'b00110; // Select Output port MI6
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 5'b01000; // Select Output port MI8
+
+ else
+ addr_out_port = 5'b10000; // Select the default slave
+ end
+
+ 2'b10 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[1]
if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
- // Static address region 0x10000000-0x1fffffff
- else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Static address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Static address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Static address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xf0000000-0xf003ffff
else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0111; // Select Output port MI7
+ addr_out_port = 5'b01000; // Select Output port MI8
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end
- 1'b1 : begin
+ 2'b11 : begin
// Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[1]
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x00000000-0x0fffffff
else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
- // Static address region 0x10000000-0x1fffffff
- else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Static address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Static address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Static address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xf0000000-0xf003ffff
else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0111; // Select Output port MI7
+ addr_out_port = 5'b01000; // Select Output port MI8
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end
- default : addr_out_port = {4{1'bx}};
+ default : addr_out_port = {5{1'bx}};
endcase
end // if (trans_dec != 2'b00)
@@ -445,19 +580,21 @@ module nanosoc_matrix_decode_CPU_0 (
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
sel_dec7 = 1'b0;
+ sel_dec8 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
case (addr_out_port)
- 4'b0000 : sel_dec0 = 1'b1;
- 4'b0001 : sel_dec1 = 1'b1;
- 4'b0010 : sel_dec2 = 1'b1;
- 4'b0011 : sel_dec3 = 1'b1;
- 4'b0100 : sel_dec4 = 1'b1;
- 4'b0101 : sel_dec5 = 1'b1;
- 4'b0110 : sel_dec6 = 1'b1;
- 4'b0111 : sel_dec7 = 1'b1;
- 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ 5'b00000 : sel_dec0 = 1'b1;
+ 5'b00001 : sel_dec1 = 1'b1;
+ 5'b00010 : sel_dec2 = 1'b1;
+ 5'b00011 : sel_dec3 = 1'b1;
+ 5'b00100 : sel_dec4 = 1'b1;
+ 5'b00101 : sel_dec5 = 1'b1;
+ 5'b00110 : sel_dec6 = 1'b1;
+ 5'b00111 : sel_dec7 = 1'b1;
+ 5'b01000 : sel_dec8 = 1'b1;
+ 5'b10000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
sel_dec1 = 1'bx;
@@ -467,6 +604,7 @@ module nanosoc_matrix_decode_CPU_0 (
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
sel_dec7 = 1'bx;
+ sel_dec8 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -483,19 +621,21 @@ module nanosoc_matrix_decode_CPU_0 (
active_dec5 or
active_dec6 or
active_dec7 or
+ active_dec8 or
addr_out_port
)
begin : p_active_comb
case (addr_out_port)
- 4'b0000 : active_dec = active_dec0;
- 4'b0001 : active_dec = active_dec1;
- 4'b0010 : active_dec = active_dec2;
- 4'b0011 : active_dec = active_dec3;
- 4'b0100 : active_dec = active_dec4;
- 4'b0101 : active_dec = active_dec5;
- 4'b0110 : active_dec = active_dec6;
- 4'b0111 : active_dec = active_dec7;
- 4'b1000 : active_dec = 1'b1; // Select the default slave
+ 5'b00000 : active_dec = active_dec0;
+ 5'b00001 : active_dec = active_dec1;
+ 5'b00010 : active_dec = active_dec2;
+ 5'b00011 : active_dec = active_dec3;
+ 5'b00100 : active_dec = active_dec4;
+ 5'b00101 : active_dec = active_dec5;
+ 5'b00110 : active_dec = active_dec6;
+ 5'b00111 : active_dec = active_dec7;
+ 5'b01000 : active_dec = active_dec8;
+ 5'b10000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
end // block: p_active_comb
@@ -515,13 +655,13 @@ module nanosoc_matrix_decode_CPU_0 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_out_port_seq
if (~HRESETn)
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
else
if (HREADYS)
if (sel_dec & trans_dec[1])
data_out_port <= addr_out_port;
else
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
end // block: p_data_out_port_seq
// HREADYOUTS output decode
@@ -535,19 +675,21 @@ module nanosoc_matrix_decode_CPU_0 (
readyout_dec5 or
readyout_dec6 or
readyout_dec7 or
+ readyout_dec8 or
data_out_port
)
begin : p_ready_comb
case (data_out_port)
- 4'b0000 : HREADYOUTS = readyout_dec0;
- 4'b0001 : HREADYOUTS = readyout_dec1;
- 4'b0010 : HREADYOUTS = readyout_dec2;
- 4'b0011 : HREADYOUTS = readyout_dec3;
- 4'b0100 : HREADYOUTS = readyout_dec4;
- 4'b0101 : HREADYOUTS = readyout_dec5;
- 4'b0110 : HREADYOUTS = readyout_dec6;
- 4'b0111 : HREADYOUTS = readyout_dec7;
- 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ 5'b00000 : HREADYOUTS = readyout_dec0;
+ 5'b00001 : HREADYOUTS = readyout_dec1;
+ 5'b00010 : HREADYOUTS = readyout_dec2;
+ 5'b00011 : HREADYOUTS = readyout_dec3;
+ 5'b00100 : HREADYOUTS = readyout_dec4;
+ 5'b00101 : HREADYOUTS = readyout_dec5;
+ 5'b00110 : HREADYOUTS = readyout_dec6;
+ 5'b00111 : HREADYOUTS = readyout_dec7;
+ 5'b01000 : HREADYOUTS = readyout_dec8;
+ 5'b10000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
end // block: p_ready_comb
@@ -563,19 +705,21 @@ module nanosoc_matrix_decode_CPU_0 (
resp_dec5 or
resp_dec6 or
resp_dec7 or
+ resp_dec8 or
data_out_port
)
begin : p_resp_comb
case (data_out_port)
- 4'b0000 : HRESPS = resp_dec0;
- 4'b0001 : HRESPS = resp_dec1;
- 4'b0010 : HRESPS = resp_dec2;
- 4'b0011 : HRESPS = resp_dec3;
- 4'b0100 : HRESPS = resp_dec4;
- 4'b0101 : HRESPS = resp_dec5;
- 4'b0110 : HRESPS = resp_dec6;
- 4'b0111 : HRESPS = resp_dec7;
- 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ 5'b00000 : HRESPS = resp_dec0;
+ 5'b00001 : HRESPS = resp_dec1;
+ 5'b00010 : HRESPS = resp_dec2;
+ 5'b00011 : HRESPS = resp_dec3;
+ 5'b00100 : HRESPS = resp_dec4;
+ 5'b00101 : HRESPS = resp_dec5;
+ 5'b00110 : HRESPS = resp_dec6;
+ 5'b00111 : HRESPS = resp_dec7;
+ 5'b01000 : HRESPS = resp_dec8;
+ 5'b10000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
end // block: p_resp_comb
@@ -590,19 +734,21 @@ module nanosoc_matrix_decode_CPU_0 (
rdata_dec5 or
rdata_dec6 or
rdata_dec7 or
+ rdata_dec8 or
data_out_port
)
begin : p_rdata_comb
case (data_out_port)
- 4'b0000 : HRDATAS = rdata_dec0;
- 4'b0001 : HRDATAS = rdata_dec1;
- 4'b0010 : HRDATAS = rdata_dec2;
- 4'b0011 : HRDATAS = rdata_dec3;
- 4'b0100 : HRDATAS = rdata_dec4;
- 4'b0101 : HRDATAS = rdata_dec5;
- 4'b0110 : HRDATAS = rdata_dec6;
- 4'b0111 : HRDATAS = rdata_dec7;
- 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ 5'b00000 : HRDATAS = rdata_dec0;
+ 5'b00001 : HRDATAS = rdata_dec1;
+ 5'b00010 : HRDATAS = rdata_dec2;
+ 5'b00011 : HRDATAS = rdata_dec3;
+ 5'b00100 : HRDATAS = rdata_dec4;
+ 5'b00101 : HRDATAS = rdata_dec5;
+ 5'b00110 : HRDATAS = rdata_dec6;
+ 5'b00111 : HRDATAS = rdata_dec7;
+ 5'b01000 : HRDATAS = rdata_dec8;
+ 5'b10000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
index 19fe1e92d401eb537dea999522cbfef72adbfb5d..1004262cfacc64e6a7ee7baab4039a1f0322579c 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -96,6 +96,12 @@ module nanosoc_matrix_decode_DEBUG (
resp_dec7,
rdata_dec7,
+ // Bus-switch output 8
+ active_dec8,
+ readyout_dec8,
+ resp_dec8,
+ rdata_dec8,
+
// Output port selection signals
sel_dec0,
sel_dec1,
@@ -105,6 +111,7 @@ module nanosoc_matrix_decode_DEBUG (
sel_dec5,
sel_dec6,
sel_dec7,
+ sel_dec8,
// Selected Output port data and control signals
active_dec,
@@ -124,7 +131,7 @@ module nanosoc_matrix_decode_DEBUG (
input HRESETn; // AHB System Reset
// Internal address remapping control
- input [0:0] remapping_dec; // Internal remap signal
+ input [1:0] remapping_dec; // Internal remap signal
// Signals from the Input stage
input HREADYS; // Transfer done
@@ -180,6 +187,12 @@ module nanosoc_matrix_decode_DEBUG (
input [1:0] resp_dec7; // HRESP input
input [31:0] rdata_dec7; // HRDATA input
+ // Bus-switch output MI8
+ input active_dec8; // Output stage MI8 active_dec signal
+ input readyout_dec8; // HREADYOUT input
+ input [1:0] resp_dec8; // HRESP input
+ input [31:0] rdata_dec8; // HRDATA input
+
// Output port selection signals
output sel_dec0; // HSEL output
output sel_dec1; // HSEL output
@@ -189,6 +202,7 @@ module nanosoc_matrix_decode_DEBUG (
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
output sel_dec7; // HSEL output
+ output sel_dec8; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
@@ -205,7 +219,7 @@ module nanosoc_matrix_decode_DEBUG (
wire HCLK; // AHB System Clock
wire HRESETn; // AHB System Reset
// Internal address remapping control
- wire [0:0] remapping_dec; // Internal remap signal
+ wire [1:0] remapping_dec; // Internal remap signal
// Signals from the Input stage
wire HREADYS; // Transfer done
@@ -269,6 +283,13 @@ module nanosoc_matrix_decode_DEBUG (
wire [31:0] rdata_dec7; // HRDATA input
reg sel_dec7; // HSEL output
+ // Bus-switch output MI8
+ wire active_dec8; // active_dec signal
+ wire readyout_dec8; // HREADYOUT input
+ wire [1:0] resp_dec8; // HRESP input
+ wire [31:0] rdata_dec8; // HRDATA input
+ reg sel_dec8; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -280,8 +301,8 @@ module nanosoc_matrix_decode_DEBUG (
reg [1:0] HRESPS; // Combinatorial HRESPS signal
reg [31:0] HRDATAS; // Read data bus
- reg [3:0] addr_out_port; // Address output ports
- reg [3:0] data_out_port; // Data output ports
+ reg [4:0] addr_out_port; // Address output ports
+ reg [4:0] data_out_port; // Data output ports
// Default slave signals
reg sel_dft_slv; // HSEL signal
@@ -334,98 +355,212 @@ module nanosoc_matrix_decode_DEBUG (
if (trans_dec != 2'b00)
begin
- case (remapping_dec) // Composition: REMAP[0]
- 1'b0 : begin
+ case (remapping_dec) // Composition: { REMAP[1], REMAP[0] }
+ 2'b00 : begin
+ // Static address region 0x00000000-0x0fffffff
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 5'b00011; // Select Output port MI3
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 5'b00100; // Select Output port MI4
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 5'b00101; // Select Output port MI5
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 5'b00110; // Select Output port MI6
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 5'b01000; // Select Output port MI8
+
+ else
+ addr_out_port = 5'b10000; // Select the default slave
+ end
+
+ 2'b01 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
+ if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
// Static address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x20000000-0x2fffffff
+ else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Static address region 0x30000000-0x3fffffff
+ else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
+ addr_out_port = 5'b00011; // Select Output port MI3
+
+ // Static address region 0x40000000-0x5fffffff
+ else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
+ addr_out_port = 5'b00100; // Select Output port MI4
+
+ // Static address region 0x80000000-0x8fffffff
+ else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
+ addr_out_port = 5'b00101; // Select Output port MI5
+
+ // Static address region 0x90000000-0x9fffffff
+ else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
+ addr_out_port = 5'b00110; // Select Output port MI6
+
+ // Static address region 0x60000000-0x7fffffff
+ else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+ // Static address region 0xa0000000-0xdfffffff
+ else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
+ addr_out_port = 5'b00111; // Select Output port MI7
+
+ // Static address region 0xf0000000-0xf003ffff
+ else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
+ addr_out_port = 5'b01000; // Select Output port MI8
+
+ else
+ addr_out_port = 5'b10000; // Select the default slave
+ end
+
+ 2'b10 : begin
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[1]
if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
- // Static address region 0x10000000-0x1fffffff
- else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ addr_out_port = 5'b00001; // Select Output port MI1
+
+ // Static address region 0x00000000-0x0fffffff
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Static address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Static address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Static address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xf0000000-0xf003ffff
else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0111; // Select Output port MI7
+ addr_out_port = 5'b01000; // Select Output port MI8
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end
- 1'b1 : begin
+ 2'b11 : begin
// Remapped address region 0x00000000-0x0fffffff due to REMAP[0]
if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
+
+ // Remapped address region 0x00000000-0x0fffffff due to REMAP[1]
+ else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x00000000-0x0fffffff
else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
- // Static address region 0x10000000-0x1fffffff
- else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ addr_out_port = 5'b00000; // Select Output port MI0
+ // Static address region 0x10000000-0x17ffffff
+ else if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Static address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Static address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Static address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Static address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Static address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Static address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Static address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Static address region 0xf0000000-0xf003ffff
else if ((decode_addr_dec >= 22'h3c0000) & (decode_addr_dec <= 22'h3c00ff))
- addr_out_port = 4'b0111; // Select Output port MI7
+ addr_out_port = 5'b01000; // Select Output port MI8
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end
- default : addr_out_port = {4{1'bx}};
+ default : addr_out_port = {5{1'bx}};
endcase
end // if (trans_dec != 2'b00)
@@ -445,19 +580,21 @@ module nanosoc_matrix_decode_DEBUG (
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
sel_dec7 = 1'b0;
+ sel_dec8 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
case (addr_out_port)
- 4'b0000 : sel_dec0 = 1'b1;
- 4'b0001 : sel_dec1 = 1'b1;
- 4'b0010 : sel_dec2 = 1'b1;
- 4'b0011 : sel_dec3 = 1'b1;
- 4'b0100 : sel_dec4 = 1'b1;
- 4'b0101 : sel_dec5 = 1'b1;
- 4'b0110 : sel_dec6 = 1'b1;
- 4'b0111 : sel_dec7 = 1'b1;
- 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ 5'b00000 : sel_dec0 = 1'b1;
+ 5'b00001 : sel_dec1 = 1'b1;
+ 5'b00010 : sel_dec2 = 1'b1;
+ 5'b00011 : sel_dec3 = 1'b1;
+ 5'b00100 : sel_dec4 = 1'b1;
+ 5'b00101 : sel_dec5 = 1'b1;
+ 5'b00110 : sel_dec6 = 1'b1;
+ 5'b00111 : sel_dec7 = 1'b1;
+ 5'b01000 : sel_dec8 = 1'b1;
+ 5'b10000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
sel_dec1 = 1'bx;
@@ -467,6 +604,7 @@ module nanosoc_matrix_decode_DEBUG (
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
sel_dec7 = 1'bx;
+ sel_dec8 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -483,19 +621,21 @@ module nanosoc_matrix_decode_DEBUG (
active_dec5 or
active_dec6 or
active_dec7 or
+ active_dec8 or
addr_out_port
)
begin : p_active_comb
case (addr_out_port)
- 4'b0000 : active_dec = active_dec0;
- 4'b0001 : active_dec = active_dec1;
- 4'b0010 : active_dec = active_dec2;
- 4'b0011 : active_dec = active_dec3;
- 4'b0100 : active_dec = active_dec4;
- 4'b0101 : active_dec = active_dec5;
- 4'b0110 : active_dec = active_dec6;
- 4'b0111 : active_dec = active_dec7;
- 4'b1000 : active_dec = 1'b1; // Select the default slave
+ 5'b00000 : active_dec = active_dec0;
+ 5'b00001 : active_dec = active_dec1;
+ 5'b00010 : active_dec = active_dec2;
+ 5'b00011 : active_dec = active_dec3;
+ 5'b00100 : active_dec = active_dec4;
+ 5'b00101 : active_dec = active_dec5;
+ 5'b00110 : active_dec = active_dec6;
+ 5'b00111 : active_dec = active_dec7;
+ 5'b01000 : active_dec = active_dec8;
+ 5'b10000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
end // block: p_active_comb
@@ -515,13 +655,13 @@ module nanosoc_matrix_decode_DEBUG (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_out_port_seq
if (~HRESETn)
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
else
if (HREADYS)
if (sel_dec & trans_dec[1])
data_out_port <= addr_out_port;
else
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
end // block: p_data_out_port_seq
// HREADYOUTS output decode
@@ -535,19 +675,21 @@ module nanosoc_matrix_decode_DEBUG (
readyout_dec5 or
readyout_dec6 or
readyout_dec7 or
+ readyout_dec8 or
data_out_port
)
begin : p_ready_comb
case (data_out_port)
- 4'b0000 : HREADYOUTS = readyout_dec0;
- 4'b0001 : HREADYOUTS = readyout_dec1;
- 4'b0010 : HREADYOUTS = readyout_dec2;
- 4'b0011 : HREADYOUTS = readyout_dec3;
- 4'b0100 : HREADYOUTS = readyout_dec4;
- 4'b0101 : HREADYOUTS = readyout_dec5;
- 4'b0110 : HREADYOUTS = readyout_dec6;
- 4'b0111 : HREADYOUTS = readyout_dec7;
- 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ 5'b00000 : HREADYOUTS = readyout_dec0;
+ 5'b00001 : HREADYOUTS = readyout_dec1;
+ 5'b00010 : HREADYOUTS = readyout_dec2;
+ 5'b00011 : HREADYOUTS = readyout_dec3;
+ 5'b00100 : HREADYOUTS = readyout_dec4;
+ 5'b00101 : HREADYOUTS = readyout_dec5;
+ 5'b00110 : HREADYOUTS = readyout_dec6;
+ 5'b00111 : HREADYOUTS = readyout_dec7;
+ 5'b01000 : HREADYOUTS = readyout_dec8;
+ 5'b10000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
end // block: p_ready_comb
@@ -563,19 +705,21 @@ module nanosoc_matrix_decode_DEBUG (
resp_dec5 or
resp_dec6 or
resp_dec7 or
+ resp_dec8 or
data_out_port
)
begin : p_resp_comb
case (data_out_port)
- 4'b0000 : HRESPS = resp_dec0;
- 4'b0001 : HRESPS = resp_dec1;
- 4'b0010 : HRESPS = resp_dec2;
- 4'b0011 : HRESPS = resp_dec3;
- 4'b0100 : HRESPS = resp_dec4;
- 4'b0101 : HRESPS = resp_dec5;
- 4'b0110 : HRESPS = resp_dec6;
- 4'b0111 : HRESPS = resp_dec7;
- 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ 5'b00000 : HRESPS = resp_dec0;
+ 5'b00001 : HRESPS = resp_dec1;
+ 5'b00010 : HRESPS = resp_dec2;
+ 5'b00011 : HRESPS = resp_dec3;
+ 5'b00100 : HRESPS = resp_dec4;
+ 5'b00101 : HRESPS = resp_dec5;
+ 5'b00110 : HRESPS = resp_dec6;
+ 5'b00111 : HRESPS = resp_dec7;
+ 5'b01000 : HRESPS = resp_dec8;
+ 5'b10000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
end // block: p_resp_comb
@@ -590,19 +734,21 @@ module nanosoc_matrix_decode_DEBUG (
rdata_dec5 or
rdata_dec6 or
rdata_dec7 or
+ rdata_dec8 or
data_out_port
)
begin : p_rdata_comb
case (data_out_port)
- 4'b0000 : HRDATAS = rdata_dec0;
- 4'b0001 : HRDATAS = rdata_dec1;
- 4'b0010 : HRDATAS = rdata_dec2;
- 4'b0011 : HRDATAS = rdata_dec3;
- 4'b0100 : HRDATAS = rdata_dec4;
- 4'b0101 : HRDATAS = rdata_dec5;
- 4'b0110 : HRDATAS = rdata_dec6;
- 4'b0111 : HRDATAS = rdata_dec7;
- 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ 5'b00000 : HRDATAS = rdata_dec0;
+ 5'b00001 : HRDATAS = rdata_dec1;
+ 5'b00010 : HRDATAS = rdata_dec2;
+ 5'b00011 : HRDATAS = rdata_dec3;
+ 5'b00100 : HRDATAS = rdata_dec4;
+ 5'b00101 : HRDATAS = rdata_dec5;
+ 5'b00110 : HRDATAS = rdata_dec6;
+ 5'b00111 : HRDATAS = rdata_dec7;
+ 5'b01000 : HRDATAS = rdata_dec8;
+ 5'b10000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
index 3168cdcc67e04382a2ca1d1f527368cf136937b1..ef547ec50af0c90ad769753e7aa833fdb51269cc 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -87,6 +87,12 @@ module nanosoc_matrix_decode_DMAC_0 (
resp_dec6,
rdata_dec6,
+ // Bus-switch output 7
+ active_dec7,
+ readyout_dec7,
+ resp_dec7,
+ rdata_dec7,
+
// Output port selection signals
sel_dec0,
sel_dec1,
@@ -95,6 +101,7 @@ module nanosoc_matrix_decode_DMAC_0 (
sel_dec4,
sel_dec5,
sel_dec6,
+ sel_dec7,
// Selected Output port data and control signals
active_dec,
@@ -161,6 +168,12 @@ module nanosoc_matrix_decode_DMAC_0 (
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
+ // Bus-switch output MI7
+ input active_dec7; // Output stage MI7 active_dec signal
+ input readyout_dec7; // HREADYOUT input
+ input [1:0] resp_dec7; // HRESP input
+ input [31:0] rdata_dec7; // HRDATA input
+
// Output port selection signals
output sel_dec0; // HSEL output
output sel_dec1; // HSEL output
@@ -169,6 +182,7 @@ module nanosoc_matrix_decode_DMAC_0 (
output sel_dec4; // HSEL output
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
+ output sel_dec7; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
@@ -240,6 +254,13 @@ module nanosoc_matrix_decode_DMAC_0 (
wire [31:0] rdata_dec6; // HRDATA input
reg sel_dec6; // HSEL output
+ // Bus-switch output MI7
+ wire active_dec7; // active_dec signal
+ wire readyout_dec7; // HREADYOUT input
+ wire [1:0] resp_dec7; // HRESP input
+ wire [31:0] rdata_dec7; // HRDATA input
+ reg sel_dec7; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -251,8 +272,8 @@ module nanosoc_matrix_decode_DMAC_0 (
reg [1:0] HRESPS; // Combinatorial HRESPS signal
reg [31:0] HRDATAS; // Read data bus
- reg [3:0] addr_out_port; // Address output ports
- reg [3:0] data_out_port; // Data output ports
+ reg [4:0] addr_out_port; // Address output ports
+ reg [4:0] data_out_port; // Data output ports
// Default slave signals
reg sel_dft_slv; // HSEL signal
@@ -304,42 +325,46 @@ module nanosoc_matrix_decode_DMAC_0 (
if (trans_dec != 2'b00)
begin
- // Address region 0x10000000-0x1fffffff
- if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ // Address region 0x10000000-0x17ffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Address region 0x00000000-0x0fffffff
else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end // if (trans_dec != 2'b00)
else
@@ -357,18 +382,20 @@ module nanosoc_matrix_decode_DMAC_0 (
sel_dec4 = 1'b0;
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
+ sel_dec7 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
case (addr_out_port)
- 4'b0000 : sel_dec0 = 1'b1;
- 4'b0001 : sel_dec1 = 1'b1;
- 4'b0010 : sel_dec2 = 1'b1;
- 4'b0011 : sel_dec3 = 1'b1;
- 4'b0100 : sel_dec4 = 1'b1;
- 4'b0101 : sel_dec5 = 1'b1;
- 4'b0110 : sel_dec6 = 1'b1;
- 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ 5'b00000 : sel_dec0 = 1'b1;
+ 5'b00001 : sel_dec1 = 1'b1;
+ 5'b00010 : sel_dec2 = 1'b1;
+ 5'b00011 : sel_dec3 = 1'b1;
+ 5'b00100 : sel_dec4 = 1'b1;
+ 5'b00101 : sel_dec5 = 1'b1;
+ 5'b00110 : sel_dec6 = 1'b1;
+ 5'b00111 : sel_dec7 = 1'b1;
+ 5'b10000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
sel_dec1 = 1'bx;
@@ -377,6 +404,7 @@ module nanosoc_matrix_decode_DMAC_0 (
sel_dec4 = 1'bx;
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
+ sel_dec7 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -392,18 +420,20 @@ module nanosoc_matrix_decode_DMAC_0 (
active_dec4 or
active_dec5 or
active_dec6 or
+ active_dec7 or
addr_out_port
)
begin : p_active_comb
case (addr_out_port)
- 4'b0000 : active_dec = active_dec0;
- 4'b0001 : active_dec = active_dec1;
- 4'b0010 : active_dec = active_dec2;
- 4'b0011 : active_dec = active_dec3;
- 4'b0100 : active_dec = active_dec4;
- 4'b0101 : active_dec = active_dec5;
- 4'b0110 : active_dec = active_dec6;
- 4'b1000 : active_dec = 1'b1; // Select the default slave
+ 5'b00000 : active_dec = active_dec0;
+ 5'b00001 : active_dec = active_dec1;
+ 5'b00010 : active_dec = active_dec2;
+ 5'b00011 : active_dec = active_dec3;
+ 5'b00100 : active_dec = active_dec4;
+ 5'b00101 : active_dec = active_dec5;
+ 5'b00110 : active_dec = active_dec6;
+ 5'b00111 : active_dec = active_dec7;
+ 5'b10000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
end // block: p_active_comb
@@ -423,13 +453,13 @@ module nanosoc_matrix_decode_DMAC_0 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_out_port_seq
if (~HRESETn)
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
else
if (HREADYS)
if (sel_dec & trans_dec[1])
data_out_port <= addr_out_port;
else
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
end // block: p_data_out_port_seq
// HREADYOUTS output decode
@@ -442,18 +472,20 @@ module nanosoc_matrix_decode_DMAC_0 (
readyout_dec4 or
readyout_dec5 or
readyout_dec6 or
+ readyout_dec7 or
data_out_port
)
begin : p_ready_comb
case (data_out_port)
- 4'b0000 : HREADYOUTS = readyout_dec0;
- 4'b0001 : HREADYOUTS = readyout_dec1;
- 4'b0010 : HREADYOUTS = readyout_dec2;
- 4'b0011 : HREADYOUTS = readyout_dec3;
- 4'b0100 : HREADYOUTS = readyout_dec4;
- 4'b0101 : HREADYOUTS = readyout_dec5;
- 4'b0110 : HREADYOUTS = readyout_dec6;
- 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ 5'b00000 : HREADYOUTS = readyout_dec0;
+ 5'b00001 : HREADYOUTS = readyout_dec1;
+ 5'b00010 : HREADYOUTS = readyout_dec2;
+ 5'b00011 : HREADYOUTS = readyout_dec3;
+ 5'b00100 : HREADYOUTS = readyout_dec4;
+ 5'b00101 : HREADYOUTS = readyout_dec5;
+ 5'b00110 : HREADYOUTS = readyout_dec6;
+ 5'b00111 : HREADYOUTS = readyout_dec7;
+ 5'b10000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
end // block: p_ready_comb
@@ -468,18 +500,20 @@ module nanosoc_matrix_decode_DMAC_0 (
resp_dec4 or
resp_dec5 or
resp_dec6 or
+ resp_dec7 or
data_out_port
)
begin : p_resp_comb
case (data_out_port)
- 4'b0000 : HRESPS = resp_dec0;
- 4'b0001 : HRESPS = resp_dec1;
- 4'b0010 : HRESPS = resp_dec2;
- 4'b0011 : HRESPS = resp_dec3;
- 4'b0100 : HRESPS = resp_dec4;
- 4'b0101 : HRESPS = resp_dec5;
- 4'b0110 : HRESPS = resp_dec6;
- 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ 5'b00000 : HRESPS = resp_dec0;
+ 5'b00001 : HRESPS = resp_dec1;
+ 5'b00010 : HRESPS = resp_dec2;
+ 5'b00011 : HRESPS = resp_dec3;
+ 5'b00100 : HRESPS = resp_dec4;
+ 5'b00101 : HRESPS = resp_dec5;
+ 5'b00110 : HRESPS = resp_dec6;
+ 5'b00111 : HRESPS = resp_dec7;
+ 5'b10000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
end // block: p_resp_comb
@@ -493,18 +527,20 @@ module nanosoc_matrix_decode_DMAC_0 (
rdata_dec4 or
rdata_dec5 or
rdata_dec6 or
+ rdata_dec7 or
data_out_port
)
begin : p_rdata_comb
case (data_out_port)
- 4'b0000 : HRDATAS = rdata_dec0;
- 4'b0001 : HRDATAS = rdata_dec1;
- 4'b0010 : HRDATAS = rdata_dec2;
- 4'b0011 : HRDATAS = rdata_dec3;
- 4'b0100 : HRDATAS = rdata_dec4;
- 4'b0101 : HRDATAS = rdata_dec5;
- 4'b0110 : HRDATAS = rdata_dec6;
- 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ 5'b00000 : HRDATAS = rdata_dec0;
+ 5'b00001 : HRDATAS = rdata_dec1;
+ 5'b00010 : HRDATAS = rdata_dec2;
+ 5'b00011 : HRDATAS = rdata_dec3;
+ 5'b00100 : HRDATAS = rdata_dec4;
+ 5'b00101 : HRDATAS = rdata_dec5;
+ 5'b00110 : HRDATAS = rdata_dec6;
+ 5'b00111 : HRDATAS = rdata_dec7;
+ 5'b10000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
index de20dcb82bfe62cdcc90b29355dfcf82a784f3cd..c95c0f45d407a8bb51b2afd4150550aaff9b03cf 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
@@ -87,6 +87,12 @@ module nanosoc_matrix_decode_DMAC_1 (
resp_dec6,
rdata_dec6,
+ // Bus-switch output 7
+ active_dec7,
+ readyout_dec7,
+ resp_dec7,
+ rdata_dec7,
+
// Output port selection signals
sel_dec0,
sel_dec1,
@@ -95,6 +101,7 @@ module nanosoc_matrix_decode_DMAC_1 (
sel_dec4,
sel_dec5,
sel_dec6,
+ sel_dec7,
// Selected Output port data and control signals
active_dec,
@@ -161,6 +168,12 @@ module nanosoc_matrix_decode_DMAC_1 (
input [1:0] resp_dec6; // HRESP input
input [31:0] rdata_dec6; // HRDATA input
+ // Bus-switch output MI7
+ input active_dec7; // Output stage MI7 active_dec signal
+ input readyout_dec7; // HREADYOUT input
+ input [1:0] resp_dec7; // HRESP input
+ input [31:0] rdata_dec7; // HRDATA input
+
// Output port selection signals
output sel_dec0; // HSEL output
output sel_dec1; // HSEL output
@@ -169,6 +182,7 @@ module nanosoc_matrix_decode_DMAC_1 (
output sel_dec4; // HSEL output
output sel_dec5; // HSEL output
output sel_dec6; // HSEL output
+ output sel_dec7; // HSEL output
// Selected Output port data and control signals
output active_dec; // Combinatorial active_dec O/P
@@ -240,6 +254,13 @@ module nanosoc_matrix_decode_DMAC_1 (
wire [31:0] rdata_dec6; // HRDATA input
reg sel_dec6; // HSEL output
+ // Bus-switch output MI7
+ wire active_dec7; // active_dec signal
+ wire readyout_dec7; // HREADYOUT input
+ wire [1:0] resp_dec7; // HRESP input
+ wire [31:0] rdata_dec7; // HRDATA input
+ reg sel_dec7; // HSEL output
+
// -----------------------------------------------------------------------------
// Signal declarations
@@ -251,8 +272,8 @@ module nanosoc_matrix_decode_DMAC_1 (
reg [1:0] HRESPS; // Combinatorial HRESPS signal
reg [31:0] HRDATAS; // Read data bus
- reg [3:0] addr_out_port; // Address output ports
- reg [3:0] data_out_port; // Data output ports
+ reg [4:0] addr_out_port; // Address output ports
+ reg [4:0] data_out_port; // Data output ports
// Default slave signals
reg sel_dft_slv; // HSEL signal
@@ -304,42 +325,46 @@ module nanosoc_matrix_decode_DMAC_1 (
if (trans_dec != 2'b00)
begin
- // Address region 0x10000000-0x1fffffff
- if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h07ffff))
- addr_out_port = 4'b0000; // Select Output port MI0
+ // Address region 0x10000000-0x17ffffff
+ if ((decode_addr_dec >= 22'h040000) & (decode_addr_dec <= 22'h05ffff))
+ addr_out_port = 5'b00000; // Select Output port MI0
+
+ // Address region 0x18000000-0x1fffffff
+ else if ((decode_addr_dec >= 22'h060000) & (decode_addr_dec <= 22'h07ffff))
+ addr_out_port = 5'b00001; // Select Output port MI1
// Address region 0x00000000-0x0fffffff
else if ((decode_addr_dec >= 22'h000000) & (decode_addr_dec <= 22'h03ffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Address region 0x20000000-0x2fffffff
else if ((decode_addr_dec >= 22'h080000) & (decode_addr_dec <= 22'h0bffff))
- addr_out_port = 4'b0001; // Select Output port MI1
+ addr_out_port = 5'b00010; // Select Output port MI2
// Address region 0x30000000-0x3fffffff
else if ((decode_addr_dec >= 22'h0c0000) & (decode_addr_dec <= 22'h0fffff))
- addr_out_port = 4'b0010; // Select Output port MI2
+ addr_out_port = 5'b00011; // Select Output port MI3
// Address region 0x40000000-0x5fffffff
else if ((decode_addr_dec >= 22'h100000) & (decode_addr_dec <= 22'h17ffff))
- addr_out_port = 4'b0011; // Select Output port MI3
+ addr_out_port = 5'b00100; // Select Output port MI4
// Address region 0x80000000-0x8fffffff
else if ((decode_addr_dec >= 22'h200000) & (decode_addr_dec <= 22'h23ffff))
- addr_out_port = 4'b0100; // Select Output port MI4
+ addr_out_port = 5'b00101; // Select Output port MI5
// Address region 0x90000000-0x9fffffff
else if ((decode_addr_dec >= 22'h240000) & (decode_addr_dec <= 22'h27ffff))
- addr_out_port = 4'b0101; // Select Output port MI5
+ addr_out_port = 5'b00110; // Select Output port MI6
// Address region 0x60000000-0x7fffffff
else if ((decode_addr_dec >= 22'h180000) & (decode_addr_dec <= 22'h1fffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
// Address region 0xa0000000-0xdfffffff
else if ((decode_addr_dec >= 22'h280000) & (decode_addr_dec <= 22'h37ffff))
- addr_out_port = 4'b0110; // Select Output port MI6
+ addr_out_port = 5'b00111; // Select Output port MI7
else
- addr_out_port = 4'b1000; // Select the default slave
+ addr_out_port = 5'b10000; // Select the default slave
end // if (trans_dec != 2'b00)
else
@@ -357,18 +382,20 @@ module nanosoc_matrix_decode_DMAC_1 (
sel_dec4 = 1'b0;
sel_dec5 = 1'b0;
sel_dec6 = 1'b0;
+ sel_dec7 = 1'b0;
sel_dft_slv = 1'b0;
if (sel_dec)
case (addr_out_port)
- 4'b0000 : sel_dec0 = 1'b1;
- 4'b0001 : sel_dec1 = 1'b1;
- 4'b0010 : sel_dec2 = 1'b1;
- 4'b0011 : sel_dec3 = 1'b1;
- 4'b0100 : sel_dec4 = 1'b1;
- 4'b0101 : sel_dec5 = 1'b1;
- 4'b0110 : sel_dec6 = 1'b1;
- 4'b1000 : sel_dft_slv = 1'b1; // Select the default slave
+ 5'b00000 : sel_dec0 = 1'b1;
+ 5'b00001 : sel_dec1 = 1'b1;
+ 5'b00010 : sel_dec2 = 1'b1;
+ 5'b00011 : sel_dec3 = 1'b1;
+ 5'b00100 : sel_dec4 = 1'b1;
+ 5'b00101 : sel_dec5 = 1'b1;
+ 5'b00110 : sel_dec6 = 1'b1;
+ 5'b00111 : sel_dec7 = 1'b1;
+ 5'b10000 : sel_dft_slv = 1'b1; // Select the default slave
default : begin
sel_dec0 = 1'bx;
sel_dec1 = 1'bx;
@@ -377,6 +404,7 @@ module nanosoc_matrix_decode_DMAC_1 (
sel_dec4 = 1'bx;
sel_dec5 = 1'bx;
sel_dec6 = 1'bx;
+ sel_dec7 = 1'bx;
sel_dft_slv = 1'bx;
end
endcase // case(addr_out_port)
@@ -392,18 +420,20 @@ module nanosoc_matrix_decode_DMAC_1 (
active_dec4 or
active_dec5 or
active_dec6 or
+ active_dec7 or
addr_out_port
)
begin : p_active_comb
case (addr_out_port)
- 4'b0000 : active_dec = active_dec0;
- 4'b0001 : active_dec = active_dec1;
- 4'b0010 : active_dec = active_dec2;
- 4'b0011 : active_dec = active_dec3;
- 4'b0100 : active_dec = active_dec4;
- 4'b0101 : active_dec = active_dec5;
- 4'b0110 : active_dec = active_dec6;
- 4'b1000 : active_dec = 1'b1; // Select the default slave
+ 5'b00000 : active_dec = active_dec0;
+ 5'b00001 : active_dec = active_dec1;
+ 5'b00010 : active_dec = active_dec2;
+ 5'b00011 : active_dec = active_dec3;
+ 5'b00100 : active_dec = active_dec4;
+ 5'b00101 : active_dec = active_dec5;
+ 5'b00110 : active_dec = active_dec6;
+ 5'b00111 : active_dec = active_dec7;
+ 5'b10000 : active_dec = 1'b1; // Select the default slave
default : active_dec = 1'bx;
endcase // case(addr_out_port)
end // block: p_active_comb
@@ -423,13 +453,13 @@ module nanosoc_matrix_decode_DMAC_1 (
always @ (negedge HRESETn or posedge HCLK)
begin : p_data_out_port_seq
if (~HRESETn)
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
else
if (HREADYS)
if (sel_dec & trans_dec[1])
data_out_port <= addr_out_port;
else
- data_out_port <= 4'b1000;
+ data_out_port <= 5'b10000;
end // block: p_data_out_port_seq
// HREADYOUTS output decode
@@ -442,18 +472,20 @@ module nanosoc_matrix_decode_DMAC_1 (
readyout_dec4 or
readyout_dec5 or
readyout_dec6 or
+ readyout_dec7 or
data_out_port
)
begin : p_ready_comb
case (data_out_port)
- 4'b0000 : HREADYOUTS = readyout_dec0;
- 4'b0001 : HREADYOUTS = readyout_dec1;
- 4'b0010 : HREADYOUTS = readyout_dec2;
- 4'b0011 : HREADYOUTS = readyout_dec3;
- 4'b0100 : HREADYOUTS = readyout_dec4;
- 4'b0101 : HREADYOUTS = readyout_dec5;
- 4'b0110 : HREADYOUTS = readyout_dec6;
- 4'b1000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
+ 5'b00000 : HREADYOUTS = readyout_dec0;
+ 5'b00001 : HREADYOUTS = readyout_dec1;
+ 5'b00010 : HREADYOUTS = readyout_dec2;
+ 5'b00011 : HREADYOUTS = readyout_dec3;
+ 5'b00100 : HREADYOUTS = readyout_dec4;
+ 5'b00101 : HREADYOUTS = readyout_dec5;
+ 5'b00110 : HREADYOUTS = readyout_dec6;
+ 5'b00111 : HREADYOUTS = readyout_dec7;
+ 5'b10000 : HREADYOUTS = readyout_dft_slv; // Select the default slave
default : HREADYOUTS = 1'bx;
endcase // case(data_out_port)
end // block: p_ready_comb
@@ -468,18 +500,20 @@ module nanosoc_matrix_decode_DMAC_1 (
resp_dec4 or
resp_dec5 or
resp_dec6 or
+ resp_dec7 or
data_out_port
)
begin : p_resp_comb
case (data_out_port)
- 4'b0000 : HRESPS = resp_dec0;
- 4'b0001 : HRESPS = resp_dec1;
- 4'b0010 : HRESPS = resp_dec2;
- 4'b0011 : HRESPS = resp_dec3;
- 4'b0100 : HRESPS = resp_dec4;
- 4'b0101 : HRESPS = resp_dec5;
- 4'b0110 : HRESPS = resp_dec6;
- 4'b1000 : HRESPS = resp_dft_slv; // Select the default slave
+ 5'b00000 : HRESPS = resp_dec0;
+ 5'b00001 : HRESPS = resp_dec1;
+ 5'b00010 : HRESPS = resp_dec2;
+ 5'b00011 : HRESPS = resp_dec3;
+ 5'b00100 : HRESPS = resp_dec4;
+ 5'b00101 : HRESPS = resp_dec5;
+ 5'b00110 : HRESPS = resp_dec6;
+ 5'b00111 : HRESPS = resp_dec7;
+ 5'b10000 : HRESPS = resp_dft_slv; // Select the default slave
default : HRESPS = {2{1'bx}};
endcase // case (data_out_port)
end // block: p_resp_comb
@@ -493,18 +527,20 @@ module nanosoc_matrix_decode_DMAC_1 (
rdata_dec4 or
rdata_dec5 or
rdata_dec6 or
+ rdata_dec7 or
data_out_port
)
begin : p_rdata_comb
case (data_out_port)
- 4'b0000 : HRDATAS = rdata_dec0;
- 4'b0001 : HRDATAS = rdata_dec1;
- 4'b0010 : HRDATAS = rdata_dec2;
- 4'b0011 : HRDATAS = rdata_dec3;
- 4'b0100 : HRDATAS = rdata_dec4;
- 4'b0101 : HRDATAS = rdata_dec5;
- 4'b0110 : HRDATAS = rdata_dec6;
- 4'b1000 : HRDATAS = {32{1'b0}}; // Select the default slave
+ 5'b00000 : HRDATAS = rdata_dec0;
+ 5'b00001 : HRDATAS = rdata_dec1;
+ 5'b00010 : HRDATAS = rdata_dec2;
+ 5'b00011 : HRDATAS = rdata_dec3;
+ 5'b00100 : HRDATAS = rdata_dec4;
+ 5'b00101 : HRDATAS = rdata_dec5;
+ 5'b00110 : HRDATAS = rdata_dec6;
+ 5'b00111 : HRDATAS = rdata_dec7;
+ 5'b10000 : HRDATAS = {32{1'b0}}; // Select the default slave
default : HRDATAS = {32{1'bx}};
endcase // case (data_out_port)
end // block: p_rdata_comb
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
index d8f6faa12de9f41fe2e523e6f1c3f42ce9be1749..2a8ab327069812db5086149a92db72f000d51fdf 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
index e06782c3c5bb7e27fafcd09541cfaecdabd7f178..c8f1bc10cd4269c79ecd31eb84a4162f654363fb 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
index aabb3151cda23a9bdb48506f3778e9aa527d824d..81356b33aa75446911ef9344880f18aaab157374 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
index fa9842dbd9cf78a3b9af2d406ce5b92509716610..73bdc733f21c9a1dd03530cc1c1ce1eb7ea70505 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
index d772da2bafc3b613335fb2230de3618b6f7b5b56..59ed236ce174fdf11b98b99601d532f1ddc0eabd 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..17f53d2e8bd6f02892131f873351aed85259a35e
--- /dev/null
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXTROM_0.v
@@ -0,0 +1,563 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : The Output Stage is used to route the required input
+// stage to the shared slave output.
+//
+// Notes : The bus matrix has sparse connectivity,
+// and has a burst arbiter scheme.
+//
+//-----------------------------------------------------------------------------
+
+
+
+module nanosoc_target_output_EXTROM_0 (
+
+ // Common AHB signals
+ HCLK,
+ HRESETn,
+
+ // Port 0 Signals
+ sel_op0,
+ addr_op0,
+ trans_op0,
+ write_op0,
+ size_op0,
+ burst_op0,
+ prot_op0,
+ master_op0,
+ mastlock_op0,
+ wdata_op0,
+ held_tran_op0,
+
+ // Port 1 Signals
+ sel_op1,
+ addr_op1,
+ trans_op1,
+ write_op1,
+ size_op1,
+ burst_op1,
+ prot_op1,
+ master_op1,
+ mastlock_op1,
+ wdata_op1,
+ held_tran_op1,
+
+ // Port 2 Signals
+ sel_op2,
+ addr_op2,
+ trans_op2,
+ write_op2,
+ size_op2,
+ burst_op2,
+ prot_op2,
+ master_op2,
+ mastlock_op2,
+ wdata_op2,
+ held_tran_op2,
+
+ // Port 3 Signals
+ sel_op3,
+ addr_op3,
+ trans_op3,
+ write_op3,
+ size_op3,
+ burst_op3,
+ prot_op3,
+ master_op3,
+ mastlock_op3,
+ wdata_op3,
+ held_tran_op3,
+
+ // Slave read data and response
+ HREADYOUTM,
+
+ active_op0,
+ active_op1,
+ active_op2,
+ active_op3,
+
+ // Slave Address/Control Signals
+ HSELM,
+ HADDRM,
+ HTRANSM,
+ HWRITEM,
+ HSIZEM,
+ HBURSTM,
+ HPROTM,
+ HMASTERM,
+ HMASTLOCKM,
+ HREADYMUXM,
+ HWDATAM
+
+ );
+
+
+// -----------------------------------------------------------------------------
+// Input and Output declarations
+// -----------------------------------------------------------------------------
+
+ // Common AHB signals
+ input HCLK; // AHB system clock
+ input HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ input sel_op0; // Port 0 HSEL signal
+ input [31:0] addr_op0; // Port 0 HADDR signal
+ input [1:0] trans_op0; // Port 0 HTRANS signal
+ input write_op0; // Port 0 HWRITE signal
+ input [2:0] size_op0; // Port 0 HSIZE signal
+ input [2:0] burst_op0; // Port 0 HBURST signal
+ input [3:0] prot_op0; // Port 0 HPROT signal
+ input [3:0] master_op0; // Port 0 HMASTER signal
+ input mastlock_op0; // Port 0 HMASTLOCK signal
+ input [31:0] wdata_op0; // Port 0 HWDATA signal
+ input held_tran_op0; // Port 0 HeldTran signal
+
+ // Bus-switch input 1
+ input sel_op1; // Port 1 HSEL signal
+ input [31:0] addr_op1; // Port 1 HADDR signal
+ input [1:0] trans_op1; // Port 1 HTRANS signal
+ input write_op1; // Port 1 HWRITE signal
+ input [2:0] size_op1; // Port 1 HSIZE signal
+ input [2:0] burst_op1; // Port 1 HBURST signal
+ input [3:0] prot_op1; // Port 1 HPROT signal
+ input [3:0] master_op1; // Port 1 HMASTER signal
+ input mastlock_op1; // Port 1 HMASTLOCK signal
+ input [31:0] wdata_op1; // Port 1 HWDATA signal
+ input held_tran_op1; // Port 1 HeldTran signal
+
+ // Bus-switch input 2
+ input sel_op2; // Port 2 HSEL signal
+ input [31:0] addr_op2; // Port 2 HADDR signal
+ input [1:0] trans_op2; // Port 2 HTRANS signal
+ input write_op2; // Port 2 HWRITE signal
+ input [2:0] size_op2; // Port 2 HSIZE signal
+ input [2:0] burst_op2; // Port 2 HBURST signal
+ input [3:0] prot_op2; // Port 2 HPROT signal
+ input [3:0] master_op2; // Port 2 HMASTER signal
+ input mastlock_op2; // Port 2 HMASTLOCK signal
+ input [31:0] wdata_op2; // Port 2 HWDATA signal
+ input held_tran_op2; // Port 2 HeldTran signal
+
+ // Bus-switch input 3
+ input sel_op3; // Port 3 HSEL signal
+ input [31:0] addr_op3; // Port 3 HADDR signal
+ input [1:0] trans_op3; // Port 3 HTRANS signal
+ input write_op3; // Port 3 HWRITE signal
+ input [2:0] size_op3; // Port 3 HSIZE signal
+ input [2:0] burst_op3; // Port 3 HBURST signal
+ input [3:0] prot_op3; // Port 3 HPROT signal
+ input [3:0] master_op3; // Port 3 HMASTER signal
+ input mastlock_op3; // Port 3 HMASTLOCK signal
+ input [31:0] wdata_op3; // Port 3 HWDATA signal
+ input held_tran_op3; // Port 3 HeldTran signal
+
+ input HREADYOUTM; // HREADY feedback
+
+ output active_op0; // Port 0 Active signal
+ output active_op1; // Port 1 Active signal
+ output active_op2; // Port 2 Active signal
+ output active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ output HSELM; // Slave select line
+ output [31:0] HADDRM; // Address
+ output [1:0] HTRANSM; // Transfer type
+ output HWRITEM; // Transfer direction
+ output [2:0] HSIZEM; // Transfer size
+ output [2:0] HBURSTM; // Burst type
+ output [3:0] HPROTM; // Protection control
+ output [3:0] HMASTERM; // Master ID
+ output HMASTLOCKM; // Locked transfer
+ output HREADYMUXM; // Transfer done
+ output [31:0] HWDATAM; // Write data
+
+
+// -----------------------------------------------------------------------------
+// Wire declarations
+// -----------------------------------------------------------------------------
+ wire HCLK; // AHB system clock
+ wire HRESETn; // AHB system reset
+
+ // Bus-switch input 0
+ wire sel_op0; // Port 0 HSEL signal
+ wire [31:0] addr_op0; // Port 0 HADDR signal
+ wire [1:0] trans_op0; // Port 0 HTRANS signal
+ wire write_op0; // Port 0 HWRITE signal
+ wire [2:0] size_op0; // Port 0 HSIZE signal
+ wire [2:0] burst_op0; // Port 0 HBURST signal
+ wire [3:0] prot_op0; // Port 0 HPROT signal
+ wire [3:0] master_op0; // Port 0 HMASTER signal
+ wire mastlock_op0; // Port 0 HMASTLOCK signal
+ wire [31:0] wdata_op0; // Port 0 HWDATA signal
+ wire held_tran_op0; // Port 0 HeldTran signal
+ reg active_op0; // Port 0 Active signal
+
+ // Bus-switch input 1
+ wire sel_op1; // Port 1 HSEL signal
+ wire [31:0] addr_op1; // Port 1 HADDR signal
+ wire [1:0] trans_op1; // Port 1 HTRANS signal
+ wire write_op1; // Port 1 HWRITE signal
+ wire [2:0] size_op1; // Port 1 HSIZE signal
+ wire [2:0] burst_op1; // Port 1 HBURST signal
+ wire [3:0] prot_op1; // Port 1 HPROT signal
+ wire [3:0] master_op1; // Port 1 HMASTER signal
+ wire mastlock_op1; // Port 1 HMASTLOCK signal
+ wire [31:0] wdata_op1; // Port 1 HWDATA signal
+ wire held_tran_op1; // Port 1 HeldTran signal
+ reg active_op1; // Port 1 Active signal
+
+ // Bus-switch input 2
+ wire sel_op2; // Port 2 HSEL signal
+ wire [31:0] addr_op2; // Port 2 HADDR signal
+ wire [1:0] trans_op2; // Port 2 HTRANS signal
+ wire write_op2; // Port 2 HWRITE signal
+ wire [2:0] size_op2; // Port 2 HSIZE signal
+ wire [2:0] burst_op2; // Port 2 HBURST signal
+ wire [3:0] prot_op2; // Port 2 HPROT signal
+ wire [3:0] master_op2; // Port 2 HMASTER signal
+ wire mastlock_op2; // Port 2 HMASTLOCK signal
+ wire [31:0] wdata_op2; // Port 2 HWDATA signal
+ wire held_tran_op2; // Port 2 HeldTran signal
+ reg active_op2; // Port 2 Active signal
+
+ // Bus-switch input 3
+ wire sel_op3; // Port 3 HSEL signal
+ wire [31:0] addr_op3; // Port 3 HADDR signal
+ wire [1:0] trans_op3; // Port 3 HTRANS signal
+ wire write_op3; // Port 3 HWRITE signal
+ wire [2:0] size_op3; // Port 3 HSIZE signal
+ wire [2:0] burst_op3; // Port 3 HBURST signal
+ wire [3:0] prot_op3; // Port 3 HPROT signal
+ wire [3:0] master_op3; // Port 3 HMASTER signal
+ wire mastlock_op3; // Port 3 HMASTLOCK signal
+ wire [31:0] wdata_op3; // Port 3 HWDATA signal
+ wire held_tran_op3; // Port 3 HeldTran signal
+ reg active_op3; // Port 3 Active signal
+
+ // Slave Address/Control Signals
+ wire HSELM; // Slave select line
+ reg [31:0] HADDRM; // Address
+ wire [1:0] HTRANSM; // Transfer type
+ reg HWRITEM; // Transfer direction
+ reg [2:0] HSIZEM; // Transfer size
+ wire [2:0] HBURSTM; // Burst type
+ reg [3:0] HPROTM; // Protection control
+ reg [3:0] HMASTERM; // Master ID
+ wire HMASTLOCKM; // Locked transfer
+ wire HREADYMUXM; // Transfer done
+ reg [31:0] HWDATAM; // Write data
+ wire HREADYOUTM; // HREADY feedback
+
+
+// -----------------------------------------------------------------------------
+// Signal declarations
+// -----------------------------------------------------------------------------
+ wire req_port0; // Port 0 request signal
+ wire req_port1; // Port 1 request signal
+ wire req_port2; // Port 2 request signal
+ wire req_port3; // Port 3 request signal
+
+ wire [1:0] addr_in_port; // Address input port
+ reg [1:0] data_in_port; // Data input port
+ wire no_port; // No port selected signal
+ reg slave_sel; // Slave select signal
+ reg wdata_phase; // Used to prevent unnecesary toggling
+
+ reg hsel_lock; // Held HSELS during locked sequence
+ wire next_hsel_lock; // Pre-registered hsel_lock
+ wire hlock_arb; // HMASTLOCK modified by HSEL for arbitration
+
+ reg i_hselm; // Internal HSELM
+ reg [1:0] i_htransm; // Internal HTRANSM
+ reg [2:0] i_hburstm; // Internal HBURSTM
+ wire i_hreadymuxm; // Internal HREADYMUXM
+ reg i_hmastlockm; // Internal HMASTLOCKM
+
+
+// -----------------------------------------------------------------------------
+// Beginning of main code
+// -----------------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
+// Port Selection
+// -----------------------------------------------------------------------------
+
+ assign req_port0 = held_tran_op0 & sel_op0;
+ assign req_port1 = held_tran_op1 & sel_op1;
+ assign req_port2 = held_tran_op2 & sel_op2;
+ assign req_port3 = held_tran_op3 & sel_op3;
+
+ // Arbiter instance for resolving requests to this output stage
+ nanosoc_arbiter_EXTROM_0 u_output_arb (
+
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ .req_port0 (req_port0),
+ .req_port1 (req_port1),
+ .req_port2 (req_port2),
+ .req_port3 (req_port3),
+
+ .HREADYM (i_hreadymuxm),
+ .HSELM (i_hselm),
+ .HTRANSM (i_htransm),
+ .HBURSTM (i_hburstm),
+ .HMASTLOCKM (hlock_arb),
+
+ .addr_in_port (addr_in_port),
+ .no_port (no_port)
+
+ );
+
+
+ // Active signal combinatorial decode
+ always @ (addr_in_port or no_port)
+ begin : p_active_comb
+ // Default value(s)
+ active_op0 = 1'b0;
+ active_op1 = 1'b0;
+ active_op2 = 1'b0;
+ active_op3 = 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ 2'b00 : active_op0 = 1'b1;
+ 2'b01 : active_op1 = 1'b1;
+ 2'b10 : active_op2 = 1'b1;
+ 2'b11 : active_op3 = 1'b1;
+ default : begin
+ active_op0 = 1'bx;
+ active_op1 = 1'bx;
+ active_op2 = 1'bx;
+ active_op3 = 1'bx;
+ end
+ endcase // case(addr_in_port)
+ end // block: p_active_comb
+
+
+ // Address/control output decode
+ always @ (
+ sel_op0 or addr_op0 or trans_op0 or write_op0 or
+ size_op0 or burst_op0 or prot_op0 or
+ master_op0 or mastlock_op0 or
+ sel_op1 or addr_op1 or trans_op1 or write_op1 or
+ size_op1 or burst_op1 or prot_op1 or
+ master_op1 or mastlock_op1 or
+ sel_op2 or addr_op2 or trans_op2 or write_op2 or
+ size_op2 or burst_op2 or prot_op2 or
+ master_op2 or mastlock_op2 or
+ sel_op3 or addr_op3 or trans_op3 or write_op3 or
+ size_op3 or burst_op3 or prot_op3 or
+ master_op3 or mastlock_op3 or
+ addr_in_port or no_port
+ )
+ begin : p_addr_mux
+ // Default values
+ i_hselm = 1'b0;
+ HADDRM = {32{1'b0}};
+ i_htransm = 2'b00;
+ HWRITEM = 1'b0;
+ HSIZEM = 3'b000;
+ i_hburstm = 3'b000;
+ HPROTM = {4{1'b0}};
+ HMASTERM = 4'b0000;
+ i_hmastlockm= 1'b0;
+
+ // Decode selection when enabled
+ if (~no_port)
+ case (addr_in_port)
+ // Bus-switch input 0
+ 2'b00 :
+ begin
+ i_hselm = sel_op0;
+ HADDRM = addr_op0;
+ i_htransm = trans_op0;
+ HWRITEM = write_op0;
+ HSIZEM = size_op0;
+ i_hburstm = burst_op0;
+ HPROTM = prot_op0;
+ HMASTERM = master_op0;
+ i_hmastlockm= mastlock_op0;
+ end // case: 4'b00
+
+ // Bus-switch input 1
+ 2'b01 :
+ begin
+ i_hselm = sel_op1;
+ HADDRM = addr_op1;
+ i_htransm = trans_op1;
+ HWRITEM = write_op1;
+ HSIZEM = size_op1;
+ i_hburstm = burst_op1;
+ HPROTM = prot_op1;
+ HMASTERM = master_op1;
+ i_hmastlockm= mastlock_op1;
+ end // case: 4'b01
+
+ // Bus-switch input 2
+ 2'b10 :
+ begin
+ i_hselm = sel_op2;
+ HADDRM = addr_op2;
+ i_htransm = trans_op2;
+ HWRITEM = write_op2;
+ HSIZEM = size_op2;
+ i_hburstm = burst_op2;
+ HPROTM = prot_op2;
+ HMASTERM = master_op2;
+ i_hmastlockm= mastlock_op2;
+ end // case: 4'b10
+
+ // Bus-switch input 3
+ 2'b11 :
+ begin
+ i_hselm = sel_op3;
+ HADDRM = addr_op3;
+ i_htransm = trans_op3;
+ HWRITEM = write_op3;
+ HSIZEM = size_op3;
+ i_hburstm = burst_op3;
+ HPROTM = prot_op3;
+ HMASTERM = master_op3;
+ i_hmastlockm= mastlock_op3;
+ end // case: 4'b11
+
+ default :
+ begin
+ i_hselm = 1'bx;
+ HADDRM = {32{1'bx}};
+ i_htransm = 2'bxx;
+ HWRITEM = 1'bx;
+ HSIZEM = 3'bxxx;
+ i_hburstm = 3'bxxx;
+ HPROTM = {4{1'bx}};
+ HMASTERM = 4'bxxxx;
+ i_hmastlockm= 1'bx;
+ end // case: default
+ endcase // case(addr_in_port)
+ end // block: p_addr_mux
+
+ // hsel_lock provides support for AHB masters that address other
+ // slave regions in the middle of a locked sequence (i.e. HSEL is
+ // de-asserted during the locked sequence). Unless HMASTLOCK is
+ // held during these intermediate cycles, the OutputArb scheme will
+ // lose track of the locked sequence and may allow another input
+ // port to access the output port which should be locked
+ assign next_hsel_lock = (i_hselm & i_htransm[1] & i_hmastlockm) ? 1'b1 :
+ (i_hmastlockm == 1'b0) ? 1'b0 :
+ hsel_lock;
+
+ // Register hsel_lock
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_hsel_lock
+ if (~HRESETn)
+ hsel_lock <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ hsel_lock <= next_hsel_lock;
+ end
+
+ // Version of HMASTLOCK which is masked when not selected, unless a
+ // locked sequence has already begun through this port
+ assign hlock_arb = i_hmastlockm & (hsel_lock | i_hselm);
+
+ assign HTRANSM = i_htransm;
+ assign HBURSTM = i_hburstm;
+ assign HSELM = i_hselm;
+ assign HMASTLOCKM = i_hmastlockm;
+
+ // Dataport register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_data_in_port_reg
+ if (~HRESETn)
+ data_in_port <= 2'b11;
+ else
+ if (i_hreadymuxm)
+ data_in_port <= addr_in_port;
+ end
+
+ // Dataphase register
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_wdata_phase_reg
+ if (~HRESETn)
+ wdata_phase <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ wdata_phase <= i_hselm & i_htransm[1];
+ end
+
+
+ // HWDATAM output decode
+ always @ (
+ wdata_op0 or
+ wdata_op1 or
+ wdata_op2 or
+ wdata_op3 or
+ data_in_port or wdata_phase
+ )
+ begin : p_data_mux
+ // Default value
+ HWDATAM = {32{1'b0}};
+
+ // If interface active
+ if (wdata_phase)
+ // Decode selection
+ case (data_in_port)
+ 2'b00 : HWDATAM = wdata_op0;
+ 2'b01 : HWDATAM = wdata_op1;
+ 2'b10 : HWDATAM = wdata_op2;
+ 2'b11 : HWDATAM = wdata_op3;
+ default : HWDATAM = {32{1'bx}};
+ endcase // case(data_in_port)
+ end // block: p_data_mux
+
+
+ // ---------------------------------------------------------------------------
+ // HREADYMUXM generation
+ // ---------------------------------------------------------------------------
+ // The HREADY signal on the shared slave is generated directly from
+ // the shared slave HREADYOUTS if the slave is selected, otherwise
+ // it mirrors the HREADY signal of the appropriate input port
+ always @ (negedge HRESETn or posedge HCLK)
+ begin : p_slave_sel_reg
+ if (~HRESETn)
+ slave_sel <= 1'b0;
+ else
+ if (i_hreadymuxm)
+ slave_sel <= i_hselm;
+ end
+
+ // HREADYMUXM output selection
+ assign i_hreadymuxm = (slave_sel) ? HREADYOUTM : 1'b1;
+
+ // Drive output with internal version of the signal
+ assign HREADYMUXM = i_hreadymuxm;
+
+
+endmodule
+
+// --================================= End ===================================--
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
index b369f495bc2a930c3d4e1ceabdd53eee88cee5a9..b1a79494c6f22dd11a910f58fbe1100ac3d78d08 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
index 86b47f186ec24ae027cac3849a5d248a28fab80e..f73bcaa2da45e5c7063a8d8534b12ed9706d0aa8 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
index f84cb2b2650c823d1e90d3e4d224fbec97983e41..6161188eba749874582bcb4fd08344bea0d00919 100644
--- a/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
+++ b/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
@@ -3,7 +3,7 @@
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
-// (C) COPYRIGHT 2001-2023 Arm Limited or its affiliates.
+// (C) COPYRIGHT 2001-2025 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
diff --git a/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml b/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
index eb0be4dd0b6576eb1ebbae716f2e7256a4994573..643061dd17623cd7d62ea964231bca9b5d978423 100644
--- a/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
+++ b/nanosoc/nanosoc_busmatrix/xml/nanosoc.xml
@@ -35,7 +35,7 @@
<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
<!-- Purpose : based on Example XML file, defining an interconnect for -->
<!-- (was 2 AHB Masters and 3 AHB Slaves.) -->
-<!-- 4 AHB Managers and 8 AHB Subordinates -->
+<!-- 4 AHB Managers and 9 AHB Subordinates -->
<!-- -->
<!-- Note : This information will overwrite parameters -->
<!-- specified on the command line -->
@@ -63,6 +63,7 @@
<slave_interface name="_DEBUG">
<sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_EXTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
<sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
@@ -71,7 +72,8 @@
<sparse_connect interface="_EXPRAM_H"/>
<sparse_connect interface="_SYSTABLE"/>
<address_region interface="_BOOTROM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='17ffffff' remapping='none'/>
+ <address_region interface="_EXTROM_0" mem_lo='18000000' mem_hi='1fffffff' remapping='none'/>
<address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
<address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
@@ -81,10 +83,12 @@
<address_region interface="_EXP" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
<address_region interface="_SYSTABLE" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
<remap_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ <remap_region interface="_EXTROM_0" mem_lo='00000000' mem_hi='0fffffff' bit='1'/>
</slave_interface>
<slave_interface name="_DMAC_0">
<sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_EXTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
<sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
@@ -92,7 +96,8 @@
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
<address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='17ffffff' remapping='none'/>
+ <address_region interface="_EXTROM_0" mem_lo='18000000' mem_hi='1fffffff' remapping='none'/>
<address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
<address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
@@ -104,6 +109,7 @@
<slave_interface name="_DMAC_1">
<sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_EXTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
<sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
@@ -111,7 +117,8 @@
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
<address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='17ffffff' remapping='none'/>
+ <address_region interface="_EXTROM_0" mem_lo='18000000' mem_hi='1fffffff' remapping='none'/>
<address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
<address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
@@ -123,6 +130,7 @@
<slave_interface name="_CPU_0">
<sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_EXTROM_0"/>
<sparse_connect interface="_IMEM_0"/>
<sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
@@ -131,7 +139,8 @@
<sparse_connect interface="_EXPRAM_H"/>
<sparse_connect interface="_SYSTABLE"/>
<address_region interface="_BOOTROM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='17ffffff' remapping='none'/>
+ <address_region interface="_EXTROM_0" mem_lo='18000000' mem_hi='1fffffff' remapping='none'/>
<address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
<address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
@@ -141,11 +150,13 @@
<address_region interface="_EXP" mem_lo='a0000000' mem_hi='dfffffff' remapping='none'/>
<address_region interface="_SYSTABLE" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
<remap_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ <remap_region interface="_EXTROM_0" mem_lo='00000000' mem_hi='0fffffff' bit='1'/>
</slave_interface>
<!-- Master interface definitions -->
<master_interface name="_BOOTROM_0"/>
+ <master_interface name="_EXTROM_0"/>
<master_interface name="_IMEM_0"/>
<master_interface name="_DMEM_0"/>
<master_interface name="_SYSIO"/>
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index b08b10afc0c620a0cf054ea5b872825bcbff98dd..46c146b2d2ba52fb95085460dc81ef87def5b1cd 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -73,7 +73,7 @@ module nanosoc_region_sysio #(
output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 irqs
// CPU power/reset control
- output wire REMAP_CTRL, // REMAP control bit
+ output wire [ 3:0] REMAP_CTRL, // REMAP control bit
output wire APBACTIVE, // APB bus active (for clock gating of PCLKG)
input wire SYSRESETREQ, // Processor control - system reset request
output wire WDOGRESETREQ, // Watchdog reset request
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
index 8cf8a1cd639a66edddec05663c2c55d9b081509c..36341458463e40cb15a3b7746368a29c309a179e 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
@@ -84,7 +84,7 @@ module nanosoc_sysctrl #(
input wire [3:0] ECOREVNUM, // ECO revision number
// System control signals
- output wire REMAP, // memory remap
+ output wire [3:0] REMAP, // memory remap
output wire PMUENABLE, // Power Management Unit enable, will be disabled in design
// start version
output wire LOCKUPRESET // Enable reset if lockup
@@ -118,7 +118,7 @@ localparam ARM_CMSDK_CM0_SYSCTRL_CID3 = {32'h000000B1}; // 0xFFC : CID 3
reg [31:0] read_mux;
reg [31:0] read_mux_le; // little endian of read mux
- reg reg_remap;
+ reg [ 3:0] reg_remap;
`ifdef CORTEX_M0DESIGNSTART
wire reg_pmuenable;
`else
@@ -194,7 +194,7 @@ localparam ARM_CMSDK_CM0_SYSCTRL_CID3 = {32'h000000B1}; // 0xFFC : CID 3
begin
if (reg_addr[11:5] == 7'h00) begin
case(reg_addr[4:2])
- 3'b000: read_mux_le ={{31{1'b0}}, reg_remap} ;
+ 3'b000: read_mux_le ={{28{1'b0}}, reg_remap} ;
3'b001: read_mux_le ={{31{1'b0}}, reg_pmuenable} ;
3'b010: read_mux_le ={{31{1'b0}}, reg_lockupreset} ;
3'b100: read_mux_le ={{29{1'b0}}, reg_resetinfo} ;
@@ -262,9 +262,9 @@ localparam ARM_CMSDK_CM0_SYSCTRL_CID3 = {32'h000000B1}; // 0xFFC : CID 3
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
- reg_remap <= 1'b1;
+ reg_remap <= 4'b0001;
else if (reg_remap_write)
- reg_remap <= HWDATALE[0];
+ reg_remap <= HWDATALE[3:0];
end
// ----------------------------------------------------------
diff --git a/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v b/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
index 155dbee0e9911fefc95548ed8d6da8716232f6da..eaa24f3325fa644aa003e81f838b59c08daa8570 100644
--- a/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
+++ b/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
@@ -92,6 +92,21 @@ module nanosoc_ss_interconnect #(
output wire BOOTROM_0_HMASTLOCK, // Locked Sequence
output wire BOOTROM_0_HREADYMUX, // Transfer done
+ // EXTROM 0 Region Slave Port
+ input wire [31:0] EXTROM_0_HRDATA, // Read data bus
+ input wire EXTROM_0_HREADYOUT, // HREADY feedback
+ input wire EXTROM_0_HRESP, // Transfer response
+ output wire EXTROM_0_HSEL, // Slave Select
+ output wire [31:0] EXTROM_0_HADDR, // Address bus
+ output wire [1:0] EXTROM_0_HTRANS, // Transfer type
+ output wire EXTROM_0_HWRITE, // Transfer direction
+ output wire [2:0] EXTROM_0_HSIZE, // Transfer size
+ output wire [2:0] EXTROM_0_HBURST, // Burst type
+ output wire [3:0] EXTROM_0_HPROT, // Protection control
+ output wire [31:0] EXTROM_0_HWDATA, // Write data
+ output wire EXTROM_0_HMASTLOCK, // Locked Sequence
+ output wire EXTROM_0_HREADYMUX, // Transfer done
+
// CPU 0 Instruction Memory Region Slave Port
input wire [31:0] IMEM_0_HRDATA, // Read data bus
input wire IMEM_0_HREADYOUT, // HREADY feedback
@@ -264,19 +279,34 @@ module nanosoc_ss_interconnect #(
.HRESP_CPU_0 (CPU_0_HRESP), // Transfer response
// CPU 0 Bootrom Memory Region Slave Port
- .HRDATA_BOOTROM_0 (BOOTROM_0_HRDATA), // Read data bus
- .HREADYOUT_BOOTROM_0 (BOOTROM_0_HREADYOUT), // HREADY feedback
- .HRESP_BOOTROM_0 (BOOTROM_0_HRESP), // Transfer response
- .HSEL_BOOTROM_0 (BOOTROM_0_HSEL), // Slave Select
- .HADDR_BOOTROM_0 (BOOTROM_0_HADDR), // Address bus
- .HTRANS_BOOTROM_0 (BOOTROM_0_HTRANS), // Transfer type
- .HWRITE_BOOTROM_0 (BOOTROM_0_HWRITE), // Transfer direction
- .HSIZE_BOOTROM_0 (BOOTROM_0_HSIZE), // Transfer size
- .HBURST_BOOTROM_0 (BOOTROM_0_HBURST), // Burst type
- .HPROT_BOOTROM_0 (BOOTROM_0_HPROT), // Protection control
- .HWDATA_BOOTROM_0 (BOOTROM_0_HWDATA), // Write data
- .HMASTLOCK_BOOTROM_0 (BOOTROM_0_HMASTLOCK), // Locked Sequence
- .HREADYMUX_BOOTROM_0 (BOOTROM_0_HREADYMUX), // Transfer done
+ .HRDATA_BOOTROM_0 (BOOTROM_0_HRDATA), // Read data bus
+ .HREADYOUT_BOOTROM_0 (BOOTROM_0_HREADYOUT), // HREADY feedback
+ .HRESP_BOOTROM_0 (BOOTROM_0_HRESP), // Transfer response
+ .HSEL_BOOTROM_0 (BOOTROM_0_HSEL), // Slave Select
+ .HADDR_BOOTROM_0 (BOOTROM_0_HADDR), // Address bus
+ .HTRANS_BOOTROM_0 (BOOTROM_0_HTRANS), // Transfer type
+ .HWRITE_BOOTROM_0 (BOOTROM_0_HWRITE), // Transfer direction
+ .HSIZE_BOOTROM_0 (BOOTROM_0_HSIZE), // Transfer size
+ .HBURST_BOOTROM_0 (BOOTROM_0_HBURST), // Burst type
+ .HPROT_BOOTROM_0 (BOOTROM_0_HPROT), // Protection control
+ .HWDATA_BOOTROM_0 (BOOTROM_0_HWDATA), // Write data
+ .HMASTLOCK_BOOTROM_0 (BOOTROM_0_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_BOOTROM_0 (BOOTROM_0_HREADYMUX), // Transfer done
+
+ // CPU 0 EXTROM Memory Region Slave Port
+ .HRDATA_EXTROM_0 (EXTROM_0_HRDATA), // Read data bus
+ .HREADYOUT_EXTROM_0 (EXTROM_0_HREADYOUT), // HREADY feedback
+ .HRESP_EXTROM_0 (EXTROM_0_HRESP), // Transfer response
+ .HSEL_EXTROM_0 (EXTROM_0_HSEL), // Slave Select
+ .HADDR_EXTROM_0 (EXTROM_0_HADDR), // Address bus
+ .HTRANS_EXTROM_0 (EXTROM_0_HTRANS), // Transfer type
+ .HWRITE_EXTROM_0 (EXTROM_0_HWRITE), // Transfer direction
+ .HSIZE_EXTROM_0 (EXTROM_0_HSIZE), // Transfer size
+ .HBURST_EXTROM_0 (EXTROM_0_HBURST), // Burst type
+ .HPROT_EXTROM_0 (EXTROM_0_HPROT), // Protection control
+ .HWDATA_EXTROM_0 (EXTROM_0_HWDATA), // Write data
+ .HMASTLOCK_EXTROM_0 (EXTROM_0_HMASTLOCK), // Locked Sequence
+ .HREADYMUX_EXTROM_0 (EXTROM_0_HREADYMUX), // Transfer done
// CPU 0 Instruction Memory Region Slave Port
.HRDATA_IMEM_0 (IMEM_0_HRDATA), // Read data bus
@@ -383,4 +413,4 @@ module nanosoc_ss_interconnect #(
.HMASTLOCK_SYSTABLE (SYSTABLE_HMASTLOCK), // Locked Sequence
.HREADYMUX_SYSTABLE (SYSTABLE_HREADYMUX) // Transfer done
);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
index 18ca5fe6b68ac2c23e10c0b7f4913b6df836ad87..2796e1e9e04cb533c38187bab5a640be4f5b025a 100644
--- a/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+++ b/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
@@ -102,7 +102,7 @@ module nanosoc_ss_systemctrl #(
output wire [15:0] SYS_GPIO1_IRQ, // GPIO 0 IRQs
// CPU power/reset control
- output wire SYS_REMAP_CTRL, // REMAP control bit
+ output wire [ 3:0] SYS_REMAP_CTRL, // REMAP control bits x4
output wire SYS_WDOGRESETREQ, // Watchdog reset request
output wire SYS_LOCKUPRESET, // System Controller Config - Reset if lockup
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index 4e4b3c1edca353754c7723f7d48e1765125a3daf..05751f4b05ce7a59253092226a2907c97c8926cc 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -210,6 +210,21 @@ module nanosoc_system #(
wire BOOTROM_0_HREADYOUT; // HREADY feedback
wire BOOTROM_0_HRESP; // Transfer response
+ // EXTROM 0 Region Wiring - To Interconnect Subsystem
+ wire EXTROM_0_HSEL; // Select
+ wire [31:0] EXTROM_0_HADDR; // Address bus
+ wire [1:0] EXTROM_0_HTRANS; // Transfer type
+ wire EXTROM_0_HWRITE; // Transfer direction
+ wire [2:0] EXTROM_0_HSIZE; // Transfer size
+ wire [2:0] EXTROM_0_HBURST; // Burst type
+ wire [3:0] EXTROM_0_HPROT; // Protection control
+ wire [31:0] EXTROM_0_HWDATA; // Write data
+ wire EXTROM_0_HMASTLOCK; // Locked Sequence
+ wire [31:0] EXTROM_0_HRDATA; // Read data bus
+ wire EXTROM_0_HREADY; // HREADY feedback
+ wire EXTROM_0_HREADYOUT; // HREADY feedback
+ wire EXTROM_0_HRESP; // Transfer response
+
// Instruction Memory 0 Region Wiring - To Interconnect Subsystem
wire IMEM_0_HSEL; // Select
wire [31:0] IMEM_0_HADDR; // Address bus
@@ -262,6 +277,11 @@ module nanosoc_system #(
//--------------------------
assign CPU_0_PMUENABLE = SYS_PMUENABLE;
+// QSPI ROM controller here, plus APB control port
+ assign EXTROM_0_HRDATA[31:0] = 32'hEEEEEEEE; // Read data bus
+ assign EXTROM_0_HREADYOUT = 1'b1; // HREADY tied off always ready
+ assign EXTROM_0_HRESP = 1'b0; // Transfer response no error
+
// Instantiate Subsystem
//--------------------------
@@ -1059,8 +1079,8 @@ wire EXT_DAT_TXD_TREADY ;
// Bus Matrix Remap Control - To Interconnect Subsystem
- wire SYSIO_REMAP_CTRL; // REMAP control bit
- wire [3:0] SYS_REMAP_CTRL; // REMAP control bit
+ wire [3:0] SYSIO_REMAP_CTRL; // REMAP IO control bit
+ wire [3:0] SYS_REMAP_CTRL; // REMAP system control bit
// Lockup Signals - To System
wire SYS_WDOGRESETREQ; // Watchdog reset request
@@ -1076,7 +1096,7 @@ wire EXT_DAT_TXD_TREADY ;
// Remap Wiring
//--------------------------
- assign SYS_REMAP_CTRL [3:0] = { 3'b000, !SYSIO_REMAP_CTRL};
+ assign SYS_REMAP_CTRL [3:0] = { 2'b00, SYSIO_REMAP_CTRL[1], !SYSIO_REMAP_CTRL[0]};
// Combined CPU Wiring
@@ -1475,6 +1495,21 @@ extio8x4_axis_initiator u_extio8x4_axis_initiator
.BOOTROM_0_HMASTLOCK(BOOTROM_0_HMASTLOCK),
.BOOTROM_0_HREADYMUX(BOOTROM_0_HREADY),
+ // EXTROM 0 Region Slave Port
+ .EXTROM_0_HRDATA(EXTROM_0_HRDATA),
+ .EXTROM_0_HREADYOUT(EXTROM_0_HREADYOUT),
+ .EXTROM_0_HRESP(EXTROM_0_HRESP),
+ .EXTROM_0_HSEL(EXTROM_0_HSEL),
+ .EXTROM_0_HADDR(EXTROM_0_HADDR),
+ .EXTROM_0_HTRANS(EXTROM_0_HTRANS),
+ .EXTROM_0_HWRITE(EXTROM_0_HWRITE),
+ .EXTROM_0_HSIZE(EXTROM_0_HSIZE),
+ .EXTROM_0_HBURST(EXTROM_0_HBURST),
+ .EXTROM_0_HPROT(EXTROM_0_HPROT),
+ .EXTROM_0_HWDATA(EXTROM_0_HWDATA),
+ .EXTROM_0_HMASTLOCK(EXTROM_0_HMASTLOCK),
+ .EXTROM_0_HREADYMUX(EXTROM_0_HREADY),
+
// CPU 0 Instruction Memory Region Slave Port
.IMEM_0_HRDATA(IMEM_0_HRDATA),
.IMEM_0_HREADYOUT(IMEM_0_HREADYOUT),