From c70d82104fca9eb7236d5e9d559fda952fba1939 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Tue, 21 Nov 2023 13:45:25 +0000
Subject: [PATCH] update QS testbench to fix binary code uploads
---
verif/tb/verilog/nanosoc_tb_qs.v | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index abaffd3..a32dd26 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -360,15 +360,15 @@ nanosoc_ft1248x1_track
`endif
`ifndef COCOTB_SIM
- nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_ip.log"))
- u_nanosoc_uart_capture2(
- .RESETn (NRST),
- .CLK (ft_clk2uart),
- .RXD (ft_txd2uart),
- .DEBUG_TESTER_ENABLE ( ),
- .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
- .AUXCTRL ()
- );
+// nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_ip.log"))
+// u_nanosoc_uart_capture2(
+// .RESETn (NRST),
+// .CLK (ft_clk2uart),
+// .RXD (ft_txd2uart),
+// .DEBUG_TESTER_ENABLE ( ),
+// .SIMULATIONEND (), // This signal set to 1 at the end of simulation.
+// .AUXCTRL ()
+// );
`endif
// --------------------------------------------------------------------------------
--
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