diff --git a/fpga/makefile b/fpga/makefile
index f0eb71999fa1547ae7ee28370642b0c6c4de1d43..62ea7d8060c419ebb7625921019b44dca8cad641 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -89,7 +89,7 @@ defs_nanosoc:
 flist_nanosoc: defs_nanosoc
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR) -d $(NANOSOC_DEFINES);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
 
 # Package NanoSoC Socket Components
 package_socket:
diff --git a/makefile b/makefile
index 856f9e02a633d622384284fdde296750aa718194..bd508e2e9fdc30cb4bfc20165035673900c3e37f 100644
--- a/makefile
+++ b/makefile
@@ -95,7 +95,7 @@ ifeq ($(ACCELERATOR),yes)
 	NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
 endif
 
-NANOSOC_DEFINES += IMEM_0_ROM
+NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 
 # Is the Arm QuickStart being used?
 QUICKSTART ?= no
diff --git a/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v b/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
index 72298185fc8fced1b3d969e5923eaa75c0b52d99..245ba1fc4ae1ba8fe1b43ba848638fe7b07932d5 100644
--- a/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+++ b/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
@@ -36,7 +36,7 @@ module nanosoc_region_imem_0 #(
   output wire  [SYS_DATA_W-1:0] HRDATA
 );
 
-`ifdef IMEM_0_ROM
+`ifdef IMEM_0_RAM_PRELOAD
   // ROM Instantiation
   sl_ahb_rom #(
     .SYS_DATA_W (SYS_DATA_W),
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index e3c85ab6c67113ad8547a129cac01dae494c4c15..04639f9ccf3717e38e741dadd5027453f6856a37 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit e3c85ab6c67113ad8547a129cac01dae494c4c15
+Subproject commit 04639f9ccf3717e38e741dadd5027453f6856a37