diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v index 58972ffb2a7d1d04e303d8f90c9b4f67b676f670..4d9fa6a6ddf6df7bc54060c88090ddac16e3a459 100644 --- a/system/src/verilog/nanosoc_chip.v +++ b/system/src/verilog/nanosoc_chip.v @@ -875,47 +875,8 @@ nanosoc_exp #(.ADDRWIDTH(29) .HRESP (HRESP_exp) ); assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data - -`endif -// soclabs_ahb_aes128_ctrl u_exp_aes128 ( -// .ahb_hclk (HCLK), -// .ahb_hresetn (HRESETn), -// .ahb_hsel (HSEL_exp), -// .ahb_haddr16 (HADDR_exp[15:0]), -// .ahb_htrans (HTRANS_exp), -// .ahb_hwrite (HWRITE_exp), -// .ahb_hsize (HSIZE_exp), -// // .ahb_hburst (HBURST_exp), -// .ahb_hprot (HPROT_exp), -// .ahb_hwdata (HWDATA_exp), -// // .ahb_hmastlock (HMASTLOCK_exp), -// .ahb_hready (HREADYMUX_exp), -// .ahb_hrdata (HRDATA_exp), -// .ahb_hreadyout (HREADYOUT_exp), -// .ahb_hresp (HRESP_exp), -// .drq_ipdma128 (aes128_ip_req), -// .dlast_ipdma128 (1'b0), -// .drq_opdma128 (aes128_op_req), -// .dlast_opdma128 (1'b0), -// .irq_key128 (exp_irq0), -// .irq_ip128 (exp_irq1), -// .irq_op128 (exp_irq2), -// .irq_error (exp_irq3), -// .irq_merged (aes128_irq) -// ); - -// // Default slave -// cmsdk_ahb_default_slave u_ahb_exp ( -// .HCLK (HCLK), -// .HRESETn (HRESETn), -// .HSEL (HSEL_exp), -// .HTRANS (HTRANS_exp), -// .HREADY (HREADYMUX_exp), -// .HREADYOUT (HREADYOUT_exp), -// .HRESP (HRESP_exp) -// ); -// assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data +`endif assign HRUSER_exp = 2'b00;