diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 1bb5c8a8fdc713c9ff2b238520808ad31861ab17..77721ca94327284717bc21a2db2220c2f982588c 100644
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -90,7 +90,7 @@ module nanosoc_chip #(
wire CLK;
assign xtal_clk_o = xtal_clk_out;
- wire nrst_in = nrst_i;
+ wire SYSRESETn = nrst_i;
wire [15:0] p0_in; // level-shifted input from pad
wire [15:0] p0_out; // output port drive
wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
@@ -262,7 +262,7 @@ module nanosoc_chip #(
u_nanosoc_mcu_clkctrl(
// inputs
.XTAL1 (CLK),
- .NRST (nrst_in),
+ .NRST (SYSRESETn),
.APBACTIVE (APBACTIVE),
.SLEEPING (SLEEPING),
@@ -289,16 +289,16 @@ module nanosoc_chip #(
.PRESETn (PRESETn)
);
- wire gated_hclk;
- wire gated_dclk;
- wire gated_sclk;
+ wire HCLKG;
+ wire DCLKG;
+ wire SCLKG;
cortexm0_rst_ctl u_rst_ctl
(// Inputs
- .GLOBALRESETn (nrst_in),
+ .GLOBALRESETn (SYSRESETn),
.FCLK (FCLK),
- .HCLK (gated_hclk),
- .DCLK (gated_dclk),
+ .HCLK (HCLKG),
+ .DCLK (DCLKG),
.SYSRESETREQ (NANOSOC_SYSRESETREQ),
.PMUHRESETREQ (PMUHRESETREQ),
.PMUDBGRESETREQ (PMUDBGRESETREQ),
@@ -332,9 +332,9 @@ module nanosoc_chip #(
.CGBYPASS (TESTMODE),
// Outputs
- .HCLK (gated_hclk),
- .DCLK (gated_dclk),
- .SCLK (gated_sclk),
+ .HCLK (HCLKG),
+ .DCLK (DCLKG),
+ .SCLK (SCLKG),
.WICENREQ (WICENREQ),
.CDBGPWRUPACK (CDBGPWRUPACK),
.SYSISOLATEn (SYSISOLATEn),
@@ -348,9 +348,9 @@ module nanosoc_chip #(
);
// Bypass clock gating cell in PMU if CLKGATE_PRESENT is 0
- assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_hclk;
- assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_dclk;
- assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : gated_sclk;
+ assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : HCLKG;
+ assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : DCLKG;
+ assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : SCLKG;
// In this example system, power control takes place immediately.
@@ -1370,7 +1370,7 @@ localparam AWRAM8 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
// Cortex-M0 integration level
nanosoc_cpu u_nanosoc_cpu (
- .HCLK (gated_hclk), //HCLK),
+ .HCLK (HCLKG), //HCLK),
.FCLK (FCLK),
.DCLK (DCLK),
.SCLK (SCLK),
diff --git a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
index 03416193cc212f526c5ef7b501e236d40ecc6dd5..e8d033eaee6c32a60cabd7348fab0fd40e335b6e 100644
--- a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+++ b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
@@ -21,13 +21,16 @@ module nanosoc_interconnect #(
// System Manager Parameters
parameter DMA_CHANNEL_NUM = 2
)(
- // Global Clocks and Reset
- input wire GLOBALRESETn, // Global Reset
-
- // Clocks, Gated-Clocks and Reset - AHB-lite
- input wire HCLK, // Clock
- input wire HCLKG, // Gated Clock
- input wire HRESETn, // Reset
+ // System Clocks and Resets
+ input wire FCLK, // Free-running Clock
+ input wire SYSRESETn, // System Reset
+ input wire PORESETn, // Power On Reset
+
+ // Clocks, Gated-Clocks and Reset - Generated from CPU
+ output wire HCLK, // Clock
+ output wire SCLK, // System Clock
+ output wire HCLKG, // Gated Clock
+ output wire HRESETn, // Reset
// Clocks, Gated-Clocks and Resets - APB
input wire PCLK, // Clock
@@ -39,11 +42,6 @@ module nanosoc_interconnect #(
input wire DCLKG, // Gated Clock
input wire DBGRESETn, // Reset
- // System Clocks and Resets
- input wire FCLK, // Free-running Clock
- input wire SCLK, // System Clock
- input wire PORESETn, // Power On Reset
-
// Serial Wire Debug Interface
input wire SWCLK, // SWD data input
input wire SWDI, // SWD clock
@@ -198,8 +196,8 @@ module nanosoc_interconnect #(
// Instantiate NanoSoC Bus Matrix
nanosoc_busmatrix_lite u_busmatrix (
// AHB Clock and Reset Signals
- .HCLK (HCLK),
- .HRESETn (HRESETn),
+ .HCLK (FCLK),
+ .HRESETn (SYSRESETn),
// System Address Remap Control
.REMAP ({3'b0, !ROM_REMAP}),
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
index 52512dac01d511f61eb419bdee6caf4b04a80144..da16b48a697e75323081e641a658ff9100cde74b 100644
--- a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
+++ b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
@@ -61,7 +61,7 @@ module nanosoc_manager_cortexm0 #(
output wire CCTRLRESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
// Generated Clocks and Resets
- output wire HCLK, // (HCLK master)
+ output wire HCLK, // AHB Clock
output wire SCLK, // System clock
output wire HRESETn, // AHB and System reset
output wire PORESETn, // Power on reset
@@ -106,14 +106,14 @@ module nanosoc_manager_cortexm0 #(
// Cortex-M0 Power Management and Reset Control Unit
// ---------------------------------------------------
// Cortex-M0 Control to Core Connectivity
- wire GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
- wire WAKEUP; // Wake-up Signaling from Core
- wire CDBGPWRUPREQ; // Core Debug Power Up Request
- wire CDBGPWRUPACK; // Core Debug Power Up Acknowledge
- wire WICENREQ; // WIC enable request from PMU
- wire WICENACK; // Wake-on-Interrupt Enable ACK from Core
- wire SLEEPHOLDREQn; // Core Sleep Hold Request
- wire SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
+ wire GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
+ wire WAKEUP; // Wake-up Signaling from Core
+ wire CDBGPWRUPREQ; // Core Debug Power Up Request
+ wire CDBGPWRUPACK; // Core Debug Power Up Acknowledge
+ wire WICENREQ; // WIC enable request from PMU
+ wire WICENACK; // Wake-on-Interrupt Enable ACK from Core
+ wire SLEEPHOLDREQn; // Core Sleep Hold Request
+ wire SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
// Cortex-M0 Control Instantiation
nanosoc_cortexm0_control #(
@@ -167,7 +167,7 @@ module nanosoc_manager_cortexm0 #(
.DIV_RATIO (18'd01000)
) u_stclkctrl (
.FCLK (FCLK),
- .SYSRESETn (HRESETn),
+ .SYSRESETn (SYSRESETn),
.STCLKEN (STCLKEN),
.STCALIB (STCALIB)
@@ -247,17 +247,16 @@ module nanosoc_manager_cortexm0 #(
.IRQLATENCY (8'h00),
.ECOREVNUM (28'h0),
+
// Systick
.STCLKEN (STCLKEN),
.STCALIB (STCALIB),
// Debug - JTAG or Serial wire
- // inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
- // outputs
.TDO ( ),
.nTDOEN ( ),
.SWDO (SWDO),