diff --git a/flows/makefile.asic b/flows/makefile.asic
index f53dcedb756e4a6e2ada93e169b8cf76b871f285..0731453f6d5b5d9132f64b19c9e9a9fd4dc42762 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -27,10 +27,10 @@ DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/
DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v
# Name of generated filelist by python script
-TCL_FLIST_DIR := $(IMP_NANOSOC_ASIC_DIR)/flist
-TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
-GENUS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/genus_flist.tcl
-SYNTHESIS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/synth_flist_copy.sh
+TCL_ASIC_FLIST_DIR := $(IMP_NANOSOC_ASIC_DIR)/flist
+TCL_ASIC_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/gen_flist.tcl
+GENUS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/genus_flist.tcl
+SYNTHESIS_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/synth_flist_copy.sh
# Location of outputs from synthesis
MEMORIES_DIR := $(SOCLABS_PROJECT_DIR)/memories
diff --git a/flows/makefile.regression b/flows/makefile.regression
index a40ce596be12d533f0d72afaa5aa405646cf4664..84689520c3f4062c570e7e12e6d05e323c463acc 100644
--- a/flows/makefile.regression
+++ b/flows/makefile.regression
@@ -13,7 +13,7 @@
PARALLEL_TESTS = 4
# Regression Simulation Timeout
-TIMEOUT = 20m
+TIMEOUT = 40m
# Create a Directory to Run a Regression in
$(eval REGRESSION_NAME =$(shell date +%Y_%m_%d_%H_%M_%S))
diff --git a/makefile b/makefile
index 61af86150aeb8ab914717f6c49c880964568f188..c7d38e08a9633f3a917273a95c2ac633b88355ee 100644
--- a/makefile
+++ b/makefile
@@ -77,7 +77,7 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
- NANOSOC_DEFINES += DMAC_0_PL230 POWER_PINS
+ NANOSOC_DEFINES += DMAC_DMA350 POWER_PINS
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
diff --git a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index 6f05a199a41a9b7d8309a71a7a76cf4dd38a32a1..685c9d06161ddca89264b1349b1f5bc28a3dcc3a 100644
--- a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -202,6 +202,12 @@ module nanosoc_ss_dma #(
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH)
);
+
+ // APB Tie-off signals
+ assign DMAC_0_PREADY = 1'b1;
+ assign DMAC_0_PSLVERR = 1'b1;
+ assign DMAC_0_PRDATA = 32'd0;
+
`else
`ifdef DMAC_0_PL230
// -------------------------------
diff --git a/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s b/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
index 723f4764a5e92e426e50f0ca70c19b144332def8..8a0bf63f900328b74acbc9aa01e6b78279c3ad91 100644
--- a/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
+++ b/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
@@ -41,7 +41,7 @@ __initial_sp
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
-Heap_Size EQU 0x00000100
+Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
diff --git a/software/common/validation/dma350_tests.c b/software/common/validation/dma350_tests.c
index c339c0f1f44d070a54f654d2407f2ab991b034fc..bd79e16568d09e92dea319119ba589faa1777263 100644
--- a/software/common/validation/dma350_tests.c
+++ b/software/common/validation/dma350_tests.c
@@ -1,4 +1,19 @@
+#ifdef CORTEX_M0
#include "CMSDK_CM0.h"
+#endif
+
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+
#include <stdio.h>
#include "uart_stdout.h"
#include "CMSDK_driver.h"
@@ -13,12 +28,7 @@
// Note: Please add more channels if DMA has more than 8 channels
#define CH0 0
#define CH1 1
-#define CH2 2
-#define CH3 3
-#define CH4 4
-#define CH5 5
-#define CH6 6
-#define CH7 7
+
// Note: Please modify the addresses according to the system memory map
#define COPY_ADDR_SRC 0x80000000
@@ -27,7 +37,7 @@
#define COPY_ADDR_DST_M1 0x98000000
// Note: Please modify to the desired data size
-#define DATA_SIZE 256
+#define DATA_SIZE 64
#define LARGE_DATA_SIZE 10000
#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
@@ -55,10 +65,15 @@ volatile int dma_error_irq_expected;
volatile int hardfault_occurred;
volatile int hardfault_expected;
volatile int temp_data;
+volatile int current_channel;
-
+uint8_t dma350_detect(void);
void delay(uint32_t t);
void SystemInitialization(void);
+void DMAClearChIrq(uint32_t ch);
+void DMA_Handler(void) __attribute__((interrupt));
+void initialise_destination(void);
+uint8_t check_destination(void);
int main(void) {
@@ -66,6 +81,7 @@ int main(void) {
uint32_t ch_num;
uint32_t trig_in_num;
uint32_t trig_out_num;
+ uint32_t errors = 0;
unsigned int actual_addr;
hardfault_occurred = 0;
hardfault_expected = 0;
@@ -183,23 +199,23 @@ int main(void) {
.YTYPE = OPTYPE_DISABLE
};
- // Set the transfer types (2D and wrapping support)
- // 2D transfer - not used in the testbench, only an example
- AdaWrapCommandType command_2d_wrap = {
- .FILLVAL = 0,
- .XTYPE = OPTYPE_CONTINUE,
- .YTYPE = OPTYPE_CONTINUE
- };
-
- // Set the 2D transfer parameters
- // 32 words * 16 lines -> 32 words * 16 lines
- // It is not used in the testbench, only an example
- Ada2DCommandType command_2d = {
- .SRCYSIZE = 16,
- .DESYSIZE = 16,
- .SRCYADDRSTRIDE = 64,
- .DESYADDRSTRIDE = 64
- };
+ // // Set the transfer types (2D and wrapping support)
+ // // 2D transfer - not used in the testbench, only an example
+ // AdaWrapCommandType command_2d_wrap = {
+ // .FILLVAL = 0,
+ // .XTYPE = OPTYPE_CONTINUE,
+ // .YTYPE = OPTYPE_CONTINUE
+ // };
+
+ // // Set the 2D transfer parameters
+ // // 32 words * 16 lines -> 32 words * 16 lines
+ // // It is not used in the testbench, only an example
+ // Ada2DCommandType command_2d = {
+ // .SRCYSIZE = 16,
+ // .DESYSIZE = 16,
+ // .SRCYADDRSTRIDE = 64,
+ // .DESYADDRSTRIDE = 64
+ // };
// Enable/disable the interupts of the channel
// Error and done interrupts are enabled
@@ -246,8 +262,13 @@ int main(void) {
.STREAMTYPE = OUT_ONLY
} ;
+
+ if(dma350_detect()!=0){
+ return 0;
+ }
+
//Initialize TCM
- printf("Initialize SRAM: \n");
+ printf("Initialize SRAM... ");
actual_addr = command_base.SRCADDR;
unsigned int test_data[command_base.SRCXSIZE];
int j;
@@ -257,25 +278,7 @@ int main(void) {
//printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
actual_addr = actual_addr+4;
}
- for(j = 0; j < 64; j++){
- test_data[j] = j;
- address_test_write(actual_addr,test_data[j]);
- //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
- actual_addr = actual_addr+4;
- }
- for(j = 0; j < 64; j++){
- test_data[j] = j;
- address_test_write(actual_addr,test_data[j]);
- //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
- actual_addr = actual_addr+4;
- }
- for(j = 0; j < 64; j++){
- test_data[j] = j;
- address_test_write(actual_addr,test_data[j]);
- //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
- actual_addr = actual_addr+4;
- }
-
+ printf("done\n");
//Get the configuration information
@@ -287,43 +290,64 @@ int main(void) {
printf("Number of DMA channels: %d \n", ch_num);
printf("Number of DMA trigger inputs: %d \n", trig_in_num);
printf("Number of DMA trigger outputs: %d \n", trig_out_num);
- __disable_irq();
- printf("---STARTING 1D Command Tests No interrupts---\n");
- // **********************************************************************************************
- // Stage #1: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
- // Simple 1D command with no interrupts
- // **********************************************************************************************
+
+ printf("---STARTING 1D Command Tests With interrupts---\n");
+ __enable_irq();
printf("Test BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
+ current_channel=ch;
//
// Write all settings to the DMA registers
AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
- //AdaSetIntEn(ch_irqs, ch, SECURE);
+ AdaSetIntEn(ch_irqs, ch, SECURE);
- printf("DMA %d configured. Starting the transfer.\n", ch);
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+
+ printf("DMA %d configured. Starting the transfer.\n", ch);
+
+
// Start DMA operation and wait for done IRQ
AdaEnable(ch, SECURE);
-
+ __WFI();
+ printf("Return from interrupt\n");
uint8_t ch_enabled = 1;
while (ch_enabled == 1) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
+
+ //AdaClearChDone(ch, SECURE);
printf("DMA transfer finished\n");
+
+ if (check_destination()!=0){
+ errors++;
+ }
+ else{
+ printf("Passed\n");
+ }
+
+ initialise_destination();
}
+ NVIC_DisableIRQ(DMA_IRQn);
+ __disable_irq();
+ printf("---STARTING 1D Command Tests No interrupts---\n");
// **********************************************************************************************
- // Stage #2: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
+ // Stage #1: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
// Simple 1D command with no interrupts
// **********************************************************************************************
- printf("Test NO BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
+ printf("Test BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
- AdaChannelInit(ch_settings_no_burst, ch_srcattr, ch_desattr, ch, SECURE);
+ AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
@@ -338,20 +362,30 @@ int main(void) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
+
+ if (check_destination()!=0){
+ errors++;
+ }
+ else{
+ printf("Passed\n");
+ }
+
+ initialise_destination();
}
- printf("Test Stream interface with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
+ // **********************************************************************************************
+ // Stage #2: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
+ // Simple 1D command with no interrupts
+ // **********************************************************************************************
+ printf("Test NO BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
- AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
- Ada1DIncrCommand(str_command_base, command_1d_incr, ch, SECURE);
+ AdaChannelInit(ch_settings_no_burst, ch_srcattr, ch_desattr, ch, SECURE);
+ Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
- AdaStreamInit(command_stream, ch, SECURE);
- AdaStreamEnable(1, ch, SECURE);
-
printf("DMA %d configured. Starting the transfer.\n", ch);
// Start DMA operation and wait for done IRQ
@@ -362,7 +396,17 @@ int main(void) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
+
+ if (check_destination()!=0){
+ errors++;
+ }
+ else{
+ printf("Passed\n");
+ }
+
+ initialise_destination();
}
+
printf("Test NO BURST with 1D basic commands using M1 interface...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
@@ -382,6 +426,15 @@ int main(void) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
+
+ if (check_destination()!=0){
+ errors++;
+ }
+ else{
+ printf("Passed\n");
+ }
+
+ initialise_destination();
}
printf("Test Software Trigger interface\n");
@@ -421,44 +474,22 @@ int main(void) {
}
printf("DMA transfer finished\n");
- }
-
- printf("---STARTING 1D Command Tests With interrupts---\n");
- __enable_irq();
- printf("Test BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
- for (uint32_t ch=0; ch < ch_num; ch++) {
- //
- // Write all settings to the DMA registers
- AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
- Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
- SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
- AdaSetIntEn(ch_irqs, ch, SECURE);
-
-
- dma_done_irq_expected = 1;
- dma_done_irq_occurred = 0;
- NVIC_ClearPendingIRQ(DMA_IRQn);
- NVIC_EnableIRQ(DMA_IRQn);
-
-
- printf("DMA %d configured. Starting the transfer.\n", ch);
-
- // Start DMA operation and wait for done IRQ
- AdaEnable(ch, SECURE);
- printf("debug\n");
- while (dma_done_irq_occurred==0){
- __WFE();
+ if (check_destination()!=0){
+ errors++;
}
- printf("DMA Interrupt Handled\n");
- uint8_t ch_enabled = 1;
- while (ch_enabled == 1) {
- ch_enabled = AdaGetEnable(ch, SECURE);
+ else{
+ printf("Passed\n");
}
- printf("DMA transfer finished\n");
- }
- NVIC_DisableIRQ(DMA_IRQn);
+ initialise_destination();
+ }
+
+ if(errors!=0){
+ printf("\n** TEST FAILED **, Error code = (0x%x)\n",errors);
+ } else {
+ printf ("\n** TEST PASSED **\n");
+ }
UartEndSimulation();
return 0;
@@ -475,6 +506,51 @@ void SystemInitialization(void){
puts("\nCortex Microcontroller System Design Kit - DMA Test - revision $Revision: 371321 $\n");
}
+uint8_t dma350_detect(void)
+{
+ uint8_t result;
+ int volatile rdata;
+ unsigned const int dma350_iidr = 0x3a00043b;
+ puts("Detect if DMA350 controller is present...");
+ hardfault_occurred = 0;
+ hardfault_expected = 1;
+ rdata = address_test_read(ADA_DMA_S_BASE+0xFC8);
+ hardfault_expected = 0;
+ result = hardfault_occurred ? 1 : (rdata!=dma350_iidr);
+ if (result!=0) {
+ puts("** TEST SKIPPED ** DMA controller is not present.\n");
+ UartEndSimulation();
+ }
+ return(result);
+}
+
+void initialise_destination(void)
+{
+ unsigned int actual_addr = COPY_ADDR_DST;
+ int j;
+ for(j = 0; j < 64; j++){
+ address_test_write(actual_addr,0);
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+}
+
+uint8_t check_destination(void)
+{
+ uint32_t mismatches=0;
+ uint32_t value;
+ unsigned int actual_addr = COPY_ADDR_DST;
+ int j;
+ for(j = 0; j < 64; j++){
+ if (address_test_read(actual_addr)!=j)
+ {
+ mismatches++;
+ }
+ //printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
+ actual_addr = actual_addr+4;
+ }
+ return mismatches;
+}
#if defined ( __CC_ARM )
/* Test function for write - for ARM / Keil */
@@ -537,13 +613,12 @@ void DMAClearChIrq(uint32_t ch) {
}
}
-void DMA_Handler(void){
+void DMA_Handler(void){
__disable_irq();
- printf("DMA Interrupted \n");
+ DMAClearChIrq(current_channel);
dma_done_irq_occurred++;
- DMAClearChIrq(0);
- DMAClearChIrq(1);
__enable_irq();
+ return;
}
#if defined ( __CC_ARM )
@@ -581,10 +656,10 @@ void HardFault_Handler(void)
" ldr r1,=HardFault_Handler_c \n"
" bx r1\n"
".pool\n" );
-}
+}}
#endif
-
+/* C part of the fault handler - common between ARM / Keil /gcc */
void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
{
unsigned int stacked_pc;
diff --git a/software/drivers/dma_350_regdef.h b/software/drivers/dma_350_regdef.h
index 4d837f20c24a94800b80a9ace9ffdbd3af1aa533..4124a19a622fd2e22bc0134ff10b89f179ebc2cc 100755
--- a/software/drivers/dma_350_regdef.h
+++ b/software/drivers/dma_350_regdef.h
@@ -164,12 +164,12 @@ typedef struct
#define DMAINFO_S_BASE (ADA_DMA_S_BASE + 0x0F00UL)
#define DMACH0_S_BASE (ADA_DMA_S_BASE + 0x1000UL)
#define DMACH1_S_BASE (ADA_DMA_S_BASE + 0x1100UL)
-#define DMACH2_S_BASE (ADA_DMA_S_BASE + 0x1200UL)
-#define DMACH3_S_BASE (ADA_DMA_S_BASE + 0x1300UL)
-#define DMACH4_S_BASE (ADA_DMA_S_BASE + 0x1400UL)
-#define DMACH5_S_BASE (ADA_DMA_S_BASE + 0x1500UL)
-#define DMACH6_S_BASE (ADA_DMA_S_BASE + 0x1600UL)
-#define DMACH7_S_BASE (ADA_DMA_S_BASE + 0x1700UL)
+// #define DMACH2_S_BASE (ADA_DMA_S_BASE + 0x1200UL)
+// #define DMACH3_S_BASE (ADA_DMA_S_BASE + 0x1300UL)
+// #define DMACH4_S_BASE (ADA_DMA_S_BASE + 0x1400UL)
+// #define DMACH5_S_BASE (ADA_DMA_S_BASE + 0x1500UL)
+// #define DMACH6_S_BASE (ADA_DMA_S_BASE + 0x1600UL)
+// #define DMACH7_S_BASE (ADA_DMA_S_BASE + 0x1700UL)
#ifndef ADA_DMA_NS_BASE
#define ADA_DMA_NS_BASE 0x4000C000UL
@@ -181,12 +181,12 @@ typedef struct
#define DMAINFO_NS_BASE (ADA_DMA_NS_BASE + 0x0F00UL)
#define DMACH0_NS_BASE (ADA_DMA_NS_BASE + 0x1000UL)
#define DMACH1_NS_BASE (ADA_DMA_NS_BASE + 0x1100UL)
-#define DMACH2_NS_BASE (ADA_DMA_NS_BASE + 0x1200UL)
-#define DMACH3_NS_BASE (ADA_DMA_NS_BASE + 0x1300UL)
-#define DMACH4_NS_BASE (ADA_DMA_NS_BASE + 0x1400UL)
-#define DMACH5_NS_BASE (ADA_DMA_NS_BASE + 0x1500UL)
-#define DMACH6_NS_BASE (ADA_DMA_NS_BASE + 0x1600UL)
-#define DMACH7_NS_BASE (ADA_DMA_NS_BASE + 0x1700UL)
+// #define DMACH2_NS_BASE (ADA_DMA_NS_BASE + 0x1200UL)
+// #define DMACH3_NS_BASE (ADA_DMA_NS_BASE + 0x1300UL)
+// #define DMACH4_NS_BASE (ADA_DMA_NS_BASE + 0x1400UL)
+// #define DMACH5_NS_BASE (ADA_DMA_NS_BASE + 0x1500UL)
+// #define DMACH6_NS_BASE (ADA_DMA_NS_BASE + 0x1600UL)
+// #define DMACH7_NS_BASE (ADA_DMA_NS_BASE + 0x1700UL)
/******************************************************************************/
/* ADA_DMA register block declaration */
@@ -197,12 +197,12 @@ typedef struct
#define DMAINFO_S ((DMAINFO_TypeDef *) DMAINFO_S_BASE)
#define DMACH0_S ((DMACH_TypeDef *) DMACH0_S_BASE)
#define DMACH1_S ((DMACH_TypeDef *) DMACH1_S_BASE)
-#define DMACH2_S ((DMACH_TypeDef *) DMACH2_S_BASE)
-#define DMACH3_S ((DMACH_TypeDef *) DMACH3_S_BASE)
-#define DMACH4_S ((DMACH_TypeDef *) DMACH4_S_BASE)
-#define DMACH5_S ((DMACH_TypeDef *) DMACH5_S_BASE)
-#define DMACH6_S ((DMACH_TypeDef *) DMACH6_S_BASE)
-#define DMACH7_S ((DMACH_TypeDef *) DMACH7_S_BASE)
+// #define DMACH2_S ((DMACH_TypeDef *) DMACH2_S_BASE)
+// #define DMACH3_S ((DMACH_TypeDef *) DMACH3_S_BASE)
+// #define DMACH4_S ((DMACH_TypeDef *) DMACH4_S_BASE)
+// #define DMACH5_S ((DMACH_TypeDef *) DMACH5_S_BASE)
+// #define DMACH6_S ((DMACH_TypeDef *) DMACH6_S_BASE)
+// #define DMACH7_S ((DMACH_TypeDef *) DMACH7_S_BASE)
#define DMASECCFG_NS ((DMASECCFG_TypeDef *) DMASECCFG_NS_BASE)
#define DMASECCTRL_NS ((DMASECCTRL_TypeDef *) DMASECCTRL_NS_BASE)
@@ -210,12 +210,12 @@ typedef struct
#define DMAINFO_NS ((DMAINFO_TypeDef *) DMAINFO_NS_BASE)
#define DMACH0_NS ((DMACH_TypeDef *) DMACH0_NS_BASE)
#define DMACH1_NS ((DMACH_TypeDef *) DMACH1_NS_BASE)
-#define DMACH2_NS ((DMACH_TypeDef *) DMACH2_NS_BASE)
-#define DMACH3_NS ((DMACH_TypeDef *) DMACH3_NS_BASE)
-#define DMACH4_NS ((DMACH_TypeDef *) DMACH4_NS_BASE)
-#define DMACH5_NS ((DMACH_TypeDef *) DMACH5_NS_BASE)
-#define DMACH6_NS ((DMACH_TypeDef *) DMACH6_NS_BASE)
-#define DMACH7_NS ((DMACH_TypeDef *) DMACH7_NS_BASE)
+// #define DMACH2_NS ((DMACH_TypeDef *) DMACH2_NS_BASE)
+// #define DMACH3_NS ((DMACH_TypeDef *) DMACH3_NS_BASE)
+// #define DMACH4_NS ((DMACH_TypeDef *) DMACH4_NS_BASE)
+// #define DMACH5_NS ((DMACH_TypeDef *) DMACH5_NS_BASE)
+// #define DMACH6_NS ((DMACH_TypeDef *) DMACH6_NS_BASE)
+// #define DMACH7_NS ((DMACH_TypeDef *) DMACH7_NS_BASE)
/******************************************************************************/
/* Field Definitions of Registers */
diff --git a/testcodes/dma350_tests/makefile b/testcodes/dma350_tests/makefile
index 1e9cebbaa540270011f35ffbcedbfb07d81c8769..e12935a66438e43a5c15df4d4806ff271572aecb 100644
--- a/testcodes/dma350_tests/makefile
+++ b/testcodes/dma350_tests/makefile
@@ -29,7 +29,7 @@
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
-CPU_PRODUCT = CORTEX_M0
+CPU_PRODUCT = CORTEX_M0PLUS
# Shared software directory
SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
@@ -108,11 +108,13 @@ COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
-ARM_CC_OPTIONS = -c --c99 -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
+ARM_CC_OPTIONS = -c --c99 -O3 -g -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
-I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
-ARM_ASM_OPTIONS =
+ARM_CC_OPTIONS_DRIVER = -c --c99 -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
+ARM_ASM_OPTIONS = -g
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
- --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+ --rw_base 0x30000000 --ro_base 0x00000000 --map
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
@@ -161,7 +163,7 @@ $(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(GENERIC_FILE)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
dma_350_driver.o : $(SOFTWARE_DIR)/drivers/dma_350_command_lib.c $(DEPS_LIST)
- armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+ armcc $(ARM_CC_OPTIONS_DRIVER) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
@@ -182,17 +184,18 @@ $(TESTNAME).hex : $(TESTNAME).ELF
fromelf --vhx --8x1 $< --output $@
$(TESTNAME).lst : $(TESTNAME).ELF
- fromelf -c -d -e -s -z -v $< --output $@
+ fromelf -c -d -e -s $< --output $@
# ---------------------------------------------------------------------------------------
# gcc
all_gcc:
$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
- $(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
$(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/drivers/dma_350_command_lib.c \
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
- -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR)\
-I $(SOFTWARE_DIR)/common/retarget \
-I $(SOFTWARE_DIR)/drivers \
-L $(LINKER_SCRIPT_PATH) \
diff --git a/testcodes/software_list.txt b/testcodes/software_list.txt
index 52260e2e034dbf570c0a068062e02f9c50f29c10..2cf00c1f2a96d55025c33f179002d0113356081a 100644
--- a/testcodes/software_list.txt
+++ b/testcodes/software_list.txt
@@ -10,6 +10,7 @@ timer_tests
debug_tests
default_slaves_tests
dma_tests
+dma350_tests
gpio_driver_tests
timer_driver_tests
apb_mux_tests