From b36f7041c7c96e7af7ed10647a667ee319f440ce Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 5 Jul 2023 21:35:59 +0100
Subject: [PATCH] Move ADP drivers to ci_tools
---
.../ci_tools}/ADP_test.py | 0
.../ci_tools}/bootrom_test.py | 0
.../ci_tools}/drivers/ADP_UART_driver.py | 0
.../ci_tools}/drivers/NanoSoC_Verification.py | 0
.../ci_tools}/romtable_test.py | 0
fpga/ci_tools/run_full_verification.py | 19 +
.../ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl | 86 -
.../uart_to_AXI_master_1.0/component.xml | 1707 -----------------
.../example_designs/bfm_design/design.tcl | 94 -
.../bfm_design/uart_to_AXI_master_v1_0_tb.sv | 94 -
.../debug_hw_design/design.tcl | 179 --
.../uart_to_AXI_master_v1_0_hw_test.tcl | 87 -
.../hdl/uart_to_AXI_master_v1_0.v | 125 --
.../hdl/uart_to_AXI_master_v1_0_M00_AXI.v | 907 ---------
.../uart_to_AXI_master_1.0/src/dbg_bridge.v | 623 ------
.../src/dbg_bridge_fifo.v | 118 --
.../src/dbg_bridge_uart.v | 341 ----
.../xgui/uart_to_AXI_master_v1_0.tcl | 190 --
18 files changed, 19 insertions(+), 4551 deletions(-)
rename {system/fpga_imp/python_verification => fpga/ci_tools}/ADP_test.py (100%)
rename {system/fpga_imp/python_verification => fpga/ci_tools}/bootrom_test.py (100%)
rename {system/fpga_imp/python_verification => fpga/ci_tools}/drivers/ADP_UART_driver.py (100%)
rename {system/fpga_imp/python_verification => fpga/ci_tools}/drivers/NanoSoC_Verification.py (100%)
rename {system/fpga_imp/python_verification => fpga/ci_tools}/romtable_test.py (100%)
create mode 100644 fpga/ci_tools/run_full_verification.py
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/design.tcl
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/uart_to_AXI_master_v1_0_tb.sv
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/design.tcl
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/uart_to_AXI_master_v1_0_hw_test.tcl
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
delete mode 100644 system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
diff --git a/system/fpga_imp/python_verification/ADP_test.py b/fpga/ci_tools/ADP_test.py
similarity index 100%
rename from system/fpga_imp/python_verification/ADP_test.py
rename to fpga/ci_tools/ADP_test.py
diff --git a/system/fpga_imp/python_verification/bootrom_test.py b/fpga/ci_tools/bootrom_test.py
similarity index 100%
rename from system/fpga_imp/python_verification/bootrom_test.py
rename to fpga/ci_tools/bootrom_test.py
diff --git a/system/fpga_imp/python_verification/drivers/ADP_UART_driver.py b/fpga/ci_tools/drivers/ADP_UART_driver.py
similarity index 100%
rename from system/fpga_imp/python_verification/drivers/ADP_UART_driver.py
rename to fpga/ci_tools/drivers/ADP_UART_driver.py
diff --git a/system/fpga_imp/python_verification/drivers/NanoSoC_Verification.py b/fpga/ci_tools/drivers/NanoSoC_Verification.py
similarity index 100%
rename from system/fpga_imp/python_verification/drivers/NanoSoC_Verification.py
rename to fpga/ci_tools/drivers/NanoSoC_Verification.py
diff --git a/system/fpga_imp/python_verification/romtable_test.py b/fpga/ci_tools/romtable_test.py
similarity index 100%
rename from system/fpga_imp/python_verification/romtable_test.py
rename to fpga/ci_tools/romtable_test.py
diff --git a/fpga/ci_tools/run_full_verification.py b/fpga/ci_tools/run_full_verification.py
new file mode 100644
index 0000000..ad14039
--- /dev/null
+++ b/fpga/ci_tools/run_full_verification.py
@@ -0,0 +1,19 @@
+import os, warnings
+from pynq import PL
+from pynq import Overlay
+
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
+
+if not os.path.exists(PL.bitfile_name):
+ warnings.warn('There is no overlay loaded after boot.', UserWarning)
+
+ol = Overlay(PL.bitfile_name)
+
+ol.download()
+
+if ol.is_loaded():
+ print("Overlay Loaded")
+else:
+ print("Overlay failed to load")
+
+
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
deleted file mode 100644
index 4804aeb..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/bd/bd.tcl
+++ /dev/null
@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
- set full_sbusif_list [list ]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
- set busif_param_list [list]
- set busif_name [get_property NAME $busif]
- if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
- continue
- }
- foreach tparam $axi_standard_param_list {
- lappend busif_param_list "C_${busif_name}_${tparam}"
- }
- bd::mark_propagate_only $cell_handle $busif_param_list
- }
- }
-}
-
-
-proc pre_propagate {cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
- continue
- }
- if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
- continue
- }
-
- set busif_name [get_property NAME $busif]
- foreach tparam $axi_standard_param_list {
- set busif_param_name "C_${busif_name}_${tparam}"
-
- set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
- set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
-
- if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
- if { $val_on_cell != "" } {
- set_property CONFIG.${tparam} $val_on_cell $busif
- }
- }
- }
- }
-}
-
-
-proc propagate {cellpath otherInfo } {
-
- set cell_handle [get_bd_cells $cellpath]
- set all_busif [get_bd_intf_pins $cellpath/*]
- set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-
- foreach busif $all_busif {
- if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
- continue
- }
- if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
- continue
- }
-
- set busif_name [get_property NAME $busif]
- foreach tparam $axi_standard_param_list {
- set busif_param_name "C_${busif_name}_${tparam}"
-
- set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
- set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
-
- if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
- #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
- if { $val_on_cell_intf_pin != "" } {
- set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
- }
- }
- }
- }
-}
-
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
deleted file mode 100644
index 173a620..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/component.xml
+++ /dev/null
@@ -1,1707 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>user.org</spirit:vendor>
- <spirit:library>user</spirit:library>
- <spirit:name>uart_to_AXI_master</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>M00_AXI</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
- <spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="M00_AXI"/>
- </spirit:master>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awaddr</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLEN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awlen</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWSIZE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awsize</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWBURST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awburst</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLOCK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awlock</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWCACHE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awcache</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWPROT</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awprot</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWQOS</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awqos</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awuser</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_awready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WSTRB</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wstrb</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wlast</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wuser</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_wready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_bid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BRESP</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_bresp</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_buser</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_bvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_bready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_araddr</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLEN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arlen</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARSIZE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arsize</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARBURST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arburst</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLOCK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arlock</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARCACHE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arcache</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARPROT</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arprot</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARQOS</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arqos</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_aruser</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_arready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RRESP</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rresp</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rlast</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_ruser</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rvalid</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_rready</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>WIZ_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>M00_AXI_RST</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>m00_axi_aresetn</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/design.tcl b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/design.tcl
deleted file mode 100644
index 79b9f9c..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/design.tcl
+++ /dev/null
@@ -1,94 +0,0 @@
-proc create_ipi_design { offsetfile design_name } {
- create_bd_design $design_name
- open_bd_design $design_name
-
- # Create Clock and Reset Ports
- set ACLK [ create_bd_port -dir I -type clk ACLK ]
- set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
- set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
- set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
- set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
-
- # Create instance: uart_to_AXI_master_0, and set properties
- set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_to_AXI_master:1.0 uart_to_AXI_master_0]
-
- # Create External ports
- set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
- set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
- set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
-
- # Create instance: slave_0, and set properties
- set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip slave_0]
- set_property -dict [ list CONFIG.PROTOCOL {AXI4} CONFIG.INTERFACE_MODE {SLAVE} ] $slave_0
-
-connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI ] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
- # Create port connections
- connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/ACLK] [get_bd_pins uart_to_AXI_master_0/M00_AXI_ACLK]
- connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/ARESETN] [get_bd_pins uart_to_AXI_master_0/M00_AXI_ARESETN]
- connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins uart_to_AXI_master_0/M00_AXI_INIT_AXI_TXN]
- connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins uart_to_AXI_master_0/M00_AXI_ERROR]
- connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins uart_to_AXI_master_0/M00_AXI_TXN_DONE]
-set_property target_simulator XSim [current_project]
-set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
-
- # Auto assign address
- assign_bd_address
-
- # Copy all address to interface_address.vh file
- set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
- upvar 1 $offsetfile offset_file
- set offset_file "${bd_path}/uart_to_AXI_master_v1_0_tb_include.svh"
- set fp [open $offset_file "w"]
- puts $fp "`ifndef uart_to_AXI_master_v1_0_tb_include_vh_"
- puts $fp "`define uart_to_AXI_master_v1_0_tb_include_vh_\n"
- puts $fp "//Configuration current bd names"
- puts $fp "`define BD_NAME ${design_name}"
- puts $fp "`define BD_INST_NAME ${design_name}_i"
- puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
- puts $fp "//Configuration address parameters"
-
- puts $fp "`endif"
- close $fp
-}
-
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:uart_to_AXI_master:1.0]]]]
-set test_bench_file ${ip_path}/example_designs/bfm_design/uart_to_AXI_master_v1_0_tb.sv
-set interface_address_vh_file ""
-
-# Set IP Repository and Update IP Catalogue
-set repo_paths [get_property ip_repo_paths [current_fileset]]
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
- set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
- update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
- set design_name "uart_to_AXI_master_v1_0_bfm_${i}"
- if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
- break
- }
-}
-
-create_ipi_design interface_address_vh_file ${design_name}
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-import_files -fileset sim_1 -norecurse -force $test_bench_file
-remove_files -quiet -fileset sim_1 uart_to_AXI_master_v1_0_tb_include.vh
-import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
-set_property top uart_to_AXI_master_v1_0_tb [get_filesets sim_1]
-set_property top_lib {} [get_filesets sim_1]
-set_property top_file {} [get_filesets sim_1]
-launch_simulation -simset sim_1 -mode behavioral
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/uart_to_AXI_master_v1_0_tb.sv b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/uart_to_AXI_master_v1_0_tb.sv
deleted file mode 100644
index 5c1652a..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/bfm_design/uart_to_AXI_master_v1_0_tb.sv
+++ /dev/null
@@ -1,94 +0,0 @@
-
-`timescale 1ns / 1ps
-`include "uart_to_AXI_master_v1_0_tb_include.svh"
-
-import axi_vip_pkg::*;
-import uart_to_AXI_master_v1_0_bfm_1_slave_0_0_pkg::*;
-
-module uart_to_AXI_master_v1_0_tb();
-
-
-xil_axi_uint error_cnt = 0;
-xil_axi_uint comparison_cnt = 0;
-axi_transaction wr_transaction;
-axi_transaction rd_transaction;
-axi_monitor_transaction mst_monitor_transaction;
-axi_monitor_transaction master_moniter_transaction_queue[$];
-xil_axi_uint master_moniter_transaction_queue_size =0;
-axi_monitor_transaction mst_scb_transaction;
-axi_monitor_transaction passthrough_monitor_transaction;
-axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
-xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
-axi_monitor_transaction passthrough_mst_scb_transaction;
-axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
-xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
-axi_monitor_transaction passthrough_slv_scb_transaction;
-axi_monitor_transaction slv_monitor_transaction;
-axi_monitor_transaction slave_moniter_transaction_queue[$];
-xil_axi_uint slave_moniter_transaction_queue_size =0;
-axi_monitor_transaction slv_scb_transaction;
-xil_axi_uint mst_agent_verbosity = 0;
-xil_axi_uint slv_agent_verbosity = 0;
-xil_axi_uint passthrough_agent_verbosity = 0;
-bit clock;
-bit reset;
-xil_axi_ulong mem_rd_addr;
-xil_axi_ulong mem_wr_addr;
-bit[32-1:0] write_data;
-bit write_strb[];
-bit[32-1:0] read_data;
-uart_to_AXI_master_v1_0_bfm_1_slave_0_0_slv_mem_t slv_agent_0;
-bit error_0;
-bit done_0;
-bit init_0;
-
- `BD_WRAPPER DUT(
- .ARESETN(reset),
-.M00_AXI_INIT_AXI_TXN(init_0),
-.M00_AXI_TXN_DONE(done_0),
-.M00_AXI_ERROR(error_0),
- .ACLK(clock)
- );
-
-initial begin
- slv_agent_0 = new("slave vip agent",DUT.`BD_INST_NAME.slave_0.inst.IF);
- slv_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
- slv_agent_0.set_agent_tag("Slave VIP");
- slv_agent_0.set_verbosity(slv_agent_verbosity);
- slv_agent_0.start_slave();
- $timeformat (-12, 1, " ps", 1);
- end
- initial begin
- reset <= 1'b0;
- #200ns;
- reset <= 1'b1;
- repeat (5) @(negedge clock);
- end
- always #5 clock <= ~clock;
- initial begin
- init_0 = 0;
- #200ns;
- init_0 =1'b1;
- #20ns;
- init_0 = 1'b0;
- $display("EXAMPLE TEST M00_AXI:");
- wait( done_0 == 1'b1);
- $display("M00_AXI: PTGEN_TEST_FINISHED!");
- if ( error_0 ) begin
- $display("PTGEN_TEST: FAILED!");
- end else begin
- $display("PTGEN_TEST: PASSED!");
- end
- #1ns;
- $finish;
- end
- initial begin
- #1;
- forever begin
- slv_agent_0.monitor.item_collected_port.get(slv_monitor_transaction);
- slave_moniter_transaction_queue.push_back(slv_monitor_transaction);
- slave_moniter_transaction_queue_size++;
- end
- end
-
-endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/design.tcl b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/design.tcl
deleted file mode 100644
index 421d952..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/design.tcl
+++ /dev/null
@@ -1,179 +0,0 @@
-
-proc create_ipi_design { offsetfile design_name } {
-
- create_bd_design $design_name
- open_bd_design $design_name
-
- # Create and configure Clock/Reset
- create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
- create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
-
- #Constraints will be provided manually while pin planning.
- create_bd_port -dir I -type rst reset_rtl
- set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
- connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
- connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
- set external_reset_port reset_rtl
- create_bd_port -dir I -type clk clock_rtl
- connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
- set external_clock_port clock_rtl
-
- #Avoid IPI DRC, make clock port synchronous to reset
- if { $external_clock_port ne "" && $external_reset_port ne "" } {
- set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
- }
-
- # Connect other sys_reset pins
- connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
-
- # Create instance: uart_to_AXI_master_0, and set properties
- set uart_to_AXI_master_0 [ create_bd_cell -type ip -vlnv user.org:user:uart_to_AXI_master:1.0 uart_to_AXI_master_0 ]
-
- # Create instance: jtag_axi_0, and set properties
- set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
- set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
- connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
- # Create instance: axi_peri_interconnect, and set properties
- set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
- connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
- set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
- connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
-
- set_property -dict [ list CONFIG.NUM_MI {3} ] $axi_peri_interconnect
- connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
- # Create instance: axi_mem_interconnect, and set properties
- set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_mem_interconnect ]
- connect_bd_net [get_bd_pins axi_mem_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_mem_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
- set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_mem_interconnect
- connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
- set_property -dict [ list CONFIG.NUM_SI {2} ] $axi_mem_interconnect
- connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_peri_interconnect/M00_AXI]
-
- # Create instance: axi_bram_ctrl_0, and set properties
- set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ]
- connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
- connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
- # Create instance: axi_bram_0, and set properties
- set axi_bram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen axi_bram_0 ]
- set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} ] $axi_bram_0
- connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_0/BRAM_PORTA]
- connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_0/BRAM_PORTB]
-
- # Create instance: axi_gpio_out, and set properties
- set axi_gpio_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_out ]
- set_property -dict [ list CONFIG.C_ALL_OUTPUTS {1} CONFIG.C_GPIO_WIDTH {1} ] $axi_gpio_out
- connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_intf_net [get_bd_intf_pins axi_gpio_out/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M01_AXI]
-
- # Create instance: axi_gpio_in, and set properties
- set axi_gpio_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_in ]
- set_property -dict [ list CONFIG.C_ALL_INPUTS {1} CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_in
- connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_intf_net [get_bd_intf_pins axi_gpio_in/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M02_AXI]
-
- # Create instance: xlconcat_0, and set properties
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_0 ]
- set_property -dict [ list CONFIG.NUM_PORTS {2} ] $xlconcat_0
- connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_gpio_in/gpio_io_i]
-
- # Connect all clock, reset & status pins of uart_to_AXI_master_0 master interfaces..
- connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins uart_to_AXI_master_0/M00_AXI]
- connect_bd_net [get_bd_pins uart_to_AXI_master_0/m00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
- connect_bd_net [get_bd_pins uart_to_AXI_master_0/m00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
- connect_bd_net [get_bd_pins uart_to_AXI_master_0/m00_axi_txn_done] [get_bd_pins xlconcat_0/In0]
- connect_bd_net [get_bd_pins uart_to_AXI_master_0/m00_axi_error] [get_bd_pins xlconcat_0/In1]
- connect_bd_net [get_bd_pins uart_to_AXI_master_0/m00_axi_init_axi_txn] [ get_bd_pins axi_gpio_out/gpio_io_o ]
-
-
- # Auto assign address
- assign_bd_address
-
- # Configure address param & range of uart_to_AXI_master_0 master interfaces..
- set_property range 16K [get_bd_addr_segs {jtag_axi_0/Data/SEG_axi_bram_ctrl_0_Mem0}]
- set_property range 16K [get_bd_addr_segs {uart_to_AXI_master_0/M00_AXI/SEG_axi_bram_ctrl_0_Mem0}]
- set_property -dict [list CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0xC0000000} ] [get_bd_cells uart_to_AXI_master_0]
-
- # Copy all address to uart_to_AXI_master_v1_0_include.tcl file
- set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
- upvar 1 $offsetfile offset_file
- set offset_file "${bd_path}/uart_to_AXI_master_v1_0_include.tcl"
- set fp [open $offset_file "w"]
- puts $fp "# Configuration address parameters"
-
- set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_in_Reg ]]
- puts $fp "set axi_gpio_in_addr ${offset}"
-
- set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_out_Reg ]]
- puts $fp "set axi_gpio_out_addr ${offset}"
-
- close $fp
-}
-
-# Set IP Repository and Update IP Catalogue
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:uart_to_AXI_master:1.0]]]]
-set hw_test_file ${ip_path}/example_designs/debug_hw_design/uart_to_AXI_master_v1_0_hw_test.tcl
-
-set repo_paths [get_property ip_repo_paths [current_fileset]]
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
- set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
- update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
- set design_name "uart_to_AXI_master_v1_0_hw_${i}"
- if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
- break
- }
-}
-
-set intf_address_include_file ""
-create_ipi_design intf_address_include_file ${design_name}
-save_bd_design
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-puts "-------------------------------------------------------------------------------------------------"
-puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
-puts " please perform following steps to test design in targeted board."
-puts "1. Generate bitstream"
-puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
-puts "3. Download generated bitstream"
-puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
-puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
-puts " : source -notrace ${hw_test_file}"
-puts "-------------------------------------------------------------------------------------------------"
-
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/uart_to_AXI_master_v1_0_hw_test.tcl b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/uart_to_AXI_master_v1_0_hw_test.tcl
deleted file mode 100644
index b3968b8..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/example_designs/debug_hw_design/uart_to_AXI_master_v1_0_hw_test.tcl
+++ /dev/null
@@ -1,87 +0,0 @@
-# Runtime Tcl commands to interact with - uart_to_AXI_master_v1_0
-
-# Sourcing design address info tcl
-set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-source ${bd_path}/uart_to_AXI_master_v1_0_include.tcl
-
-# jtag axi master interface hardware name, change as per your design.
-set jtag_axi_master hw_axi_1
-set ec 0
-
-# hw test script
-# Delete all previous axis transactions
-if { [llength [get_hw_axi_txns -quiet]] } {
- delete_hw_axi_txn [get_hw_axi_txns -quiet]
-}
-
-
-# Master Tests..
-# CIP Master performs write and read transaction followed by data comparison.
-# To initiate the master "init_axi_txn" port needs to be asserted high. The same assertion is done by axi_gpio_out driven by jtag_axi_lite master.
-# Writing 32'b1 to axi_gpio_out reg will initiate the first master. Subsequent masters will take following gpio bits.
-# Master 0 init_axi_txn is controlled by bit_0 of axi_gpio_out while bit_1 initiates Master 1.
-
-# To monitor the result of the data comparison by Master 0, error and done flags are being monitored by axi_gpio_in.
-# Reading bit 0 of gpio_1_reg gives the done status of the master transaction while bit 1 gives the error
-# status of the transaction initiated by the master. bit_0 being '1' means the transaction is complete
-# while bit_1 being 1 means the transaction is completed with error. The status of subsequent masters
-# will take up higher order bits in the same order. Master 1 has bit_2 as done bit, bit_3 as error bit.
-
-# Utility procs
-proc get_done_and_error_bit { rdata totmaster position } {
- # position can be 0 1 2 3 ...
- # Always Done is at sequence of bit 0 & error is at bit 1 position.
- set hexdata [string range $rdata 0 7 ]
- # In case of 64 bit data width
- #set hexdata [string range $rdata 8 15 ]
- binary scan [binary format H* $hexdata] B* bindata
- set bindata [string range $bindata [expr 32 - $totmaster * 2] 31 ]
- set DE [string range $bindata [ expr ($totmaster - ($position + 1) ) * 2 ] [expr ($totmaster - ($position + 1) ) * 2 + 1] ]
- return $DE
-}
-
-proc bin2hex {bin} {
- set result ""
- set prepend [string repeat 0 [expr (4-[string length $bin]%4)%4]]
- foreach g [regexp -all -inline {[01]{4}} $prepend$bin] {
- foreach {b3 b2 b1 b0} [split $g ""] {
- append result [format %X [expr {$b3*8+$b2*4+$b1*2+$b0}]]
- }
- }
- return $result
-}
-
-proc get_init_data { position } {
- # position can be 0, 1, 2, 3, 4...15
- set initbit 00000000000000000000000000000000
- set position [ expr 31 - $position ]
- set newinitbit [string replace $initbit $position $position 1]
- set hexdata [bin2hex $newinitbit]
- return $hexdata
-}
-
-# Test: M00_AXI
-set wdata_m00_axi [get_init_data 0]
-create_hw_axi_txn w_m00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $axi_gpio_out_addr -data ${wdata_m00_axi}
-create_hw_axi_txn r_m00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $axi_gpio_in_addr
-# Initiate transactions
-run_hw_axi r_m00_axi_addr
-run_hw_axi w_m00_axi_addr
-run_hw_axi r_m00_axi_addr
-set rdata_tmp [get_property DATA [get_hw_axi_txn r_m00_axi_addr]]
-set DE [ get_done_and_error_bit $rdata_tmp 1 0 ]
-# Compare read data
-if { $DE == 01 } {
- puts "Data comparison test pass for - M00_AXI"
-} else {
- puts "Data comparison test fail for - M00_AXI, rdata-$rdata_tmp expected-01 actual-$DE"
- inc ec
-}
-
-# Check error flag
-if { $ec == 0 } {
- puts "PTGEN_TEST: PASSED!"
-} else {
- puts "PTGEN_TEST: FAILED!"
-}
-
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
deleted file mode 100644
index 8baf1d3..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0.v
+++ /dev/null
@@ -1,125 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module uart_to_AXI_master_v1_0 #
- (
- // Users to add parameters here
- parameter integer CLK_SPEED = 10000000,
- parameter integer UART_BAUD_RATE = 115200,
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
-
- // Parameters of Axi Master Bus Interface M00_AXI
- parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
- parameter integer C_M00_AXI_BURST_LEN = 16,
- parameter integer C_M00_AXI_ID_WIDTH = 4,
- parameter integer C_M00_AXI_ADDR_WIDTH = 32,
- parameter integer C_M00_AXI_DATA_WIDTH = 32,
- parameter integer C_M00_AXI_AWUSER_WIDTH = 4,
- parameter integer C_M00_AXI_ARUSER_WIDTH = 4,
- parameter integer C_M00_AXI_WUSER_WIDTH = 4,
- parameter integer C_M00_AXI_RUSER_WIDTH = 4,
- parameter integer C_M00_AXI_BUSER_WIDTH = 4
- )
- (
- // Users to add ports her
- // User ports ends
- // Do not modify the ports beyond this line
-
-
- // Ports of Axi Master Bus Interface M00_AXI
- input wire UART_RX,
- output wire UART_TX,
- input wire m00_axi_aclk,
- input wire m00_axi_aresetn,
- output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
- output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
- output wire [7 : 0] m00_axi_awlen,
- output wire [2 : 0] m00_axi_awsize,
- output wire [1 : 0] m00_axi_awburst,
- output wire m00_axi_awlock,
- output wire [3 : 0] m00_axi_awcache,
- output wire [2 : 0] m00_axi_awprot,
- output wire [3 : 0] m00_axi_awqos,
- output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
- output wire m00_axi_awvalid,
- input wire m00_axi_awready,
- output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
- output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
- output wire m00_axi_wlast,
- output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
- output wire m00_axi_wvalid,
- input wire m00_axi_wready,
- input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
- input wire [1 : 0] m00_axi_bresp,
- input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
- input wire m00_axi_bvalid,
- output wire m00_axi_bready,
- output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
- output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
- output wire [7 : 0] m00_axi_arlen,
- output wire [2 : 0] m00_axi_arsize,
- output wire [1 : 0] m00_axi_arburst,
- output wire m00_axi_arlock,
- output wire [3 : 0] m00_axi_arcache,
- output wire [2 : 0] m00_axi_arprot,
- output wire [3 : 0] m00_axi_arqos,
- output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
- output wire m00_axi_arvalid,
- input wire m00_axi_arready,
- input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
- input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
- input wire [1 : 0] m00_axi_rresp,
- input wire m00_axi_rlast,
- input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
- input wire m00_axi_rvalid,
- output wire m00_axi_rready
- );
-// Instantiation of Axi Bus Interface M00_AXI
-
- // Add user logic here
- dbg_bridge #(.CLK_FREQ(CLK_SPEED),
- .UART_SPEED(UART_BAUD_RATE),
- .AXI_ID(4'd0),
- .GPIO_ADDRESS(32'hf0000000),
- .STS_ADDRESS(32'hf0000004))
- dbg_bridge_inst (
- .clk_i (m00_axi_aclk),
- .rst_i (~m00_axi_aresetn),
- .uart_rxd_i (UART_RX),
- .uart_txd_o (UART_TX),
- .gpio_inputs_i (),
- .gpio_outputs_o (),
- .mem_awready_i (m00_axi_awready),
- .mem_wready_i (m00_axi_wready),
- .mem_bvalid_i (m00_axi_bvalid),
- .mem_bresp_i (m00_axi_bresp),
- .mem_bid_i (m00_axi_bid),
- .mem_arready_i (m00_axi_arready),
- .mem_rvalid_i (m00_axi_rvalid),
- .mem_rdata_i (m00_axi_rdata),
- .mem_rresp_i (m00_axi_rresp),
- .mem_rid_i (m00_axi_rid),
- .mem_rlast_i (m00_axi_rlast),
- .mem_awvalid_o (m00_axi_awvalid),
- .mem_awaddr_o (m00_axi_awaddr),
- .mem_awid_o (m00_axi_awid),
- .mem_awlen_o (m00_axi_awlen),
- .mem_awburst_o (m00_axi_awburst),
- .mem_wvalid_o (m00_axi_wvalid),
- .mem_wdata_o (m00_axi_wdata),
- .mem_wstrb_o (m00_axi_wstrb),
- .mem_wlast_o (m00_axi_wlast),
- .mem_bready_o (m00_axi_bready),
- .mem_arvalid_o (m00_axi_arvalid),
- .mem_araddr_o (m00_axi_araddr),
- .mem_arid_o (m00_axi_arid),
- .mem_arlen_o (m00_axi_arlen),
- .mem_arburst_o (m00_axi_arburst),
- .mem_rready_o (m00_axi_rready)
- );
- // User logic ends
-
- endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
deleted file mode 100644
index ac7d455..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/hdl/uart_to_AXI_master_v1_0_M00_AXI.v
+++ /dev/null
@@ -1,907 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
- module uart_to_AXI_master_v1_0_M00_AXI #
- (
- // Users to add parameters here
-
- // User parameters ends
- // Do not modify the parameters beyond this line
-
- // Base address of targeted slave
- parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
- // Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
- parameter integer C_M_AXI_BURST_LEN = 16,
- // Thread ID Width
- parameter integer C_M_AXI_ID_WIDTH = 1,
- // Width of Address Bus
- parameter integer C_M_AXI_ADDR_WIDTH = 32,
- // Width of Data Bus
- parameter integer C_M_AXI_DATA_WIDTH = 32,
- // Width of User Write Address Bus
- parameter integer C_M_AXI_AWUSER_WIDTH = 0,
- // Width of User Read Address Bus
- parameter integer C_M_AXI_ARUSER_WIDTH = 0,
- // Width of User Write Data Bus
- parameter integer C_M_AXI_WUSER_WIDTH = 0,
- // Width of User Read Data Bus
- parameter integer C_M_AXI_RUSER_WIDTH = 0,
- // Width of User Response Bus
- parameter integer C_M_AXI_BUSER_WIDTH = 0
- )
- (
- // Users to add ports here
-
- // User ports ends
- // Do not modify the ports beyond this line
-
- // Initiate AXI transactions
- input wire INIT_AXI_TXN,
- // Asserts when transaction is complete
- output wire TXN_DONE,
- // Asserts when ERROR is detected
- output reg ERROR,
- // Global Clock Signal.
- input wire M_AXI_ACLK,
- // Global Reset Singal. This Signal is Active Low
- input wire M_AXI_ARESETN,
- // Master Interface Write Address ID
- output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
- // Master Interface Write Address
- output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
- // Burst length. The burst length gives the exact number of transfers in a burst
- output wire [7 : 0] M_AXI_AWLEN,
- // Burst size. This signal indicates the size of each transfer in the burst
- output wire [2 : 0] M_AXI_AWSIZE,
- // Burst type. The burst type and the size information,
- // determine how the address for each transfer within the burst is calculated.
- output wire [1 : 0] M_AXI_AWBURST,
- // Lock type. Provides additional information about the
- // atomic characteristics of the transfer.
- output wire M_AXI_AWLOCK,
- // Memory type. This signal indicates how transactions
- // are required to progress through a system.
- output wire [3 : 0] M_AXI_AWCACHE,
- // Protection type. This signal indicates the privilege
- // and security level of the transaction, and whether
- // the transaction is a data access or an instruction access.
- output wire [2 : 0] M_AXI_AWPROT,
- // Quality of Service, QoS identifier sent for each write transaction.
- output wire [3 : 0] M_AXI_AWQOS,
- // Optional User-defined signal in the write address channel.
- output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
- // Write address valid. This signal indicates that
- // the channel is signaling valid write address and control information.
- output wire M_AXI_AWVALID,
- // Write address ready. This signal indicates that
- // the slave is ready to accept an address and associated control signals
- input wire M_AXI_AWREADY,
- // Master Interface Write Data.
- output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
- // Write strobes. This signal indicates which byte
- // lanes hold valid data. There is one write strobe
- // bit for each eight bits of the write data bus.
- output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
- // Write last. This signal indicates the last transfer in a write burst.
- output wire M_AXI_WLAST,
- // Optional User-defined signal in the write data channel.
- output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
- // Write valid. This signal indicates that valid write
- // data and strobes are available
- output wire M_AXI_WVALID,
- // Write ready. This signal indicates that the slave
- // can accept the write data.
- input wire M_AXI_WREADY,
- // Master Interface Write Response.
- input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
- // Write response. This signal indicates the status of the write transaction.
- input wire [1 : 0] M_AXI_BRESP,
- // Optional User-defined signal in the write response channel
- input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
- // Write response valid. This signal indicates that the
- // channel is signaling a valid write response.
- input wire M_AXI_BVALID,
- // Response ready. This signal indicates that the master
- // can accept a write response.
- output wire M_AXI_BREADY,
- // Master Interface Read Address.
- output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
- // Read address. This signal indicates the initial
- // address of a read burst transaction.
- output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
- // Burst length. The burst length gives the exact number of transfers in a burst
- output wire [7 : 0] M_AXI_ARLEN,
- // Burst size. This signal indicates the size of each transfer in the burst
- output wire [2 : 0] M_AXI_ARSIZE,
- // Burst type. The burst type and the size information,
- // determine how the address for each transfer within the burst is calculated.
- output wire [1 : 0] M_AXI_ARBURST,
- // Lock type. Provides additional information about the
- // atomic characteristics of the transfer.
- output wire M_AXI_ARLOCK,
- // Memory type. This signal indicates how transactions
- // are required to progress through a system.
- output wire [3 : 0] M_AXI_ARCACHE,
- // Protection type. This signal indicates the privilege
- // and security level of the transaction, and whether
- // the transaction is a data access or an instruction access.
- output wire [2 : 0] M_AXI_ARPROT,
- // Quality of Service, QoS identifier sent for each read transaction
- output wire [3 : 0] M_AXI_ARQOS,
- // Optional User-defined signal in the read address channel.
- output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
- // Write address valid. This signal indicates that
- // the channel is signaling valid read address and control information
- output wire M_AXI_ARVALID,
- // Read address ready. This signal indicates that
- // the slave is ready to accept an address and associated control signals
- input wire M_AXI_ARREADY,
- // Read ID tag. This signal is the identification tag
- // for the read data group of signals generated by the slave.
- input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
- // Master Read Data
- input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
- // Read response. This signal indicates the status of the read transfer
- input wire [1 : 0] M_AXI_RRESP,
- // Read last. This signal indicates the last transfer in a read burst
- input wire M_AXI_RLAST,
- // Optional User-defined signal in the read address channel.
- input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
- // Read valid. This signal indicates that the channel
- // is signaling the required read data.
- input wire M_AXI_RVALID,
- // Read ready. This signal indicates that the master can
- // accept the read data and response information.
- output wire M_AXI_RREADY
- );
-
-
- // function called clogb2 that returns an integer which has the
- //value of the ceiling of the log base 2
-
- // function called clogb2 that returns an integer which has the
- // value of the ceiling of the log base 2.
- function integer clogb2 (input integer bit_depth);
- begin
- for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
- bit_depth = bit_depth >> 1;
- end
- endfunction
-
- // C_TRANSACTIONS_NUM is the width of the index counter for
- // number of write or read transaction.
- localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1);
-
- // Burst length for transactions, in C_M_AXI_DATA_WIDTHs.
- // Non-2^n lengths will eventually cause bursts across 4K address boundaries.
- localparam integer C_MASTER_LENGTH = 12;
- // total number of burst transfers is master length divided by burst length and burst size
- localparam integer C_NO_BURSTS_REQ = C_MASTER_LENGTH-clogb2((C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8)-1);
- // Example State machine to initialize counter, initialize write transactions,
- // initialize read transactions and comparison of read data with the
- // written data words.
- parameter [1:0] IDLE = 2'b00, // This state initiates AXI4Lite transaction
- // after the state machine changes state to INIT_WRITE
- // when there is 0 to 1 transition on INIT_AXI_TXN
- INIT_WRITE = 2'b01, // This state initializes write transaction,
- // once writes are done, the state machine
- // changes state to INIT_READ
- INIT_READ = 2'b10, // This state initializes read transaction
- // once reads are done, the state machine
- // changes state to INIT_COMPARE
- INIT_COMPARE = 2'b11; // This state issues the status of comparison
- // of the written data with the read data
-
- reg [1:0] mst_exec_state;
-
- // AXI4LITE signals
- //AXI4 internal temp signals
- reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
- reg axi_awvalid;
- reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
- reg axi_wlast;
- reg axi_wvalid;
- reg axi_bready;
- reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
- reg axi_arvalid;
- reg axi_rready;
- //write beat count in a burst
- reg [C_TRANSACTIONS_NUM : 0] write_index;
- //read beat count in a burst
- reg [C_TRANSACTIONS_NUM : 0] read_index;
- //size of C_M_AXI_BURST_LEN length burst in bytes
- wire [C_TRANSACTIONS_NUM+2 : 0] burst_size_bytes;
- //The burst counters are used to track the number of burst transfers of C_M_AXI_BURST_LEN burst length needed to transfer 2^C_MASTER_LENGTH bytes of data.
- reg [C_NO_BURSTS_REQ : 0] write_burst_counter;
- reg [C_NO_BURSTS_REQ : 0] read_burst_counter;
- reg start_single_burst_write;
- reg start_single_burst_read;
- reg writes_done;
- reg reads_done;
- reg error_reg;
- reg compare_done;
- reg read_mismatch;
- reg burst_write_active;
- reg burst_read_active;
- reg [C_M_AXI_DATA_WIDTH-1 : 0] expected_rdata;
- //Interface response error flags
- wire write_resp_error;
- wire read_resp_error;
- wire wnext;
- wire rnext;
- reg init_txn_ff;
- reg init_txn_ff2;
- reg init_txn_edge;
- wire init_txn_pulse;
-
-
- // I/O Connections assignments
-
- //I/O Connections. Write Address (AW)
- assign M_AXI_AWID = 'b0;
- //The AXI address is a concatenation of the target base address + active offset range
- assign M_AXI_AWADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
- //Burst LENgth is number of transaction beats, minus 1
- assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1;
- //Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
- assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
- //INCR burst type is usually used, except for keyhole bursts
- assign M_AXI_AWBURST = 2'b01;
- assign M_AXI_AWLOCK = 1'b0;
- //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
- assign M_AXI_AWCACHE = 4'b0010;
- assign M_AXI_AWPROT = 3'h0;
- assign M_AXI_AWQOS = 4'h0;
- assign M_AXI_AWUSER = 'b1;
- assign M_AXI_AWVALID = axi_awvalid;
- //Write Data(W)
- assign M_AXI_WDATA = axi_wdata;
- //All bursts are complete and aligned in this example
- assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
- assign M_AXI_WLAST = axi_wlast;
- assign M_AXI_WUSER = 'b0;
- assign M_AXI_WVALID = axi_wvalid;
- //Write Response (B)
- assign M_AXI_BREADY = axi_bready;
- //Read Address (AR)
- assign M_AXI_ARID = 'b0;
- assign M_AXI_ARADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_araddr;
- //Burst LENgth is number of transaction beats, minus 1
- assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1;
- //Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
- assign M_AXI_ARSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
- //INCR burst type is usually used, except for keyhole bursts
- assign M_AXI_ARBURST = 2'b01;
- assign M_AXI_ARLOCK = 1'b0;
- //Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
- assign M_AXI_ARCACHE = 4'b0010;
- assign M_AXI_ARPROT = 3'h0;
- assign M_AXI_ARQOS = 4'h0;
- assign M_AXI_ARUSER = 'b1;
- assign M_AXI_ARVALID = axi_arvalid;
- //Read and Read Response (R)
- assign M_AXI_RREADY = axi_rready;
- //Example design I/O
- assign TXN_DONE = compare_done;
- //Burst size in bytes
- assign burst_size_bytes = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
- assign init_txn_pulse = (!init_txn_ff2) && init_txn_ff;
-
-
- //Generate a pulse to initiate AXI transaction.
- always @(posedge M_AXI_ACLK)
- begin
- // Initiates AXI transaction delay
- if (M_AXI_ARESETN == 0 )
- begin
- init_txn_ff <= 1'b0;
- init_txn_ff2 <= 1'b0;
- end
- else
- begin
- init_txn_ff <= INIT_AXI_TXN;
- init_txn_ff2 <= init_txn_ff;
- end
- end
-
-
- //--------------------
- //Write Address Channel
- //--------------------
-
- // The purpose of the write address channel is to request the address and
- // command information for the entire transaction. It is a single beat
- // of information.
-
- // The AXI4 Write address channel in this example will continue to initiate
- // write commands as fast as it is allowed by the slave/interconnect.
- // The address will be incremented on each accepted address transaction,
- // by burst_size_byte to point to the next address.
-
- always @(posedge M_AXI_ACLK)
- begin
-
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_awvalid <= 1'b0;
- end
- // If previously not valid , start next transaction
- else if (~axi_awvalid && start_single_burst_write)
- begin
- axi_awvalid <= 1'b1;
- end
- /* Once asserted, VALIDs cannot be deasserted, so axi_awvalid
- must wait until transaction is accepted */
- else if (M_AXI_AWREADY && axi_awvalid)
- begin
- axi_awvalid <= 1'b0;
- end
- else
- axi_awvalid <= axi_awvalid;
- end
-
-
- // Next address after AWREADY indicates previous address acceptance
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- begin
- axi_awaddr <= 'b0;
- end
- else if (M_AXI_AWREADY && axi_awvalid)
- begin
- axi_awaddr <= axi_awaddr + burst_size_bytes;
- end
- else
- axi_awaddr <= axi_awaddr;
- end
-
-
- //--------------------
- //Write Data Channel
- //--------------------
-
- //The write data will continually try to push write data across the interface.
-
- //The amount of data accepted will depend on the AXI slave and the AXI
- //Interconnect settings, such as if there are FIFOs enabled in interconnect.
-
- //Note that there is no explicit timing relationship to the write address channel.
- //The write channel has its own throttling flag, separate from the AW channel.
-
- //Synchronization between the channels must be determined by the user.
-
- //The simpliest but lowest performance would be to only issue one address write
- //and write data burst at a time.
-
- //In this example they are kept in sync by using the same address increment
- //and burst sizes. Then the AW and W channels have their transactions measured
- //with threshold counters as part of the user logic, to make sure neither
- //channel gets too far ahead of each other.
-
- //Forward movement occurs when the write channel is valid and ready
-
- assign wnext = M_AXI_WREADY & axi_wvalid;
-
- // WVALID logic, similar to the axi_awvalid always block above
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_wvalid <= 1'b0;
- end
- // If previously not valid, start next transaction
- else if (~axi_wvalid && start_single_burst_write)
- begin
- axi_wvalid <= 1'b1;
- end
- /* If WREADY and too many writes, throttle WVALID
- Once asserted, VALIDs cannot be deasserted, so WVALID
- must wait until burst is complete with WLAST */
- else if (wnext && axi_wlast)
- axi_wvalid <= 1'b0;
- else
- axi_wvalid <= axi_wvalid;
- end
-
-
- //WLAST generation on the MSB of a counter underflow
- // WVALID logic, similar to the axi_awvalid always block above
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_wlast <= 1'b0;
- end
- // axi_wlast is asserted when the write index
- // count reaches the penultimate count to synchronize
- // with the last write data when write_index is b1111
- // else if (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
- else if (((write_index == C_M_AXI_BURST_LEN-2 && C_M_AXI_BURST_LEN >= 2) && wnext) || (C_M_AXI_BURST_LEN == 1 ))
- begin
- axi_wlast <= 1'b1;
- end
- // Deassrt axi_wlast when the last write data has been
- // accepted by the slave with a valid response
- else if (wnext)
- axi_wlast <= 1'b0;
- else if (axi_wlast && C_M_AXI_BURST_LEN == 1)
- axi_wlast <= 1'b0;
- else
- axi_wlast <= axi_wlast;
- end
-
-
- /* Burst length counter. Uses extra counter register bit to indicate terminal
- count to reduce decode logic */
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_write == 1'b1)
- begin
- write_index <= 0;
- end
- else if (wnext && (write_index != C_M_AXI_BURST_LEN-1))
- begin
- write_index <= write_index + 1;
- end
- else
- write_index <= write_index;
- end
-
-
- /* Write Data Generator
- Data pattern is only a simple incrementing count from 0 for each burst */
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- axi_wdata <= 'b1;
- //else if (wnext && axi_wlast)
- // axi_wdata <= 'b0;
- else if (wnext)
- axi_wdata <= axi_wdata + 1;
- else
- axi_wdata <= axi_wdata;
- end
-
-
- //----------------------------
- //Write Response (B) Channel
- //----------------------------
-
- //The write response channel provides feedback that the write has committed
- //to memory. BREADY will occur when all of the data and the write address
- //has arrived and been accepted by the slave.
-
- //The write issuance (number of outstanding write addresses) is started by
- //the Address Write transfer, and is completed by a BREADY/BRESP.
-
- //While negating BREADY will eventually throttle the AWREADY signal,
- //it is best not to throttle the whole data channel this way.
-
- //The BRESP bit [1] is used indicate any errors from the interconnect or
- //slave for the entire write burst. This example will capture the error
- //into the ERROR output.
-
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_bready <= 1'b0;
- end
- // accept/acknowledge bresp with axi_bready by the master
- // when M_AXI_BVALID is asserted by slave
- else if (M_AXI_BVALID && ~axi_bready)
- begin
- axi_bready <= 1'b1;
- end
- // deassert after one clock cycle
- else if (axi_bready)
- begin
- axi_bready <= 1'b0;
- end
- // retain the previous value
- else
- axi_bready <= axi_bready;
- end
-
-
- //Flag any write response errors
- assign write_resp_error = axi_bready & M_AXI_BVALID & M_AXI_BRESP[1];
-
-
- //----------------------------
- //Read Address Channel
- //----------------------------
-
- //The Read Address Channel (AW) provides a similar function to the
- //Write Address channel- to provide the tranfer qualifiers for the burst.
-
- //In this example, the read address increments in the same
- //manner as the write address channel.
-
- always @(posedge M_AXI_ACLK)
- begin
-
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_arvalid <= 1'b0;
- end
- // If previously not valid , start next transaction
- else if (~axi_arvalid && start_single_burst_read)
- begin
- axi_arvalid <= 1'b1;
- end
- else if (M_AXI_ARREADY && axi_arvalid)
- begin
- axi_arvalid <= 1'b0;
- end
- else
- axi_arvalid <= axi_arvalid;
- end
-
-
- // Next address after ARREADY indicates previous address acceptance
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- begin
- axi_araddr <= 'b0;
- end
- else if (M_AXI_ARREADY && axi_arvalid)
- begin
- axi_araddr <= axi_araddr + burst_size_bytes;
- end
- else
- axi_araddr <= axi_araddr;
- end
-
-
- //--------------------------------
- //Read Data (and Response) Channel
- //--------------------------------
-
- // Forward movement occurs when the channel is valid and ready
- assign rnext = M_AXI_RVALID && axi_rready;
-
-
- // Burst length counter. Uses extra counter register bit to indicate
- // terminal count to reduce decode logic
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_read)
- begin
- read_index <= 0;
- end
- else if (rnext && (read_index != C_M_AXI_BURST_LEN-1))
- begin
- read_index <= read_index + 1;
- end
- else
- read_index <= read_index;
- end
-
-
- /*
- The Read Data channel returns the results of the read request
-
- In this example the data checker is always able to accept
- more data, so no need to throttle the RREADY signal
- */
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- axi_rready <= 1'b0;
- end
- // accept/acknowledge rdata/rresp with axi_rready by the master
- // when M_AXI_RVALID is asserted by slave
- else if (M_AXI_RVALID)
- begin
- if (M_AXI_RLAST && axi_rready)
- begin
- axi_rready <= 1'b0;
- end
- else
- begin
- axi_rready <= 1'b1;
- end
- end
- // retain the previous value
- end
-
- //Check received read data against data generator
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- begin
- read_mismatch <= 1'b0;
- end
- //Only check data when RVALID is active
- else if (rnext && (M_AXI_RDATA != expected_rdata))
- begin
- read_mismatch <= 1'b1;
- end
- else
- read_mismatch <= 1'b0;
- end
-
- //Flag any read response errors
- assign read_resp_error = axi_rready & M_AXI_RVALID & M_AXI_RRESP[1];
-
-
- //----------------------------------------
- //Example design read check data generator
- //-----------------------------------------
-
- //Generate expected read data to check against actual read data
-
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)// || M_AXI_RLAST)
- expected_rdata <= 'b1;
- else if (M_AXI_RVALID && axi_rready)
- expected_rdata <= expected_rdata + 1;
- else
- expected_rdata <= expected_rdata;
- end
-
-
- //----------------------------------
- //Example design error register
- //----------------------------------
-
- //Register and hold any data mismatches, or read/write interface errors
-
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- begin
- error_reg <= 1'b0;
- end
- else if (read_mismatch || write_resp_error || read_resp_error)
- begin
- error_reg <= 1'b1;
- end
- else
- error_reg <= error_reg;
- end
-
-
- //--------------------------------
- //Example design throttling
- //--------------------------------
-
- // For maximum port throughput, this user example code will try to allow
- // each channel to run as independently and as quickly as possible.
-
- // However, there are times when the flow of data needs to be throtted by
- // the user application. This example application requires that data is
- // not read before it is written and that the write channels do not
- // advance beyond an arbitrary threshold (say to prevent an
- // overrun of the current read address by the write address).
-
- // From AXI4 Specification, 13.13.1: "If a master requires ordering between
- // read and write transactions, it must ensure that a response is received
- // for the previous transaction before issuing the next transaction."
-
- // This example accomplishes this user application throttling through:
- // -Reads wait for writes to fully complete
- // -Address writes wait when not read + issued transaction counts pass
- // a parameterized threshold
- // -Writes wait when a not read + active data burst count pass
- // a parameterized threshold
-
- // write_burst_counter counter keeps track with the number of burst transaction initiated
- // against the number of burst transactions the master needs to initiate
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
- begin
- write_burst_counter <= 'b0;
- end
- else if (M_AXI_AWREADY && axi_awvalid)
- begin
- if (write_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
- begin
- write_burst_counter <= write_burst_counter + 1'b1;
- //write_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
- end
- end
- else
- write_burst_counter <= write_burst_counter;
- end
-
- // read_burst_counter counter keeps track with the number of burst transaction initiated
- // against the number of burst transactions the master needs to initiate
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- begin
- read_burst_counter <= 'b0;
- end
- else if (M_AXI_ARREADY && axi_arvalid)
- begin
- if (read_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
- begin
- read_burst_counter <= read_burst_counter + 1'b1;
- //read_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
- end
- end
- else
- read_burst_counter <= read_burst_counter;
- end
-
-
- //implement master command interface state machine
-
- always @ ( posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 1'b0 )
- begin
- // reset condition
- // All the signals are assigned default values under reset condition
- mst_exec_state <= IDLE;
- start_single_burst_write <= 1'b0;
- start_single_burst_read <= 1'b0;
- compare_done <= 1'b0;
- ERROR <= 1'b0;
- end
- else
- begin
-
- // state transition
- case (mst_exec_state)
-
- IDLE:
- // This state is responsible to wait for user defined C_M_START_COUNT
- // number of clock cycles.
- if ( init_txn_pulse == 1'b1)
- begin
- mst_exec_state <= INIT_WRITE;
- ERROR <= 1'b0;
- compare_done <= 1'b0;
- end
- else
- begin
- mst_exec_state <= IDLE;
- end
-
- INIT_WRITE:
- // This state is responsible to issue start_single_write pulse to
- // initiate a write transaction. Write transactions will be
- // issued until burst_write_active signal is asserted.
- // write controller
- if (writes_done)
- begin
- mst_exec_state <= INIT_READ;//
- end
- else
- begin
- mst_exec_state <= INIT_WRITE;
-
- if (~axi_awvalid && ~start_single_burst_write && ~burst_write_active)
- begin
- start_single_burst_write <= 1'b1;
- end
- else
- begin
- start_single_burst_write <= 1'b0; //Negate to generate a pulse
- end
- end
-
- INIT_READ:
- // This state is responsible to issue start_single_read pulse to
- // initiate a read transaction. Read transactions will be
- // issued until burst_read_active signal is asserted.
- // read controller
- if (reads_done)
- begin
- mst_exec_state <= INIT_COMPARE;
- end
- else
- begin
- mst_exec_state <= INIT_READ;
-
- if (~axi_arvalid && ~burst_read_active && ~start_single_burst_read)
- begin
- start_single_burst_read <= 1'b1;
- end
- else
- begin
- start_single_burst_read <= 1'b0; //Negate to generate a pulse
- end
- end
-
- INIT_COMPARE:
- // This state is responsible to issue the state of comparison
- // of written data with the read data. If no error flags are set,
- // compare_done signal will be asseted to indicate success.
- //if (~error_reg)
- begin
- ERROR <= error_reg;
- mst_exec_state <= IDLE;
- compare_done <= 1'b1;
- end
- default :
- begin
- mst_exec_state <= IDLE;
- end
- endcase
- end
- end //MASTER_EXECUTION_PROC
-
-
- // burst_write_active signal is asserted when there is a burst write transaction
- // is initiated by the assertion of start_single_burst_write. burst_write_active
- // signal remains asserted until the burst write is accepted by the slave
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- burst_write_active <= 1'b0;
-
- //The burst_write_active is asserted when a write burst transaction is initiated
- else if (start_single_burst_write)
- burst_write_active <= 1'b1;
- else if (M_AXI_BVALID && axi_bready)
- burst_write_active <= 0;
- end
-
- // Check for last write completion.
-
- // This logic is to qualify the last write count with the final write
- // response. This demonstrates how to confirm that a write has been
- // committed.
-
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- writes_done <= 1'b0;
-
- //The writes_done should be associated with a bready response
- //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
- else if (M_AXI_BVALID && (write_burst_counter[C_NO_BURSTS_REQ]) && axi_bready)
- writes_done <= 1'b1;
- else
- writes_done <= writes_done;
- end
-
- // burst_read_active signal is asserted when there is a burst write transaction
- // is initiated by the assertion of start_single_burst_write. start_single_burst_read
- // signal remains asserted until the burst read is accepted by the master
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- burst_read_active <= 1'b0;
-
- //The burst_write_active is asserted when a write burst transaction is initiated
- else if (start_single_burst_read)
- burst_read_active <= 1'b1;
- else if (M_AXI_RVALID && axi_rready && M_AXI_RLAST)
- burst_read_active <= 0;
- end
-
-
- // Check for last read completion.
-
- // This logic is to qualify the last read count with the final read
- // response. This demonstrates how to confirm that a read has been
- // committed.
-
- always @(posedge M_AXI_ACLK)
- begin
- if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
- reads_done <= 1'b0;
-
- //The reads_done should be associated with a rready response
- //else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
- else if (M_AXI_RVALID && axi_rready && (read_index == C_M_AXI_BURST_LEN-1) && (read_burst_counter[C_NO_BURSTS_REQ]))
- reads_done <= 1'b1;
- else
- reads_done <= reads_done;
- end
-
- // Add user logic here
-
- // User logic ends
-
- endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
deleted file mode 100644
index c410c75..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge.v
+++ /dev/null
@@ -1,623 +0,0 @@
-//-----------------------------------------------------------------
-// UART -> AXI Debug Bridge
-// V1.0
-// Ultra-Embedded.com
-// Copyright 2017-2019
-//
-// Email: admin@ultra-embedded.com
-//
-// License: LGPL
-//-----------------------------------------------------------------
-//
-// This source file may be used and distributed without
-// restriction provided that this copyright statement is not
-// removed from the file and that any derivative work contains
-// the original copyright notice and the associated disclaimer.
-//
-// This source file is free software; you can redistribute it
-// and/or modify it under the terms of the GNU Lesser General
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any
-// later version.
-//
-// This source is distributed in the hope that it will be
-// useful, but WITHOUT ANY WARRANTY; without even the implied
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-// PURPOSE. See the GNU Lesser General Public License for more
-// details.
-//
-// You should have received a copy of the GNU Lesser General
-// Public License along with this source; if not, write to the
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-// Boston, MA 02111-1307 USA
-//-----------------------------------------------------------------
-
-//-----------------------------------------------------------------
-// Generated File
-//-----------------------------------------------------------------
-
-module dbg_bridge
-//-----------------------------------------------------------------
-// Params
-//-----------------------------------------------------------------
-#(
- parameter CLK_FREQ = 24000000
- ,parameter UART_SPEED = 115200
- ,parameter AXI_ID = 4'd0
- ,parameter GPIO_ADDRESS = 32'hf0000000
- ,parameter STS_ADDRESS = 32'hf0000004
-)
-//-----------------------------------------------------------------
-// Ports
-//-----------------------------------------------------------------
-(
- // Inputs
- input clk_i
- ,input rst_i
- ,input uart_rxd_i
- ,input mem_awready_i
- ,input mem_wready_i
- ,input mem_bvalid_i
- ,input [ 1:0] mem_bresp_i
- ,input [ 3:0] mem_bid_i
- ,input mem_arready_i
- ,input mem_rvalid_i
- ,input [ 31:0] mem_rdata_i
- ,input [ 1:0] mem_rresp_i
- ,input [ 3:0] mem_rid_i
- ,input mem_rlast_i
- ,input [ 31:0] gpio_inputs_i
-
- // Outputs
- ,output uart_txd_o
- ,output mem_awvalid_o
- ,output [ 31:0] mem_awaddr_o
- ,output [ 3:0] mem_awid_o
- ,output [ 7:0] mem_awlen_o
- ,output [ 1:0] mem_awburst_o
- ,output mem_wvalid_o
- ,output [ 31:0] mem_wdata_o
- ,output [ 3:0] mem_wstrb_o
- ,output mem_wlast_o
- ,output mem_bready_o
- ,output mem_arvalid_o
- ,output [ 31:0] mem_araddr_o
- ,output [ 3:0] mem_arid_o
- ,output [ 7:0] mem_arlen_o
- ,output [ 1:0] mem_arburst_o
- ,output mem_rready_o
- ,output [ 31:0] gpio_outputs_o
-);
-
-
-
-//-----------------------------------------------------------------
-// Defines
-//-----------------------------------------------------------------
-localparam REQ_WRITE = 8'h10;
-localparam REQ_READ = 8'h11;
-
-`define STATE_W 4
-`define STATE_R 3:0
-localparam STATE_IDLE = 4'd0;
-localparam STATE_LEN = 4'd2;
-localparam STATE_ADDR0 = 4'd3;
-localparam STATE_ADDR1 = 4'd4;
-localparam STATE_ADDR2 = 4'd5;
-localparam STATE_ADDR3 = 4'd6;
-localparam STATE_WRITE = 4'd7;
-localparam STATE_READ = 4'd8;
-localparam STATE_DATA0 = 4'd9;
-localparam STATE_DATA1 = 4'd10;
-localparam STATE_DATA2 = 4'd11;
-localparam STATE_DATA3 = 4'd12;
-
-//-----------------------------------------------------------------
-// Wires / Regs
-//-----------------------------------------------------------------
-wire uart_wr_w;
-wire [7:0] uart_wr_data_w;
-wire uart_wr_busy_w;
-
-wire uart_rd_w;
-wire [7:0] uart_rd_data_w;
-wire uart_rd_valid_w;
-
-wire uart_rx_error_w;
-
-wire tx_valid_w;
-wire [7:0] tx_data_w;
-wire tx_accept_w;
-wire read_skip_w;
-
-wire rx_valid_w;
-wire [7:0] rx_data_w;
-wire rx_accept_w;
-
-reg [31:0] mem_addr_q;
-reg mem_busy_q;
-reg mem_wr_q;
-
-reg [7:0] len_q;
-
-// Byte Index
-reg [1:0] data_idx_q;
-
-// Word storage
-reg [31:0] data_q;
-
-wire magic_addr_w = (mem_addr_q == GPIO_ADDRESS || mem_addr_q == STS_ADDRESS);
-
-//-----------------------------------------------------------------
-// UART core
-//-----------------------------------------------------------------
-dbg_bridge_uart
-#( .UART_DIVISOR_W(32) )
-u_uart
-(
- .clk_i(clk_i),
- .rst_i(rst_i),
-
- // Control
- .bit_div_i((CLK_FREQ / UART_SPEED) - 1),
- .stop_bits_i(1'b0), // 0 = 1, 1 = 2
-
- // Transmit
- .wr_i(uart_wr_w),
- .data_i(uart_wr_data_w),
- .tx_busy_o(uart_wr_busy_w),
-
- // Receive
- .rd_i(uart_rd_w),
- .data_o(uart_rd_data_w),
- .rx_ready_o(uart_rd_valid_w),
-
- .rx_err_o(uart_rx_error_w),
-
- // UART pins
- .rxd_i(uart_rxd_i),
- .txd_o(uart_txd_o)
-);
-
-//-----------------------------------------------------------------
-// Output FIFO
-//-----------------------------------------------------------------
-wire uart_tx_pop_w = ~uart_wr_busy_w;
-
-dbg_bridge_fifo
-#(
- .WIDTH(8),
- .DEPTH(8),
- .ADDR_W(3)
-)
-u_fifo_tx
-(
- .clk_i(clk_i),
- .rst_i(rst_i),
-
- // In
- .push_i(tx_valid_w),
- .data_in_i(tx_data_w),
- .accept_o(tx_accept_w),
-
- // Out
- .pop_i(uart_tx_pop_w),
- .data_out_o(uart_wr_data_w),
- .valid_o(uart_wr_w)
-);
-
-//-----------------------------------------------------------------
-// Input FIFO
-//-----------------------------------------------------------------
-dbg_bridge_fifo
-#(
- .WIDTH(8),
- .DEPTH(8),
- .ADDR_W(3)
-)
-u_fifo_rx
-(
- .clk_i(clk_i),
- .rst_i(rst_i),
-
- // In
- .push_i(uart_rd_valid_w),
- .data_in_i(uart_rd_data_w),
- .accept_o(uart_rd_w),
-
- // Out
- .pop_i(rx_accept_w),
- .data_out_o(rx_data_w),
- .valid_o(rx_valid_w)
-);
-
-//-----------------------------------------------------------------
-// States
-//-----------------------------------------------------------------
-reg [`STATE_R] state_q;
-reg [`STATE_R] next_state_r;
-
-always @ *
-begin
- next_state_r = state_q;
-
- case (next_state_r)
- //-------------------------------------------------------------
- // IDLE:
- //-------------------------------------------------------------
- STATE_IDLE:
- begin
- if (rx_valid_w)
- begin
- case (rx_data_w)
- REQ_WRITE,
- REQ_READ:
- next_state_r = STATE_LEN;
- default:
- ;
- endcase
- end
- end
- //-----------------------------------------
- // STATE_LEN
- //-----------------------------------------
- STATE_LEN :
- begin
- if (rx_valid_w)
- next_state_r = STATE_ADDR0;
- end
- //-----------------------------------------
- // STATE_ADDR
- //-----------------------------------------
- STATE_ADDR0 : if (rx_valid_w) next_state_r = STATE_ADDR1;
- STATE_ADDR1 : if (rx_valid_w) next_state_r = STATE_ADDR2;
- STATE_ADDR2 : if (rx_valid_w) next_state_r = STATE_ADDR3;
- STATE_ADDR3 :
- begin
- if (rx_valid_w && mem_wr_q)
- next_state_r = STATE_WRITE;
- else if (rx_valid_w)
- next_state_r = STATE_READ;
- end
- //-----------------------------------------
- // STATE_WRITE
- //-----------------------------------------
- STATE_WRITE :
- begin
- if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
- next_state_r = STATE_IDLE;
- else
- next_state_r = STATE_WRITE;
- end
- //-----------------------------------------
- // STATE_READ
- //-----------------------------------------
- STATE_READ :
- begin
- // Data ready
- if (mem_rvalid_i || magic_addr_w)
- next_state_r = STATE_DATA0;
- end
- //-----------------------------------------
- // STATE_DATA
- //-----------------------------------------
- STATE_DATA0 :
- begin
- if (read_skip_w)
- next_state_r = STATE_DATA1;
- else if (tx_accept_w && (len_q == 8'b0))
- next_state_r = STATE_IDLE;
- else if (tx_accept_w)
- next_state_r = STATE_DATA1;
- end
- STATE_DATA1 :
- begin
- if (read_skip_w)
- next_state_r = STATE_DATA2;
- else if (tx_accept_w && (len_q == 8'b0))
- next_state_r = STATE_IDLE;
- else if (tx_accept_w)
- next_state_r = STATE_DATA2;
- end
- STATE_DATA2 :
- begin
- if (read_skip_w)
- next_state_r = STATE_DATA3;
- else if (tx_accept_w && (len_q == 8'b0))
- next_state_r = STATE_IDLE;
- else if (tx_accept_w)
- next_state_r = STATE_DATA3;
- end
- STATE_DATA3 :
- begin
- if (tx_accept_w && (len_q != 8'b0))
- next_state_r = STATE_READ;
- else if (tx_accept_w)
- next_state_r = STATE_IDLE;
- end
- default:
- ;
- endcase
-end
-
-// State storage
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- state_q <= STATE_IDLE;
-else
- state_q <= next_state_r;
-
-//-----------------------------------------------------------------
-// RD/WR to and from UART
-//-----------------------------------------------------------------
-
-// Write to UART Tx buffer in the following states
-assign tx_valid_w = ((state_q == STATE_DATA0) |
- (state_q == STATE_DATA1) |
- (state_q == STATE_DATA2) |
- (state_q == STATE_DATA3)) && !read_skip_w;
-
-// Accept data in the following states
-assign rx_accept_w = (state_q == STATE_IDLE) |
- (state_q == STATE_LEN) |
- (state_q == STATE_ADDR0) |
- (state_q == STATE_ADDR1) |
- (state_q == STATE_ADDR2) |
- (state_q == STATE_ADDR3) |
- (state_q == STATE_WRITE && !mem_busy_q);
-
-//-----------------------------------------------------------------
-// Capture length
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- len_q <= 8'd0;
-else if (state_q == STATE_LEN && rx_valid_w)
- len_q[7:0] <= rx_data_w;
-else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
- len_q <= len_q - 8'd1;
-else if (state_q == STATE_READ && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
- len_q <= len_q - 8'd1;
-else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w && !read_skip_w))
- len_q <= len_q - 8'd1;
-
-//-----------------------------------------------------------------
-// Capture addr
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- mem_addr_q <= 'd0;
-else if (state_q == STATE_ADDR0 && rx_valid_w)
- mem_addr_q[31:24] <= rx_data_w;
-else if (state_q == STATE_ADDR1 && rx_valid_w)
- mem_addr_q[23:16] <= rx_data_w;
-else if (state_q == STATE_ADDR2 && rx_valid_w)
- mem_addr_q[15:8] <= rx_data_w;
-else if (state_q == STATE_ADDR3 && rx_valid_w)
- mem_addr_q[7:0] <= rx_data_w;
-// Address increment on every access issued
-else if (state_q == STATE_WRITE && (mem_busy_q && mem_bvalid_i))
- mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
-else if (state_q == STATE_READ && (mem_busy_q && mem_rvalid_i))
- mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
-
-//-----------------------------------------------------------------
-// Data Index
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- data_idx_q <= 2'b0;
-else if (state_q == STATE_ADDR3)
- data_idx_q <= rx_data_w[1:0];
-else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
- data_idx_q <= data_idx_q + 2'd1;
-else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && tx_accept_w && (data_idx_q != 2'b0))
- data_idx_q <= data_idx_q - 2'd1;
-
-assign read_skip_w = (data_idx_q != 2'b0);
-
-//-----------------------------------------------------------------
-// Data Sample
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- data_q <= 32'b0;
-// Write to memory
-else if (state_q == STATE_WRITE && rx_valid_w && !mem_busy_q)
-begin
- case (data_idx_q)
- 2'd0: data_q[7:0] <= rx_data_w;
- 2'd1: data_q[15:8] <= rx_data_w;
- 2'd2: data_q[23:16] <= rx_data_w;
- 2'd3: data_q[31:24] <= rx_data_w;
- endcase
-end
-// Read from GPIO Input?
-else if (state_q == STATE_READ && mem_addr_q == GPIO_ADDRESS)
-begin
- data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
-end
-// Read from status register?
-else if (state_q == STATE_READ && mem_addr_q == STS_ADDRESS)
- data_q <= {16'hcafe, 15'd0, mem_busy_q};
-// Read from memory
-else if (state_q == STATE_READ && mem_rvalid_i)
- data_q <= mem_rdata_i;
-// Shift data out (read response -> UART)
-else if (((state_q == STATE_DATA0) || (state_q == STATE_DATA1) || (state_q == STATE_DATA2)) && (tx_accept_w || read_skip_w))
- data_q <= {8'b0, data_q[31:8]};
-
-assign tx_data_w = data_q[7:0];
-
-assign mem_wdata_o = data_q;
-
-//-----------------------------------------------------------------
-// AXI: Write Request
-//-----------------------------------------------------------------
-reg mem_awvalid_q;
-reg mem_awvalid_r;
-
-reg mem_wvalid_q;
-reg mem_wvalid_r;
-
-always @ *
-begin
- mem_awvalid_r = 1'b0;
- mem_wvalid_r = 1'b0;
-
- // Hold
- if (mem_awvalid_o && !mem_awready_i)
- mem_awvalid_r = mem_awvalid_q;
- else if (mem_awvalid_o)
- mem_awvalid_r = 1'b0;
- // Every 4th byte, issue bus access
- else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
- mem_awvalid_r = !magic_addr_w;
-
- // Hold
- if (mem_wvalid_o && !mem_wready_i)
- mem_wvalid_r = mem_wvalid_q;
- else if (mem_wvalid_o)
- mem_wvalid_r = 1'b0;
- // Every 4th byte, issue bus access
- else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
- mem_wvalid_r = !magic_addr_w;
-end
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- mem_awvalid_q <= 1'b0;
- mem_wvalid_q <= 1'b0;
-end
-else
-begin
- mem_awvalid_q <= mem_awvalid_r;
- mem_wvalid_q <= mem_wvalid_r;
-end
-
-assign mem_awvalid_o = mem_awvalid_q;
-assign mem_wvalid_o = mem_wvalid_q;
-assign mem_awaddr_o = {mem_addr_q[31:2], 2'b0};
-assign mem_awid_o = AXI_ID;
-assign mem_awlen_o = 8'b0;
-assign mem_awburst_o = 2'b01;
-assign mem_wlast_o = 1'b1;
-
-assign mem_bready_o = 1'b1;
-
-//-----------------------------------------------------------------
-// AXI: Read Request
-//-----------------------------------------------------------------
-reg mem_arvalid_q;
-reg mem_arvalid_r;
-
-always @ *
-begin
- mem_arvalid_r = 1'b0;
-
- // Hold
- if (mem_arvalid_o && !mem_arready_i)
- mem_arvalid_r = mem_arvalid_q;
- else if (mem_arvalid_o)
- mem_arvalid_r = 1'b0;
- else if (state_q == STATE_READ && !mem_busy_q)
- mem_arvalid_r = !magic_addr_w;
-end
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- mem_arvalid_q <= 1'b0;
-else
- mem_arvalid_q <= mem_arvalid_r;
-
-assign mem_arvalid_o = mem_arvalid_q;
-assign mem_araddr_o = {mem_addr_q[31:2], 2'b0};
-assign mem_arid_o = AXI_ID;
-assign mem_arlen_o = 8'b0;
-assign mem_arburst_o = 2'b01;
-
-assign mem_rready_o = 1'b1;
-
-//-----------------------------------------------------------------
-// Write mask
-//-----------------------------------------------------------------
-reg [3:0] mem_sel_q;
-reg [3:0] mem_sel_r;
-
-always @ *
-begin
- mem_sel_r = 4'b1111;
-
- case (data_idx_q)
- 2'd0: mem_sel_r = 4'b0001;
- 2'd1: mem_sel_r = 4'b0011;
- 2'd2: mem_sel_r = 4'b0111;
- 2'd3: mem_sel_r = 4'b1111;
- endcase
-
- case (mem_addr_q[1:0])
- 2'd0: mem_sel_r = mem_sel_r & 4'b1111;
- 2'd1: mem_sel_r = mem_sel_r & 4'b1110;
- 2'd2: mem_sel_r = mem_sel_r & 4'b1100;
- 2'd3: mem_sel_r = mem_sel_r & 4'b1000;
- endcase
-end
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- mem_sel_q <= 4'b0;
-// Idle - reset for read requests
-else if (state_q == STATE_IDLE)
- mem_sel_q <= 4'b1111;
-// Every 4th byte, issue bus access
-else if (state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
- mem_sel_q <= mem_sel_r;
-
-assign mem_wstrb_o = mem_sel_q;
-
-//-----------------------------------------------------------------
-// Write enable
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- mem_wr_q <= 1'b0;
-else if (state_q == STATE_IDLE && rx_valid_w)
- mem_wr_q <= (rx_data_w == REQ_WRITE);
-
-//-----------------------------------------------------------------
-// Access in progress
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i == 1'b1)
- mem_busy_q <= 1'b0;
-else if (mem_arvalid_o || mem_awvalid_o)
- mem_busy_q <= 1'b1;
-else if (mem_bvalid_i || mem_rvalid_i)
- mem_busy_q <= 1'b0;
-
-//-----------------------------------------------------------------
-// GPIO Outputs
-//-----------------------------------------------------------------
-reg gpio_wr_q;
-reg [31:0] gpio_output_q;
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- gpio_wr_q <= 1'b0;
-else if (mem_addr_q == GPIO_ADDRESS && state_q == STATE_WRITE && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
- gpio_wr_q <= 1'b1;
-else
- gpio_wr_q <= 1'b0;
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- gpio_output_q <= 32'h0;
-else if (gpio_wr_q)
- gpio_output_q <= data_q[31:0];
-
-assign gpio_outputs_o = gpio_output_q;
-
-
-
-endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
deleted file mode 100644
index 8f43639..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_fifo.v
+++ /dev/null
@@ -1,118 +0,0 @@
-//-----------------------------------------------------------------
-// UART -> AXI Debug Bridge
-// V1.0
-// Ultra-Embedded.com
-// Copyright 2017-2019
-//
-// Email: admin@ultra-embedded.com
-//
-// License: LGPL
-//-----------------------------------------------------------------
-//
-// This source file may be used and distributed without
-// restriction provided that this copyright statement is not
-// removed from the file and that any derivative work contains
-// the original copyright notice and the associated disclaimer.
-//
-// This source file is free software; you can redistribute it
-// and/or modify it under the terms of the GNU Lesser General
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any
-// later version.
-//
-// This source is distributed in the hope that it will be
-// useful, but WITHOUT ANY WARRANTY; without even the implied
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-// PURPOSE. See the GNU Lesser General Public License for more
-// details.
-//
-// You should have received a copy of the GNU Lesser General
-// Public License along with this source; if not, write to the
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-// Boston, MA 02111-1307 USA
-//-----------------------------------------------------------------
-
-//-----------------------------------------------------------------
-// Generated File
-//-----------------------------------------------------------------
-module dbg_bridge_fifo
-//-----------------------------------------------------------------
-// Params
-//-----------------------------------------------------------------
-#(
- parameter WIDTH = 8,
- parameter DEPTH = 4,
- parameter ADDR_W = 2
-)
-//-----------------------------------------------------------------
-// Ports
-//-----------------------------------------------------------------
-(
- // Inputs
- input clk_i
- ,input rst_i
- ,input [WIDTH-1:0] data_in_i
- ,input push_i
- ,input pop_i
-
- // Outputs
- ,output [WIDTH-1:0] data_out_o
- ,output accept_o
- ,output valid_o
-);
-
-//-----------------------------------------------------------------
-// Local Params
-//-----------------------------------------------------------------
-localparam COUNT_W = ADDR_W + 1;
-
-//-----------------------------------------------------------------
-// Registers
-//-----------------------------------------------------------------
-reg [WIDTH-1:0] ram_q[DEPTH-1:0];
-reg [ADDR_W-1:0] rd_ptr_q;
-reg [ADDR_W-1:0] wr_ptr_q;
-reg [COUNT_W-1:0] count_q;
-
-//-----------------------------------------------------------------
-// Sequential
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- count_q <= {(COUNT_W) {1'b0}};
- rd_ptr_q <= {(ADDR_W) {1'b0}};
- wr_ptr_q <= {(ADDR_W) {1'b0}};
-end
-else
-begin
- // Push
- if (push_i & accept_o)
- begin
- ram_q[wr_ptr_q] <= data_in_i;
- wr_ptr_q <= wr_ptr_q + 1;
- end
-
- // Pop
- if (pop_i & valid_o)
- rd_ptr_q <= rd_ptr_q + 1;
-
- // Count up
- if ((push_i & accept_o) & ~(pop_i & valid_o))
- count_q <= count_q + 1;
- // Count down
- else if (~(push_i & accept_o) & (pop_i & valid_o))
- count_q <= count_q - 1;
-end
-
-//-------------------------------------------------------------------
-// Combinatorial
-//-------------------------------------------------------------------
-/* verilator lint_off WIDTH */
-assign valid_o = (count_q != 0);
-assign accept_o = (count_q != DEPTH);
-/* verilator lint_on WIDTH */
-
-assign data_out_o = ram_q[rd_ptr_q];
-
-endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
deleted file mode 100644
index fc3c570..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/src/dbg_bridge_uart.v
+++ /dev/null
@@ -1,341 +0,0 @@
-//-----------------------------------------------------------------
-// UART -> AXI Debug Bridge
-// V1.0
-// Ultra-Embedded.com
-// Copyright 2017-2019
-//
-// Email: admin@ultra-embedded.com
-//
-// License: LGPL
-//-----------------------------------------------------------------
-//
-// This source file may be used and distributed without
-// restriction provided that this copyright statement is not
-// removed from the file and that any derivative work contains
-// the original copyright notice and the associated disclaimer.
-//
-// This source file is free software; you can redistribute it
-// and/or modify it under the terms of the GNU Lesser General
-// Public License as published by the Free Software Foundation;
-// either version 2.1 of the License, or (at your option) any
-// later version.
-//
-// This source is distributed in the hope that it will be
-// useful, but WITHOUT ANY WARRANTY; without even the implied
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-// PURPOSE. See the GNU Lesser General Public License for more
-// details.
-//
-// You should have received a copy of the GNU Lesser General
-// Public License along with this source; if not, write to the
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-// Boston, MA 02111-1307 USA
-//-----------------------------------------------------------------
-
-//-----------------------------------------------------------------
-// Generated File
-//-----------------------------------------------------------------
-module dbg_bridge_uart
-
-//-----------------------------------------------------------------
-// Params
-//-----------------------------------------------------------------
-#(
- parameter UART_DIVISOR_W = 9
-)
-
-//-----------------------------------------------------------------
-// Ports
-//-----------------------------------------------------------------
-(
- // Clock & Reset
- input clk_i,
- input rst_i,
-
- // Control
- input [UART_DIVISOR_W-1:0] bit_div_i,
- input stop_bits_i, // 0 = 1, 1 = 2
-
- // Transmit
- input wr_i,
- input [7:0] data_i,
- output tx_busy_o,
-
- // Receive
- input rd_i,
- output [7:0] data_o,
- output rx_ready_o,
-
- output rx_err_o,
-
- // UART pins
- input rxd_i,
- output txd_o
-);
-
-//-----------------------------------------------------------------
-// Registers
-//-----------------------------------------------------------------
-localparam START_BIT = 4'd0;
-localparam STOP_BIT0 = 4'd9;
-localparam STOP_BIT1 = 4'd10;
-
-// Xilinx placement pragmas:
-//synthesis attribute IOB of txd_q is "TRUE"
-
-// TX Signals
-reg tx_busy_q;
-reg [3:0] tx_bits_q;
-reg [UART_DIVISOR_W-1:0] tx_count_q;
-reg [7:0] tx_shift_reg_q;
-reg txd_q;
-
-// RX Signals
-reg rxd_q;
-reg [7:0] rx_data_q;
-reg [3:0] rx_bits_q;
-reg [UART_DIVISOR_W-1:0] rx_count_q;
-reg [7:0] rx_shift_reg_q;
-reg rx_ready_q;
-reg rx_busy_q;
-
-reg rx_err_q;
-
-//-----------------------------------------------------------------
-// Re-sync RXD
-//-----------------------------------------------------------------
-reg rxd_ms_q;
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- rxd_ms_q <= 1'b1;
- rxd_q <= 1'b1;
-end
-else
-begin
- rxd_ms_q <= rxd_i;
- rxd_q <= rxd_ms_q;
-end
-
-//-----------------------------------------------------------------
-// RX Clock Divider
-//-----------------------------------------------------------------
-wire rx_sample_w = (rx_count_q == {(UART_DIVISOR_W){1'b0}});
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- rx_count_q <= {(UART_DIVISOR_W){1'b0}};
-else
-begin
- // Inactive
- if (!rx_busy_q)
- rx_count_q <= {1'b0, bit_div_i[UART_DIVISOR_W-1:1]};
- // Rx bit timer
- else if (rx_count_q != 0)
- rx_count_q <= (rx_count_q - 1);
- // Active
- else if (rx_sample_w)
- begin
- // Last bit?
- if ((rx_bits_q == STOP_BIT0 && !stop_bits_i) || (rx_bits_q == STOP_BIT1 && stop_bits_i))
- rx_count_q <= {(UART_DIVISOR_W){1'b0}};
- else
- rx_count_q <= bit_div_i;
- end
-end
-
-//-----------------------------------------------------------------
-// RX Shift Register
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- rx_shift_reg_q <= 8'h00;
- rx_busy_q <= 1'b0;
-end
-// Rx busy
-else if (rx_busy_q && rx_sample_w)
-begin
- // Last bit?
- if (rx_bits_q == STOP_BIT0 && !stop_bits_i)
- rx_busy_q <= 1'b0;
- else if (rx_bits_q == STOP_BIT1 && stop_bits_i)
- rx_busy_q <= 1'b0;
- else if (rx_bits_q == START_BIT)
- begin
- // Start bit should still be low as sampling mid
- // way through start bit, so if high, error!
- if (rxd_q)
- rx_busy_q <= 1'b0;
- end
- // Rx shift register
- else
- rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
-end
-// Start bit?
-else if (!rx_busy_q && rxd_q == 1'b0)
-begin
- rx_shift_reg_q <= 8'h00;
- rx_busy_q <= 1'b1;
-end
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- rx_bits_q <= START_BIT;
-else if (rx_sample_w && rx_busy_q)
-begin
- if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
- rx_bits_q <= START_BIT;
- else
- rx_bits_q <= rx_bits_q + 4'd1;
-end
-else if (!rx_busy_q && (bit_div_i == {(UART_DIVISOR_W){1'b0}}))
- rx_bits_q <= START_BIT + 4'd1;
-else if (!rx_busy_q)
- rx_bits_q <= START_BIT;
-
-//-----------------------------------------------------------------
-// RX Data
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- rx_ready_q <= 1'b0;
- rx_data_q <= 8'h00;
- rx_err_q <= 1'b0;
-end
-else
-begin
- // If reading data, reset data state
- if (rd_i == 1'b1)
- begin
- rx_ready_q <= 1'b0;
- rx_err_q <= 1'b0;
- end
-
- if (rx_busy_q && rx_sample_w)
- begin
- // Stop bit
- if ((rx_bits_q == STOP_BIT1 && stop_bits_i) || (rx_bits_q == STOP_BIT0 && !stop_bits_i))
- begin
- // RXD should be still high
- if (rxd_q)
- begin
- rx_data_q <= rx_shift_reg_q;
- rx_ready_q <= 1'b1;
- end
- // Bad Stop bit - wait for a full bit period
- // before allowing start bit detection again
- else
- begin
- rx_ready_q <= 1'b0;
- rx_data_q <= 8'h00;
- rx_err_q <= 1'b1;
- end
- end
- // Mid start bit sample - if high then error
- else if (rx_bits_q == START_BIT && rxd_q)
- rx_err_q <= 1'b1;
- end
-end
-
-//-----------------------------------------------------------------
-// TX Clock Divider
-//-----------------------------------------------------------------
-wire tx_sample_w = (tx_count_q == {(UART_DIVISOR_W){1'b0}});
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- tx_count_q <= {(UART_DIVISOR_W){1'b0}};
-else
-begin
- // Idle
- if (!tx_busy_q)
- tx_count_q <= bit_div_i;
- // Tx bit timer
- else if (tx_count_q != 0)
- tx_count_q <= (tx_count_q - 1);
- else if (tx_sample_w)
- tx_count_q <= bit_div_i;
-end
-
-//-----------------------------------------------------------------
-// TX Shift Register
-//-----------------------------------------------------------------
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
-begin
- tx_shift_reg_q <= 8'h00;
- tx_busy_q <= 1'b0;
-end
-// Tx busy
-else if (tx_busy_q)
-begin
- // Shift tx data
- if (tx_bits_q != START_BIT && tx_sample_w)
- tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};
-
- // Last bit?
- if (tx_bits_q == STOP_BIT0 && tx_sample_w && !stop_bits_i)
- tx_busy_q <= 1'b0;
- else if (tx_bits_q == STOP_BIT1 && tx_sample_w && stop_bits_i)
- tx_busy_q <= 1'b0;
-end
-// Buffer data to transmit
-else if (wr_i)
-begin
- tx_shift_reg_q <= data_i;
- tx_busy_q <= 1'b1;
-end
-
-always @ (posedge clk_i or posedge rst_i )
-if (rst_i)
- tx_bits_q <= 4'd0;
-else if (tx_sample_w && tx_busy_q)
-begin
- if ((tx_bits_q == STOP_BIT1 && stop_bits_i) || (tx_bits_q == STOP_BIT0 && !stop_bits_i))
- tx_bits_q <= START_BIT;
- else
- tx_bits_q <= tx_bits_q + 4'd1;
-end
-
-//-----------------------------------------------------------------
-// UART Tx Pin
-//-----------------------------------------------------------------
-reg txd_r;
-
-always @ *
-begin
- txd_r = 1'b1;
-
- if (tx_busy_q)
- begin
- // Start bit (TXD = L)
- if (tx_bits_q == START_BIT)
- txd_r = 1'b0;
- // Stop bits (TXD = H)
- else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
- txd_r = 1'b1;
- // Data bits
- else
- txd_r = tx_shift_reg_q[0];
- end
-end
-
-always @ (posedge clk_i or posedge rst_i)
-if (rst_i)
- txd_q <= 1'b1;
-else
- txd_q <= txd_r;
-
-//-----------------------------------------------------------------
-// Outputs
-//-----------------------------------------------------------------
-assign tx_busy_o = tx_busy_q;
-assign rx_ready_o = rx_ready_q;
-assign txd_o = txd_q;
-assign data_o = rx_data_q;
-assign rx_err_o = rx_err_q;
-
-endmodule
diff --git a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl b/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
deleted file mode 100644
index 5460b99..0000000
--- a/system/fpga_imp/ip_repo/uart_to_AXI_master_1.0/xgui/uart_to_AXI_master_v1_0.tcl
+++ /dev/null
@@ -1,190 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
- ipgui::add_param $IPINST -name "Component_Name"
- #Adding Page
- set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
- ipgui::add_param $IPINST -name "C_M00_AXI_TARGET_SLAVE_BASE_ADDR" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_BURST_LEN" -parent ${Page_0} -widget comboBox
- ipgui::add_param $IPINST -name "C_M00_AXI_ID_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
- ipgui::add_param $IPINST -name "C_M00_AXI_AWUSER_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_ARUSER_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_WUSER_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_RUSER_WIDTH" -parent ${Page_0}
- ipgui::add_param $IPINST -name "C_M00_AXI_BUSER_WIDTH" -parent ${Page_0}
-
- ipgui::add_param $IPINST -name "CLK_SPEED"
- ipgui::add_param $IPINST -name "UART_BAUD_RATE"
-
-}
-
-proc update_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
- # Procedure called to update CLK_SPEED when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.CLK_SPEED { PARAM_VALUE.CLK_SPEED } {
- # Procedure called to validate CLK_SPEED
- return true
-}
-
-proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
- # Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
- # Procedure called to validate UART_BAUD_RATE
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
- # Procedure called to update C_M00_AXI_TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
- # Procedure called to validate C_M00_AXI_TARGET_SLAVE_BASE_ADDR
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
- # Procedure called to update C_M00_AXI_BURST_LEN when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
- # Procedure called to validate C_M00_AXI_BURST_LEN
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
- # Procedure called to update C_M00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
- # Procedure called to validate C_M00_AXI_ID_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
- # Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
- # Procedure called to validate C_M00_AXI_ADDR_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
- # Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
- # Procedure called to validate C_M00_AXI_DATA_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
- # Procedure called to update C_M00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
- # Procedure called to validate C_M00_AXI_AWUSER_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
- # Procedure called to update C_M00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
- # Procedure called to validate C_M00_AXI_ARUSER_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
- # Procedure called to update C_M00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
- # Procedure called to validate C_M00_AXI_WUSER_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
- # Procedure called to update C_M00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
- # Procedure called to validate C_M00_AXI_RUSER_WIDTH
- return true
-}
-
-proc update_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
- # Procedure called to update C_M00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
- # Procedure called to validate C_M00_AXI_BUSER_WIDTH
- return true
-}
-
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_BURST_LEN { MODELPARAM_VALUE.C_M00_AXI_BURST_LEN PARAM_VALUE.C_M00_AXI_BURST_LEN } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BURST_LEN}] ${MODELPARAM_VALUE.C_M00_AXI_BURST_LEN}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.CLK_SPEED { MODELPARAM_VALUE.CLK_SPEED PARAM_VALUE.CLK_SPEED } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.CLK_SPEED}] ${MODELPARAM_VALUE.CLK_SPEED}
-}
-
-proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
- # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
- set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
-}
-
--
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