From b05b752d4cb38afe96c9bd5fd5d62b7919526694 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Thu, 27 Apr 2023 11:30:07 +0100 Subject: [PATCH] SOC1-167: Fixed .gitignore --- .gitignore | 2 +- systems/mcu/rtl_sim/adp.cmd | 56 ++++ systems/mcu/rtl_sim/makefile | 585 +++++++++++++++++++++++++++++++++++ 3 files changed, 642 insertions(+), 1 deletion(-) create mode 100644 systems/mcu/rtl_sim/adp.cmd create mode 100644 systems/mcu/rtl_sim/makefile diff --git a/.gitignore b/.gitignore index 3f6daa7..4e2d043 100644 --- a/.gitignore +++ b/.gitignore @@ -12,7 +12,7 @@ /systems/mcu/testcodes/*.lst /systems/mcu/testcodes/*.o -/systems/mcu/rtl_sim* +/systems/mcu/rtl_sim/* !/systems/mcu/rtl_sim/*.cmd !/systems/mcu/rtl_sim/makefile !/systems/mcu/rtl_sim/*.py diff --git a/systems/mcu/rtl_sim/adp.cmd b/systems/mcu/rtl_sim/adp.cmd new file mode 100644 index 0000000..62cc629 --- /dev/null +++ b/systems/mcu/rtl_sim/adp.cmd @@ -0,0 +1,56 @@ +A +A 0 +R +R +A +A +S 7e +A +a 1000000 +r 10 +a 20000000 +r +r +a 30000000 +r +r +a 40006000 +r +r +r +r +A + +v 0xe5e5e5e5 +a 80000000 +f 4000 +A +a 90000000 +U 4 +0123456789ABCDE +A +A 0x90000000 +R 5 +A e0000000 +w 1 +r +A +A 0x10000000 +R +m 0xf0000000 +V 0x30000000 +P 1fff +A +A 0x10000000 +M +V +P 200 +A +! illegal +C +C ff +C 200 +C 201 + A +X +! diff --git a/systems/mcu/rtl_sim/makefile b/systems/mcu/rtl_sim/makefile new file mode 100644 index 0000000..f1d25a3 --- /dev/null +++ b/systems/mcu/rtl_sim/makefile @@ -0,0 +1,585 @@ +#----------------------------------------------------------------------------- +# customised simulation makefile +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Flynn (d.w.flynn@soton.ac.uk) +# +# Copyright � 2021-3, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +#----------------------------------------------------------------------------- +# The confidential and proprietary information contained in this file may +# only be used by a person authorised under and to the extent permitted +# by a subsisting licensing agreement from Arm Limited or its affiliates. +# +# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates. +# ALL RIGHTS RESERVED +# +# This entire notice must be reproduced on all copies of this file +# and copies of this file may only be made by a person if such person is +# permitted to do so under the terms of a subsisting license agreement +# from Arm Limited or its affiliates. +# +# SVN Information +# +# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ +# +# Revision : $Revision: 371321 $ +# +# Release Information : Cortex-M System Design Kit-r1p1-00rel0 +#----------------------------------------------------------------------------- +# +# Cortex-M0/Cortex-M0+ System Design Kit simulation make file +# +#----------------------------------------------------------------------------- +# +# Configurations +# +# Name of test directory (e.g. hello, dhry) +# TESTNAME must be specified on the make command line +TESTNAME = + +# List of all tests (this is used when running 'make all/clean') +TEST_LIST = hello dhry sleep_demo interrupt_demo dualtimer_demo \ + self_reset_demo watchdog_demo rtx_demo gpio_tests timer_tests \ + uart_tests debug_tests default_slaves_tests dma_tests \ + gpio_driver_tests uart_driver_tests timer_driver_tests apb_mux_tests \ + memory_tests romtable_tests + +# Default to DS-5 tool-chain +TOOL_CHAIN = ds5 + +# Choose the core instantiated, can be either +# - CORTEX_M0PLUS (Cortex-M0+) +# - CORTEX_M0 (Cortex-M0) +# - CORTEX_M0_DS (Cortex-M0 DesignStart version) +# Note: for all processors, make sure that the __MPU_PRESENT variable in the header file agrees with the setting made in +# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is either: +# ../../../software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h +# or +# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h +# to match the CPU_PRODUCT selected +# Note: for the M0+ processor, make sure that the __VTOR_PRESENT variable in the header file agrees with the setting made in +# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is: +# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h +#DF#CPU_PRODUCT = CORTEX_M0PLUS +CPU_PRODUCT = CORTEX_M0 +DMA_PRODUCT = DMA_230 + +# Select Verilog Command File based on CPU type +ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS) + # For Cortex-M0+ product users + TBENCH_VC = ../verilog/tbench_M0P.vc +endif + +# Select Verilog Command File based on CPU type +ifeq ($(CPU_PRODUCT),CORTEX_M0) + # For Cortex-M0 product users +# TBENCH_VC += -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist + DEFINES_VC = +define+CORTEX_M0 +define+USE_TARMAC +endif + +ifeq ($(CPU_PRODUCT),CORTEX_M0_DS) + # For Cortex-M0 DesignStart users + TBENCH_VC = ../verilog/tbench_M0_DS.vc +endif + +ifeq ($(DMA_PRODUCT),DMA_230) + # For Cortex-M0 product users +# TBENCH_VC += -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist +endif + +TBENCH_VC += -f $(PROJECT_DIR)/flist/project/system.flist +ACCELERATOR_VC = + +# ACCELERATOR_IP = SHA_2 + +# ifeq ($(ACCELERATOR_IP),SHA_2) +# # For SHA2 Accelerator IP +# ACCELERATOR_VC = -sv -f $(SOC_TOP_DIR)/sha-2-accelerator/flist/sha-2-accelerator_src.flist +# ACCELERATOR_VC += -f $(SOC_TOP_DIR)/accelerator-wrapper/flist/accelerator-wrapper_src.flist +# endif + +#ADP command File +# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd +ADP_FILE ?= $(PROJECT_DIR)/system/stimulus/adp_hash_stim.cmd +ADP_PATH := $(shell realpath $(ADP_FILE)) +ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\" + +# Simulator type (mti/vcs/xm) +SIMULATOR = xm + +# MTI option +#DF#MTI_OPTIONS = -novopt +MTI_OPTIONS = -suppress 2892 +MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) + +# VCS option +VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug +VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc +VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) + +# XM verilog option +XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC +XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) + +# Boot Loader image +BOOTLOADER = bootloader +# Debug Tester image +DEBUGTESTER = debugtester + +# Software make options +# - Pass onto the software makefile to define targetted CPU type +# You can append additional make options for testcode here +SW_MAKE_OPTIONS = CPU_PRODUCT=$(CPU_PRODUCT) TOOL_CHAIN=$(TOOL_CHAIN) + +# ------- Simulator redirect ----------- + +compile : compile_$(SIMULATOR) + + +run : run_$(SIMULATOR) + + +sim : sim_$(SIMULATOR) + + +all : all_$(SIMULATOR) + +# ------- VCS ----------- + +# Compile RTL +compile_vcs : + vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) | tee compile_vcs.log + + +# Run simulation in batch mode +run_vcs : code + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo quit > quit.do + ./simv $(VCS_SIM_OPTION) < quit.do | tee logs/run_$(TESTNAME).log ; + +# Run simulation in interactive mode +sim_vcs : code + ./simv -gui +vcs+lic+wait +vcs+flush+log & + +# Compile RTL, and run all tests in batch mode +all_vcs : compile_vcs bootrom debugtester + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo quit > quit.do + @echo Run tests ... + for thistest in $(TEST_LIST) ; do \ + echo $$thistest ; \ + make testcode TESTNAME=$$thistest ;\ + if [ -e image.hex ] ; then \ + ./simv +vcs+lic+wait +vcs+flush+log < quit.do | tee logs/run_$$thistest.log ;\ + else \ + echo Cannot read image.hex ;\ + exit 1; \ + fi ; \ + done + +# ------- XM ----------- + +# Compile RTL +compile_xm : + @echo ADP_FILE + @echo $(ADP_OPTIONS) + xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top tb_nanosoc | tee compile_xm.log + xmvlog -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log + xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log + +# Note : If coverage is required, you can add -coverage all to xmelab + +# Run simulation in batch mode +run_xm : code compile_xm + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo run > run.tcl.tmp + @echo exit >> run.tcl.tmp + @mv run.tcl.tmp run.tcl + xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ; + # @make verify + +# Run simulation in interactive mode +sim_xm : code compile_xm + xmsim -gui $(XMSIM_OPTIONS) + @make verify + +# Compile RTL, and run all tests in batch mode +all_xm : compile_xm bootrom debugtester + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo run > run.tcl.tmp + @echo exit >> run.tcl.tmp + @mv run.tcl.tmp run.tcl + @echo Run tests ... + for thistest in $(TEST_LIST) ; do \ + echo $$thistest ; \ + make testcode TESTNAME=$$thistest ;\ + if [ -e image.hex ] ; then \ + xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$$thistest.log ;\ + else \ + echo Cannot read image.hex ;\ + exit 1; \ + fi ; \ + done + @make verify + +# ------- MTI ----------- + +# Compile RTL +compile_mti : + @if [ -d work ] ; then \ + true ; \ + else \ + vlib work; \ + fi + vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) | tee compile_mti.log + +# Run simulation in batch mode +run_mti : code + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + vsim $(MTI_OPTIONS) -c tb_cmsdk_mcu -do "radix hex;run -all;quit -f" | tee logs/run_$(TESTNAME).log ; + +# Run simulation in interactive mode +sim_mti : code + vsim $(MTI_OPTIONS) -gui tb_cmsdk_mcu & + +# Create work directory +lib_mti : + vlib work + +# Compile RTL, and run all tests in batch mode +all_mti : compile_mti bootrom debugtester + @if [ ! -d logs ] ; then \ + mkdir logs; \ + fi + @echo Run tests ... + for thistest in $(TEST_LIST) ; do \ + echo $$thistest ; \ + make testcode TESTNAME=$$thistest ;\ + if [ -e image.hex ] ; then \ + vsim $(MTI_OPTIONS) -c tb_cmsdk_mcu -do "radix hex;run -all;quit -f" | tee logs/run_$$thistest.log ;\ + else \ + echo Cannot read image.hex ;\ + exit 1; \ + fi ; \ + done + +# ------- Software ----------- + +# code target is used by other simulation targets (e.g. run_mti, sim_mti) +# Before simulation, bootrom and testcode need to be compiled. +code : testcode bootrom debugtester + +# Compile bootloader +# Note : The use of ls after compile allows the computing server to sync up +bootrom: + @(cd ../testcodes/$(BOOTLOADER) ;\ + make all $(SW_MAKE_OPTIONS) ;\ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(BOOTLOADER).hex ;\ + if [ -e $(BOOTLOADER).hex ] ; then \ + cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ + else \ + while [ ! -e $(BOOTLOADER).hex ] ; do \ + echo Wait for hex file ...; \ + ls > /dev/null; \ + sleep 5; \ + done; \ + if [ -e $(BOOTLOADER).hex ] ; then \ + cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ + else \ + echo Problem reading hex file ;\ + exit 1; \ + fi ;\ + fi ;\ + cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ + cd ../../rtl_sim ) + +# Compile test code +# Note : The use of ls after compile allows the computing server to sync up +testcode: +ifeq ($(TESTNAME),) + $(error Please specify TESTNAME on the make command line) +endif + @(if [ -d "../testcodes/$(TESTNAME)" ] ; then \ + cd ../testcodes/$(TESTNAME) ;\ + make all $(SW_MAKE_OPTIONS) ; \ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(TESTNAME).hex ;\ + if [ -e $(TESTNAME).hex ] ; then \ + cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \ + else \ + while [ ! -e $(TESTNAME).hex ] ; do \ + echo Wait for $(TESTNAME).hex file ...; \ + ls > /dev/null ; \ + sleep 5 ; \ + done; \ + if [ -e $(TESTNAME).hex ] ; then \ + cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \ + else \ + echo Problem reading hex file ;\ + exit 1; \ + fi ;\ + fi ;\ + cd ../../rtl_sim ;\ + else \ + echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\ + exit 1 ;\ + fi ;\ + ) + + +# Compile debugtester +# Note : The use of ls after compile allows the computing server to sync up +debugtester: + @(cd ../../../software/debug_tester ;\ + make all $(SW_MAKE_OPTIONS) ;\ + echo Compile done ;\ + ls > /dev/null ;\ + echo Copy $(DEBUGTESTER)_le.hex ;\ + if [ -e $(DEBUGTESTER)_le.hex ] ; then \ + cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\ + else \ + while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \ + echo Wait for hex file ...; \ + ls > /dev/null ; \ + sleep 5 ; \ + done; \ + if [ -e $(DEBUGTESTER)_le.hex ] ; then \ + cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\ + fi ;\ + fi ;\ + echo Copy $(DEBUGTESTER)_be.hex ;\ + if [ -e $(DEBUGTESTER)_be.hex ] ; then \ + cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\ + else \ + while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \ + echo Wait for hex file ...;\ + ls > /dev/null ;\ + sleep 5 ; \ + done; \ + if [ -e $(DEBUGTESTER)_be.hex ] ; then \ + cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\ + fi ;\ + fi ;\ + if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \ + echo Problem reading hex file ;\ + exit 1 ;\ + fi ;\ + cd ../../systems/mcu/rtl_sim ) + +# Compile all software including boot ROM +compile_all_code: bootrom debugtester + for thistest in $(TEST_LIST) ; do \ + echo Compiling $$thistest ; \ + echo Removing old image.hex ;\ + rm -f image.hex ;\ + make testcode TESTNAME=$$thistest;\ + if [ -e image.hex ] ; then \ + echo OK - image.hex created for test $$thistest ;\ + else \ + echo ERROR - image.hex NOT created for test $$thistest ;\ + exit 1; \ + fi ; \ + done + +# ------- document with v2html ----------- + +# +# rm -Rf * +# ../tools/v2html -f ../verilog/v2html_M0.vc -ht cmsdk_mcu_system +# cp -p tb_cmsdk_mcu.v.html hierarchy.html + +v2html: + echo building HTML tree + @if [ ! -d ../v2html_doc ] ; then \ + mkdir ../v2html_doc; \ + fi + @(cd ../v2html_doc; \ + rm *.html; rm *.gif; rm *.gz; \ + ~/tools/v2html -f ../verilog/v2html_M0.vc -ht nanosoc_chip ; \ + cp -p tb_nanosoc.v.html hierarchy.html ; \ + cd ../rtl_sim ; ) + gtar zcvf ../v2html_doc.tgz ../v2html_doc + + +# Remove all software compilation results +clean_all_code: + @(cd ../../../software/debug_tester ; make clean; cd ../../systems/mcu/rtl_sim; ) + @(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; ) + for thistest in $(TEST_LIST) ; do \ + echo Cleaning $$thistest ... ; \ + cd ../testcodes/$$thistest ; \ + make clean; \ + cd ../../rtl_sim; \ + done + +# Remove only bootloader and default selected test +clean_code: + @(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; ) + @(cd ../testcodes/$(TESTNAME) ; make clean; cd ../../rtl_sim; ) + +# ----- verification ------ +verify: + @python3 $(PROJECT_DIR)/flow/adp_verify.py + +# ------- clean ----------- + +# Remove RTL compile files, log files, software compile files +clean : clean_all_code + @if [ -d work ] ; then \ + rm -rf work ; \ + fi + @if [ -e tarmac0.log ] ; then \ + rm tarmac0.log ; \ + fi + @if [ -e tarmac1.log ] ; then \ + rm tarmac1.log ; \ + fi + @if [ -e tarmac0track.log ] ; then \ + rm tarmac0track.log ; \ + fi + @if [ -e ft1248_ip.log ] ; then \ + rm ft1248_ip.log ; \ + fi + @if [ -e ft1248_op.log ] ; then \ + rm ft1248_op.log ; \ + fi + @if [ -e uart.log ] ; then \ + rm uart.log ; \ + fi + @if [ -e uart0.log ] ; then \ + rm uart0.log ; \ + fi + @if [ -e uart1.log ] ; then \ + rm uart1.log ; \ + fi + @if [ -e uart2.log ] ; then \ + rm uart2.log ; \ + fi + @if [ -e uart3.log ] ; then \ + rm uart3.log ; \ + fi + @if [ -e vsim.wlf ] ; then \ + rm vsim.wlf ; \ + fi + @if [ -e image.hex ] ; then \ + rm image.hex ; \ + fi + @if [ -e date_file ] ; then \ + rm date_file ; \ + fi + @if [ -e bootrom.v ] ; then \ + rm bootrom.v ; \ + fi + @if [ -e bootrom.bintxt ] ; then \ + rm bootrom.bintxt ; \ + fi + @if [ -e bootloader.hex ] ; then \ + rm bootloader.hex ; \ + fi + @if [ -e debugtester_le.hex ] ; then \ + rm debugtester_le.hex ; \ + fi + @if [ -e debugtester_be.hex ] ; then \ + rm debugtester_be.hex ; \ + fi + @if [ -e compile_mti.log ] ; then \ + rm compile_mti.log ; \ + fi + @if [ -e vish_stacktrace.vstf ] ; then \ + rm vish_stacktrace.vstf ; \ + fi + @if [ -e compile_vcs.log ] ; then \ + rm compile_vcs.log ; \ + fi + @if [ -e compile_xm.log ] ; then \ + rm compile_xm.log ; \ + fi + @if [ -e transcript ] ; then \ + rm transcript ; \ + fi + @if [ -e simv ] ; then \ + rm simv ; \ + fi + @if [ -d csrc ] ; then \ + rm -rf csrc ; \ + fi + @if [ -d simv.daidir ] ; then \ + rm -rf simv.daidir ; \ + fi + @if [ -e inter.vpd ] ; then \ + rm -rf inter.vpd ; \ + fi + @if [ -e quit.do ] ; then \ + rm -rf quit.do ; \ + fi + @if [ -e ucli.key ] ; then \ + rm -rf ucli.key ; \ + fi + @if [ -d DVEfiles ] ; then \ + rm -rf DVEfiles ; \ + fi + @if [ -d INCA_libs ] ; then \ + rm -rf INCA_libs ; \ + fi + @if [ -d cov_work ] ; then \ + rm -rf cov_work ; \ + fi + @if [ -e hdl.var ] ; then \ + rm -rf hdl.var ; \ + fi + @if [ -e xmelab.args ] ; then \ + rm -rf xmelab.args ; \ + fi + @if [ -e xmvlog.args ] ; then \ + rm -rf xmvlog.args ; \ + fi + @if [ -e xmsim.args ] ; then \ + rm -rf xmsim.args ; \ + fi + @if [ -e xmprep.log ] ; then \ + rm -rf xmprep.log ; \ + fi + @if [ -e xmelab.log ] ; then \ + rm -rf xmelab.log ; \ + fi + @if [ -e xmvlog.log ] ; then \ + rm -rf xmvlog.log ; \ + fi + @if [ -e xmsim.log ] ; then \ + rm -rf xmsim.log ; \ + fi + @if [ -e run.tcl ] ; then \ + rm -rf run.tcl ; \ + fi + @if [ -e RUN_XM ] ; then \ + rm -rf RUN_XM ; \ + fi + @if [ -e xmsim.key ] ; then \ + rm -rf xmsim.key ; \ + fi + @if [ -e cds.lib ] ; then \ + rm -rf cds.lib ; \ + fi + @if [ -e logs ] ; then \ + rm -rf logs ; \ + fi + @if [ -e ../v2html_doc ] ; then \ + rm -rf ../v2html_doc ; \ + fi -- GitLab