diff --git a/flist/nanosoc_tb_qs.flist b/flist/nanosoc_tb_qs.flist
index 57addbc6b4e95de74136599c5a247c8cb8bc445d..ca472cde611a69b60767e1ffb79ca4b3fd6df03e 100644
--- a/flist/nanosoc_tb_qs.flist
+++ b/flist/nanosoc_tb_qs.flist
@@ -20,9 +20,11 @@
 
 // - Top-level testbench - QUICKSTART
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb_qs.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_target.v
+$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_tfsm.v
 
 // Include NanoSoC Testbench Components
 -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist
 
 // Include Corstone VIP Components - QUICKSTART
--f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist
\ No newline at end of file
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist