From ad92113034a95f8f6cce73c5c8f334cb471e4ee1 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 4 Jul 2023 10:09:26 +0100
Subject: [PATCH] Compiles testcode and bootrom before running package_nanosoc

---
 fpga/makefile | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/fpga/makefile b/fpga/makefile
index be5892e..e13f1da 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -47,7 +47,7 @@ TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
 NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
 
 # NanoSoC Defines File
-NANOSOC_DEFINES      ?= $(NANOSOC_FPGA_FLOW_DIR)/nanosoc_defines.tcl
+NANOSOC_DEFINES_FILE  ?= $(NANOSOC_FPGA_FLOW_DIR)/nanosoc_defines.tcl
 
 # Directory to look for FPGA specific implementation files
 TARGET_DIR            ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
@@ -72,6 +72,10 @@ else
 	ACCELERATOR_SUBSYSTEM = 0
 endif
 
+# Compile Testcodes and Bootrom
+code:
+	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) code
+
 # Generate TCL filelist from flists
 nanosoc_flist:
 	@mkdir -p $(TCL_FLIST_DIR)
@@ -80,11 +84,11 @@ nanosoc_flist:
 
 # Package NanoSoC Socket Components
 package_socket:
-	$(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket IMP_SOCKET_DIR=$(IMP_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)
+	@$(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket IMP_SOCKET_DIR=$(IMP_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)
 
 # Environment Variables for Packaging NanoSoC
 package_nanosoc: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
-package_nanosoc: export FPGA_COMPONENT_DEFINES  = $(NANOSOC_DEFINES)
+package_nanosoc: export FPGA_COMPONENT_DEFINES  = $(NANOSOC_DEFINES_FILE)
 package_nanosoc: export FPGA_COMPONENT_LIB      = $(IMP_NANOSOC_DIR)
 package_nanosoc: export FPGA_ACCELERATOR        = $(ACCELERATOR_SUBSYSTEM)
 package_nanosoc: export FPGA_DESIGN_TOP         = $(FPGA_TOP)
@@ -92,7 +96,7 @@ package_nanosoc: export FPGA_VENDOR             = $(VENDOR)
 package_nanosoc: export FPGA_CORE_REV           = $(NANOSOC_CORE_REV)
 
 # Package NanoSoC IP
-package_nanosoc: nanosoc_flist
+package_nanosoc: code nanosoc_flist
 	@echo Packaging NanoSoC
 	@mkdir -p $(RUN_DIR)
 	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
@@ -119,8 +123,17 @@ build_nanosoc_design:
 	@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
 	@echo Built NanoSoC Design
 
+# Move Output Files 
+output_nanosoc_design:
+	@echo Moving NanoSoC Design Files
+	@unzip -u -o $(PROJECT_DIR)/$(DESIGN_NAME).xsa -d $(PROJECT_DIR)/export
+	@mkdir -p $(OUTPUT_DIR)
+	@cp -p $(PROJECT_DIR)/export/$(DESIGN_NAME).bit $(OUTPUT_DIR)
+	@cp -p $(PROJECT_DIR)/export/$(DESIGN_NAME).hwh $(OUTPUT_DIR)
+	
 # Build NanoSoC Design Flow
-build_fpga: clean_fpga package_socket package_nanosoc build_nanosoc_design
+build_fpga: clean_fpga package_socket package_nanosoc build_nanosoc_design output_nanosoc_design
+	@echo NanoSOC Design Complete
 
 # Clean FPGA Run
 clean_fpga:
-- 
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