diff --git a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v index 81660001ef5235c139dc9bb7169a67d406a27060..453f69f6e07880e673d7a5053ee1fc31c9fe6dcf 100644 --- a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v +++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v @@ -119,8 +119,14 @@ module nanosoc_ss_dma #( //------------------------------- //DMA Controller 0 Instantiation //------------------------------- + wire DMAC_1_PSEL_IN; assign DMAC_1_PSEL_IN = DMAC_1_PSEL | DMAC_1_PSEL_HI; + + // DMA Status Tie-off signals + assign DMAC_0_DMA_DONE = {DMAC_0_CHANNEL_NUM{1'b0}}; + assign DMAC_0_DMA_ERR = 1'b0; + sldma350_ahb #( .SYS_ADDR_W (SYS_ADDR_W), .SYS_DATA_W (SYS_DATA_W), diff --git a/software/common/validation/dma350_tests.c b/software/common/validation/dma350_tests.c index 93e8ef29ddd62bb3d578b9822b9f1e4350397062..686f0365c4824836f9afbeec35f4044cc0f2c7d4 100644 --- a/software/common/validation/dma350_tests.c +++ b/software/common/validation/dma350_tests.c @@ -52,6 +52,12 @@ uint32_t LinkCmd[6]; // Variable to store the address of the above array uintptr_t LinkCmd_adr = (uintptr_t) LinkCmd; +volatile int dma_done_irq_occurred; +volatile int dma_done_irq_expected; +volatile int dma_error_irq_occurred; +volatile int dma_error_irq_expected; + +void delay(void); void SystemInitialization(void); int main(void) { @@ -375,6 +381,33 @@ int main(void) { printf("DMA transfer finished\n"); } + + printf("---STARTING 1D Command Tests With interrupts---\n"); + printf("Test BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n"); + for (uint32_t ch=0; ch < ch_num; ch++) { + // + // Write all settings to the DMA registers + AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE); + Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE); + SetAdaWrapRegs(command_1d_wrap, ch, SECURE); + AdaSetIntEn(ch_irqs, ch, SECURE); + + printf("DMA %d configured. Starting the transfer.\n", ch); + + dma_done_irq_expected = 1; + dma_done_irq_occurred = 0; + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_EnableIRQ(DMA_IRQn); + // Start DMA operation and wait for done IRQ + AdaEnable(ch, SECURE); + + __WFI(); + uint8_t ch_enabled = 1; + while (ch_enabled == 1) { + ch_enabled = AdaGetEnable(ch, SECURE); + } + printf("DMA transfer finished\n"); + } UartEndSimulation(); return 0; @@ -434,4 +467,21 @@ unsigned int address_test_read(unsigned int addr) " bx lr \n" ); } -#endif \ No newline at end of file +#endif + +void DMA_Handler(void){ + // Check the source of the interrupt and clear interrupts + printf("DMA Interrupted \n") + AdaStatType ST = AdaReadStatus(ch, NON_SECURE); + if (ST.STAT_DONE == 1) { + AdaClearChDone(ch, NON_SECURE); + } else if (ST.STAT_ERR == 1) { + AdaClearChError(ch, NON_SECURE); + } else if (ST.STAT_DISABLED == 1) { + AdaClearChDisabled(ch, NON_SECURE); + } else if (ST.STAT_STOPPED == 1) { + AdaClearChStopped(ch, NON_SECURE); + } else { + printf("Unknown IRQ on CH%d!\n", ch); + } +} \ No newline at end of file