From acef4af8481ec5c6dca703b610f649e18490fb63 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Tue, 8 Oct 2024 10:54:15 +0100
Subject: [PATCH] update and simplify zcu104 extio validation to 40MHz
---
.../vivado_script/2021_1/nanosoc_design.tcl | 75 +++++++------------
1 file changed, 27 insertions(+), 48 deletions(-)
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
index 5350e47..c60c93a 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
@@ -49,7 +49,6 @@ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:zynq_ultra_ps_e:3.3\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
-xilinx.com:ip:axi_uartlite:2.0\
xilinx.com:ip:axis_data_fifo:2.0\
soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:xlconcat:2.1\
@@ -130,7 +129,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
create_bd_pin -dir O -from 15 -to 0 p0_tri_i
create_bd_pin -dir I -from 15 -to 0 p0_tri_o
create_bd_pin -dir I -from 15 -to 0 p0_tri_z
- create_bd_pin -dir O -from 7 -to 0 p1_tri_i
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
create_bd_pin -dir I -from 15 -to 0 p1_tri_o
create_bd_pin -dir I -from 15 -to 0 p1_tri_z
create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
@@ -160,27 +159,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_stream_io_0, and set properties
set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
- # Create instance: axi_stream_io_1, and set properties
- set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
-
- # Create instance: axi_stream_io_2, and set properties
- set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
-
- # Create instance: axi_stream_io_3, and set properties
- set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
-
- # Create instance: axi_uartlite_0, and set properties
- set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
- set_property -dict [ list \
- CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
- ] $axi_uartlite_0
-
- # Create instance: axi_uartlite_1, and set properties
- set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
- set_property -dict [ list \
- CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
- ] $axi_uartlite_1
-
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list \
@@ -269,41 +247,45 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
- CONFIG.NUM_MI {8} \
+ CONFIG.NUM_MI {3} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
+ # Create instance: xlconcat_0, and set properties
+ set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $xlconcat_0
+
# Create instance: xlconst_zero, and set properties
set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
] $xlconst_zero
+ # Create instance: xlconst_zerox8, and set properties
+ set xlconst_zerox8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox8 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox8
+
# Create instance: xlconstant_1, and set properties
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
# Create interface connections
connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
- connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
- connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axi_stream_io_2/tx]
- connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axi_stream_io_3/tx]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
- connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/rx] [get_bd_pins axi_uartlite_0/tx]
- connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
@@ -312,7 +294,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins p1_extio_concat_z/In3]
- connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins p1_tri_i] [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout]
+ connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout] [get_bd_pins xlconcat_0/In0]
+ connect_bd_net -net p1_extio_concat_z_dout [get_bd_pins pmoda_tri_z] [get_bd_pins p1_extio_concat_z/dout]
connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins p1_o_bit0_ioreq1/Dout]
connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins p1_o_bit1_ioreq2/Dout]
connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins p1_o_bit3_iodatata4/Dout]
@@ -320,10 +303,11 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins p1_tri_i] [get_bd_pins xlconcat_0/dout]
+ connect_bd_net -net xlconst_zerox8_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconst_zerox8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -1126,10 +1110,10 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {38} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
@@ -1933,11 +1917,6 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
- assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
- assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
# Restore current instance
--
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