From a975485547e457621b7605d147b055833b5e67d5 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 30 Jun 2023 10:44:08 +0100
Subject: [PATCH] Updated Filelists
---
...atrix.flist => nanosoc_busmatrix_ip.flist} | 0
flist/nanosoc_ip.flist | 2 +-
flist/nanosoc_tb.flist | 28 ++++++++++++++++
flist/nanosoc_tb_qs.flist | 29 +++++++++++++++++
flist/nanosoc_vip.flist | 32 +++++++++++++++++++
system/socdebug_tech | 2 +-
6 files changed, 91 insertions(+), 2 deletions(-)
rename flist/{nanosoc_busmatrix.flist => nanosoc_busmatrix_ip.flist} (100%)
create mode 100644 flist/nanosoc_tb.flist
create mode 100644 flist/nanosoc_tb_qs.flist
create mode 100644 flist/nanosoc_vip.flist
diff --git a/flist/nanosoc_busmatrix.flist b/flist/nanosoc_busmatrix_ip.flist
similarity index 100%
rename from flist/nanosoc_busmatrix.flist
rename to flist/nanosoc_busmatrix_ip.flist
diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index a0d3f72..ecc9dec 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -34,7 +34,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
// Bus Matrix
--f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix.flist
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix_ip.flist
// NanoSoC Regions - Bootrom
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
diff --git a/flist/nanosoc_tb.flist b/flist/nanosoc_tb.flist
new file mode 100644
index 0000000..0933b8e
--- /dev/null
+++ b/flist/nanosoc_tb.flist
@@ -0,0 +1,28 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Testbench search path =============
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/
+
+// - Top-level testbench
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
+
+// Include NanoSoC Testbench Components
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist
+
+// Include Corstone VIP Components
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist
\ No newline at end of file
diff --git a/flist/nanosoc_tb_qs.flist b/flist/nanosoc_tb_qs.flist
new file mode 100644
index 0000000..c08e6b1
--- /dev/null
+++ b/flist/nanosoc_tb_qs.flist
@@ -0,0 +1,29 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Testbench Filelist - QUICKSTART
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+
+// ============= NanoSoC Testbench search path =============
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/
+
+// - Top-level testbench - QUICKSTART
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb_qs.v
+
+// Include NanoSoC Testbench Components
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist
+
+// Include Corstone VIP Components - QUICKSTART
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist
\ No newline at end of file
diff --git a/flist/nanosoc_vip.flist b/flist/nanosoc_vip.flist
new file mode 100644
index 0000000..549a31d
--- /dev/null
+++ b/flist/nanosoc_vip.flist
@@ -0,0 +1,32 @@
+//-----------------------------------------------------------------------------
+// NanoSoC VIP Components Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Testbench Components
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Testbench search path =============
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/
+
+// - Testbench components
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
+
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
\ No newline at end of file
diff --git a/system/socdebug_tech b/system/socdebug_tech
index d2b0337..cb454e4 160000
--- a/system/socdebug_tech
+++ b/system/socdebug_tech
@@ -1 +1 @@
-Subproject commit d2b0337147cdfb527cdbe82060083b8345834ebd
+Subproject commit cb454e4c550ff291d83b08b840c8a2399f4b6d4e
--
GitLab