diff --git a/flist/nanosoc_busmatrix.flist b/flist/nanosoc_busmatrix_ip.flist similarity index 100% rename from flist/nanosoc_busmatrix.flist rename to flist/nanosoc_busmatrix_ip.flist diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist index a0d3f72c4edea362f575444f5962f782b2f5adb5..ecc9dec080e727818300c9b560bc041b8447076c 100644 --- a/flist/nanosoc_ip.flist +++ b/flist/nanosoc_ip.flist @@ -34,7 +34,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v // Bus Matrix --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix.flist +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix_ip.flist // NanoSoC Regions - Bootrom $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v diff --git a/flist/nanosoc_tb.flist b/flist/nanosoc_tb.flist new file mode 100644 index 0000000000000000000000000000000000000000..0933b8e0f7359d5ccfd98b5bc0be530516df6672 --- /dev/null +++ b/flist/nanosoc_tb.flist @@ -0,0 +1,28 @@ +//----------------------------------------------------------------------------- +// NanoSoC Testbench Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Testbench search path ============= ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/ + +// - Top-level testbench +$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v + +// Include NanoSoC Testbench Components +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist + +// Include Corstone VIP Components +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist \ No newline at end of file diff --git a/flist/nanosoc_tb_qs.flist b/flist/nanosoc_tb_qs.flist new file mode 100644 index 0000000000000000000000000000000000000000..c08e6b15844db68249ec7d6eff908dd3f1e030c0 --- /dev/null +++ b/flist/nanosoc_tb_qs.flist @@ -0,0 +1,29 @@ +//----------------------------------------------------------------------------- +// NanoSoC Testbench Filelist - QUICKSTART +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + + +// ============= NanoSoC Testbench search path ============= ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/ + +// - Top-level testbench - QUICKSTART +$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb_qs.v + +// Include NanoSoC Testbench Components +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_vip.flist + +// Include Corstone VIP Components - QUICKSTART +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip_qs.flist \ No newline at end of file diff --git a/flist/nanosoc_vip.flist b/flist/nanosoc_vip.flist new file mode 100644 index 0000000000000000000000000000000000000000..549a31d2066442b4961c12fb662f8cf1963676e5 --- /dev/null +++ b/flist/nanosoc_vip.flist @@ -0,0 +1,32 @@ +//----------------------------------------------------------------------------- +// NanoSoC VIP Components Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for NanoSoC Testbench Components +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= NanoSoC Testbench search path ============= ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/ ++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/ + +// - Testbench components +$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v + +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v +$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v \ No newline at end of file diff --git a/system/socdebug_tech b/system/socdebug_tech index d2b0337147cdfb527cdbe82060083b8345834ebd..cb454e4c550ff291d83b08b840c8a2399f4b6d4e 160000 --- a/system/socdebug_tech +++ b/system/socdebug_tech @@ -1 +1 @@ -Subproject commit d2b0337147cdfb527cdbe82060083b8345834ebd +Subproject commit cb454e4c550ff291d83b08b840c8a2399f4b6d4e