From a83e8c97ec6c79b4bea7ee8a1132dfd767ba5cbe Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Mon, 14 Aug 2023 15:59:41 +0100
Subject: [PATCH] update ASIC flow
---
.gitignore | 3 +-
flist/corstone101_ip_ASIC.flist | 5 ++
flist/nanosoc_ASIC.flist | 4 +-
flows/makefile.asic | 77 +++++++++++++++++++
flows/makefile.fpga | 6 --
makefile | 5 +-
.../verilog/nanosoc_region_expram_h.v | 14 ++++
nanosoc/slcorem0_tech | 2 +-
nanosoc/sldma230_tech | 2 +-
synthesis/constraints.sdc | 44 +++++++++++
synthesis/genus.tcl | 5 +-
synthesis/synopsys.tcl | 38 +++++++--
12 files changed, 183 insertions(+), 22 deletions(-)
create mode 100644 flows/makefile.asic
create mode 100644 synthesis/constraints.sdc
diff --git a/.gitignore b/.gitignore
index b70865a..6cddaa5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -27,5 +27,6 @@ sim
work
-*.log
+*.log*
+*.cmd*
*.jou
\ No newline at end of file
diff --git a/flist/corstone101_ip_ASIC.flist b/flist/corstone101_ip_ASIC.flist
index f23121f..6e7fa9c 100644
--- a/flist/corstone101_ip_ASIC.flist
+++ b/flist/corstone101_ip_ASIC.flist
@@ -28,6 +28,8 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+
// CMSDK APB UART IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
@@ -37,6 +39,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
// CMSDK APB Slave Mux IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
@@ -77,6 +80,8 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_ga
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v
diff --git a/flist/nanosoc_ASIC.flist b/flist/nanosoc_ASIC.flist
index 0ca6250..3b3bbe6 100644
--- a/flist/nanosoc_ASIC.flist
+++ b/flist/nanosoc_ASIC.flist
@@ -24,10 +24,10 @@
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_ip_ASIC.flist
// SLCore Files
--f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0.flist
+-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ASIC.flist
// Debug IP
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
// DMAC IP
--f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip_ASIC.flist
diff --git a/flows/makefile.asic b/flows/makefile.asic
new file mode 100644
index 0000000..c663c72
--- /dev/null
+++ b/flows/makefile.asic
@@ -0,0 +1,77 @@
+#-----------------------------------------------------------------------------
+# NanoSoC FPGA Flow Makefile
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+# NanoSoC Synthesis Properties
+NANOSOC_VENDOR ?= soclabs.org
+NANOSOC_CORE_REV ?= 2
+
+# Top-level of RTL design to Implement
+COMPONENT_TOP ?= nanosoc_chip_pads
+
+# Name of Implemented Chip Design (Including Socket IP)
+DESIGN_NAME ?= nanosoc_design
+
+# Location to build ASIC files
+IMP_NANOSOC_ASIC_DIR := $(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc
+
+# Location of Defines File
+DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/
+DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v
+
+# Name of generated filelist by python script
+TCL_FLIST_DIR := $(IMP_NANOSOC_ASIC_DIR)/flist
+TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
+GENUS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/genus_flist.tcl
+SYNTHESIS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/synth_flist_copy.sh
+
+# NanoSoC Tech Flow Dependencies
+NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
+
+# Directory to look for FPGA specific implementation files
+TARGET_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)
+TARGET_TCL_DIR := $(TARGET_DIR)/vivado_script/$(VIVIADO_VERSION)
+PINMAP_FILE ?= $(TARGET_DIR)/fpga_pinmap.xdc
+
+# NanoSoC Tech Socket Design Dependencies
+RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
+
+flist_asic_nanosoc: gen_defs
+ @mkdir -p $(TCL_FLIST_DIR)
+ @(cd $(TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(SYNTHESIS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
+
+flist_genus_nanosoc: gen_defs
+ @mkdir -p $(TCL_FLIST_DIR)
+ @(cd $(TCL_FLIST_DIR); \
+ $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
+
+
+
+#copy_asic_nanosoc: SHELL:=/bin/bash
+copy_asic_nanosoc: flist_asic_nanosoc
+ @mkdir -p $(IMP_NANOSOC_ASIC_DIR)/src
+ @(cd $(IMP_NANOSOC_ASIC_DIR)/src)
+ @(chmod +x $(SYNTHESIS_OUTPUT_FILELIST))
+ @(source $(SYNTHESIS_OUTPUT_FILELIST))
+
+# Clean FPGA Run
+clean_synthesis:
+ @echo Cleaning Previous Runs of $(BOARD_NAME)
+ @rm -rf $(PROJECT_DIR)
+ @rm -rf $(RUN_DIR)
+
+# Clean ALL FPGA Implementation Directory
+clean_synthesis_all:
+ @echo Cleaning FPGA Implementation Directory
+ @rm -rf $(IMP_NANOSOC_ASIC_DIR)
+ @rm -rf
+ @echo Cleaning Firmware
+ @$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) clean_all_code
\ No newline at end of file
diff --git a/flows/makefile.fpga b/flows/makefile.fpga
index 1e52c09..fc041a0 100644
--- a/flows/makefile.fpga
+++ b/flows/makefile.fpga
@@ -70,12 +70,6 @@ flist_tcl_nanosoc: gen_defs
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
-flist_genus_nanosoc: gen_defs
- @mkdir -p $(TCL_FLIST_DIR)
- @(cd $(TCL_FLIST_DIR); \
- $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
-
-
# Package NanoSoC Socket Components
package_socket:
@$(MAKE) -C $(SOCLABS_SOCDEBUG_TECH_DIR)/fpga package_socket IMP_SOCKET_DIR=$(IMP_SOCKET_DIR) RTL_SOCKET_DIR=$(RTL_SOCKET_DIR)
diff --git a/makefile b/makefile
index 123c4b8..9833a53 100644
--- a/makefile
+++ b/makefile
@@ -77,7 +77,7 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
- NANOSOC_DEFINES += DMAC_0_PL230
+ NANOSOC_DEFINES += DMAC_0_PL230 POWER_PINS
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
@@ -114,6 +114,9 @@ include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.regression
# Include FPGA Makefile
include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.fpga
+# Include Synthesis Makefile
+include $(SOCLABS_NANOSOC_TECH_DIR)/flows/makefile.asic
+
#------------------------------------------
# - Common Targets Across Flows
#------------------------------------------
diff --git a/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v b/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
index 69d35a3..f41da67 100644
--- a/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+++ b/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
@@ -17,6 +17,13 @@ module nanosoc_region_expram_h #(
parameter EXPRAM_H_RAM_ADDR_W = 14, // Width of RAM Address - Default 16KB
parameter EXPRAM_H_RAM_DATA_W = 32 // Width of RAM Data Bus - Default 32 bits
)(
+ `ifdef POWER_PINS
+ inout wire VDDCE,
+ inout wire VDDPE,
+ inout wire VSSE,
+ inout wire VDD,
+ inout wire VSS,
+ `endif
input wire HCLK,
input wire HRESETn,
@@ -41,6 +48,13 @@ module nanosoc_region_expram_h #(
.RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W),
.RAM_DATA_W (EXPRAM_H_RAM_DATA_W)
) u_expram_h (
+ `ifdef POWER_PINS
+ .VDDCE (VDDCE),
+ .VDDPE (VDDPE),
+ .VSSE (VSSE),
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/nanosoc/slcorem0_tech b/nanosoc/slcorem0_tech
index 2714253..0be6321 160000
--- a/nanosoc/slcorem0_tech
+++ b/nanosoc/slcorem0_tech
@@ -1 +1 @@
-Subproject commit 27142533eecdb9d8c337b778a479210ec6bcc661
+Subproject commit 0be6321f76ef5b68bd91c77f4698b775bffccdad
diff --git a/nanosoc/sldma230_tech b/nanosoc/sldma230_tech
index 431c5a7..38ce5b5 160000
--- a/nanosoc/sldma230_tech
+++ b/nanosoc/sldma230_tech
@@ -1 +1 @@
-Subproject commit 431c5a7933bcbde8da0d584f850384e6e8c3ed3b
+Subproject commit 38ce5b55d3d3af4c2a21496c037ac48c3a7c071b
diff --git a/synthesis/constraints.sdc b/synthesis/constraints.sdc
new file mode 100644
index 0000000..14f09d2
--- /dev/null
+++ b/synthesis/constraints.sdc
@@ -0,0 +1,44 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Constraints for Synthesis
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#### CLOCK DEFINITION
+
+set EXTCLK "clk";
+set_units -time 1.0ns;
+
+set_units -capacitance 1.0pF;
+set EXTCLK_PERIOD 10.0;
+
+create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports XTAL1]
+
+set SKEW 0.200
+set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
+
+set MINRISE 0.20
+set MAXRISE 0.25
+set MINFALL 0.20
+set MAXFALL 0.25
+
+set_clock_transition -rise -min $MINRISE [get_clocks $EXTCLK]
+set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+
+#### DELAY DEFINITION
+
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports SWDIOTMS]
+set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports SWCLKTCK]
+
+set_max_capacitance 0.5 [all_outputs]
+set_max_fanout 10 [all_inputs]
\ No newline at end of file
diff --git a/synthesis/genus.tcl b/synthesis/genus.tcl
index 0c07cc3..ea13d31 100644
--- a/synthesis/genus.tcl
+++ b/synthesis/genus.tcl
@@ -3,9 +3,10 @@ set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/sc9_cln65lp_
set RF_LIB ../../../cadence_flow/memory/rf/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
set_db / .library "$BASE_LIB $RF_LIB"
-source $::env(SOCLABS_PROJECT_DIR)/imp/fpga/nanosoc/flist/genus_flist.tcl
-
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
elaborate nanosoc_chip_pads
+source constraints.sdc
+
set_db syn_generic_effort high
syn_generic
diff --git a/synthesis/synopsys.tcl b/synthesis/synopsys.tcl
index 71c9517..77d91ea 100644
--- a/synthesis/synopsys.tcl
+++ b/synthesis/synopsys.tcl
@@ -1,5 +1,6 @@
-create_design nanosoc_ASIC
-
+set rtlPath $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/
+set top_module nanosoc_chip_pads
+supress_message = {ELAB-405}
#####
# Set search_path
#
@@ -7,7 +8,7 @@ create_design nanosoc_ASIC
#
#####
set search_path [list . $search_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/sdb/ /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/ /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf]
-
+set search_path [concat $rtlPath $search_path]
######
# Set Target Library
#
@@ -22,15 +23,36 @@ set target_library "sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db RF_LIB_tt_1
# Set a default link library for Design Compiler to target when compiling a design
#
######
-set link_library sc9_cln65lp_base_rvt.sdb
+set link_library sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db
+
+#read_file {/home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/} -autoread -recursive -format verilog -top $top_module
+
+analyze -format verilog -lib WORK -define POWER_PINS [glob /home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/*.v]
+analyze -format sverilog -lib WORK -define POWER_PINS [glob /home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/*.sv]
+elaborate $top_module -lib WORK -update
+current_design $top_module
+
+# Link Design
+link
+
+create_clock XTAL1 -period 10 -waveform {0 5}
+set_clock_latency 0.3 XTAL1
+set_input_delay 1.0 -clock XTAL1 [all_inputs]
+set_output_delay 0.7 -clock XTAL1 [all_outputs]
+set_load 0.1 [all_outputs]
+set_max_fanout 1 [all_inputs]
+set_fanout_load 8 [all_outputs]
-source $::env(SOCLABS_PROJECT_DIR)/imp/fpga/nanosoc/flist/synopsys_flist.tcl
-
-current_design nanosoc_chip_pads
+redirect [format "%s%s%s" ./ $top_module _ports.rep { report_ports }
-compile
+compile_ultra -exact_map
write -hierarchy -format verilog -output ./nanosoc_chip_pads.vm
+redirect [format "%s%s%s" ./ $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" ./ $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" ./ $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" ./ $top_module _timing.rep] \
+ { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
exit
\ No newline at end of file
--
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