From a055cc846832539d9f731ceed9d5c38782d76800 Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Wed, 22 May 2024 14:42:00 +0100
Subject: [PATCH] Add support for ADP Program load in simulation
---
makefile | 7 +++++++
verif/tb/verilog/nanosoc_tb.v | 9 ++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/makefile b/makefile
index 16c4ae0..95e7e04 100644
--- a/makefile
+++ b/makefile
@@ -27,6 +27,8 @@ QUICKSTART ?= no
ASIC ?= no
+FAST_SIM ?= yes
+
#-------------------------------------
# - Directory Setups
#-------------------------------------
@@ -65,6 +67,11 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif
+ifeq ($(FAST_SIM),yes)
+ DEFINES_VC += +define+FAST_SIM
+ NANOSOC_DEFINES += FAST_SIM
+endif
+
# System Design Filelist
ifeq ($(QUICKSTART),yes)
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 8f41a20..b963333 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -319,9 +319,16 @@ reg baud_clk_del;
wire rxd8_tvalid;
wire [7:0] rxd8_tdata ;
+`ifdef FAST_SIM
+ parameter FAST_LOAD = 1;
+`else
+ parameter FAST_LOAD = 0;
+`endif
+
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
- .TXDFILENAME(ADP_FILENAME)
+ .TXDFILENAME(ADP_FILENAME),
+ .FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (CLK),
.aresetn (NRST),
--
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