From 9cbbf87fb040a4036db98a5015195093a50924b3 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 30 Jun 2023 16:37:54 +0100
Subject: [PATCH] Updated Waivers and filelists
---
flist/nanosoc_tb.flist | 1 -
flist/nanosoc_tb_qs.flist | 1 -
flist/nanosoc_vip.flist | 3 -
hal/corstone101_ip.bb | 4 -
hal/nanosoc_ip.bb | 4 +
hal/nanosoc_ip.waive | 80 +++++++++++++++++++
makefile | 4 +-
.../nanosoc_chip/chip/verilog/nanosoc_chip.v | 15 ++--
.../bootrom_0/verilog/nanosoc_bootrom_cpu_0.v | 27 ++++---
.../verilog/nanosoc_region_bootrom_0.v | 5 +-
.../ram/verilog/nanosoc_region_imem_0.v | 4 +-
.../rom/verilog/nanosoc_region_imem_0.v | 4 +-
.../cpu/verilog/nanosoc_ss_cpu.v | 4 +-
.../verilog/nanosoc_ss_interconnect.v | 8 +-
.../nanosoc_system/verilog/nanosoc_system.v | 44 +++++-----
system/slcorem0_tech | 2 +-
system/sldma230_tech | 2 +-
system/socdebug_tech | 2 +-
verif/tb/verilog/nanosoc_tb.v | 2 -
verif/tb/verilog/nanosoc_tb_qs.v | 2 -
20 files changed, 149 insertions(+), 69 deletions(-)
diff --git a/flist/nanosoc_tb.flist b/flist/nanosoc_tb.flist
index 0933b8e..8873895 100644
--- a/flist/nanosoc_tb.flist
+++ b/flist/nanosoc_tb.flist
@@ -16,7 +16,6 @@
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/
// - Top-level testbench
$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v
diff --git a/flist/nanosoc_tb_qs.flist b/flist/nanosoc_tb_qs.flist
index c08e6b1..57addbc 100644
--- a/flist/nanosoc_tb_qs.flist
+++ b/flist/nanosoc_tb_qs.flist
@@ -17,7 +17,6 @@
// ============= NanoSoC Testbench search path =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/
// - Top-level testbench - QUICKSTART
$(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb_qs.v
diff --git a/flist/nanosoc_vip.flist b/flist/nanosoc_vip.flist
index 549a31d..7b8db83 100644
--- a/flist/nanosoc_vip.flist
+++ b/flist/nanosoc_vip.flist
@@ -16,9 +16,6 @@
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/
-
// - Testbench components
$(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v
diff --git a/hal/corstone101_ip.bb b/hal/corstone101_ip.bb
index 8f944ce..62b87b4 100644
--- a/hal/corstone101_ip.bb
+++ b/hal/corstone101_ip.bb
@@ -69,8 +69,4 @@ bb_list
// Exclude APB Test slave as Arm IP
designunit = cmsdk_apb_test_slave;
file = $ARM_CORSTONE_101_DIR/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v;
-
- // Exclude Pads
- designunit = PAD_INOUT8MA_NOE;
- file = $SOCLABS_GENERIC_LIB_TECH_DIR/pads/verilog/PAD_INOUT8MA_NOE.v;
}
\ No newline at end of file
diff --git a/hal/nanosoc_ip.bb b/hal/nanosoc_ip.bb
index 0c16ed0..0ad69c3 100644
--- a/hal/nanosoc_ip.bb
+++ b/hal/nanosoc_ip.bb
@@ -25,4 +25,8 @@ bb_list
// Temporarily Exclude Accelerator Subsystem (just linting NanoSoC)
designunit = accelerator_subsystem;
file = $SOCLABS_PROJECT_DIR/system/src/accelerator_subsystem.v;
+
+ // Exclude Pads
+ designunit = PAD_INOUT8MA_NOE;
+ file = $SOCLABS_GENERIC_LIB_TECH_DIR/pads/verilog/PAD_INOUT8MA_NOE.v;
}
\ No newline at end of file
diff --git a/hal/nanosoc_ip.waive b/hal/nanosoc_ip.waive
index ce19aa1..d962f61 100644
--- a/hal/nanosoc_ip.waive
+++ b/hal/nanosoc_ip.waive
@@ -23,8 +23,60 @@ lint_checking designunit = nanosoc_chip_pads
lint_checking designunit = nanosoc_chip
{
+ // Not top-level of design
+ ATLGLC off;
+
// Combinatorial Wiring of outputs in top level of hierarchy
CBPAHI off;
+
+ // CLock Generation Logic around extraneous logic
+ CLKGNP off;
+
+ // Doesn't recognise XTAL as Clock or PORESETn as reset
+ CLKUCL {"XTAL|PORESTn"} off;
+
+ // Renaming of nrst_i to PRESETn
+ RSTUCL {"PRESETn"} off;
+
+ // Constant conditional expression for SYS_TESTMODE
+ CONSTC {"TESTMODE"} off;
+
+ // Pin Mux and FT signals driven by same pin
+ DALIAS {"P1_IN_MUX"} off;
+
+ // Renamed System Reset
+ DIFRST {"SYS_SYSRESETn"} off;
+
+ // Combinatorial path for Crystal Clock Input->Output
+ IOCOMB {"xtal_clk"} off;
+
+ // FT Signals One-pin Bus
+ ONPNSG {"FT_MIOSIO"} off;
+
+ // Some Pins are Tied Off
+ TIELOG {"p1_o|p1_e|p1_z"} off;
+
+ // Not Top-level in design_info
+ TPOUNR off;
+
+ // Intentionally Unconnected Signals
+ // - Chip Port Signals : P0 | P1
+ // - Scanchain output disconnected
+ UNCONO {"P0|P1|SYS_SCANOUTHCLK"} off;
+ URDWIR {"P0|P1|SYS_SCANOUTHCLK"} off;
+}
+
+lint_checking designunit = nanosoc_system
+{
+ // FT Signals One-pin Bus
+ ONPNSG {"FT_MIOSIO"} off;
+
+ // Intentionally Unconnected Signals
+ // - AHB Signals: HMASTLOCK | HBURST
+ // - System Control: CPU_0_TXEV - unused
+ // - APB SS IRQs: [3:0] are unused
+ UNCONO {"HMASTLOCK|HBURST|TXEV|SYS_APB_IRQ"} off;
+ URDWIR {"HMASTLOCK|HBURST|TXEV|SYS_APB_IRQ"} off;
}
lint_checking designunit = nanosoc_ss_cpu
@@ -125,18 +177,39 @@ lint_checking designunit = nanosoc_region_bootrom_0
{
// Some Bits of AHB Signals not Used
URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+
+ // AHB Signals bits unused:
+ // - HADDR - BITS 0 & 1
+ // - TRANS - BIT 0
+ // - HSIZE
+ // - HWDATA
+ // - HPROT
+ USEPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
}
lint_checking designunit = nanosoc_region_imem_0
{
// Some Bits of AHB Signals not Used
URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+
+ // Filename not used in SRAM
+ USEPAR {"IMEM_MEM_FPGA_IMG"} off;
+
+ // AHB Signals bits unused:
+ // - HADDR - BITS 31:15
+ // - HPROT
+ USEPRT {"HADDR|HPROT"} off;
}
lint_checking designunit = nanosoc_region_dmem_0
{
// Some Bits of AHB Signals not Used
URDPRT {"HADDR|HTRANS|HSIZE|HWDATA|HPROT"} off;
+
+ // AHB Signals bits unused:
+ // - HADDR - BITS 31:15
+ // - HPROT
+ USEPRT {"HADDR|HPROT"} off;
}
lint_checking designunit = nanosoc_region_expram_l
@@ -174,6 +247,7 @@ lint_checking designunit = nanosoc_bootrom_cpu_0
// Some Bits of AHB Signals not Used
URDPRT {"HADDR|HTRANS|HSIZE|HWDATA"} off;
+ USEPRT {"HADDR|HTRANS|HSIZE|HWDATA"} off;
}
lint_checking designunit = bootrom
@@ -292,6 +366,9 @@ lint_checking designunit = nanosoc_sysctrl
// Some AHB Signals unused
USEPRT {"HTRANS|HSIZE"} off;
+
+ // Asynchronous Reset
+ ACNCPI {"RESETn"} off;
}
lint_checking designunit = nanosoc_sysio_apb_ss
@@ -326,6 +403,9 @@ lint_checking designunit = nanosoc_sysio_apb_ss
// TODO: Uart Crossover needs looking at
USEPRT {"uart0_rxd|uart1_rxd"} off;
+
+ // Asynchronous Reset
+ ACNCPI {"HRESETn"} off;
}
lint_checking designunit = nanosoc_coresight_systable
diff --git a/makefile b/makefile
index 29ee06b..382daf5 100644
--- a/makefile
+++ b/makefile
@@ -220,14 +220,14 @@ all_vcs : compile_vcs bootrom debugtester
compile_xm : bootrom
@echo ADP_FILE
@echo $(ADP_OPTIONS)
- cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top $(TB_TOP) | tee compile_xm.log
+ cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log
cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_ver.args | tee -a compile_xm.log
cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
lint_xm: bootrom
@rm -rf $(LINT_DIR)
@mkdir -p $(LINT_DIR)
- cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ps/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
+ cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ns/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
# Note : If coverage is required, you can add -coverage all to xmelab
diff --git a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
index cfcbe68..473972b 100644
--- a/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -36,8 +36,8 @@ module nanosoc_chip #(
// Scan Wiring
wire SYS_SCANENABLE; // Scan Mode Enable
wire SYS_TESTMODE; // Test Mode Enable (Override Synchronisers)
- wire INC_SCANINHCLK; // HCLK scan wire
- wire INC_SCANOUTHCLK; // Scan Chain Output
+ wire SYS_SCANINHCLK; // HCLK scan wire
+ wire SYS_SCANOUTHCLK; // Scan Chain Output - UNUSED
// Serial-Wire Debug
wire CPU_0_SWDI; // SWD data input
@@ -64,7 +64,6 @@ module nanosoc_chip #(
wire [15:0] P0_OUTEN; // GPIO 0 output enables
wire [15:0] P0_ALTFUNC; // GPIO 0 alternate function (pin mux)
- wire [15:0] P1_IN; // GPIO 1 inputs
wire [15:0] P1_IN_MUX; // level-shifted input from pad
wire [15:0] P1_OUT; // GPIO 1 outputs
wire [15:0] P1_OUTEN; // GPIO 1 output enables
@@ -83,9 +82,9 @@ module nanosoc_chip #(
assign PLL_CLK = xtal_clk_i; // Default to no PLL
- assign SYS_SCANENABLE = 1'b0;
- assign SYS_TESTMODE = 1'b0;
- assign INC_SCANINHCLK = 1'b0;
+ assign SYS_SCANENABLE = 1'b0;
+ assign SYS_TESTMODE = 1'b0;
+ assign SYS_SCANINHCLK = 1'b0;
//--------------------------
// Clock Wiring
@@ -159,8 +158,8 @@ module nanosoc_chip #(
// Scan Wiring
.SYS_SCANENABLE(SYS_SCANENABLE),
.SYS_TESTMODE(SYS_TESTMODE),
- .INC_SCANINHCLK(INC_SCANINHCLK),
- .INC_SCANOUTHCLK(INC_SCANOUTHCLK),
+ .SYS_SCANINHCLK(SYS_SCANINHCLK),
+ .SYS_SCANOUTHCLK(SYS_SCANOUTHCLK),
// Serial-Wire Debug
.CPU_0_SWDI(CPU_0_SWDI),
diff --git a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
index 3fb1394..4fc4d0d 100644
--- a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
+++ b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
@@ -10,19 +10,20 @@
//-----------------------------------------------------------------------------
module nanosoc_bootrom_cpu_0 #(
- parameter AW = 10 // Address width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter BOOTROM_ADDR_W = 10 // Size of Bootrom (Based on Address Width) - Default 1KB
)(
- input wire HCLK, // Clock
- input wire HSEL, // Device select
- input wire [AW-1:0] HADDR, // Address
- input wire [1:0] HTRANS, // Transfer control
- input wire [2:0] HSIZE, // Transfer size
- input wire HWRITE, // Write control
- input wire [31:0] HWDATA, // Write data - not used
- input wire HREADY, // Transfer phase done
- output wire HREADYOUT, // Device ready
- output wire [31:0] HRDATA, // Read data output
- output wire HRESP // Device response (always OKAY)
+ input wire HCLK, // Clock
+ input wire HSEL, // Device select
+ input wire [BOOTROM_ADDR_W-1:0] HADDR, // Address
+ input wire [1:0] HTRANS, // Transfer control
+ input wire [2:0] HSIZE, // Transfer size
+ input wire HWRITE, // Write control
+ input wire [SYS_DATA_W-1:0] HWDATA, // Write data - not used
+ input wire HREADY, // Transfer phase done
+ output wire HREADYOUT, // Device ready
+ output wire [SYS_DATA_W-1:0] HRDATA, // Read data output
+ output wire HRESP // Device response (always OKAY)
);
//------------------------
// Internal Wiring
@@ -36,7 +37,7 @@ module nanosoc_bootrom_cpu_0 #(
bootrom u_bootrom (
.CLK (HCLK),
.EN (EN),
- .W_ADDR (HADDR[AW-1:2]),
+ .W_ADDR (HADDR[BOOTROM_ADDR_W-1:2]),
.RDATA (HRDATA)
);
diff --git a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
index 6a537e9..1fadc7d 100644
--- a/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
+++ b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
@@ -34,11 +34,12 @@ module nanosoc_region_bootrom_0 #(
);
nanosoc_bootrom_cpu_0 #(
- .AW (BOOTROM_ADDR_W)
+ .SYS_DATA_W (SYS_DATA_W),
+ .BOOTROM_ADDR_W (BOOTROM_ADDR_W)
) u_bootrom_cpu_0 (
.HCLK (HCLK),
.HSEL (HSEL),
- .HADDR (HADDR[9:0]),
+ .HADDR (HADDR[BOOTROM_ADDR_W-1:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
diff --git a/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v
index fc45b84..7c7c0e2 100644
--- a/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v
+++ b/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v
@@ -16,7 +16,7 @@ module nanosoc_region_imem_0 #(
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
- parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
+ parameter IMEM_MEM_FPGA_IMG = "image.hex" // Image to Preload into SRAM - NOT USED
)(
input wire HCLK,
input wire HRESETn,
@@ -40,7 +40,7 @@ module nanosoc_region_imem_0 #(
sl_ahb_sram #(
.SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
- .RAM_DATA_W (IMEM_RAM_DATA_W),
+ .RAM_DATA_W (IMEM_RAM_DATA_W)
) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
diff --git a/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
index 70e74e8..f5575d6 100644
--- a/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
+++ b/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
@@ -16,7 +16,7 @@ module nanosoc_region_imem_0 #(
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
- parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
+ parameter IMEM_MEM_FPGA_IMG = "image.hex" // Image to Preload into ROM
)(
input wire HCLK,
input wire HRESETn,
@@ -41,7 +41,7 @@ module nanosoc_region_imem_0 #(
.SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
.RAM_DATA_W (IMEM_RAM_DATA_W),
- .FILENAME (IMEM_RAM_FPGA_IMG)
+ .FILENAME (IMEM_MEM_FPGA_IMG)
) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
diff --git a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
index 8580b39..fbb18ed 100644
--- a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+++ b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -37,7 +37,7 @@ module nanosoc_ss_cpu #(
// IMEM 0 Parameters
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
- parameter IMEM_RAM_FPGA_IMG = "image.hex", // Image to Preload into SRAM
+ parameter IMEM_MEM_FPGA_IMG = "image.hex", // Image to Preload into SRAM
// DMEM 0 Parameters
parameter DMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
@@ -240,7 +240,7 @@ module nanosoc_ss_cpu #(
.SYS_DATA_W (SYS_DATA_W),
.IMEM_RAM_ADDR_W (IMEM_RAM_ADDR_W),
.IMEM_RAM_DATA_W (IMEM_RAM_DATA_W),
- .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG)
+ .IMEM_MEM_FPGA_IMG (IMEM_MEM_FPGA_IMG)
) u_region_imem_0 (
// Clock and Reset
.HCLK(SYS_HCLK),
diff --git a/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v b/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
index 1f5697c..155dbee 100644
--- a/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
+++ b/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
@@ -18,8 +18,8 @@ module nanosoc_ss_interconnect #(
input wire SYS_HCLK, // AHB System Clock
input wire SYS_HRESETn, // AHB System Reset
input wire SYS_SCANENABLE, // Scan enable signal
- input wire INC_SCANINHCLK, // HCLK scan input wire
- output wire INC_SCANOUTHCLK, // Scan Chain Output
+ input wire SYS_SCANINHCLK, // HCLK scan input wire
+ output wire SYS_SCANOUTHCLK, // Scan Chain Output
// System Address Remap control
input wire [3:0] SYS_REMAP_CTRL, // System Address REMAP control
@@ -205,8 +205,8 @@ module nanosoc_ss_interconnect #(
.HCLK (SYS_HCLK), // AHB System Clock
.HRESETn (SYS_HRESETn), // AHB System Reset
.SCANENABLE (SYS_SCANENABLE), // Scan enable signal
- .SCANINHCLK (INC_SCANINHCLK), // HCLK scan input wire
- .SCANOUTHCLK (INC_SCANOUTHCLK), // Scan Chain Output
+ .SCANINHCLK (SYS_SCANINHCLK), // HCLK scan input wire
+ .SCANOUTHCLK (SYS_SCANOUTHCLK), // Scan Chain Output
// System Address Remap control
.REMAP (SYS_REMAP_CTRL), // System Address REMAP control
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index c5fe7fb..fd2baef 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -24,7 +24,7 @@ module nanosoc_system #(
// IMEM 0 Parameters
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
- parameter IMEM_RAM_FPGA_IMG = "image.hex", // Image to Preload into SRAM
+ parameter IMEM_MEM_FPGA_IMG = "image.hex", // Image to Preload into SRAM
// DMEM 0 Parameters
parameter DMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
@@ -80,8 +80,8 @@ module nanosoc_system #(
// Scan Wiring
input wire SYS_SCANENABLE, // Scan Mode Enable
input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
- input wire INC_SCANINHCLK, // HCLK scan input wire
- output wire INC_SCANOUTHCLK, // Scan Chain Output
+ input wire SYS_SCANINHCLK, // HCLK scan input wire
+ output wire SYS_SCANOUTHCLK, // Scan Chain Output
// Serial-Wire Debug
input wire CPU_0_SWDI, // SWD data input
@@ -234,6 +234,10 @@ module nanosoc_system #(
wire CPU_0_SLEEPING; // Processor status - sleeping
wire CPU_0_SLEEPDEEP; // Processor status - deep sleep
+ // Interrupt Wiring
+ //--------------------------
+ assign CPU_0_NMI = SYS_NMI;
+
// Instantiate Subsystem
//--------------------------
@@ -254,7 +258,7 @@ module nanosoc_system #(
.BOOTROM_ADDR_W (BOOTROM_ADDR_W),
.IMEM_RAM_ADDR_W (IMEM_RAM_ADDR_W),
.IMEM_RAM_DATA_W (IMEM_RAM_DATA_W),
- .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG),
+ .IMEM_MEM_FPGA_IMG (IMEM_MEM_FPGA_IMG),
.DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
.DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
) u_ss_cpu (
@@ -336,7 +340,7 @@ module nanosoc_system #(
.DMEM_0_HREADYOUT(DMEM_0_HREADYOUT),
// CPU Sideband signalling
- .CPU_0_NMI(SYS_NMI),
+ .CPU_0_NMI(CPU_0_NMI),
.CPU_0_IRQ(CPU_0_IRQ),
.CPU_0_TXEV(CPU_0_TXEV),
.CPU_0_RXEV(CPU_0_RXEV),
@@ -375,10 +379,6 @@ module nanosoc_system #(
// DMAC 0 APB Configurtation Port - To System Control Subsystem
wire DMAC_0_PSEL; // APB peripheral select
- wire DMAC_0_PEN; // APB transfer enable
- wire DMAC_0_PWRITE; // APB transfer direction
- wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR; // APB address
- wire [SYS_DATA_W-1:0] DMAC_0_PWDATA; // APB write data
wire [SYS_DATA_W-1:0] DMAC_0_PRDATA; // APB read data
wire DMAC_0_PREADY; // APB Ready Signal
wire DMAC_0_PSLVERR; // APB Error Signal
@@ -412,6 +412,7 @@ module nanosoc_system #(
wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE; // DMA transfer done
wire DMAC_1_DMA_ERR; // DMA slave response not OK
+
// DMA Request Wiring
//--------------------------
@@ -427,6 +428,8 @@ module nanosoc_system #(
assign DMAC_ANY_DONE = DMAC_0_ANY_DONE | DMAC_1_ANY_DONE;
assign DMAC_ANY_ERROR = DMAC_0_DMA_ERR | DMAC_1_DMA_ERR;
+ assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}};
+
// APB Assignments
//--------------------------
assign DMAC_0_PREADY = 1'b1;
@@ -628,6 +631,8 @@ module nanosoc_system #(
wire EXP_HRESP;
wire [31:0] EXP_HRDATA;
+ wire EXP_HMASTLOCK; // AHB lock - Unused
+
// SRAM Low Region AHB Port - To Interconnect Subsystem
wire EXPRAM_L_HSEL;
wire [SYS_ADDR_W-1:0] EXPRAM_L_HADDR;
@@ -643,6 +648,8 @@ module nanosoc_system #(
wire EXPRAM_L_HRESP;
wire [31:0] EXPRAM_L_HRDATA;
+ wire EXPRAM_L_HMASTLOCK; // AHB lock - Unused
+
// SRAM High Region AHB Port - To Interconnect Subsystem
wire EXPRAM_H_HSEL;
@@ -659,6 +666,7 @@ module nanosoc_system #(
wire EXPRAM_H_HRESP;
wire [31:0] EXPRAM_H_HRDATA;
+ wire EXPRAM_H_HMASTLOCK; // AHB lock - Unused
// Interrupt Connections - TO CPU Subsystem
wire [3:0] EXP_IRQ;
@@ -931,11 +939,11 @@ module nanosoc_system #(
assign CPU_0_IRQ [3:0] = EXP_IRQ [3:0];
assign CPU_0_IRQ [ 5: 4] = SYS_APB_IRQ[ 5: 4];
- assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | (|SYS_GPIO0_ANY_IRQ);
- assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | (|SYS_GPIO1_ANY_IRQ);
+ assign CPU_0_IRQ [ 6] = SYS_APB_IRQ[ 6] | SYS_GPIO0_ANY_IRQ;
+ assign CPU_0_IRQ [ 7] = SYS_APB_IRQ[ 7] | SYS_GPIO1_ANY_IRQ;
assign CPU_0_IRQ [14: 8] = SYS_APB_IRQ[14: 8];
- assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
- assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16]| SYS_GPIO0_IRQ[15:0];
+ assign CPU_0_IRQ [15] = SYS_APB_IRQ[15] | DMAC_ANY_DONE | DMAC_ANY_ERROR;
+ assign CPU_0_IRQ [31:16] = SYS_APB_IRQ[31:16] | SYS_GPIO0_IRQ[15:0];
//--------------------------
// Interconnect Subsystem
@@ -952,8 +960,8 @@ module nanosoc_system #(
.SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn),
.SYS_SCANENABLE(SYS_SCANENABLE),
- .INC_SCANINHCLK(INC_SCANINHCLK),
- .INC_SCANOUTHCLK(INC_SCANOUTHCLK),
+ .SYS_SCANINHCLK(SYS_SCANINHCLK),
+ .SYS_SCANOUTHCLK(SYS_SCANOUTHCLK),
// System Address Remap control
.SYS_REMAP_CTRL(SYS_REMAP_CTRL),
@@ -1082,7 +1090,7 @@ module nanosoc_system #(
.EXPRAM_L_HBURST(EXPRAM_L_HBURST),
.EXPRAM_L_HPROT(EXPRAM_L_HPROT),
.EXPRAM_L_HWDATA(EXPRAM_L_HWDATA),
- .EXPRAM_L_HMASTLOCK(),
+ .EXPRAM_L_HMASTLOCK(EXPRAM_L_HMASTLOCK),
.EXPRAM_L_HREADYMUX(EXPRAM_L_HREADY),
// Expansion Memory High Region Slave Port
@@ -1097,7 +1105,7 @@ module nanosoc_system #(
.EXPRAM_H_HBURST(EXPRAM_H_HBURST),
.EXPRAM_H_HPROT(EXPRAM_H_HPROT),
.EXPRAM_H_HWDATA(EXPRAM_H_HWDATA),
- .EXPRAM_H_HMASTLOCK(),
+ .EXPRAM_H_HMASTLOCK(EXPRAM_H_HMASTLOCK),
.EXPRAM_H_HREADYMUX(EXPRAM_H_HREADY),
// Expansion Region Slave Port
@@ -1112,7 +1120,7 @@ module nanosoc_system #(
.EXP_HBURST(EXP_HBURST),
.EXP_HPROT(EXP_HPROT),
.EXP_HWDATA(EXP_HWDATA),
- .EXP_HMASTLOCK(),
+ .EXP_HMASTLOCK(EXP_HMASTLOCK),
.EXP_HREADYMUX(EXP_HREADY),
// System ROM Table Region Slave Port
diff --git a/system/slcorem0_tech b/system/slcorem0_tech
index c548cd6..b2ba5b3 160000
--- a/system/slcorem0_tech
+++ b/system/slcorem0_tech
@@ -1 +1 @@
-Subproject commit c548cd60119c081441ab4b644a0083dc4f684c92
+Subproject commit b2ba5b3f83e33c05c1107b3e1fa40f7f6af1e589
diff --git a/system/sldma230_tech b/system/sldma230_tech
index 9ccb88a..c11843b 160000
--- a/system/sldma230_tech
+++ b/system/sldma230_tech
@@ -1 +1 @@
-Subproject commit 9ccb88a6057f003c58f80168d8dca64daf76d08f
+Subproject commit c11843b9e75ce83b7118ef07cb3e1ecc2fe6c9c0
diff --git a/system/socdebug_tech b/system/socdebug_tech
index 3ad5480..b274190 160000
--- a/system/socdebug_tech
+++ b/system/socdebug_tech
@@ -1 +1 @@
-Subproject commit 3ad5480136eb91bf2c17da27c07a0bda8e2fcec3
+Subproject commit b27419058c86e958dc345ff4fa0b2662a70bb88d
diff --git a/verif/tb/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
index 352a378..5b179e0 100644
--- a/verif/tb/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -37,8 +37,6 @@
//
`timescale 1ns/1ps
-`define CORTEX_M0
-
module nanosoc_tb;
wire XTAL1; // crystal pin 1
diff --git a/verif/tb/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
index fc3bd4b..8395444 100644
--- a/verif/tb/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -37,8 +37,6 @@
//
`timescale 1ns/1ps
-`define CORTEX_M0
-
module nanosoc_tb_qs;
wire XTAL1; // crystal pin 1
--
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