From 983484f9c10a516ffb43db4c922b597435c4be4c Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Wed, 26 Apr 2023 16:50:07 +0100
Subject: [PATCH] SOC1-167: Added pragmas to adp and renamed nanosoc_tb module.
Updated makefile to compile more robustly
---
.../nanosoc/systems/mcu/rtl_sim/makefile | 20 +++---
.../nanosoc/systems/mcu/verilog/tb_nanosoc.v | 67 ++++++++++---------
IPLIB/ADPcontrol_v1_0/ADPmanager.v | 3 +
3 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
index 8dcf1b8..f1d25a3 100644
--- a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/makefile
@@ -77,7 +77,7 @@ endif
# Select Verilog Command File based on CPU type
ifeq ($(CPU_PRODUCT),CORTEX_M0)
# For Cortex-M0 product users
- TBENCH_VC += -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
+# TBENCH_VC += -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
DEFINES_VC = +define+CORTEX_M0 +define+USE_TARMAC
endif
@@ -88,7 +88,7 @@ endif
ifeq ($(DMA_PRODUCT),DMA_230)
# For Cortex-M0 product users
- TBENCH_VC += -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
+# TBENCH_VC += -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
endif
TBENCH_VC += -f $(PROJECT_DIR)/flist/project/system.flist
@@ -104,7 +104,7 @@ ACCELERATOR_VC =
#ADP command File
# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd
-ADP_FILE ?= $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/rtl_sim/
+ADP_FILE ?= $(PROJECT_DIR)/system/stimulus/adp_hash_stim.cmd
ADP_PATH := $(shell realpath $(ADP_FILE))
ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
@@ -191,25 +191,25 @@ all_vcs : compile_vcs bootrom debugtester
compile_xm :
@echo ADP_FILE
@echo $(ADP_OPTIONS)
- xmprep +overwrite $(DEFINES_VC) $(XM_VC_OPTIONS) +debug | tee compile_xm.log
- xmvlog -work worklib -f xmvlog.args | tee -a compile_xm.log
- xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
+ xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top tb_nanosoc | tee compile_xm.log
+ xmvlog -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log
+ xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
# Note : If coverage is required, you can add -coverage all to xmelab
# Run simulation in batch mode
-run_xm : code
+run_xm : code compile_xm
@if [ ! -d logs ] ; then \
mkdir logs; \
fi
@echo run > run.tcl.tmp
@echo exit >> run.tcl.tmp
@mv run.tcl.tmp run.tcl
- xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
- @make verify
+ xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
+ # @make verify
# Run simulation in interactive mode
-sim_xm : code
+sim_xm : code compile_xm
xmsim -gui $(XMSIM_OPTIONS)
@make verify
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
index aa42a2d..6515d98 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -37,7 +37,7 @@
//
`timescale 1ns/1ps
-module tb_cmsdk_mcu;
+module tb_nanosoc;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
@@ -80,6 +80,13 @@ module tb_cmsdk_mcu;
localparam BE=0;
`define ARM_CMSDK_INCLUDE_DEBUG_TESTER 1
+`ifdef ADP_FILE
+ localparam ADP_FILENAME=`ADP_FILE;
+`else
+ localparam ADP_FILENAME="adp.cmd";
+`endif
+
+
SROM_Ax32
#(.ADDRWIDTH (8),
.filename ("bootloader.hex"),
@@ -260,7 +267,7 @@ wire rxd8_valid;
wire [7:0] rxd8_data ;
axi_streamio8_txd_from_file
- #(.TXDFILENAME("adp.cmd"))
+ #(.TXDFILENAME(ADP_FILENAME))
u_axi_streamio8_txd_from_file
(
.aclk (XTAL1),
@@ -588,33 +595,33 @@ ft1248x1_track
// Tracking AES logging support
// --------------------------------------------------------------------------------
-`define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_exp_aes128
-
- aes128_log_to_file #(.FILENAME("aes128.log"),.TIMESTAMP(1))
- u_aes_log_to_file (
- .ahb_hclk (`AES_PATH.ahb_hclk ),
- .ahb_hresetn (`AES_PATH.ahb_hresetn ),
- .ahb_hsel (`AES_PATH.ahb_hsel ),
- .ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
- .ahb_htrans (`AES_PATH.ahb_htrans ),
- .ahb_hwrite (`AES_PATH.ahb_hwrite ),
- .ahb_hsize (`AES_PATH.ahb_hsize ),
- .ahb_hprot (`AES_PATH.ahb_hprot ),
- .ahb_hwdata (`AES_PATH.ahb_hwdata ),
- .ahb_hready (`AES_PATH.ahb_hready ),
- .ahb_hrdata (`AES_PATH.ahb_hrdata ),
- .ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
- .ahb_hresp (`AES_PATH.ahb_hresp ),
- .drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
- .dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
- .drq_opdma128 (`AES_PATH.drq_opdma128 ),
- .dlast_opdma128 (`AES_PATH.dlast_opdma128),
- .irq_key128 (`AES_PATH.irq_key128 ),
- .irq_ip128 (`AES_PATH.irq_ip128 ),
- .irq_op128 (`AES_PATH.irq_op128 ),
- .irq_error (`AES_PATH.irq_error ),
- .irq_merged (`AES_PATH.irq_merged )
- );
+// `define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_exp_aes128
+
+// aes128_log_to_file #(.FILENAME("aes128.log"),.TIMESTAMP(1))
+// u_aes_log_to_file (
+// .ahb_hclk (`AES_PATH.ahb_hclk ),
+// .ahb_hresetn (`AES_PATH.ahb_hresetn ),
+// .ahb_hsel (`AES_PATH.ahb_hsel ),
+// .ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
+// .ahb_htrans (`AES_PATH.ahb_htrans ),
+// .ahb_hwrite (`AES_PATH.ahb_hwrite ),
+// .ahb_hsize (`AES_PATH.ahb_hsize ),
+// .ahb_hprot (`AES_PATH.ahb_hprot ),
+// .ahb_hwdata (`AES_PATH.ahb_hwdata ),
+// .ahb_hready (`AES_PATH.ahb_hready ),
+// .ahb_hrdata (`AES_PATH.ahb_hrdata ),
+// .ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
+// .ahb_hresp (`AES_PATH.ahb_hresp ),
+// .drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
+// .dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
+// .drq_opdma128 (`AES_PATH.drq_opdma128 ),
+// .dlast_opdma128 (`AES_PATH.dlast_opdma128),
+// .irq_key128 (`AES_PATH.irq_key128 ),
+// .irq_ip128 (`AES_PATH.irq_ip128 ),
+// .irq_op128 (`AES_PATH.irq_op128 ),
+// .irq_error (`AES_PATH.irq_error ),
+// .irq_merged (`AES_PATH.irq_merged )
+// );
// --------------------------------------------------------------------------------
diff --git a/IPLIB/ADPcontrol_v1_0/ADPmanager.v b/IPLIB/ADPcontrol_v1_0/ADPmanager.v
index 8a7a0e8..a6bc70c 100755
--- a/IPLIB/ADPcontrol_v1_0/ADPmanager.v
+++ b/IPLIB/ADPcontrol_v1_0/ADPmanager.v
@@ -11,6 +11,7 @@
//`define ADPBASIC 1
+`begin_keywords "1364-2001"
module ADPmanager // AHB initiator interface
#(parameter PROMPT_CHAR = "]"
@@ -763,6 +764,8 @@ always @(posedge HCLK or negedge HRESETn)
endmodule
+`end_keywords
+
////AHBLITE_ADPMASTER instancing
//ADPmaster
// #(.PROMPT_CHAR ("]"))
--
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