diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 42784a780fbfaf339a7694f0962b58f2d264cd7f..23c6c1ad68dfd6c1ed42498bb5cb77a5d0448f03 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -240,7 +240,7 @@ module nanosoc_region_sysio #(
 
   nanosoc_sysctrl #(
     .BE (BE)
-  ) u_nanosoc_sysctrl (
+  ) u_sysctrl (
    // AHB Inputs
     .HCLK         (HCLK),
     .HRESETn      (HRESETn),
@@ -275,7 +275,7 @@ module nanosoc_region_sysio #(
     .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
     .BE                      (BE)
     )
-    u_nanosoc_gpio_0  (
+    u_gpio_0  (
    // AHB Inputs
     .HCLK         (HCLK),
     .HRESETn      (HRESETn),
@@ -308,7 +308,7 @@ module nanosoc_region_sysio #(
     .ALTERNATE_FUNC_MASK     (16'h002A), // pin muxing for Port #1
     .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
     .BE                      (BE)
-  ) u_nanosoc_gpio_1 (
+  ) u_gpio_1 (
    // AHB Inputs
     .HCLK         (HCLK),
     .HRESETn      (HRESETn),
@@ -352,8 +352,7 @@ module nanosoc_region_sysio #(
     .INCLUDE_APB_UART2       (1),  // Include simple UART #2.
     .INCLUDE_APB_WATCHDOG    (1),  // Include APB watchdog module
     .BE                      (BE)
-  ) u_nanosoc_sysio_apb_ss (
-
+  ) u_sysio_apb_ss (
   // AHB interface for AHB to APB bridge
     .HCLK          (HCLK),
     .HRESETn       (HRESETn),
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
index 124d342120bd4013f87b6382476ba94328f004db..368acd40b412ae375f2bb9ca40337c5c4ba852c4 100755
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
@@ -349,8 +349,7 @@ module nanosoc_sysio_apb_ss #(
     );
 
   // APB slave multiplexer
-  cmsdk_apb_slave_mux
-    #( // Parameter to determine which ports are used
+  cmsdk_apb_slave_mux #( // Parameter to determine which ports are used
     .PORT0_ENABLE  (INCLUDE_APB_TIMER0), // timer 0
     .PORT1_ENABLE  (INCLUDE_APB_TIMER1), // timer 1
     .PORT2_ENABLE  (INCLUDE_APB_DUALTIMER0), // dual timer 0
@@ -367,8 +366,7 @@ module nanosoc_sysio_apb_ss #(
     .PORT13_ENABLE (APB_EXT_PORT13_ENABLE),
     .PORT14_ENABLE (APB_EXT_PORT14_ENABLE),
     .PORT15_ENABLE (APB_EXT_PORT15_ENABLE)
-    )
-    u_apb_slave_mux (
+  ) u_apb_slave_mux (
     // Inputs
     .DECODE4BIT        (i_paddr[15:12]),
     .PSEL              (i_psel),
@@ -391,7 +389,7 @@ module nanosoc_sysio_apb_ss #(
     .PSEL3             (psel3),
     .PREADY3           (1'b1),
     .PRDATA3           (32'h00000000),
-    .PSLVERR3          (1'b0),
+    .PSLVERR3          (1'b1),
 
     .PSEL4             (uart0_psel),
     .PREADY4           (uart0_pready),
@@ -411,7 +409,7 @@ module nanosoc_sysio_apb_ss #(
     .PSEL7             (psel7),
     .PREADY7           (1'b1),
     .PRDATA7           (32'h00000000),
-    .PSLVERR7          (1'b0),
+    .PSLVERR7          (1'b1),
 
     .PSEL8             (watchdog_psel),
     .PREADY8           (watchdog_pready),
@@ -421,12 +419,12 @@ module nanosoc_sysio_apb_ss #(
     .PSEL9             (psel9),
     .PREADY9           (1'b1),
     .PRDATA9           (32'h00000000),
-    .PSLVERR9          (1'b0),
+    .PSLVERR9          (1'b1),
 
     .PSEL10            (psel10),
     .PREADY10          (1'b1),
     .PRDATA10          (32'h00000000),
-    .PSLVERR10         (1'b0),
+    .PSLVERR10         (1'b1),
 
     .PSEL11            (test_slave_psel),
     .PREADY11          (test_slave_pready),
diff --git a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
index 2b8f6ad243d614f0a4a574afe02dc9c46d34a8ab..dc30f11f31b87be7a43a2b680ec040990a0ebfa6 100644
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -73,8 +73,7 @@ module nanosoc_sysio_decode #(
   // Peripheral Selection decode logic
   // ----------------------------------------------------------
 
-  assign apbsys_hsel  = hsel & (haddr[31:16]==
-                         BASEADDR_APBSS[31:16]);       // 0x40000000
+  assign apbsys_hsel  = hsel & (haddr[31:16]==16'h4000); // 0x40000000
   assign gpio0_hsel   = hsel & (haddr[31:12]==
                          BASEADDR_GPIO0[31:12]);       // 0x40010000
   assign gpio1_hsel   = hsel & (haddr[31:12]==
diff --git a/software/common/validation/default_slaves_tests.c b/software/common/validation/default_slaves_tests.c
index 065dab96797f2d2e8690c631274d9e1af87c8634..3d5e82654b1058bc46fdd6ac9507030093ca59d8 100644
--- a/software/common/validation/default_slaves_tests.c
+++ b/software/common/validation/default_slaves_tests.c
@@ -1,12 +1,12 @@
 /*-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// Updated for NanoSoC System
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors
 //
 // David Flynn (d.w.flynn@soton.ac.uk)
 //
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 */