From 95c9e5c1e07a5442371fbf1a3f2b88d76c62da20 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 29 Jun 2023 21:10:06 +0100
Subject: [PATCH] Fixed issue with clocks not wired up correctly and changed
default accelerator to yes
---
makefile | 2 +-
system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/makefile b/makefile
index c8fa1c4..df5aa1e 100644
--- a/makefile
+++ b/makefile
@@ -85,7 +85,7 @@ BOOTROM_BUILD_DIR ?= $(SOCLABS_PROJECT_DIR)/system/src/bootrom
QUICKSTART ?= no
-ACCELERATOR ?= no
+ACCELERATOR ?= yes
# Simulator Defines
DEFINES_VC += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC
diff --git a/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v b/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
index 1a3278d..186f9f1 100644
--- a/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+++ b/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
@@ -42,6 +42,8 @@ module nanosoc_region_exp #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W)
) u_accelerator_ss (
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
.HSEL(HSEL),
.HADDR(HADDR),
.HTRANS(HTRANS),
--
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