From 9386e4a4c2291b47b6d27b45bb8d9b7cac9e9cbc Mon Sep 17 00:00:00 2001 From: dwf1m12 <d.w.flynn@soton.ac.uk> Date: Mon, 20 Feb 2023 21:26:14 +0000 Subject: [PATCH] update ZCU104 FPGA build for nanostep and diagnostic IO --- .../fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl | 86 ++ .../ip_repo/ADPcontrol_1.0/component.xml | 1348 +++++++++++++++++ .../ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v | 103 ++ .../hdl/ADPcontrol_v1_0_com_rx.v | 167 ++ .../hdl/ADPcontrol_v1_0_com_tx.v | 228 +++ .../hdl/ADPcontrol_v1_0_stdio_rx.v | 167 ++ .../hdl/ADPcontrol_v1_0_stdio_tx.v | 228 +++ .../ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v | 786 ++++++++++ .../soclabs.org_user_ADPcontrol_1.0.zip | Bin 0 -> 16619 bytes .../ADPcontrol_1.0/src/ADPcontrol_v1_0.v | 103 ++ .../ip_repo/ADPcontrol_1.0/src/ADPmanager.v | 786 ++++++++++ .../ip_repo/ADPcontrol_1.0/src/ADPmaster.v | 728 +++++++++ .../ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl | 24 + .../ip_repo/axi_stream_io_1.0/component.xml | 38 +- .../soclabs.org_user_axi_stream_io_1.0.zip | Bin 15835 -> 16165 bytes .../src/axi_stream_io_v1_0_axi_s.v | 42 +- .../ft1248x1_to_axi_streamio_1.0/bd/bd.tcl | 86 ++ .../component.xml | 600 ++++++++ .../ft1248x1_to_axi_streamio_0_2.xcix | Bin 0 -> 260 bytes .../hdl/SYNCHRONIZER_EDGES.v | 40 + .../hdl/ft1248x1_to_axi_streamio_v1_0.v | 199 +++ .../hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v | 167 ++ .../hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v | 228 +++ ....org_user_ft1248x1_to_axi_streamio_1.0.zip | Bin 0 -> 7881 bytes .../xgui/ft1248x1_to_axi_streamio_v1_0.tcl | 35 + .../fpga_imp/scripts/build_mcu_fpga_ip.tcl | 5 +- .../scripts/build_mcu_fpga_pynq_zcu104.tcl | 2 +- .../fpga_imp/scripts/rtl_source_dma230.tcl | 1 + .../fpga_imp/target_fpga_zcu104/design_1.tcl | 233 ++- 29 files changed, 6349 insertions(+), 81 deletions(-) create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v create mode 100755 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip create mode 100644 Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl new file mode 100755 index 0000000..690e4e1 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml new file mode 100755 index 0000000..ae447c2 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml @@ -0,0 +1,1348 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>soclabs.org</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>ADPcontrol</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>com_rx</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_rx_tdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_rx_tvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_rx_tready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>WIZ_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>com_tx</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_tx_tdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_tx_tvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>com_tx_tready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>WIZ_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>stdio_rx</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_rx_tdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_rx_tvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_rx_tready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>WIZ_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>stdio_tx</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_tx_tdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_tx_tvalid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>stdio_tx_tready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>WIZ_DATA_WIDTH</spirit:name> + <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ahb</spirit:name> + <spirit:displayName>AHB_M</spirit:displayName> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite" spirit:version="2.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite_rtl" spirit:version="2.0"/> + <spirit:master> + <spirit:addressSpaceRef spirit:addressSpaceRef="ahb"/> + </spirit:master> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HTRANS</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_htrans</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HPROT</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hprot</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HSIZE</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hsize</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HRDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hrdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HRESP</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hresp</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HWRITE</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hwrite</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HADDR</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_haddr</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HMASTLOCK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hmastlock</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HBURST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hburst</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>HWDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hwdata</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ahb_hclk</spirit:name> + <spirit:displayName>hclk</spirit:displayName> + <spirit:description>rising-edge clock</spirit:description> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hclk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:description>100000000</spirit:description> + <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_HZ"/> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_BUSIF">com_rx:com_tx:stdio_rx:stdio_tx:ahb</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_RESET">ahb_hresetn</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_TOLERANCE_HZ</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_TOLERANCE_HZ">-1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>ahb_hresetn</spirit:name> + <spirit:displayName>hresetn</spirit:displayName> + <spirit:description>active low reset</spirit:description> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>ahb_hresetn</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HRESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:addressSpaces> + <spirit:addressSpace> + <spirit:name>ahb</spirit:name> + <spirit:range spirit:format="bitString" spirit:resolve="user">0x100000000</spirit:range> + <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width> + <spirit:vendorExtensions> + <xilinx:addressSpaceInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:resolve="user" xilinx:id="ADDRSPACE_ENABLEMENT.ahb">true</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:addressSpaceInfo> + </spirit:vendorExtensions> + </spirit:addressSpace> + </spirit:addressSpaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>xilinx_verilogsynthesis</spirit:name> + <spirit:displayName>Verilog Synthesis</spirit:displayName> + <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier> + <spirit:language>verilog</spirit:language> + <spirit:modelName>ADPcontrol_v1_0</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>e3d2a4c3</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name> + <spirit:displayName>Verilog Simulation</spirit:displayName> + <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier> + <spirit:language>verilog</spirit:language> + <spirit:modelName>ADPcontrol_v1_0</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>e3d2a4c3</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>xilinx_xpgui</spirit:name> + <spirit:displayName>UI Layout</spirit:displayName> + <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier> + <spirit:fileSetRef> + <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>936ced64</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>bd_tcl</spirit:name> + <spirit:displayName>Block Diagram</spirit:displayName> + <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier> + <spirit:fileSetRef> + <spirit:localName>bd_tcl_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>16328387</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>ahb_hclk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hresetn</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_rx_tready</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_rx_tdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_rx_tvalid</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_tx_tvalid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_tx_tdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>com_tx_tready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_rx_tready</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_rx_tdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_rx_tvalid</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_tx_tvalid</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_tx_tdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>stdio_tx_tready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>gpo8</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>gpi8</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_haddr</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">31</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hburst</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">2</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hmastlock</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hprot</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">3</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hsize</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">2</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_htrans</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">1</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hwdata</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">31</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hwrite</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hrdata</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">31</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hready</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ahb_hresp</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + <spirit:modelParameters> + <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string"> + <spirit:name>PROMPT_CHAR</spirit:name> + <spirit:displayName>Prompt Char</spirit:displayName> + <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PROMPT_CHAR">]</spirit:value> + </spirit:modelParameter> + </spirit:modelParameters> + </spirit:model> + <spirit:choices> + <spirit:choice> + <spirit:name>choice_list_6fc15197</spirit:name> + <spirit:enumeration>32</spirit:enumeration> + </spirit:choice> + <spirit:choice> + <spirit:name>choice_list_9d8b0d81</spirit:name> + <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> + <spirit:enumeration>ACTIVE_LOW</spirit:enumeration> + </spirit:choice> + </spirit:choices> + <spirit:fileSets> + <spirit:fileSet> + <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name> + <spirit:file> + <spirit:name>src/ADPmanager.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>src/ADPcontrol_v1_0.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + <spirit:userFileType>CHECKSUM_5aaa5c19</spirit:userFileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name> + <spirit:file> + <spirit:name>src/ADPmanager.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>src/ADPcontrol_v1_0.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>xilinx_xpgui_view_fileset</spirit:name> + <spirit:file> + <spirit:name>xgui/ADPcontrol_v1_0.tcl</spirit:name> + <spirit:fileType>tclSource</spirit:fileType> + <spirit:userFileType>CHECKSUM_936ced64</spirit:userFileType> + <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>bd_tcl_view_fileset</spirit:name> + <spirit:file> + <spirit:name>bd/bd.tcl</spirit:name> + <spirit:fileType>tclSource</spirit:fileType> + </spirit:file> + </spirit:fileSet> + </spirit:fileSets> + <spirit:description>ADP AHB controller</spirit:description> + <spirit:parameters> + <spirit:parameter> + <spirit:name>Component_Name</spirit:name> + <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ADPcontrol_v1_0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROMPT_CHAR</spirit:name> + <spirit:displayName>Prompt Char</spirit:displayName> + <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROMPT_CHAR">]</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <xilinx:coreExtensions> + <xilinx:supportedFamilies> + <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family> + </xilinx:supportedFamilies> + <xilinx:taxonomies> + <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy> + </xilinx:taxonomies> + <xilinx:displayName>ADPcontrol_v1.0</xilinx:displayName> + <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel> + <xilinx:coreRevision>23</xilinx:coreRevision> + <xilinx:coreCreationDateTime>2023-02-19T20:54:26Z</xilinx:coreCreationDateTime> + <xilinx:tags> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1d457846_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@37c19d7d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4d9c63f5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3486ae33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@16991627_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@21280f5b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2a6297f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@d359ebf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@585c5d69_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@13554121_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5cc15ddd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@47f5cea9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2797f52a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2d4db012_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4d5ff66d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@160f397b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@9eedd13_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@383df36f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5b29af4a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6a844f8f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@dd3613f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@465ab221_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2c2a723e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7769a864_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2b6e7c2b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@348806c9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@543e517b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@23a5fd27_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5acc4197_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1b0672e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1fcd885_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3b8348bf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7a2cf9c9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@266167bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@75fc528d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@571f957b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@205b72be_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@18af816d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@76808038_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@12b6bb23_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@571354b0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@49208c72_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@96cf3b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@160b7175_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@733792a3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6741cc7c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@21688aa5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@15d88077_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3dedcd2d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@109e8ade_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@66efa591_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@33406c6a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1295e34_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@23a10fd2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@46b3edc3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@79223f91_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@25bf4cbd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3bf95837_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2d5a6e80_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@23cef462_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7701c845_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@d900de2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1b614769_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2a1ab09c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5a71cfc7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7737ed39_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3417e460_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5dcd78cc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@87e31dd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5878b3d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@414f7e53_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@448f5b33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5f4942b4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@68082003_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@67b73b35_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@63825d52_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@59bce76e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@511d4c77_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1c74144d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4e4c1934_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@378bcf30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4e795a88_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5ad7045c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6ae82c3f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4ac8e1b1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@72e7dc1b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@36456a91_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3994cf09_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6c751ad6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@44a8e456_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@58f80386_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@60462d25_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@19c41859_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3a040f48_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7d1e622a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5592457_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7aa4d1b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5b291a28_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1cad021e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7376878e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4870a6f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2fc3ca30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77cf444c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a9a0814_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1424fd5e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3453af13_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@27e0072f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@f46a21a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@18d268d4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5c1b0b80_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2973e675_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@604ab08f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3ba14fe4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@223f211e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@15bffbbe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@dc2fd1e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@54866dfc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@49d29cb3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6317da2d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2dea1246_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@22205824_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@71fb215a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3f69f943_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@10598249_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@69cc5be9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@30744b50_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77c27106_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@17c7c0e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6b1dc1ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@13c92119_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@433c97e8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@dfaa30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@498e3871_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@68ef63bf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@cabff58_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6329d1ac_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3d41686b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@17b94c6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@73c60546_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1efb46d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1c3fd36_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@94a143_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@27fa8005_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@62074f67_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3c35c7f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@23404941_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1ca68904_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3bf56a5a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1af8595a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7883ae7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3a942794_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@148bd7e5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@73d73a56_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3a2205ee_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1349a24a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5d4275c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@657d1d9b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77dc74cf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7b2335ea_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@60cfbf2f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3b5bc7f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3952de2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4ea52573_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@58fdb158_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6a3ec25b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@38e01d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@41312d17_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4960f858_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4fc1a608_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@50a7b242_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3ba5a927_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4577effb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@24950516_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3f566912_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@ce5ccb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1868af0c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1e5676a1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@482c6c08_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@439d1ccd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4d18b880_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1cb34d37_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@35956167_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@edc52ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5ca21f6a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@30cea3b8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@72dd0545_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3385e4b5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a7f120d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@64e52226_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3642d1a2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2f597e54_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@51e8ab9d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@72b9d5e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7a4741c0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4bb7f6f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@634fe21a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4aa4e91b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@30ad75d5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4911c113_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4080a163_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77494d4e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1bdef9f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4385cd7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@64412115_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6f2eee8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3c61cfc8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@21768440_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4b355e7a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@65d604b5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1d52befe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7cf526e5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@551c331c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@646f2bcc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6d01a5a8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5d95b5ff_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@27b779c7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1434a4fe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5e7326d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2fd42eaf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2a035f8e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@761ebb79_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2edf9f01_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@c5189a6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@11b06564_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@f5f8ce8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@751af23d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@57380db3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@f3d75f1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@626de2e1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@65166b70_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1b007a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3f3b6415_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@444d9f3b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@58fe3b2b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@22c722fb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@143ea435_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5a42ad29_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@c5b8ec0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a4e16b4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@42ffb207_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@714e55e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@46a7eaba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@17b1cd6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@43ddb8ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@46813502_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@20ebdb6c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3b2bcf03_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@573cb596_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@67a1e45e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@e85625c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6b0d7ccd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2f5cda36_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@51ba8691_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@782de323_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@570b95ae_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5b826b52_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@37cc7d57_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1fead495_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@395f4c4c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77419e7a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5b4eb32d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@50a26523_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2129e8aa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4c1b9123_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2bd2e4a6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@441d0859_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7f39f4dd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@179c6e39_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1de9114f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@50d3b1e8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@129ac90_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a081ede_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@46ad3f41_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6a67c8c3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77c6b087_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6941d063_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@31d57680_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5ad3812d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5053bd97_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4950b18d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@71973c4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@f73ae96_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@aa60d05_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4b98b40c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@767f6dd3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3d62773e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4932ca24_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@499b78e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@570037c0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6c5b2a33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@72a04750_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5c95f5d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@13e93f4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@26f6a801_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@69443224_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3df62b6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@67368a6e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7cc83605_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1507eb2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@135a41e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@64e63246_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4f49185c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5593e965_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@225ff805_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4beed390_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@106a0c22_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@384214bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@593ef9fb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@37cdc023_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@13a1d788_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@524f74f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4bf9a62b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@55a122c7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7c2fdaa9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@518b1cda_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@51e91952_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1278d0d9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@33a9e1f0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5761a78_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@57c6694d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6f6e2a4c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@651527ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@20634131_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4a5fc5ae_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1ea744d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@41ac8c35_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@544fed3e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@352cd72_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@25a30a08_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3a049463_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@50f12b6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@598f48b2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6449a017_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4fc6d831_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6b83cae5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3ceb3464_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a761ed2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@25804f95_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@47f1862a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@551336b0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2943bdfb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4a3f2f83_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@52f9db4e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@66396587_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4382e037_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@41949965_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1a8a1eeb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5189684d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@76bfc522_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4c88cfbd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2cbbaeda_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@77ee719d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@5d7b2699_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@73ba8e8b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1f047a95_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@22689605_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6b1c0e75_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3c70f3ac_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3d414ec0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@30a4d75_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@52a783ab_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6706deea_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6124d7d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@59e9e696_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@202e94c8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@b6ee7ad_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@11bbdbd2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@53acccb5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1bcb5b05_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6c1a5b1c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@4fa63c3e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@64e4590_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@43599237_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@784e427e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@251afaad_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@326b33d4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2b2571dc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@2fed8cc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@509a0566_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@193895f6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@725ff575_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6f25ab56_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1e921ec3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@ac8c699_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@53f24856_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@1724f6e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@610a3da7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@3b846fd8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@645d5f2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@14d3680_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@75fea7b9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@49e97fec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6cbcafe8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@e9f64d3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@6b46d36f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@7ed1f96b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.dd@27f5c251_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@472752f8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@17bc87a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@31dc304_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@352d492d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6e8cf4c8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3f9ad2c5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@32f89c42_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3778bb78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@510d9d71_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5634a7b8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@8cbb07a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2bd39894_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@49f0884e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@47766a99_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@72bfa014_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6ceae5a1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@f97815f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2ab1af41_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@736d5c8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@28ad60d2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@280a47e1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3f6f7e0d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@73674571_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2bc75aea_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4648f64d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@44e851d7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3596d0fb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@25a1a065_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3a73112f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6ff5037d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3b679be2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@343f5854_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1f0e5159_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@672205c4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5eaf4a2f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4294b19b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4a77deab_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@48460505_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@186d05f2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@77227d65_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@bf3434b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@70fe8b50_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6ea74e9c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@94baf8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2c237466_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@7477dd9e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag> + </xilinx:tags> + </xilinx:coreExtensions> + <xilinx:packagingInfo> + <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion> + <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="cf8749a1"/> + <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="2ed9224a"/> + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="84af976f"/> + <xilinx:checksum xilinx:scope="ports" xilinx:value="2212c402"/> + <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd165264"/> + <xilinx:checksum xilinx:scope="parameters" xilinx:value="35656c35"/> + <xilinx:targetDRCs> + <xilinx:targetDRC xilinx:tool="ipi"> + <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/> + </xilinx:targetDRC> + </xilinx:targetDRCs> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v new file mode 100755 index 0000000..7b8967c --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v @@ -0,0 +1,103 @@ +//----------------------------------------------------------------------------- +// top-level soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + + module ADPcontrol_v1_0 # + ( + // Users to add parameters here + parameter PROMPT_CHAR = "]" + + // User parameters ends + // Do not modify the parameters beyond this line + + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Ports of Axi Slave Bus Interface com_rx + input wire ahb_hclk, + input wire ahb_hresetn, + + output wire com_rx_tready, + input wire [7 : 0] com_rx_tdata, + input wire com_rx_tvalid, + + // Ports of Axi Master Bus Interface com_tx + output wire com_tx_tvalid, + output wire [7 : 0] com_tx_tdata, + input wire com_tx_tready, + + // Ports of Axi Slave Bus Interface stdio_rx + output wire stdio_rx_tready, + input wire [7 : 0] stdio_rx_tdata, + input wire stdio_rx_tvalid, + + // Ports of Axi Master Bus Interface stdio_tx + output wire stdio_tx_tvalid, + output wire [7 : 0] stdio_tx_tdata, + input wire stdio_tx_tready, + + output wire [7 : 0] gpo8, + input wire [7 : 0] gpi8, + + output wire [31:0] ahb_haddr , + output wire [ 2:0] ahb_hburst , + output wire ahb_hmastlock, + output wire [ 3:0] ahb_hprot , + output wire [ 2:0] ahb_hsize , + output wire [ 1:0] ahb_htrans , + output wire [31:0] ahb_hwdata , + output wire ahb_hwrite , + input wire [31:0] ahb_hrdata , + input wire ahb_hready , + input wire ahb_hresp + ); + + // Add user logic here + +ADPmanager + #(.PROMPT_CHAR (PROMPT_CHAR)) + ADPmanager( + .HCLK (ahb_hclk ), + .HRESETn (ahb_hresetn ), + .HADDR32_o (ahb_haddr ), + .HBURST3_o (ahb_hburst ), + .HMASTLOCK_o (ahb_hmastlock ), + .HPROT4_o (ahb_hprot ), + .HSIZE3_o (ahb_hsize ), + .HTRANS2_o (ahb_htrans ), + .HWDATA32_o (ahb_hwdata ), + .HWRITE_o (ahb_hwrite ), + .HRDATA32_i (ahb_hrdata ), + .HREADY_i (ahb_hready ), + .HRESP_i (ahb_hresp ), + .GPO8_o (gpo8 ), + .GPI8_i (gpi8 ), + .COMRX_TREADY_o(com_rx_tready), + .COMRX_TDATA_i(com_rx_tdata), + .COMRX_TVALID_i(com_rx_tvalid), + .STDRX_TREADY_o(stdio_rx_tready), + .STDRX_TDATA_i(stdio_rx_tdata), + .STDRX_TVALID_i(stdio_rx_tvalid), + .COMTX_TVALID_o(com_tx_tvalid), + .COMTX_TDATA_o(com_tx_tdata), + .COMTX_TREADY_i(com_tx_tready), + .STDTX_TVALID_o(stdio_tx_tvalid), + .STDTX_TDATA_o(stdio_tx_tdata), + .STDTX_TREADY_i(stdio_tx_tready) + + ); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v new file mode 100755 index 0000000..0e980d3 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_com_rx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v new file mode 100755 index 0000000..ba5f035 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_com_tx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v new file mode 100755 index 0000000..30f30e3 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_stdio_rx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v new file mode 100755 index 0000000..8f4af08 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_stdio_tx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v new file mode 100755 index 0000000..f4747ae --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v @@ -0,0 +1,786 @@ +//----------------------------------------------------------------------------- +// soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + +//`define ADPBASIC 1 + +module ADPmanager // AHB initiator interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] HADDR32_o, + output wire [ 2:0] HBURST3_o, + output wire HMASTLOCK_o, + output wire [ 3:0] HPROT4_o, + output wire [ 2:0] HSIZE3_o, + output wire [ 1:0] HTRANS2_o, + output wire [31:0] HWDATA32_o, + output wire HWRITE_o, + input wire [31:0] HRDATA32_i, + input wire HREADY_i, + input wire HRESP_i, +// COMIO interface + output wire [ 7:0] GPO8_o, + input wire [ 7:0] GPI8_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam BANNERHEX = 32'h50c1ab01; +`else + localparam BANNERHEX = 32'h50c1ab02; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function FNuppercase; +input [7:0] char8; + FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping +`ifdef ADPFSMDESIGN +localparam ADP_WRITEHEX = 6'b000000 ; +localparam ADP_WRITEHEXS = 6'b000001 ; +localparam ADP_WRITEHEX9 = 6'b000010 ; +localparam ADP_WRITEHEX8 = 6'b000011 ; +localparam ADP_WRITEHEX7 = 6'b000100 ; +localparam ADP_WRITEHEX6 = 6'b000101 ; +localparam ADP_WRITEHEX5 = 6'b000110 ; +localparam ADP_WRITEHEX4 = 6'b000111 ; +localparam ADP_WRITEHEX3 = 6'b001000 ; +localparam ADP_WRITEHEX2 = 6'b001001 ; +localparam ADP_WRITEHEX1 = 6'b001010 ; +localparam ADP_WRITEHEX0 = 6'b001011 ; +localparam ADP_LINEACK = 6'b001101 ; +localparam ADP_LINEACK2 = 6'b110010 ; +localparam ADP_PROMPT = 6'b001110 ; +localparam ADP_IOCHK = 6'b001111 ; +localparam ADP_RXCMD = 6'b010000 ; +localparam ADP_RXPARAM = 6'b010010 ; +localparam ADP_ACTION = 6'b010011 ; +localparam ADP_READ = 6'b010001 ; +localparam ADP_SYSCHK = 6'b010100 ; +localparam ADP_STDIN = 6'b010101 ; +localparam ADP_SYSCTL = 6'b010110 ; +localparam ADP_WRITE = 6'b010111 ; +localparam ADP_EXIT = 6'b011000 ; +localparam STD_IOCHK = 6'b011001 ; +localparam STD_RXD1 = 6'b011010 ; +localparam STD_RXD2 = 6'b011011 ; +localparam STD_TXD1 = 6'b011101 ; +localparam STD_TXD2 = 6'b011110 ; +localparam ADP_BCTRL = 6'b011111 ; +localparam ADP_BREADB0 = 6'b100000 ; +localparam ADP_BREADB1 = 6'b100001 ; +localparam ADP_BREADB2 = 6'b100010 ; +localparam ADP_BREADB3 = 6'b100011 ; +localparam ADP_BWRITE = 6'b100100 ; +localparam ADP_POLL = 6'b100101 ; +localparam ADP_POLL1 = 6'b100110 ; +localparam ADP_POLL2 = 6'b100111 ; +localparam ADP_ZCTRL = 6'b101110 ; +localparam ADP_ZWRITE = 6'b101111 ; +localparam ADP_ECHOCMD = 6'b110000 ; +localparam ADP_ECHOCMDSP = 6'b110001 ; +localparam ADP_UNKNOWN = 6'b101000 ; +localparam ADP_STDOUT = 6'b101010 ; +localparam ADP_STDOUT1 = 6'b101011 ; +localparam ADP_STDOUT2 = 6'b101100 ; +localparam ADP_STDOUT3 = 6'b101101 ; +reg [5:0] adp_state ; +`else +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000 +localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001 +localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010 +localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011 +localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100 +localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101 +localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110 +localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111 +localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000 +localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001 +localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010 +localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011 +localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001101 +localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b110010 +localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110 +localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111 +localparam ADP_RXCMD = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000 +localparam ADP_RXPARAM = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010010 +localparam ADP_ACTION = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010011 +localparam ADP_READ = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010001 +localparam ADP_SYSCHK = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100 +localparam ADP_STDIN = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101 +localparam ADP_SYSCTL = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110 +localparam ADP_WRITE = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111 +localparam ADP_EXIT = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000 +localparam STD_IOCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001 +localparam STD_RXD1 = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010 +localparam STD_RXD2 = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011 +localparam STD_TXD1 = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011101 +localparam STD_TXD2 = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011110 +localparam ADP_BCTRL = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011111 +localparam ADP_BREADB0 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b100000 +localparam ADP_BREADB1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100001 +localparam ADP_BREADB2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100010 +localparam ADP_BREADB3 = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100011 +localparam ADP_BWRITE = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100100 +localparam ADP_POLL = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100101 +localparam ADP_POLL1 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100110 +localparam ADP_POLL2 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100111 +localparam ADP_ZCTRL = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b101110 +localparam ADP_ZWRITE = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101111 +localparam ADP_ECHOCMD = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b110000 +localparam ADP_ECHOCMDSP = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b110001 +localparam ADP_UNKNOWN = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101000 +localparam ADP_STDOUT = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101010 +localparam ADP_STDOUT1 = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101011 +localparam ADP_STDOUT2 = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101100 +localparam ADP_STDOUT3 = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101101 +reg [47:0] adp_state ; +`endif + +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + +assign GPO8_o = adp_sys[7:0]; + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign HADDR32_o = adp_addr; +assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign HMASTLOCK_o = 1'b0; +assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign HWDATA32_o = adp_bus_data; +assign HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +reg [31:0] adp_count; +reg adp_count_dec ; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) +// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_down_zero_next; // param about to be zero +input [31:0] counter; + FNcount_down_zero_next = !(|counter[31:1]); +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= BANNERHEX; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; +`ifndef ADPBASIC + adp_count <= 0; + adp_count_dec<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; +`endif + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; +`ifndef ADPBASIC + adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param-- + adp_count_dec<= 0; +`endif + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) + begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) + begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) + begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end + else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end +// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param + else begin adp_cmd <= com_rx_byte; adp_param <= 32'hffffffff; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) +`ifndef ADPBASIC + begin adp_count <= adp_param; adp_state <= ADP_ACTION; end // parameter complete on EOL +`else + begin adp_state <= ADP_ACTION; end // parameter complete on EOL +`endif + else + begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter + if (FNexit(com_rx_byte)) + adp_state <= STD_IOCHK; + else if (FNvalid_cmd(adp_cmd) == CMD_A) + begin if (adp_param == 32'hffffffff) adp_param <= adp_addr; else adp_addr <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin + if (adp_param[31:8] == 0) // report GPO + begin adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 1) // clear bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 2) // set bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 3) // overwrite bits in GPO + begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else // 4 etc, report GPO + begin adp_state <= ADP_SYSCTL; end + end + else if (FNvalid_cmd(adp_cmd) == CMD_R) + begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else if (FNvalid_cmd(adp_cmd) == CMD_S) + begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) + begin adp_bus_data <= adp_param; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) + begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_B) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_BCTRL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_M) + begin if (adp_param == 32'hffffffff) adp_param <= adp_mask; else adp_mask <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_P) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_V) + begin if (adp_param == 32'hffffffff) adp_param <= adp_val; else adp_val <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_Z) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_ZCTRL; // non-zero count +`endif + else + begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; end + else begin ADP_BUSWRITEINC_next(); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; ADP_txchar_next("R"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_count_dec <=1; end + ADP_POLL2: + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_ZCTRL; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + if (com_tx_done) adp_state <= STD_IOCHK; + else com_tx_req <= 1; // extend stream request if not ready + + ADP_SYSCHK: // check STDIN fifo + begin // no upper flags so STDIN char + if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end + ADP_STDIN: // push char into STDIN + if (std_tx_done) begin adp_bus_data <= adp_param[7:0]; ADP_txchar_next("S"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else std_tx_req <= 1; // extend + + ADP_SYSCTL: // read current status - and report in hex + begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + + ADP_ECHOCMD: // output command and (param) data + begin adp_state <= ADP_ECHOCMDSP; ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param; end // output command char + ADP_ECHOCMDSP: // output command space and (bus) data + if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space char + else com_tx_req <= 1; // extend + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output "0" hex prefix + + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end else com_tx_req <= 1; // extend + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end + end else com_tx_req <= 1; // extend + ADP_LINEACK2: // CR + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default error + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .HADDR32_o (ahb_haddr ), +// .HBURST3_o (ahb_hburst ), +// .HMASTLOCK_o (ahb_hmastlock ), +// .HPROT4_o (ahb_hprot ), +// .HSIZE3_o (ahb_hsize ), +// .HTRANS2_o (ahb_htrans ), +// .HWDATA32_o (ahb_hwdata ), +// .HWRITE_o (ahb_hwrite ), +// .HRDATA32_i (ahb_hrdata ), +// .HREADY_i (ahb_hready ), +// .HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip new file mode 100644 index 0000000000000000000000000000000000000000..5ae9d96e74bbcd831a65923ed1cbf388a7dc8b62 GIT binary patch literal 16619 zcmWIWW@Zs#U|`^2IJ+!3Y@f)EJq=O}45ICf47>~s49WSq1^IcYc_n%kxjAoRUj|Ei zZu-Bkp7mh4^WFC3GkVNtW<|)`95DW@_NaA{--`&vOx4E3|G&c5ZeF^M?Iv4L(FwtA z3;W)zSrh*>Fm&$U)A!%!-?A=WXs@wrZu#yC{<rU1`d<H9RQxsX`{}3o`B&cE=l}QZ z^n&m&-4CO$?|oTnz0mlM=UuDj?cZH@zqqsi_Fg%@>iqBD_t*X1Wv+M2Ten=j_gJmC zRBw08cH<Y{+K;|H8@IiF>;LD+`NiK^-I?*Xd-LVbmrvK~h}1g^TnhI3-kj8UCfw@P zj9CvV-<!Lp8<@z7m+}AGw%PdUAH9;A?ezvPc5U0(yy>?7@9xm4$KD?L=KKHQgEE0% zo6{~I^4i_ElasyuczUM7;kxa%*;ZQd6+b-ov3u^By1ehS*4a02A8aw^`I`|VF-7#} zs=~8E;-2@`{;Tb6R+XC0zjwoCgE!^7uX0AqyxM&?>DQUaP|qKC*X`72+q{VN%Nu=r zQ_t!f=6N%sY@T0^{+n3s%Ey*lES|M=Z_A$kW#$u$m!-u8GP-?VRj{mfT2#pD>CYa0 z`tjkDfwk!3WyTIqJI~(OQ77@_)n?)QQdPz#{`SWHC2@OgzC53N@_oC!U;q5H4UM<T zxt^Ze!u|h?^XHIwXRYVz?Z^NBHfiR)vM*TcZ^EC$m-){I=T16R^fM>%><p8?UzTiH zRP3D>HC_5{$3c6)|5;N{uljoY<;SPL)1Ik6&3u%fzDup_x4D|+g0k(!rk5pK>$m@Y zJ-z$#{d0Wh`R%s}+3cV5Mz;3f4Xgjf`5zNE>%H3*y`w<x(eAq+``4BkN^El}nUSnp z&aW}k&@4$oee2VS*Rq$bs*ei1{`Yd=wQM6}yE{>>GVJDQ6JA{Dntm~Q^~r^66D#$6 zkFB2F`tX|0lh#e9+?FeI&N_YUh}`j~^UR@y7v1m7Vonr)C~oJzyz+ij8{5X5T<18w z=+^-z5$)ZlA74IiA9}-J-q+j*6P`X$=a*Slyx&xSH|eHS$DWvNY>O(cIQ;QpY}vUj zGSOH1XVQi2+3o(RS0Db4kCsngyV}%y?!3zjVs4ii&Y6DB#Oh?`m+2ccli5C{sh&P^ zW6c%EoIUT`4?b9w?j|r(C|XO-cB4~?);rf#-d1YcQ|dx~@7Zr-|EFXk>+uzDKWEK1 zd2y|D*6wo;UaCLy)YG0ZUEt)+pU+P(|Cz1u%~t5;*WHJg%g<Q;LyBpq#oyOYGXF_+ z)b=~D9j!lnng2|14R7O|{ma_TCwbJL-Mjnyb9M1_|IgPQ-t1NpV%rPV_w(_eFP}=o z&tCuXx=Mfc^)Dsr3YCoN-z{B>Dr#!}nbh+h+2^jbRQb~v=FcMW&I<DU`g-;?cE7G) zwlNd<Be!r$Uij|U|NcVKiNXFl%l#Fx+mGD)#-9Cl`k#-l(tf=5p7HSMr{}zXqOPx- z%l>Uks_C)lj6WV9o*zE&wL4C-S@uh}<Hem-!hb?<6mp+laVx9yK)FkQ^P^SC&pt+4 zP7!IG&cEh(&ds$4<T+$!&!5{bx%qtk*Tt(A^RHj+K6`>$*55VVix1uBf2;AgtnQQj z+VAzI#kQL3l_VFRoPWF^?(Lop{8R51X_?2~TYmG_><`Ar{X&_(UR+~$;c$2NdH3b* z)76i!y?A-P%tv#By*}0DMWt)^)ZdZ1w}0+DFW)*3)n%I$w|)}4S<Ywfs;1sAaZX<9 zUB|a~ItrYJ&z<JWX6ZkDUf%B<zrF0-HB5K%CBl1uygMlU=k4Q_*KM{tMo%g!eX;p# z)YeSzx8Ww)OBe3owtoBW`dq=r<6+gU|I;_>EM{Mq5jyYos@{2f&xO6+`uBnR1G85K zhpVSO+w&`w_x8=_{O!+|Pw#KJJ^7QU=n;?0wYO$Znwz-zp@B<v>csGh?+-q_`1Ixb z<ZJEc>-V&2oeb--Iy=ofRlUwjH+ZX!bg)IrQ_I{d=5tryYMiXwCVsds(6ZEv|K+y# zmx8q8BW~I{d@t=!a><<e=lUW3_0v!4&q>z}Tqonw`%6z)=5@#9--$1#aPQ&Tvhh}g zz{yPYGI0TuOkt~I+YbA_&{@C4v)0f;a_a}{$xW_$%a^KtJN0%#_vXVXwSIQ8|9(Au z^7!QP(|c9E-fd3&Z}w-?exJg|xtY0r^CMF)H#~cA=2S}9-kym$N0}bv?Xue<-dGmi zvVQB=II%E^b%%1!RBOL{sPuB{LFe=eSvJ?pil??@Up@EN?%l59z}K@kwiOF4EG~aF zS)n^(NvLJzKiBWu-a9?|e(p!!Q`Sw}OOJ{DzJ6l6@Tq)Xre7_e*4$sS=vu1ES;5Vp z#dk)P?=X$G`Yg8f+{TRdZUdiNS&SB!+sh_@k}J)bP`-N3qA<@TulUaF4!!X01oQI# z=xdq0Td$r{jhOOACYJsC`-5+NnZ;Js9?LQh@aHKm;rrp58}rcau=C!$zQ>XWxhCwF zykizKd-tN-=5HMfi*K7PjlOKK&Al-0{hv7w>x2JmPM9bBPwdOgUC){R*1mtWEknYU z?_RuLx!sKRce$z(k+N4M749!T{yx;Ag6ZhanYApTi!c5a`EfC1#{<@A=|2(orFQ+2 zKGUtc`o@o~cUIrA)H@TJ^l;{dWbawkb)C<Q6EkcM&1bTW2w1dY()z}Et&5iaSk_~b zotGXNG5t!0hyR<Gez)s%e|0y{obo%w?$$I5ja6Y4Q8Qi!25Ega=yQ&lu`s9mDBEYX z!y&eZ+-{bAyAzq|ygn!<wYGCM+xL9OEtj|5_t8sFp1;f{`=UZaOs(mh)nV5!1h*bo zwV|RUIHkKMO>Nf6Tsxy<xBvCu*Nu~v?#??WCS%WOA!q3nFDt$JRqyT)Q$Mlb_1Wzf zXWlK7J)>KCQ|<ol_?TGplJz-{r}l1QT5mk<;487S-H*>NFx9@Zha;ZlY<d5lxKDoy z&hf8V=z4ie&c;CThntfhuMF=GJAUjM&%Y@TD#VO;7@56#mKL{tYxC*7vp#Nb{k*4y z@!a{xpYq>6IN#EHb(7$lzP_njW9xEwb!Vlearf`yi06<ypTr%0RkpO-c>V2Jhn~ir zWw`UGGHzGP^XG+s!dXk|GI(`osik%I?c#`MkiEU3fV)5PzvoLKn|Vhi*7fx5x;XQC z?%Ib%>(f~B7;W`qnZA6s_#d79!+7E2Ro6r9c{<llI(;T->q)U=rGj?GJ>Bx{A6Ly< z%Qvm^uGrDjduJtXcm24hq~+#vA?G!GPsOjDDEVjgNbF3s!TDeQUe6QibV`rjT2T3~ z=o*rklJ!~c2bT7m+QfW6Z(?<iZ8^{1=U&9VkHO&8uavm!YhJwQ`4M(8ccaZ~d(FAY zKPPVK&u)IY_F^2{eX-M@FIi5LKV7ujEa6^T@aY$~n=0e1*gq#{zQ4wH=Jwe}sXyB? z=1mW~a3}xV<ljsg=lEAIbiKSJXJVlE!_Uf(H|pG8t^7Fk`{(Uh>)Q6|&Un65)F8kA z?)C#Gm=_xs{}U5G>tixGIy**3#P^qfyNQ=VNtnO(#I^T!%8Mw^+<$xSmFYKr?)6Cx zEDHZO_vu3Iw;7QWX7vT%zp7})bnoWR=l$u^*Dn6v?i=~x`H9)-T9&WN^Q#WeU7T%f zzp=(-@=2$@!;#;1uD-xoYs^!3tZZh}yT{KTPv*b+rCn66oc~|G-TJFCa+@!?PSic? z;C83Gbnzt5gBG(NU25s&p8h;jW#gUYD>fO;{l+!-_UxiRPY<nC;aVf6zbU@<hq;l7 zFZ)g-=gDg(zW4uc`TtCK?`HSiVZwgbs?v^a2{D;B*Yl#v@-vrGe7vStO7gCCy#M6# z%_l8^+h$JFy(stP?!Sj0Z}z^NvHHUO-KQ@_E(uw8^yr$j&3>C-X)<5!%74CU)`~Yf zBWIWE2)q9?TWecYU-V^tx4wMz9f`xT*NmCC&(1o&J-}r4#r*lt=E&YSSJ8W?f8)2q zlfQa|ZOWfB&8Rxcm&t$m(^<SmrnO0bKKoT3x&CR=Q-S*qPtMoZS?2z&E2=B}^)ono z-Tz{dd8JZv-fzD43Mc&C_w~H?N743OG20UKR&gE@wkhMg|9_Y9K@aPYm}y6C9$mh7 zI&)vv)6+~+y+1W}y4>}9!4p0I()!3spWDy(E-ci$=b8DEBeZsb>#NOaclYuCE#I9w z?RlHXR8jrRux%z2t{(e7Wx2)VzuSLz+AB<7UVHe@iq}iI8M00|+Jq(K$8MLO_WIe@ z=G$>EU$Xz7z0*@Qn19nPm1(B@m-n20tJJob{kmVW?dx`P&y0U%BIn-9{rSG|^ZdwX zPYT!He7x*v@A=twxf$<v&wb}RZL;Ux!v`PEU%qy8icr<{lm6M~JI=qFK0iv`N;Pus z1J;mt3nSmlaHxeoE4v}v`{ZGg%?AF5dX~@Le!4F<Z~4S?=Fv)F=dM)l&_2~^rBHIM zdZEqb=PTsh&K)l7^3&@+qT<-H&+!TGwdpK-pT5x*tk(@#{dI-!q0q2D;lUzPvNap` z-q3d5zIRdzSO2#?|JlFwcpr6n{o&7xzc)78S?%#LOa6Xf@7@2C!j320KmN^m`R4oH z1vmAp*4Di!U0t?O>(`eP?;kgxdUCV!<-(r{an_E??a!KxRDBkR%;MMCa;(WC!;V9Z z%Qf%dPlKim$%9WHYF<C+mSMKzQD61Kg+C8WDQ@Fzd)92-zVrKsEFZUbO^ox!l`bbe zJks#_;mqwE!Wnimo*Qy8_VMckEQxAb9W2}QUE<EEK-bzOOmTCg7Wt+;IPEHNG$Q1| zrw{YEd=B1BXp;7Ru$H^<h=&uiiF^=O?v#WJH3HgAB`h)Bs_C(c4-c%>O*bjvS$~z& z)TZjkf=21*64xHoBy_i^Fxs3rcCm8lgXHMdm%1AH<CZAuW&KF?ZaLr-Rj@qZ(+i8h z2Q>wqi=SmLI3}=tQba*<_tZ|V!|c348cPI1FVs9p`My^5L7?*?&8KISGVErkd02AF z-N|~WwDrTaFa_<6Eat_Nf>w4iwy&JPW34W0BG1CTw1;uN_?gMVEh-j%EBWtLGOfF2 zc*#+cKkr!!$Hf9(xzylOK?dpv%o7bR+64Sim@U;4WWs)yU3l6uR_1knll|094jrCS zAU(6WUuuQ#xm}AMyqZ#x=MwPXp2R{u7qtV|yQgqiA3bn(?RAcy40?PytZ733mQ0e! z(Yf^Co`kv3?iUB9ubmRY=6~>ctC0?~@Pk*)>hlA%*!%cZnU8*8zZv71x{`hSHlEEI z%<SLoB!VYK|EPAfF*@79`rYreu4a?K4x5%OlcKota#=%Ls`>Krc5c)2V3Z3f>ai{U zaL}&IXr%z#I{(N7zU&_>CaG<Gr^IT$UB}~WFVp?Y&yIN?vDk4_TutNAwFjqK3$+rs z^S-NcUb5z?6LV#KeCWV?tAMpLyE*Q}iu)Di*!-AimF(7PVtS#bK=kxt%K|%=q^1g{ zckGF8CBkH6mS0h5Q)1q(f9bIT#~;_2bEb(hcVs6YGw6SKUh6dX{2KxV6$$A!N)mTs zr-yWjd~E)FaEgoDf&I@M7cD+_VE4(OT_+@%%l$WAWYgr4+n3-L@kK^v`IN#er9Z4y zO3Y4^8rpd$aylFAn0ok>@Io64pUSS739-$_hPs&oAHs_!m1pTR)vs@iYL4W2@I%9Y z6K9+G?-{oxbpQBzzxVj^;n4#h&WFl7wx-?^eyg*iR8Yh_|3SW&pgfP-2mRB+P6FX9 zF|{5tx(8+M+_|Jta)n1`xkTaIWvn%q9W$Qq;C)aNpdz_h=FVS_i`)|>8rMhb%q`)# zvxlSmv~KQ))b5p+PyS|T*Ie8wD0#p<vBo4@;Fa-Orcj|jOB`1Su(sBFpPBh&c2PkA zhu4<lY<JX`%u8Iz@}p5=T9`5Wx=X61OobKG1==%aHrVqY?sM}$c=Lh|>x~Eh6eeEO zXnC;R)}!diB8K~Cm-Q8?A2hXE$YXf+fUZoLn?~<}!#h$^b{c$0lrak|<UQXW(lv`= ze^gJJOIATe!m>5f8DqLVU#XgY2-jVqxjmk#LZV&sa@zrQ?nib9OL+6v6~5ef{XyT# zDfc{|9auYOOG}X4frp9{y3G#B^9G&HEwVenY`MzvV`IZ=elZ^Pm?rC!F|PR^rC4sX zvAI7m?g<hVh-(**(@>LZu6Fd{o^r>jpkl*|4T2nV`1^b=z2W)8%AXZ{WWmGY8biI* z4#Aq6Ldz^4N!+vc-8kpMhnaq{56(57=L&P0*>PZQu*{ALhYn<yy3Q&15Y-d-c4P4a z^<QU_Q$_!<YQE7)m9y()dOB<R$rlTLa@;Fqs&_g$SJC3o@}`9+Se<o$Y?^wc`pCm# zuYgq*31V~jb5f45G_E#0$fVwKz*@d(>5PL7*77Pvy3FkNt)5zFB%4~;sd)Mn{9xH~ zX@ilZ?2etO*G_3X_};{lYPjZLZD|@0cNOowBG+Ty?+$*ox-4PM^FNB!nM+dVz|RSj zGM`EQn5VkU&V_e>UgRhHIqcsjv1;$HY(6->yF-QL$M51RokmMVE#z6e7fM7kYr9+W z3*Fhp@s2f$J^$|V8AdJzx@xgcTn@;uDDIP8Dp6DHvtfyYPR%Lfhk|Bz8ea3iGu>{} zG=GLr=F%%4G?@$+pE3ARI=e(u^-%NUW|#9G1|NPHbbR9YziFR{#gYcTKekLlHAQ}c zKh*X=j>u$|d-M3yW^<W;+JT0NR}NM$Pu;i3L*qxB!1NGB{{KPgOEj<aKj?N<>6P<n zc;1|>xQ2ya>e3?D4~opaSGd^ZZyFuj<G07*^TAM_D~IY|_6ewSHtx@z7;`8=qGnfU zo`m7NhTU>~(V`E&U)`9<$o*r@fu187oJ{>ODrt?yKWyZEBqVwMR9a0Fv;Hytip1A@ zS`~!`3k{xf{M#YI`g$$H{RU0lIo%&l?wQ>EM(6qi3(-pt4m{Z0!+Ml8vf125=Ti}{ zUhl*cbIm{K?<~sc75ZS=xKzpRLg^1V<xR7sKRlgOW2mH4!&f&;tozG{lVOEC$BcR3 ztqDG>T>QaPXK6~r`hz=Vw(CT2%@6BVc4le6F3&RglXu61&xd5TNv&_RS)<-~Fki*E z%{Hnz=AKcItmGf_i5sr?vHb8)OO!V`#`8y}OW9wy?fygmSBEY3vduQ|c*yYIHe9V| zxuD(IHUlTCt!(mqQ}tX8xbDab@4B-5!*ni9zkMqk>c6+C&(PY#mnX3NT6RIr6n&$p zH3yz5Zk%?-@WbXdjg_1qW;-6^c=E8=({T0F)DQU~UW$u9$i;P6IxboA;aXVmBc2++ zgk@W&a{UVx))QPL^v}b`BCoUYf5LJVHbc(&-P5hlD!1D+A2NCIWNuTmxY8m6u78&z zK5<E^e)!e=OQS>df#cE%AsWp88G~QWS;TbjU2<Q_h7XzD22a}(e<+t8Y+8{0L6<>n z<}t2+1%1VHO;#}+*HpA|W8EJ&gZF9r+k<a)-3}?ZKj2?1qC6w=!-`EUnO8oT-<XvD zO1A0#ljBzs^shf)KGEXJxqteZoGWez;<r4x^Wf7aRTKG5f0QN}K1k=4S^epi#E+XY z#~qV->$mlHhR9WZs9bpEMT7E=nU8}Klpk)LQKIA;^dL-+b!wx;kJWrl$$lz-e7&1k zbd95&J|E=i&*NRE@i0Lp`NMi6qnuNVEerDJ8jDTd&1a`SMfkbuj#9-t0VxkIvrLQk zzs~b-#iYd@*As)gvPEZZdhkP_C$ssQf@ML;A?=E-dTSP)JCI(oKriCdgZQ1k>t-A{ z*!*}(L2E?I{>oD+N4x|I%sYyGR&IE3&+1}N6#stC!#uqzS{1*Y7JU=5+doYpgqyG4 zwKLF_smZ_n^oF!5UbC$m1KHXc_Qjn#BII<ieS6Ri5x0Z+S;ot!bbpwA>qula)1P-U zrYL&w%zr<nI<xb_gWbuKq82wX#c#JzQsdnt@6zGH#qzJfFXBzWga<VN>VZpMe+&%Y z#`cq0!|2Rme{OX*t*isn*G};Gv4L&=heIm9+<)>EuRF3c){9P85He}@H_37}+Rk?8 zR#MK|?H?}M`Omtt)AWRKmauRc@0vM>+oFH`nWrP=DEsHxu7t+IAJUdRMQb^03baEf zu}^$(+3D1g3bwf3KqVdDc>*T#M}+h?vd3>zVO#%T^QWREypNdfyh!$)`b=;Re`H+2 zlMjBII$ET;|68WXm>gvM_x0Q-g=*eyG8VlpD@|vJc}9q27x+snJMU%OzU_*Zno<pq zs>FAjbq8(hp1qXX^GCaq$1UnZ>gk{i?PP}S+YUvhE7j<=E?AuKA-|mKw96sQA4mBm zZTg}b-g^j2?)2uf){*}x?;~{5^P987@9TGGZ+O4ot)}_pzXh*v9pn3!{QlIN`=aH? z%HyXQ>#PmFdB^WS&qa}-fGL}gU+5`(H1piEc!p;_EKif_=JU@mmfHI9$kQf<jB}S( zUD5kpTa<BbNyxRd_Z`f|#|%H+Iz1<>^_fq=v^$GUr_3z6_DuLHv$5Nn<xww9L$>(1 zFA4cJEpXcAYoUfYrH8Kn?R!}geDh!6c6*-h`F4vUPd-RA;4yFhD_w3a<-U5y%e^xH zgSZkmDSmVNpx@cc_HgRNjd_2##eE*!?7xxE@;}hKwesBb`yAgoH{N*id1Wrk|4Cfu z=iZ9>sr{Jslw5Hh$Nv)sGyh&X>-NEaafeZg{kDCAf7JhY9}EBf=~{1n(%dI%)zYcT zKhm3476oS}|4er*ob&h92e%LYJH_Nu_5bFx{8!m&$Cj$!oX_(Aibt2>&4}OHNl!XX z^~UbM!nHE@M#TR{BdMK_q^0*g=wLd2)8vu#!Tl3j6yBMI{j*u};%Lsge~B)}-CvL0 z(ob9RMX`EyrSXq&ABA~)!*&Y(NuGK~Ud}x1|LG<5OYX<~KYlFb;3iIc^QPL)qyV$o z2TGNHh^L;KxS-fv#;oc8l0Uw89^BP-Uy*V%dy4eI{V6A_D)+jzi(lPza7RH{h*4dU zJ<nXni*J3j)k|$3|I1z1b?$1WdRh7rwW*K)*YW?|^qA3+<^4m+t4B{Qo%haaM?HUD z{<29jJM#29FWuwwvp#&G|5)q6cUwN4+mau=wA;%l_rtq?T~~U(|22?^`BHSn<HIb0 zw6JAj-DN-0_gCLuJu&Evi>_<T%n<#vdA(eUGc4LpoC;Z2`}@onVV21UvaZZI-Xwf5 zY}vJJ71x~)4h6=ko0|MxZD3<(KdV74+I*?mo3h*Q%evz>TIbKn{I}EGry?>Y@o1>J z;}+515AD~!{;&7h{LTF~%Y5#D`4`UUG`Sv27d74Sf0O+S(Z5MQzJX?A;$zh|Ye8p$ zY<}GS&l~`ssw(X?3;o`*uHdya1H;*V1_l8J28QCIWPL}MfZW8q#Prl6y|SmV)y2~0 zlm7pXdHTK~W3^Cb_%;`>ZK)^E>3#hWCAzmOB<c9RIYvtDm)4w=e0S!;q|ZCv7vKMM z;VuK4|GAzeXYXG1U6nL3<IDQp7ahzE7<O#?_C#_1@&0SqA|~>xUraq%)x7tx^EUbT zbL($J&YODEVD^T@Y11mrW*)J;^zDZICKcVAzSHU-rC!bq67igNOnKVUH%9yV)RL$5 z-c-1q>^|qY*6ihrEz<YaoT@sUA>uz-@qe;}IO}Yc!xp-amLCwWe9stCWU0S-PeA-T z_xY0rtBrq7T9#A!<;$~|694{0A3W+k-|g`7&;Hs{%{Qmp?A)byvwq{ds_mbb>|Ujk zc-q|D+`n~||K>kjt8aeWasBfT!9Ux#efz8-r=EGH>Ua9?y$2u4y*}{$a*oOT2h%TW z^sd_xcwkO`dE_LuRH4G9KjTy9^e;~Q^FuKCjsNM*8vV-*|M$)P>fe9<oc_0a-+uYn zuD^N7-`nF<*bDieI>lj|D^K3=opij4(Ki2k-@a(m><zP|{x%;xSotdC)HBs9m$Yl| zyvSMqpQV29+qdt(o9_~jT%5H=d-dD8`|@-0O;(55=J!`Oe_nif@B3Mye@>XG$eF+U znRYqK>(s%A?aggYbt$J*p8vgfa=}VZE$@A|-_QL%Yu2W!d;4C?&y%mn`Y9ECaPM30 zElUDzzZR&!eEYwmJ*wGw4U6rMFF!t9dBxt=C4ZA!;M4o`<<VZcbN6c5-<f2i%T-}< z#`XW-Mxm>R8z+CcA3vvAbx+D8!4&&1eSF_V=PvhUk&WbF;pZ;<_pf()u<DJSB0f<E z_&HKkW}FXFi@jPBv*F;+eK)!45-o4O{QkVO?Ma9)kLHOiUd<P;csRA@Owf!Co0{UQ zqj@4rSMx=Ss=R&F&BjD|%_;jo8vfS4oLXigBoaO$W6gx~x1=VyF23nnS3U9g|0gAC z>fg3LO|@PX7TC8cYT43C-OEcl)LI^?P7PRA7nG+ExN7E_iI>lxoYC$q%6+hEa*l+r z!M2Te@0~p9`2X#}>bUB~zt4W%{54U1SIqkltL%?YW@2xs`lL5$`Qnr_FXinoX}yts zA0OkU?6>dd*{4?ZWpf_MHG6m+oh!>0xU<7M??vFb%_1QRrluPt-gvReKIrEun{0Aw z|AwDAlL|ki&eQ4L^w35({D#H(WhZ{?*B462hWA)C33^OAKIgcJmYt>Oxh-5yUySFi z+W1;S{;tb|nWqo)B+Q*<zhaiG=4TVF_UmtoO=ceF`^nxL!%*At`OQg-hZ&AvQzl28 z`DRkhnKt8Rs&Ko=B-x8*my|Mi9b$NA7A^=C`oo?Ya<1D{MnvXUc~{)cM{543Dhy9m zubt-5nLl}w)%l8feBSfKHk+&8S#a_N)2`ezrGGXtx3C{Im~}Mg#O;?Km8CrG9(AzX z&w1N$*;>@{hLM=?)7RH~a%+q4?raHcyB(<{^+Mk8=)^T`moN6o=ShfeJU93E>7e|~ z==CQbZroh(YN<xdmgl;+ninPRSn*!>m2;q+o>WCQTR=!l_r1#QdyW@<cf8oU{e`W_ zUAFE!6O%Kqd+*_{(L3yV{NAEujahBo=k~a!2bge+|9znQi?PeDz1yy$+s@&l{y`;6 zy8>y~&z?JdCvN>zyQocZws2E_n{8~EW|~d>LA$nkL%Wq)i%+}R_G*2IODi?LcY4=r z?Kj)+zxj8Z`&#@uomchwewTixTndv}!CbT><8}AJgg*;EKK<f5!#3dO)tLJ{D|f~% zR*U@b;0wpY@4ptjxX2_aQtL25L*>K@w+TOU#GXIUvQ8{;4VL`*(_j0|`bW(E9Tt~1 zf8@F?cHd%xk9_j{ZpX6nc|LC95(@M3<6@3)U;LzNd;6s37cP|!HuoL=ynlMBti$^H z1Irc#6YGkwK)1@s4JP{%Pw)T0A=@9OqLO}egSJ_M>%CnwBzvoQXMEJZsndV_WG=6} zREqqh$G?*L_IJIvv#UPYyH_jd$o)!Zoziy!o10B{zs)Y=D1OXm%2~X*^laaS&o^bW zgr0r=X4*PW|6RajgYCDjwM>!8-nYlu_s|lT6`{Th)meX+nQ~6Pw8G3Zwff!tg=&d% zTh?oSsVQ!s)#5obW%jH~+otGlUF|tzO8d5znz`1yoP7`V+`cYS)%QL?*f2F{>xykZ zyq@s5>*%%D)P<h=yk$aa&+(nFHTHJ7^KRPUptI*sP}awaKpBxK0!w4X7U=!yUb1=; z^QYUtI79flT)Ahno$p;|<f6)av9ri~OPFHR<8uW|7kPHvdtvvj<%PiNSpvOh<_O3p zmEBcXpyaOZa)0(>;YGfEPaa6$?T^hV<zPD~aCbqPg3I;mJgqO-OqmsTZA&w7F<&9c zaq+9Ev*Iqtvko2WR!j0-<jrDpDycmi(2*BlEU+j$o6WhTc~+x9Y`n3^BIzqUEiZ1( zf*Ey<rwwA%zBCON^A$T4TxM@Q8vamV@5Nm4MSnM5;JMiSXo0;8x7dPpvWs>;J8)il zk?+L`|7TCmG-2kBS-@$saDj=hp1yj6f8q?gB*Ff}20S0x-(-Gx5cJVtvofbuTvMOY ziyxLH+D!KCyq*_0Pi%-3{9$Pm%)%%+FPx>0PoIU6XH{I&+O7lVA1+nmI3W<qQpY!a zl0r&*qU(d_20<*0l8?F$oKNIoiTYo}aY5c`FKfJ(+n(m5mcJE$%JdqA)p(wMy~Bg+ zSmfDBU%cu!e@!dcQ*U7LXZO#%M*BT)nBos!)?WSm$%5CfbB@>erUvnuTsoI@X}W0U z^0wF0+@cPDZB=@E<>apz<+Trgtx;M#xinaL?ZaJ)o(G?bPcAdPB(-jC*A~BPrM*`U zPwnXE^XIFozONayeq)K3qV^ZXeun>SQ?{tDNP4;0d0PAO>U`6T{wXfk>-U%M(SLDZ zmY%(0^8de)>+f5y^QgVxaO1YMy^Za~7d01-d|I&Fx%x#z)`!Onf>>uAYwmvY!FRsf z_J;eGI!@eH^W{R5vrFXamK;C$+xe!-g)+Ok565Eig>sVl=T>apr(Y{L=h$)oOP=4^ zb}8&Ho;&}#Ue~%u;@eKYyH^>1^Ze_mL#bs88_Qke9iJCPN-c5nQd#>@>o*slQ@7{Q zjK(E;;a@sq*RH*|HFnyfwdei%Ti$s*f4KaFR_>u~EW5l!=j(R9b51QTaXoi_@iBJi zURU4Z4d1_ol-86)g*(kHC|EYJET_Qn_urG{>dW7|h##5v%4n%x$LtO*t8m$a6FH_T zo;)cYpcULShg)-Ma6o&-AC3O?62E`&2>Dg~kDC(6xx1$9$}*98aw(aAo>*x|&f(h} zXp{8uZO$Z~$wi-zCR^&V-?-BhxZ^6b?s36Dk6*`HE(j`=XYe=LWjd4`5|~iDrENjp z66X@J491;a(Hswx*p4viDjd(`RNURhb}{mb*aYdV%?>Q=NsVF?g10s)ut+BbMmy+T zV{=ll5a8a@z;}bmNoj__hg=CJx8`R8Tn8H?7O?X8_9|*YRQ}1~TBv9tFingl=;;bx z#S#|oLxoYY3oD}~IILKn`Al2L(&5!D?Kp#Do0uHOkqIxOg*mtnHg4cmRY)<q$8gBa zKw-m$HU);6N3J_taG13m4`^8U>3<Z5_`${x5?vw-S31kKupewIm@|#x%9_P&huRYy zOYUqFkVrbTN#aoV1BaHa2X>xw;;?VxeVF+!YtE`h4h0K=bz&`wX%XBCP8@110XqeL zJ<;J2bSY4%iOTrAOTk6rVB3eSt#+zBjyetn3QkcSH&Ymr1e;hN7Dpv3y=sr>NO1na z!^)@nd_!EvQ4YSA#jH##cCP1N#OBzpaLK@Bf$l2-nGV*dAGa5Y9c(MOy{PF!TJu-1 zy2O@aE7&;1T#n~*Gb)9#>2#=Z@U^UNbt;&>Td;}u;Wk&+hbHC5EbK}PT4PRKP?S=d zA#m?rFUP!Rd0h`2ETR%@f=;W8x+JqOGiA>dkUGFHEmp*(n1%h&YS*oC%8F465p7Z1 zw+cvPt#o(T;<!Qa&a-s_tLiRt9c=s{wJIvcsiTZzoBPhTRSHiGZU`N0d~u=b+Hv2S zy|31!Ulglxbk?tHd{z_})3eBE((1%7F>aYs&%bPsG&-|PTy?I&>aYs}fm0s5PTcNS zS1rhEfAh|RJ+qGb&bcY9`bc+6=+W~&tC;WnQ7yT1TtxcR0|q9Wpq5iMoA%xjvd~*{ z_2PsDPn0~{^X5MCRxFgW@9I+8>2;Jd{9a!Z!%`=vd%Ny<NBp<FZrQ(hrA3FjTw=(5 z#)Gnsnm(EuN2{wJ?|I!P#4P_gLQ#EPRG$0EV!3I{my|gQeCAl#8YFvML?JY|TH|Qv znXW0?zMnqGh1_h{eZ11-RjBr|l3NEo(&qPUIiu>)x|3z)^_WF#jKZJJo?3A#CTHiF z2eS_gdz-y{owBR3_E(Vml%=Q2(#$_j3_G^kYIec;dmr=o^VMd!vBua5h~{*r#9rcO zef_Ssw$gA`?B$)@zU)8j4!v(xK3(_2^tV=o`-F+NL`Byt^Us(pdi1PF&a^W-OfEiA zdvy0j{^`wYI^4qz<BAxb2VDBmWp`PWts>aTDDI!v|25eR^W!dVR6drlbAIsVR8Co? z_;n$zkCje6d&S3c<!z~{P{`Ru@2n@NNK5Q0kchXkx%pau<LSz{DLg9{pHz|CIQz9l zul?s`nx8dvk8M1+b{AXYj#3NrwGlC84!1MoHpefl5bgZ%U-p;%o2wH|kGQhSe|*Lq zx|sW+tNLVfX%5}GwLF`+OzYfhFX_|<9r?c|Yh^dD$>)rX?h_rw)GJ=6SQIVZTYLQN zwQCs;%XN=Oq(?jxzEkF-8g-yq==}Hj%J;Vy$Xx&YRcH2(6(0rG{fV=A^}9RJre$LM z`(FVTUFsL7cLz?3`nz~iS)pRi)~#HQd)^&YIh`h+S;H+9`f<M7NA8;|k4=8D>cQT* zQ?DETPJ1tX_4YAO8_AtB7BA_@NS_vasC~N1-W{C<`qN+RxU5;;lBJV)J<v*P-C}>k z$M=1>54yNWUYO*#`nr61_*JjXv+N!unx1zoGxS)Um1gikc5?XD5|iwTqgiq$PoGEd zALIYX+S~U@Se_-*LNM)dnD)-shH^#^GJez?J7#g@?z9bOcRhKmAm;4db+jxi^F{S$ zn|TKpelXcL^T1aV8z$Z2-J27q@IB`2zNCLZS>H1F)aMUvGV{J14Zp*`g{7aryr$&R z=Uw3?R_nJb8@tFjxPErtbkaWC=&ixKGJ^@*l41|{{^u{buA`uLwvfl*@yi2ip8PTw zcidfnT$y7k+tV9=>lz-5%b$)-tkCX${Op2Q$qkuzL64ZusBN^!*I06;_Q}=Pe4at7 z8(wM8%)DftxblE{v(rPz-|Q1Se;ibrX|i(N(QDVe)C!f^bHDPuVavVMbIr{m`Tq*t zDMBmvv|g6$bNG;&kiAB?CtPgFH)$uH8cl|-{fg3)rcK^*YiGEi=cd^r$7|QR7A_Ks zEn1j(VMmYTlxXYPjb>_s8`fSw-rXM%ulrx^#e%Ts>d!;o*cKUVl2{sMlyyNSw9N1) zn}|}XtEw^Uf}rwd4X)a4T7Md&S&r{eubIG{cX@}#BJINS6D+%1rAnr`zEOU9lDlW7 z<r00-opXw-PX3f>5%(&p4STI>zVo$ll>W|>vF|(Lie6lqq3`xdV)H6>^<5$U`hncS zew}k({PK1Q-|lr~hl1CgDQg$Grhonvo;f-A&}7qJ52iRAdZs^da(?6@y-AJh+=Llk zou6fT(VDxt``P+en=dl$`5v1tESLAZQf|3coN)L5^?l2&1(!LTDqkhT5u{=<Z~cq^ zhs<tn`_+;0f&Kld0{`xlG2ag_yVuqfvU8^<=l>tGwWcQpzExkN{A5u}eDD4O(*>+c zcj{ZphzU#1%?*fi$-J@sTC+FX@|^F-H{VNmFy)eRVB@rVS$U6LO%K1Gv0XQ%@6N<! zu65kWCTsf>j`(jDlInflT=>sY^4RJtya|sEuwPyERI=w$!SM+(MMBIwCATEp2|aZn zeFEFP`XmG9N(~7|hg4$&x2o1d4;OJfUGOOIa^b~zh6mX%*Guhtc95~AqIl(p)>mx| zyJSsjr?S+`tXSijTYmI%-9O$GMJ3k2O_@oF^DlO-nd9<Ip=nl-pnBz}llMb+?yk6? z(Dy34Kssn;@Tp%*TBkW5Jizg~y`W9AS6%MDR;yjqvCNLvd2gql4%AeTs8Hr?i`0KF zpdop#FC?B(@uim9liqtL|NTktKd_1M%oewaCw}`o2&QOgJ6f-qaaK+GoR`b=LccAK zW_G`rtQ5epWEp4w!RsHAUwPIg1nSwkO)hco*JkW*wB;x}%~8-EW};l-UMc(BoKsy& z^{Bxq_d_>U1@3UFXnpfi^6-~_?IO#QZSx;+#I!0M-fk?_y4PXH@;50LlK<4cd1v=h z;;g8f&A&o<sV^4Z!aEGE=`C^pxboSuC1Pw3S(fu$ln5)UJo98$-=h@|l=sTbj@*2Y zogvXz{F|NgiT}16IhPz<TOQXd)gqVO5?i%3#C#Kzil&CabsNU_@k}CR8^T?_uMPI< zzgXdt)$=+=!rwY#-V>JIh7BS{Z<iH>gzh_fq*^r2q`zC}!NJUgl=V%kj_oUr`D*Ua z9TC-N-JEPO$EnfOFQaD8hN%4d+l~8jA38|K?VNk-Yg7J=y3e`H`wLyN44H0zYN<YO z@8!qB_bKz|e*M*ac=CR0moE}h4|gnFDrgWRdNF;^XKDA%Cnjtt+{R$OZKkG^!M%bP zDOSDioFW%%r$||w&XOp<7rExB`r)6SBreHGOi}Jvk~_w}++FPUs<#On8UMUp?=AOz zk?diu>W7=%8@He8@;}-0ELd;b;aFyMk*E_DuHTRK9Zl9<Unv{+W^$O)L5GQF6(Zb( zh1l~luG^k}-@eT^nlH?W=k#8^ha7gX+a66k@;>oIqyNK$X5YVUtCBB{QM3_U?w;*E zCv5*BQPGeKm+ht<*RXE5n7GxdZECh&OWEQL{IAd1Jk6R|6(hpywsT=^ZBxvTW0m%G zJ6BnM>^dIWTJnT>-?#iH-C<g8t0vDboEO4qrLdQK0qgVGOZI$IYKu7`p!L9S+k#!f zALD#i8(qH0b%&KRyyIJqaLkI3n?JYSynAwTsPF;yC`TuopBGCkR;$W}TQ0a;dGAB; z@`G_1XTm>hxU#Qxd;Gff0mtX3R&vg6ZjwuL%f9m^pL==dbH`T-mkNYFpS+eD^eFm4 zYeQ1;q%E_5{W1N0zRNZ*zDj~|w}!%*n0Ko8@<X-lmy}3r#D1H3KH($pjo6euy8~pZ zg!MWjYc0Yv-(RndKhMJRdhX**`HajQUw-s&%g{b}K)sRKmAyJ=sx;#sZpIhumxKhr z^LX3){XpE;iI4o0_I~eVS-fG|lgCeY`Ch8ANL5}EA+T2Z<ksv{u21$&?+MM{RLobr zU~2Q$z@Ft62C9v=ZU-hSx<zO9*M{XthZa-^sA}x1G5T}x)ucYN@10ud^&NX3mK<Q7 z@w>g<!2Hd{RYzK;H`LGAX#Yp?*s)@vxNPg6>INTXi0pXr`gqN^r_!}Y3>i%Sox5x! zmlmEGbY$^Xm8WGAy0c6^3-(=X<n|CtR4IS)V&f#gHOfWjES`TpvvQyQvXJ*aN3-qB zn(r$-erfS8zUx`)G3GZ0{mTviU26@B{T29C%us+stg=CH@0^d(H#~iw9nm>gWbrYo zzq3<jd)I2MvoA_~)4ihSPwTODl<w9zulhu|qixk|#Z|x7s&@sp^?y0&E_H;f(qZYn zy0S0)GtP^bh*jKu=(+yC^6!6dUX(N*=A0QI@WSs3+XUBBYkTLv-0nZ+M<`3|9w&u! z-zS<)S^D|dkzC{17N^6kSxY|Uy3TYrxA8s_-?Q=AlM7w*IQN9B+*~!Gv&`IZ>Xl^) zjvEiJUd`5Y&C54jhvk3$%z1Zv-=6z?tm;>Ilx&Oj>zll<PF{PzI`jEWv)fr~GAnYw zC7RsbF?(6mME&@-V6mPwhqg%z8^vFRRhu~38qe{y@37sn<E!7_6oGvgj@eG0W?J*u zaDAup?pp_#R@=p_&N|((YM;XT1!pz3R=O(udii*I-m)t<{#{w6+Vr@pfam#4=4agQ z%a^C~aoV=MRs6rEt>DH@If?yCubyRKyMID<)rRDghFo$ROnn#aQ;WHAsW1D{4bcPb z;fedaZl_9{?0xsQVO4w5?PYe)kA2?hw|M5;H(GgxUteAi-GAh;+=0(KmYzzHN-utY zCt;@%?+nMBZB3k)xqkEinY~>r?e=Rqft}hRI<D@AC)FK0<5r~g=uPTG`#Osk^EW+i zejGe6;s(nXiL}Ekd+io)s11tOIN<3s+wPf$Yx>-~W=r4yKhGbWB=kjJeo0;5S<TR| z;U^;d_}Q!dIBl=FxSv^nX8OGP+z*$8wO*@RxqQm8-nAlgZ)2{&RUXa6kL@l;<hz+f zm)|@weS@ZE?=`OVFYSA3w&b}BU8<YN_>Nyn{jra8$hy<+sedl27p__<@Lc!p_a{rH zZBz6rFerOda%G$P&Sh+?^y4<L8tmRV=jO!x^6ANX?c4X>^_F`lxO>T&+<1p%DIpc% z$rmdNeWlm@xDq9CBJ0C}ed^T;mva-fx0z(vF8#9e=OWvXzU6be8zm2K+4p;v|88;r zMSrdSdD-jvl+RiGB<ZW1{e*9_J8V9c_y4Q@e)0aBB`!%ks?KjiW&c+F;8IhIo9ooD z?Tkf<pZlxwi>p{pWtKi|n`YzYZv0@+qs#fT7YNB53p^-U!(?^xO~Qj$TaGM{^-1Iu z-OXUP?Xu<CWxcU($IVQpI!SaL;;!yF_(e&yUVZ7l-l$ibx9nT;m!~`bC~w8hopI8K z_kH2m6sO;DXtnX`@JG|XPpmkt{Bf=OqucFMDqh<O?N{jREiQCB*Ynyo`q3XL52mKe z2hF}c+P7$b!JTV|cdqq1pB?&YUxTX7dav{ES6})(!OQCTHZ9xL;hD+1wf!Zdv}|{; z_d4&S^>WVbRa+ug2R&ESIZzpTYtMSG*@{z3&gF*QS`q&8X4&%B;hB&3Y0Zq5Wu9|; z)s?m3E1A37<EHNV9(wXlnbd<jVN3nidTj`ikdU+b9_p#{ZU@A`xb>IV*3?ynUJ?&| zzvNPt$I{YmI%$!ug&*YgY9CylmpJ8+5~IhIUP(V~y~l;qj{hisayL6a%0*d0sBmM$ z262v^6+yr4O}$rb-<+6vaQ+*g(_QS#-PNn2ZX9q()cx*y>22_-Sf(76{R-D4AMW}W zw}0-1ywz>%8!l|?+m?~`_8sed$)3~VT6MZT3Vo~cvd=!9p7L_FoBr9S7q45KH#U6R z`Bb0x;rs`-f97YJ%{n}lZ3EZNZP%)IS0DNPn)NwH_z#&cKWnBOUgG>`qhj2?dbjU} zoy<!0QFW^#*_Ot|{mSJ07Pao-M*T%`YM+)@h{W4g#9sVb;FP}T=BZUn7BT;13zZXB ztqTs!oGvBUYjr&OV#anULEhM;lnWW<qJq39c-VKENEIdqs`9_zaKde|V7N%AiR&ls zSf}8N8Q+BkdFQnmWp26M(ebP;Y$>mlL};nbtM_cZQ76OAN`4-=-6!9;Xj8GtucXU7 z=Q@^TbxYQ<NEJHu*qXjScu;Qk{kQ`~w_bE7rNw+$mf@f`+a;!QaYn)SZY3#+>km#e z8;Z?P5K5SIj6qmM$mi0GglBhci*!B-UwoS0b?lnY?iTlp7EZ4dk|v%Ejc1;0vMtSO z#u7z?kCz$`ewF;si#jnV8M7*CJu?Ht1#SigQN+Yxa(-S(QGQN*nPI$vUfJ4duk&u3 zi8Rz-Z@B+(!QW)&zDX9WVkHs=S3ij@KACjlRi10&38CELiJr|%-c;pp*)F5M$VIED zD`|1!fk!_p@@%Y*PoFOS|M{!$distR{<=2utzhumtQ1?wAwKygkJ1(`bA$Ad3q4{J z0+l3mxsH5UDe!O63=WH+Zz`#~WuM6eHx(^l3Cox*mc1Z5;sWO#@43nvo_!K6IqZqk zo@KNf|5SFK<J@TMV!<^fZf*4<pNFBE8jruGO_3|$vlmr&N|?ZYJYj9!zY|NVRXjE? zsFAYb`ljAy9?kgwz>ln&T0^<3^A0?yuwe^b!I&ytyJqgp|66|9ey!ZPxH3|KV{zrw z-A^A@RkG$U$xzt8e#v5a%cPil3`;8ceot9yt#aj@nBkT8jWJ)<&OAQeUb$(`oz{&) zGrltK`S&L(dh@Fo(~c*5gj_{9L=|cey%z4!E!rt+6*%d1?3%o0g|!70*ZfbllwLGm z^F4ms%87o(uMWg?r`~LdH_++&((s`6WTM-W>90+kS6!I)rhAd$&FPzd88|b%EZce~ z?datd!3PA~n=)qpx)gM!A#l40&(fbOYkyrX|G>A-?s~wyt}SP;9CD6&P;*80g!8GZ ze{K6+UU<Z`uX^h?U%xCi=t|`DDHqtTJ`D=b+j+up?WWg1Q&{6q1~-@Py4tbdGW=PF z`?fU?vVUgn5Rb`zzQ%iE%xv4er6wgOHcp)VJzUrS^4YJ}%(Gri(H9BkUu<mAV_Oqy zq<8M|xl2F%mTg`zv&wka2mgY{nfFhpt(QCZXrHmn|FypJj{Xf`_2#T+%uju`;@vBo zcRJ0+I#<>;?>2w3!aVlj&NBY|u&XX9i3iLd)U20Fk>%Nc{pk|7WpCy#&6>h`_r%L| z=@oPMcTZU&Z5r`(qIvUzyD!<#9Shi&Y8tdknYmPL$Lu@x8@{n`lb&^a;WvvN-OIZ( zon#Jeac$>Vtg%m0KhyWdr8S-3<sZ8iJr>v|mHkLDM&*0|Wd2EpExHG0O<1UszqPAt zgK4;M_s#ji$xD=SW?pp>YTvID<DZ*)^+<l;j21Ns=Nm~`9Tn4jVzsx`&FTrYDww-* zTVI8gTfIi*<ltb{ylc<dGB&N_J}hK^UOvB9d{V&Lqkq11+{|6-B>2P9u(GD3K3?sZ zwAF{US^X<IrtMG*v9bG*U18rX<Fx%MSES0s>}95+H7kss^s~rsTozTl@T2-lMd9GP z&uU#}XK~o8v4(695!Nk_HC|i!$a$(_{j?t)rdOpjoWIUG{rb|}1@|ZapKvDraNYZO zL=Hc*EI2IXZO&vLMg|5cW(Ecc1_p+T^wLbw+&@YdFG<c>8?Z6&kb%gYkKuC~7Rq{A zZ+2~932NvFnzpLz&W}VLR_mfUN>WenziwF+w924#<CF6D@9xI(C*RUqJI83&@)K)3 zAMo@{jalt~$dS`i@A$QdlslhnEjRsaFzq(gpVsQs8EF!2vp#TPO2er?1r|@7j_|Vo z&Hv$8%~;}|Heb^B)=}>N@2lMO1)MTFJG^&^O(;3Le*1?jsXd`@o-8@RQZC|tP;18V z*$Oo?c@|wQl3V-uqDe$$eXd9Dj?2zZTs=glP55A<8dzR%>B!S>iSAM{@`>9DteY0} zZ291*x9j6t6N&AcZd7ZyZ+d*|xK;Jv2P=QoZ%@DKy?;&eNzrS+H@X)850Cu(v_fcG ztX83L-t7AZGbSHSv*J_qoE&=c@v;3YC)!`VD#^9$^!tzJiv5kGUI$k6Zte^3s-4iY z#(G{_#nk%rznhMxetotv`s1oytMw5v@V7@XxV_m(%$J#gVYVCt11AFmLsE)<Qi@(l za?aa`!0g)w0(E`|{yU!jWa4o=!N1imC3idPwX_mh*(nJj(Rn_yHz!ZM6!ho5_FSRc zfvMN?*7P{;bLu>Qt#+UP^4*91>=QS(J4qFNX|WM<<$P8w^4T&`Sn7y|@UyoMzm#@| zTKtXkvS@jH&hV>p)4F`l^8A|cTR|o<?pBwlZ#&k-&An=NsuY`Lut((sHAUTxwSNp= ze=T9}-H=wvad%30hr#E&EXI2Z78^W$A@$GS@6PIzC!dy^?ECfi^_QgD!oXb`_cd<s z7ulb#y)Hr1$xCsW5$B}u_a$7VIi@M3u~Zi?DUlTuDxWwh^+d;kx22~dJ@N&A?mi+Y zb@9gGms;gVEIm0M_rJ)gD(Y(cpk!>~p<Lt7W?WLzVz;*}!ofmwtx)Lw{cno}7i<jJ zb3xfce*ROzFDfPCZVmBEgQf_bIdZJ$1oO9wb(cT5p3)Hd%D3Pmhs!OMv!73PYx2LG z^rU<j%Z8L)TeBHXTjg86+2C=fD>!<#PAS8*xR%K+0sm9Yc>C@?3|?5Hw(iR66z03Z ztYsS4dh0889C*WbN%($}-<=t5{i`z8t^Tgn-z70yWo^lP(~3N44!+k$Yaf0wUatRt zL8^L>$fSkK&qaUVm-;_mH+uPYw&m*#%YRFKVljVr`uOF~>nG>4+v_ize);js{zb0+ z|9$Mb`Tnlk<m@cF=~j)(0-2X?(iux{Ju}&SKvR89*cut@khPv$>$O!H^ENYiUP;rr ze0@Kc=Y@(d70vaWH%e+-S|hUB`j#DRD875c@{_>3LKQdO4E@Td=GUj#O!>2950|j_ z)Z*CFImtg(D&Jn1WGb4P5wa;KHz=UN_2QK2r=~VL{=Kv;K%^*|XZM8s!kIB|x4&D? zb!z`rC4P}>T#r`WdiBij;h)13Z{FLXvr&HLcje83es@o-vEQTmL~z~8tH;E)%%2&( zGVLEz#M;nC*;Q$)T|M6Xc(X-v_SdJq3YJkm=iYiI+<)79cGpp@PZ2%A^Ed8$^Zfa( zSC^jt`D3?Fy{FZ#F_XQdi+PEZX(Hpd4)4}gHq*=mN==+T91N9VVA-l;>+pidUMb&i zk9BICn&%mdk5BV-jxw`%y*aueZqMIu!Mhi&khsPhombP_yZ(gQ|FGTM0THPaBBoZ~ zy`wqjF8|x}0p5&EBFwmV=QA)cFfcMOF#Ko)v67MZ>LY8#wpt3L0i^Y9<7z3)wNvQ2 z(VJ8V-AByex=~8sGGrsLmDw;Oel#w#!d-$Rn}V&}L71XpgH#Fyc(byBq*xhP87vtY J80Of6cmP_($ngLG literal 0 HcmV?d00001 diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v new file mode 100755 index 0000000..7b8967c --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v @@ -0,0 +1,103 @@ +//----------------------------------------------------------------------------- +// top-level soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + + module ADPcontrol_v1_0 # + ( + // Users to add parameters here + parameter PROMPT_CHAR = "]" + + // User parameters ends + // Do not modify the parameters beyond this line + + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Ports of Axi Slave Bus Interface com_rx + input wire ahb_hclk, + input wire ahb_hresetn, + + output wire com_rx_tready, + input wire [7 : 0] com_rx_tdata, + input wire com_rx_tvalid, + + // Ports of Axi Master Bus Interface com_tx + output wire com_tx_tvalid, + output wire [7 : 0] com_tx_tdata, + input wire com_tx_tready, + + // Ports of Axi Slave Bus Interface stdio_rx + output wire stdio_rx_tready, + input wire [7 : 0] stdio_rx_tdata, + input wire stdio_rx_tvalid, + + // Ports of Axi Master Bus Interface stdio_tx + output wire stdio_tx_tvalid, + output wire [7 : 0] stdio_tx_tdata, + input wire stdio_tx_tready, + + output wire [7 : 0] gpo8, + input wire [7 : 0] gpi8, + + output wire [31:0] ahb_haddr , + output wire [ 2:0] ahb_hburst , + output wire ahb_hmastlock, + output wire [ 3:0] ahb_hprot , + output wire [ 2:0] ahb_hsize , + output wire [ 1:0] ahb_htrans , + output wire [31:0] ahb_hwdata , + output wire ahb_hwrite , + input wire [31:0] ahb_hrdata , + input wire ahb_hready , + input wire ahb_hresp + ); + + // Add user logic here + +ADPmanager + #(.PROMPT_CHAR (PROMPT_CHAR)) + ADPmanager( + .HCLK (ahb_hclk ), + .HRESETn (ahb_hresetn ), + .HADDR32_o (ahb_haddr ), + .HBURST3_o (ahb_hburst ), + .HMASTLOCK_o (ahb_hmastlock ), + .HPROT4_o (ahb_hprot ), + .HSIZE3_o (ahb_hsize ), + .HTRANS2_o (ahb_htrans ), + .HWDATA32_o (ahb_hwdata ), + .HWRITE_o (ahb_hwrite ), + .HRDATA32_i (ahb_hrdata ), + .HREADY_i (ahb_hready ), + .HRESP_i (ahb_hresp ), + .GPO8_o (gpo8 ), + .GPI8_i (gpi8 ), + .COMRX_TREADY_o(com_rx_tready), + .COMRX_TDATA_i(com_rx_tdata), + .COMRX_TVALID_i(com_rx_tvalid), + .STDRX_TREADY_o(stdio_rx_tready), + .STDRX_TDATA_i(stdio_rx_tdata), + .STDRX_TVALID_i(stdio_rx_tvalid), + .COMTX_TVALID_o(com_tx_tvalid), + .COMTX_TDATA_o(com_tx_tdata), + .COMTX_TREADY_i(com_tx_tready), + .STDTX_TVALID_o(stdio_tx_tvalid), + .STDTX_TDATA_o(stdio_tx_tdata), + .STDTX_TREADY_i(stdio_tx_tready) + + ); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v new file mode 100755 index 0000000..f4747ae --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v @@ -0,0 +1,786 @@ +//----------------------------------------------------------------------------- +// soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + +//`define ADPBASIC 1 + +module ADPmanager // AHB initiator interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] HADDR32_o, + output wire [ 2:0] HBURST3_o, + output wire HMASTLOCK_o, + output wire [ 3:0] HPROT4_o, + output wire [ 2:0] HSIZE3_o, + output wire [ 1:0] HTRANS2_o, + output wire [31:0] HWDATA32_o, + output wire HWRITE_o, + input wire [31:0] HRDATA32_i, + input wire HREADY_i, + input wire HRESP_i, +// COMIO interface + output wire [ 7:0] GPO8_o, + input wire [ 7:0] GPI8_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam BANNERHEX = 32'h50c1ab01; +`else + localparam BANNERHEX = 32'h50c1ab02; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function FNuppercase; +input [7:0] char8; + FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping +`ifdef ADPFSMDESIGN +localparam ADP_WRITEHEX = 6'b000000 ; +localparam ADP_WRITEHEXS = 6'b000001 ; +localparam ADP_WRITEHEX9 = 6'b000010 ; +localparam ADP_WRITEHEX8 = 6'b000011 ; +localparam ADP_WRITEHEX7 = 6'b000100 ; +localparam ADP_WRITEHEX6 = 6'b000101 ; +localparam ADP_WRITEHEX5 = 6'b000110 ; +localparam ADP_WRITEHEX4 = 6'b000111 ; +localparam ADP_WRITEHEX3 = 6'b001000 ; +localparam ADP_WRITEHEX2 = 6'b001001 ; +localparam ADP_WRITEHEX1 = 6'b001010 ; +localparam ADP_WRITEHEX0 = 6'b001011 ; +localparam ADP_LINEACK = 6'b001101 ; +localparam ADP_LINEACK2 = 6'b110010 ; +localparam ADP_PROMPT = 6'b001110 ; +localparam ADP_IOCHK = 6'b001111 ; +localparam ADP_RXCMD = 6'b010000 ; +localparam ADP_RXPARAM = 6'b010010 ; +localparam ADP_ACTION = 6'b010011 ; +localparam ADP_READ = 6'b010001 ; +localparam ADP_SYSCHK = 6'b010100 ; +localparam ADP_STDIN = 6'b010101 ; +localparam ADP_SYSCTL = 6'b010110 ; +localparam ADP_WRITE = 6'b010111 ; +localparam ADP_EXIT = 6'b011000 ; +localparam STD_IOCHK = 6'b011001 ; +localparam STD_RXD1 = 6'b011010 ; +localparam STD_RXD2 = 6'b011011 ; +localparam STD_TXD1 = 6'b011101 ; +localparam STD_TXD2 = 6'b011110 ; +localparam ADP_BCTRL = 6'b011111 ; +localparam ADP_BREADB0 = 6'b100000 ; +localparam ADP_BREADB1 = 6'b100001 ; +localparam ADP_BREADB2 = 6'b100010 ; +localparam ADP_BREADB3 = 6'b100011 ; +localparam ADP_BWRITE = 6'b100100 ; +localparam ADP_POLL = 6'b100101 ; +localparam ADP_POLL1 = 6'b100110 ; +localparam ADP_POLL2 = 6'b100111 ; +localparam ADP_ZCTRL = 6'b101110 ; +localparam ADP_ZWRITE = 6'b101111 ; +localparam ADP_ECHOCMD = 6'b110000 ; +localparam ADP_ECHOCMDSP = 6'b110001 ; +localparam ADP_UNKNOWN = 6'b101000 ; +localparam ADP_STDOUT = 6'b101010 ; +localparam ADP_STDOUT1 = 6'b101011 ; +localparam ADP_STDOUT2 = 6'b101100 ; +localparam ADP_STDOUT3 = 6'b101101 ; +reg [5:0] adp_state ; +`else +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000 +localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001 +localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010 +localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011 +localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100 +localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101 +localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110 +localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111 +localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000 +localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001 +localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010 +localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011 +localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001101 +localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b110010 +localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110 +localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111 +localparam ADP_RXCMD = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000 +localparam ADP_RXPARAM = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010010 +localparam ADP_ACTION = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010011 +localparam ADP_READ = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010001 +localparam ADP_SYSCHK = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100 +localparam ADP_STDIN = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101 +localparam ADP_SYSCTL = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110 +localparam ADP_WRITE = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111 +localparam ADP_EXIT = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000 +localparam STD_IOCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001 +localparam STD_RXD1 = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010 +localparam STD_RXD2 = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011 +localparam STD_TXD1 = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011101 +localparam STD_TXD2 = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011110 +localparam ADP_BCTRL = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011111 +localparam ADP_BREADB0 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b100000 +localparam ADP_BREADB1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100001 +localparam ADP_BREADB2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100010 +localparam ADP_BREADB3 = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100011 +localparam ADP_BWRITE = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100100 +localparam ADP_POLL = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100101 +localparam ADP_POLL1 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100110 +localparam ADP_POLL2 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100111 +localparam ADP_ZCTRL = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b101110 +localparam ADP_ZWRITE = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101111 +localparam ADP_ECHOCMD = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b110000 +localparam ADP_ECHOCMDSP = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b110001 +localparam ADP_UNKNOWN = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101000 +localparam ADP_STDOUT = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101010 +localparam ADP_STDOUT1 = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101011 +localparam ADP_STDOUT2 = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101100 +localparam ADP_STDOUT3 = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101101 +reg [47:0] adp_state ; +`endif + +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + +assign GPO8_o = adp_sys[7:0]; + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign HADDR32_o = adp_addr; +assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign HMASTLOCK_o = 1'b0; +assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign HWDATA32_o = adp_bus_data; +assign HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +reg [31:0] adp_count; +reg adp_count_dec ; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) +// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_down_zero_next; // param about to be zero +input [31:0] counter; + FNcount_down_zero_next = !(|counter[31:1]); +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= BANNERHEX; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; +`ifndef ADPBASIC + adp_count <= 0; + adp_count_dec<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; +`endif + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; +`ifndef ADPBASIC + adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param-- + adp_count_dec<= 0; +`endif + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) + begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) + begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) + begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end + else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end +// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param + else begin adp_cmd <= com_rx_byte; adp_param <= 32'hffffffff; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) +`ifndef ADPBASIC + begin adp_count <= adp_param; adp_state <= ADP_ACTION; end // parameter complete on EOL +`else + begin adp_state <= ADP_ACTION; end // parameter complete on EOL +`endif + else + begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter + if (FNexit(com_rx_byte)) + adp_state <= STD_IOCHK; + else if (FNvalid_cmd(adp_cmd) == CMD_A) + begin if (adp_param == 32'hffffffff) adp_param <= adp_addr; else adp_addr <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin + if (adp_param[31:8] == 0) // report GPO + begin adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 1) // clear bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 2) // set bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 3) // overwrite bits in GPO + begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else // 4 etc, report GPO + begin adp_state <= ADP_SYSCTL; end + end + else if (FNvalid_cmd(adp_cmd) == CMD_R) + begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else if (FNvalid_cmd(adp_cmd) == CMD_S) + begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) + begin adp_bus_data <= adp_param; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) + begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_B) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_BCTRL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_M) + begin if (adp_param == 32'hffffffff) adp_param <= adp_mask; else adp_mask <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_P) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_V) + begin if (adp_param == 32'hffffffff) adp_param <= adp_val; else adp_val <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_Z) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_ZCTRL; // non-zero count +`endif + else + begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; end + else begin ADP_BUSWRITEINC_next(); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; ADP_txchar_next("R"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_count_dec <=1; end + ADP_POLL2: + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_ZCTRL; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + if (com_tx_done) adp_state <= STD_IOCHK; + else com_tx_req <= 1; // extend stream request if not ready + + ADP_SYSCHK: // check STDIN fifo + begin // no upper flags so STDIN char + if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end + ADP_STDIN: // push char into STDIN + if (std_tx_done) begin adp_bus_data <= adp_param[7:0]; ADP_txchar_next("S"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else std_tx_req <= 1; // extend + + ADP_SYSCTL: // read current status - and report in hex + begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + + ADP_ECHOCMD: // output command and (param) data + begin adp_state <= ADP_ECHOCMDSP; ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param; end // output command char + ADP_ECHOCMDSP: // output command space and (bus) data + if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space char + else com_tx_req <= 1; // extend + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output "0" hex prefix + + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end else com_tx_req <= 1; // extend + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end + end else com_tx_req <= 1; // extend + ADP_LINEACK2: // CR + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default error + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .HADDR32_o (ahb_haddr ), +// .HBURST3_o (ahb_hburst ), +// .HMASTLOCK_o (ahb_hmastlock ), +// .HPROT4_o (ahb_hprot ), +// .HSIZE3_o (ahb_hsize ), +// .HTRANS2_o (ahb_htrans ), +// .HWDATA32_o (ahb_hwdata ), +// .HWRITE_o (ahb_hwrite ), +// .HRDATA32_i (ahb_hrdata ), +// .HREADY_i (ahb_hready ), +// .HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v new file mode 100755 index 0000000..c2caf15 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v @@ -0,0 +1,728 @@ +/* +* ASCII Debug COntroller +* A joint work commissioned on behalf of SoC Labs. +* +* Contributors +* +* David Flynn (d.w.flynn@soton.ac.uk) +* +* Copyright © 2021, SoC Labs (www.soclabs.org) +*/ + +//`define ADPBASIC 1 + +module ADPmaster // bus master interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] M_HADDR32_o, + output wire [ 2:0] M_HBURST3_o, + output wire M_HMASTLOCK_o, + output wire [ 3:0] M_HPROT4_o, + output wire [ 2:0] M_HSIZE3_o, + output wire [ 1:0] M_HTRANS2_o, + output wire [31:0] M_HWDATA32_o, + output wire M_HWRITE_o, + input wire [31:0] M_HRDATA32_i, + input wire M_HREADY_i, + input wire M_HRESP_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam ADP_ID= 32'hADB0DF03; +`else + localparam ADP_ID= 32'hADC0DF03; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping + +//localparam ADP_WRITEHEX = 6'b000000 ; +//localparam ADP_WRITEHEXS = 6'b000001 ; +//localparam ADP_WRITEHEX9 = 6'b000010 ; +//localparam ADP_WRITEHEX8 = 6'b000011 ; +//localparam ADP_WRITEHEX7 = 6'b000100 ; +//localparam ADP_WRITEHEX6 = 6'b000101 ; +//localparam ADP_WRITEHEX5 = 6'b000110 ; +//localparam ADP_WRITEHEX4 = 6'b000111 ; +//localparam ADP_WRITEHEX3 = 6'b001000 ; +//localparam ADP_WRITEHEX2 = 6'b001001 ; +//localparam ADP_WRITEHEX1 = 6'b001010 ; +//localparam ADP_WRITEHEX0 = 6'b001011 ; +//localparam ADP_READEOL = 6'b001100 ; +//localparam ADP_LINEACK = 6'b001101 ; +//localparam ADP_PROMPT = 6'b001110 ; +//localparam ADP_IOCHK = 6'b001111 ; +//localparam ADP_RXCMD = 6'b010000 ; +//localparam ADP_READ = 6'b010001 ; +//localparam ADP_RXPARAM = 6'b010010 ; +//localparam ADP_ACTION = 6'b010011 ; +//localparam ADP_SYSCHK = 6'b010100 ; +//localparam ADP_STDIN = 6'b010101 ; +//localparam ADP_STAT = 6'b010110 ; +//localparam ADP_WRITE = 6'b010111 ; +//localparam ADP_EXIT = 6'b011000 ; +//localparam STD_IOCHK = 6'b011001 ; +//localparam STD_RXD1 = 6'b011010 ; +//localparam STD_RXD2 = 6'b011011 ; +//localparam STD_TXD1 = 6'b011101 ; +//localparam STD_TXD2 = 6'b011110 ; +//localparam ADP_BCTRL = 6'b011111 ; +//localparam ADP_BREADB0 = 6'b100000 ; +//localparam ADP_BREADB1 = 6'b100001 ; +//localparam ADP_BREADB2 = 6'b100010 ; +//localparam ADP_BREADB3 = 6'b100011 ; +//localparam ADP_BWRITE = 6'b100100 ; +//localparam ADP_POLL = 6'b100101 ; +//localparam ADP_POLL1 = 6'b100110 ; +//localparam ADP_POLL2 = 6'b100111 ; +//localparam ADP_UNKNOWN = 6'b101000 ; +//localparam ADP_STDOUT = 6'b101010 ; +//localparam ADP_STDOUT1 = 6'b101011 ; +//localparam ADP_STDOUT2 = 6'b101100 ; +//localparam ADP_STDOUT3 = 6'b101101 ; +//localparam ADP_ZCTRL = 6'b101110 ; +//localparam ADP_ZWRITE = 6'b101111 ; +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 46'b0000000000000000000000000000000000000000000001 ; +localparam ADP_WRITEHEXS = 46'b0000000000000000000000000000000000000000000010 ; +localparam ADP_WRITEHEX9 = 46'b0000000000000000000000000000000000000000000100 ; +localparam ADP_WRITEHEX8 = 46'b0000000000000000000000000000000000000000001000 ; +localparam ADP_WRITEHEX7 = 46'b0000000000000000000000000000000000000000010000 ; +localparam ADP_WRITEHEX6 = 46'b0000000000000000000000000000000000000000100000 ; +localparam ADP_WRITEHEX5 = 46'b0000000000000000000000000000000000000001000000 ; +localparam ADP_WRITEHEX4 = 46'b0000000000000000000000000000000000000010000000 ; +localparam ADP_WRITEHEX3 = 46'b0000000000000000000000000000000000000100000000 ; +localparam ADP_WRITEHEX2 = 46'b0000000000000000000000000000000000001000000000 ; +localparam ADP_WRITEHEX1 = 46'b0000000000000000000000000000000000010000000000 ; +localparam ADP_WRITEHEX0 = 46'b0000000000000000000000000000000000100000000000 ; +localparam ADP_READEOL = 46'b0000000000000000000000000000000001000000000000 ; +localparam ADP_LINEACK = 46'b0000000000000000000000000000000010000000000000 ; +localparam ADP_PROMPT = 46'b0000000000000000000000000000000100000000000000 ; +localparam ADP_IOCHK = 46'b0000000000000000000000000000001000000000000000 ; +localparam ADP_RXCMD = 46'b0000000000000000000000000000010000000000000000 ; +localparam ADP_READ = 46'b0000000000000000000000000000100000000000000000 ; +localparam ADP_RXPARAM = 46'b0000000000000000000000000001000000000000000000 ; +localparam ADP_ACTION = 46'b0000000000000000000000000010000000000000000000 ; +localparam ADP_SYSCHK = 46'b0000000000000000000000000100000000000000000000 ; +localparam ADP_STDIN = 46'b0000000000000000000000001000000000000000000000 ; +localparam ADP_STAT = 46'b0000000000000000000000010000000000000000000000 ; +localparam ADP_WRITE = 46'b0000000000000000000000100000000000000000000000 ; +localparam ADP_EXIT = 46'b0000000000000000000001000000000000000000000000 ; +localparam STD_IOCHK = 46'b0000000000000000000010000000000000000000000000 ; +localparam STD_RXD1 = 46'b0000000000000000000100000000000000000000000000 ; +localparam STD_RXD2 = 46'b0000000000000000001000000000000000000000000000 ; +localparam STD_TXD1 = 46'b0000000000000000010000000000000000000000000000 ; +localparam STD_TXD2 = 46'b0000000000000000100000000000000000000000000000 ; +localparam ADP_BCTRL = 46'b0000000000000001000000000000000000000000000000 ; +localparam ADP_BREADB0 = 46'b0000000000000010000000000000000000000000000000 ; +localparam ADP_BREADB1 = 46'b0000000000000100000000000000000000000000000000 ; +localparam ADP_BREADB2 = 46'b0000000000001000000000000000000000000000000000 ; +localparam ADP_BREADB3 = 46'b0000000000010000000000000000000000000000000000 ; +localparam ADP_BWRITE = 46'b0000000000100000000000000000000000000000000000 ; +localparam ADP_POLL = 46'b0000000001000000000000000000000000000000000000 ; +localparam ADP_POLL1 = 46'b0000000010000000000000000000000000000000000000 ; +localparam ADP_POLL2 = 46'b0000000100000000000000000000000000000000000000 ; +localparam ADP_ZCTRL = 46'b0000001000000000000000000000000000000000000000 ; +localparam ADP_ZWRITE = 46'b0000010000000000000000000000000000000000000000 ; +localparam ADP_UNKNOWN = 46'b0000100000000000000000000000000000000000000000 ; +localparam ADP_STDOUT = 46'b0001000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT1 = 46'b0010000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT2 = 46'b0100000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT3 = 46'b1000000000000000000000000000000000000000000000 ; + +reg [45:0] adp_state ; +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg adp_param_dec ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & M_HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (M_HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign M_HADDR32_o = adp_addr; +assign M_HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign M_HMASTLOCK_o = 1'b0; +assign M_HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign M_HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign M_HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign M_HWDATA32_o = adp_bus_data; +assign M_HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion +input[31:0] data; + begin adp_bus_req <=1; adp_bus_write <=1; adp_bus_data <= data; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_zero_next; // param about to be zero +input [31:0] counter; + FNcount_zero_next = (counter[31:0] == 32'h00000001); +endfunction + +function FNcount_zero; // param about to be zero +input [31:0] counter; + FNcount_zero = (counter[31:0] == 32'h0000000); // exactly 0 +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= 32'h50c1ab01; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_param_dec<= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; + + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; + adp_param <= (adp_param_dec & adp_bus_done & (|adp_param)) ? adp_param - 1 : adp_param; // param-- + adp_param_dec<= 0; + + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) begin adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end +// else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_EOL(com_rx_byte)) ADP_LINEACK_next(); // dummy command + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_cmd(com_rx_byte) == CMD_R) begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else begin adp_cmd <= com_rx_byte; adp_param <= 0; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) adp_state <= ADP_ACTION; // paremeter complete on EOL + else begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter +// if (FNexit(adp_cmd)) adp_state <= STD_IOCHK; + if (FNvalid_cmd(adp_cmd) == CMD_A) begin adp_addr <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin adp_sys <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_S) begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) begin ADP_BUSWRITEINC_next(adp_param); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) begin adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_M) begin adp_mask <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_V) begin adp_val <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_B) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_BCTRL; end // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_P) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_POLL; end // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_Z) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_ZCTRL; end // non-zero count +`endif + else begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; com_tx_req <= 1; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin ADP_LINEACK_next(); end + else begin ADP_BUSWRITEINC_next(adp_param); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= M_HRDATA32_i; adp_state <= ADP_WRITEHEX; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next({adp_bus_data[31:8],com_rx_byte[7:0]}); adp_param_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_zero_next(adp_param)) ADP_LINEACK_next(); else begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(adp_bus_data); adp_param_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_param_dec <=1; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= M_HRDATA32_i; adp_param_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_param_dec <=1; end + ADP_POLL2: + if (FNcount_zero(adp_param)) ADP_LINEACK_next(); // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write zero to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_zero_next(adp_param)) ADP_LINEACK_next(); else begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; end + end else begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + adp_state <= STD_IOCHK; + + ADP_SYSCHK: // check STDIN fifo + if (adp_param[31:8] == 0) begin // no upper flags so STDIN char + std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; + end else begin adp_sys <= adp_sys ^ adp_param; adp_state <= ADP_STAT; end + ADP_STDIN: // push char into STDIN + if(std_tx_done) ADP_LINEACK_next(); + else std_tx_req <= 1; // extend + ADP_STAT: // read current status - and report in hex + begin adp_bus_data <= adp_sys; adp_state <= ADP_WRITEHEX; end + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space prefix + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin adp_state <= ADP_READEOL; com_rx_ack <= 1'b1; end // discard any param + end else com_tx_req <= 1; // extend + + ADP_READEOL: // read flush until EOL + if (com_rx_done) begin // RX byte + if (FNvalid_EOL(com_rx_byte)) begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // parameter complete on EOL + else com_rx_ack <= 1; + end else com_rx_ack <= 1; + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default to hold state + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .M_HADDR32_o (ahb_haddr ), +// .M_HBURST3_o (ahb_hburst ), +// .M_HMASTLOCK_o (ahb_hmastlock ), +// .M_HPROT4_o (ahb_hprot ), +// .M_HSIZE3_o (ahb_hsize ), +// .M_HTRANS2_o (ahb_htrans ), +// .M_HWDATA32_o (ahb_hwdata ), +// .M_HWRITE_o (ahb_hwrite ), +// .M_HRDATA32_i (ahb_hrdata ), +// .M_HREADY_i (ahb_hready ), +// .M_HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl new file mode 100755 index 0000000..7b1f377 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to update PROMPT_CHAR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to validate PROMPT_CHAR + return true +} + + +proc update_MODELPARAM_VALUE.PROMPT_CHAR { MODELPARAM_VALUE.PROMPT_CHAR PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PROMPT_CHAR}] ${MODELPARAM_VALUE.PROMPT_CHAR} +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml index afd116f..5696e41 100755 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml @@ -381,7 +381,7 @@ <spirit:parameters> <spirit:parameter> <spirit:name>viewChecksum</spirit:name> - <spirit:value>fc7589fa</spirit:value> + <spirit:value>4d515fed</spirit:value> </spirit:parameter> </spirit:parameters> </spirit:view> @@ -397,7 +397,7 @@ <spirit:parameters> <spirit:parameter> <spirit:name>viewChecksum</spirit:name> - <spirit:value>fc7589fa</spirit:value> + <spirit:value>4d515fed</spirit:value> </spirit:parameter> </spirit:parameters> </spirit:view> @@ -896,7 +896,7 @@ <spirit:file> <spirit:name>src/axi_stream_io_v1_0_axi_s.v</spirit:name> <spirit:fileType>verilogSource</spirit:fileType> - <spirit:userFileType>CHECKSUM_fc7589fa</spirit:userFileType> + <spirit:userFileType>CHECKSUM_4d515fed</spirit:userFileType> </spirit:file> </spirit:fileSet> <spirit:fileSet> @@ -1023,11 +1023,11 @@ <xilinx:displayName>axi_stream_io_v1.0</xilinx:displayName> <xilinx:vendorDisplayName>SoC Labs</xilinx:vendorDisplayName> <xilinx:vendorURL>http://www.soclabs.org</xilinx:vendorURL> - <xilinx:coreRevision>16</xilinx:coreRevision> + <xilinx:coreRevision>18</xilinx:coreRevision> <xilinx:upgrades> <xilinx:canUpgradeFrom>xilinx.com:user:axi_stream_io:1.0</xilinx:canUpgradeFrom> </xilinx:upgrades> - <xilinx:coreCreationDateTime>2021-12-12T20:49:24Z</xilinx:coreCreationDateTime> + <xilinx:coreCreationDateTime>2023-02-19T21:07:14Z</xilinx:coreCreationDateTime> <xilinx:tags> <xilinx:tag xilinx:name="ui.data.coregen.dd@16fed581_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag> <xilinx:tag xilinx:name="ui.data.coregen.dd@2ec9608d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag> @@ -1441,13 +1441,39 @@ <xilinx:tag xilinx:name="ui.data.coregen.df@a1c64f7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag> <xilinx:tag xilinx:name="ui.data.coregen.df@74feff94_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag> <xilinx:tag xilinx:name="ui.data.coregen.df@4f3615f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@519e5f78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@7528fe9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@140ccca_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@19984aed_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@29788adb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@fd26a57_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@297fa2f6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@47ec066a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@377a7bfc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6b725b5d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3eeb33d6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@30630a09_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4bfe4edb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@29cc3150_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4a07c44b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4b170789_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@398d3842_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@19987ff9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@54481846_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@77667cfb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@47d2390f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@7337b6ef_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1d4cfc6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6d178b5c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@33a003ad_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6e2ec915_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag> </xilinx:tags> </xilinx:coreExtensions> <xilinx:packagingInfo> <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion> <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5562313f"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="d6592117"/> - <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="323cdeea"/> + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f0ec23b4"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="7c2aad6e"/> <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd9ec9b5"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="6cced3b9"/> diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip index 2a22446f1995db34a975c88b9976e397a70995e4..6427293a7e3a842cbc0c6c8b2efec11dd4817b08 100644 GIT binary patch delta 11693 zcmcazy|k`Az?+#xgn@y9gW>s#;IQfw?n?V)85k;-F*5KnFfb(N=N9DWrRJ6BRpjQp zjg2mrHlJ2EKYrn*!`IF@tK8AQ7qNMhj{2&PYgH^yp5x{Y->EIKQdKi@R{Z{quADe2 z->o8Dc10IgP7#jb<Fl)=c+QZ)WdHy3w@tf?h1m`-x?jDwzWe)ycYZH+?$fUlUthj| z&i>z?Z~uLMkZ;ewzRS_D>gliP;eX>^^p*u}z4zg2?nT|I?d!|;_qm0y|Mq=<?eA^n z^S4a*dgsS=_j;^G$^0k3_9oUFXsy%#{;RqBuf5$K`{MY+OK;l$t|_W2+SlLu$X>AJ zOUR|S8zKZg_x5QoQ>qB7|Gj*Xxy;OY+`HN9Z{M7mRVQ4v&)!1fTkQ24iIH!g|2?{9 z=b^iY_|80d_n=CGEp%h%qnMrZcJi=4+xCLTy*WY8+I7E{?YXFodY+GtP8I7O{@$`P z>04FBCFxd26Fr{OJvG;A&rMQFpL^KeFN;g3(_;T_E^BVt`n}fnDcy5x_eR(I%wDs} z>)`tG;Pv|HN5wg|?7x%4RAXY0H^pns)}QARuH>#fv>`iB%OdUM^oN`5cl=IR=jS|! zYnFfYUTd~ezk4G0SQ~>2!#mHee3bIQ$Z~U!<)*LtT<N>!2Y3E_v-Du?=i3i|Pu_m> zqU`jw5woU;z5Mt!Z^r5Kfh#X>JG<vX<hP>w``6h{y?puc;qCvm5eL~a{h5~L&aPZ2 z&G6LMn^k&=E$5VNxzAej7^WP)A6>N5@y_Ic%)1$JuiO$cEem)b&ExPs?e;myoayxQ z%l^;#wQnfA?Od@X+gQJZdBLB5-#+~LkoZ@s#g=pOG~Z{bc?^@DaG$fYUlZTFLEZ7v zrjvWl@H*5NRov=3#(QaAi|1{#&raqHr!u|mFDShAT(Bh<Y>do2xqY?Ozcw`SUYf_^ z1y;j&>it`hoC)7d0;0Cf6yL=eaO>C|-beG=yl#Ws!r*=T#U{sFlLInur^UTcbI7#J z;=MGF&FeJ8_{8Y+3kvT%S8T~M(Jy7*Q2(c{tnSw{h%=`^ooW8|&}p_r|E49WlPhOR zH$2&LS80jkjmZj`H&f!$gjG(zysDSFbdlteX>N%VZttJ-?CGyE`<Z_K?rL6r_owdD zw?Eg@o~pkzUsfIamgV@r2bX%{-k1H}+nwdS{loh5`!$x<mESF0bLFj0&Zx1hzbE~8 z^Y$BIp@(bVitF`k&wc-Y^JU$(#eE%o#cQ6vV^p0Q_xM}!f~(fQEO_kdeqOM&{rB`I z;|!A!(fvAAN1uLu`a0IkTWkBt(<*(QQ!Nbkb_cvW>_5vo;XL=Lo72zFx1T$2eyQEE z39l}{pKBiPcRoz#+BHW1Z6`%db{ZW`xKYShFRY|<&vu6OqReg&+w`g$<FhN~-}m_) zbw0AGpkVgV>~;U7&WE<?_J_=S9+Lj!hV$I0SDPwVKYjAzTEgDx#~$vP8=EH(wsNBB z?a!)e&G#fLjg9!XPZzg19ry0ruMZiL4^2I)nG`bZ#Qr^G`z&PM=y7_fL-Q7O1tX4Q z_igVa#3j`WE1iC+Zxm+nH+gZRlWlshT*8*G43@llXAMrSRMp?SZQA7I$iq`&q&m*d z+H=v{pmKIem#V^rxsTjp9XL;1V-?}md+>+7h%tGx<&J$)sRw5Xe~yT@(b20)ODptV zDa;(Z?b;=w|E%#FcGX_E_u$FnpC4booPJ*W+UD1D->vpE(5vSw+BILc-p1O}{^#2# zHLa<0mgt}P`ew_zg!{86|GseL+N}itHTP^Q>i^vS`1{;?_5Ekw@bzfg-L$Z;`oCVs z<Mq79>u#6VZ<`bSdfxrV+vE+moA0}pFV#|b@T=b|_O{v>xhHGvY^;BmloVCe{n=Jr zRa3U-5SQO2`FXdDb-qno`o2Dl-TUeP+L}LiYLl)Xv$Bi6e(Y%3<)D98Uwpf|<HTd@ zu=A1o1EZM!TE4xcz;pO}m-Vq+=WX8F=I7@h)mtm^vru%xvX`Hie{Wy@y3<T7;l^yP zI)ghOPARSb@b2KlK(2s3>-YA5_jS&kdsZTR*0&wM8V`qDDf;!v<IIT(uA66d-CJIN z)3_$M>f5ggcPE>lsVm!Tp>R3r8qeW}dlzUP;6A-~=jNF^7nNE*4qms1rESZKmY&mB zSJ!L*d6B*EmrrBi!m7KDJ2XzUdi3Rf*Z6a>vi#G#U}mAshxSRtm7cwO{I``gcj>dw zMWKf;@OG`fq$9V-RC#moYWr}7;CiEJ^OJm@ePF1+yC`zK_-3Qh_M`Pu6OK=vu<49U z(bbGA3$l4%{S<bHUH3U6;QW836`LoAFIX^duKc|1R%hqAuM2xAxM5!JnHN<%j6>g? zJfZdCgxuWu`|3?LZT0GR__pG{H1Dsw`}x-X*1Mo*ZuLBM)f!gzF#p(+rds)3lYdQK zGFz!;wX0%kQf)>3@#a$b=(3=ih$R)-71yO}c@HPuFj%zn<Da+tUY(0vn^%^wT*>ME zvm@>IR&=;BWnB6f`M>Ic)1~jne*C+$z99apX!M$R;rqUNA8)Cwx0o1nb+u7e=&_8x zsk*-=-#>Kk0pF_`x0B5HLT5&OjVL)BDX~;S>-Zv*OV9QtF+ZAHG{LHV>4YPPXKoAK zYPGwF*Kc-o-xjH&=f=}J0#_A(G2LO`etkM`&W!cN@;pZ84f_+zE^QW3K9@QF;=+06 z$wjIKeW&`DZRd?Y>w8gt#=8wW_Pm>QDaPbWuIlC2Q?Gk|-StJj<+bIH?OV=2S=;^X zaGgx8aq|QAqi5%Au9@*NeR7v|zIb-MUDGqmwEEl8m!2>tJ#VXGJu9~Rx3ht^#W5Av z2Qx~mOABo`i|`A-I(_n7b@BE6^LUTMFTRwURhRGA{8cFP&Tjc8`x`;dr5h4{B-f@t z*~R<o`3&Q}iRJgio++)|p!V%X(6f2*lXj}{-TnUIctZaImq1nXgY#OKEcM-6RK9iF z3e9@q*B-sQzg%Gayye68qzyM_d+zdo`S|XSX4h_0-?Jf_u2ZYO=R3zpEY9gX%CuQ& z@f6!M_sDHo+r4sEgffLan|>xUB1WgdTK9KG;m#j#6HkVAvN06>{9L{8^G(x#XC^OT zHI(}$lIz`b>%&&T@5utmN7XCOALyPvrL;aV+;+Y6qk4_~Pfd)Erp~N+>sa`4>%w0- z%r!9@-DR;Gc>=eG#J#C+TNPRGSzz7VQ>*Qk<(z+-R9BzOI`#A1ERBmMD$#LQ6l1jY z<$ld|t&ZEWt?*}@>68qq$-0KG1lG-!$o^QH`_}dD;WMAMt;^pTX8d)V&%C8!K5_mP z_otou=?79eNw;4AmB6~G;{0{9cd5E<7CQT=P9kZ|AB%$1y=khmj{Y^c6H&VU#;=uu z{SIlBy$dgz6biKcedk-T_x0h>7gM8ehF&u{dUx-=ztvNp{j&SB_e1@E{o<?g|Gu~T z=l9<~UvFG>WoE(zfgS&!-mE=X|0ntRa@jxqcbTI~v!o~GrU!=BPpaQ#&>a?&$C)A~ zd!|l%XX@u^XG8ybzG9jk{<p5~Z^^mxH49xXZ^+ph*#04M$HrIFKfm3%@ow^O#*-Ug zX?^&1B_rGH)w#53*I%&Cx1KiVZqf!B?{oW>-P?8lt<I`f{z1>vFLu3lkAI;Pb=>6E z{lMF$k;31%2WL*RvY)!G@y#@;;+6HEuiQAcF*@(e@^gjBS97nQcj(=<e&$otT@QA~ zKhK@}0OA~*+1DSlL|?YNzp+io_wc5tZnB4-KR8yk=Yg5Sua7G>ev(}FHF)v6?6k^W zzYiN<U(j0n)TpG|Xh+EEncr?lns~>~aJ@bG;GQJOb$K`U-1yHEz4^g2#TqfQ_3G2= zbG)C|9GCJk;XOS~x|CyntMuzm)$Ol)<R{3imOEX=mUU(CS)KJ4dF{##W?EjpA;)X> zq0YKDZRO|78M_T{E{JGb9c`xn&HnH;ogI}N^PA7U=2XLUXVb~IPLEpyk`*(9>TfOm z=$bqK_4G9<o6GaskJd|kzP@|%pGnsHr;6{Ma%<}UbB8RAjZzQ&^;Q#4+z|cz#*E6Z z0`C~p^kO)66>lr9h<?+PzxeOoJ$)5@leO3VjNI|1s&q+}U{zv*+rjY2r>Zw~l`cM0 zFIjcPwL+fZ|H=dB%%bKq<W%lA;Ymopn^Ci|RCOKi%;Z!0&w7K^IKP|Es@M0O_4~-v zhf>Y6s=YP2e{TtU5gR|vV9K%LKK;)pyI-9*|L4)VO#i@^FpbXvKE4}6O`or?$&dW_ z<E{SjxtAwzp4`7Vx=ud$>)nUHziYo<$9m%A-EV6f=fpJr7f~_Z{``8@zoT}#cK>g0 z3%(p_&9yzVub=IDVqI;}<&CX9Gw!6%sE=QIr6t8`*OU_b`RbmNt1nJl_Fknla&2L` z^rDtOQ*$gEP8nU^qI&ai<8AZpuIWXYSr^y8^L@+nJ#SNx_|s`=^&k0etO}YMySl=b zr@8#{oyGC}{r^h8J#}7Q_V$I-#?1N8mg@5!VCv|1HxoD5YcXLy^L#V$iFQJhssj)6 z==@HtH`q91U-?V<T}+9MTAz;=%Ve!EdwI`!t1*YY^K|)rp_`<BhJ0ZRTJ!EhO|bN< z0!wAP8TQVRzZ>(OnfP7Z-+ruH*`(X<b60rtgMXJ^*j%|D`8KKIQt{nv`BO^lOFysH z(o4$~S~~Mn^c1PUS3J(<eTNFZI3L<N;fu)s&5!;)a^F=y_tU(mXF76@+zKo7dn@$# zs`7>jzmMz3`&sRmoj-4G&956Xb<Y+FU9%EeoyS=BL?U8;{@*IW{F_&wZfV_7^Y7%; zE!*zzGzkwsIQ=~5%z66rvo@74-cWpg_S{!1zj!^l)U6x5@^m@t^-I$mrIQOw<fY5* z$;^{AubUdKxo?B(B&~P#Jmp!U#?mU6f8Bg57~ONutyyWidr(nsVs%PkdP?BuRSESE z4nO#+w_a$K*uD09M_;^t9qV<;==Ha|PyCnue3W;}r0~y_2Or;Rd^uIl@Z4PCeeN-y z2b1I8oZpnr>U91_-VUC<t;)+I>kMt=rhl-$+_Gx*ae4mxd+h%e{Q0=&-u>qKk4+z+ z|4r58*77MXwhEbfQ|?T{Nu_{P{g1B;w`gx?ndh=Q>ZtGKyj2H`-X3w@;yl@2zo#s; zKHlUlxMz52S@5S6)t6!(mnTVaUz*<8SkC|Ip+g@_{l@OCbAL>|d**G`c5A;AOk1nY zSDRLu9-ZAMaE<u_GduHYhOBa(4>1h&wiO~1jxV3LOJItL&-RlcrGFhG&dq+xw|@Pp z!&@KRpLu$Uk*&cDeWBBHcCTFeQp`~1?#{edpPoDZc=>t3`}N1wSL|m0zw`Cq`(H!9 zS4GV1{Jp9^@X4<wGY_uVG4=Jd>#_3>*q@$II9JM#WnJvi*IT(`^z+*?m-YDM_j=qD zY5uy}vR?hmb#wV^>etuIefgUG%9<IsLyHzy&N4GM+Wt50zftxMwaW6RUTZ&FE@{1f z-N0b;&VZ--+oQy-L@nQIPjhav4dFbobBgD+y&LPS!yl}v-}3q14av2yTsIl*o3qdU zhm}<9-dp$oe|vlT-iG(PJWs{d7i?5nsk1|6VF}mrhs!i-57je<g|@bSS!#7XT%7rF zv4i#H-$nC(=3Ur7C+9?uysXyVN2^&E#GQS-C8V%YW?J-|>;E)PYIjainpY5~(!-(j zMct+D(62cU!aepKdUK!q@2aaS0$(a!-af@jwOBG)#XbJbRO^q`OHXuPxc&KG{f3T% z#jV!u%iZ_in_np>J8yo?ulgO;58~d|OHQ+{u`7FDwfFC8mtTJ$tup2a|GU(7S!F`d zYX9I?mgTHLat&HRmrv-nF5px>BD9ckg%VSumI23#2(gk50h2_Rh;&i*1zenSs+OrR zgtB})`9qQ0K~&7ggu|6#Re{usKq02^4GK|${EVU}7po{5Fsw>QZ7P&$imey)sL)dI zQCKCzHBFIWRe|P~jw22MtjfIw1q>mACnlfR!?1wM^oTT%QbEx?V{Ik|-<D;XP74Gc z-4f{hB#=~_w`181#{(@Hnks<;fA}v>JfWcABk!|U*~_^jv|@o$lEg-?OBX$tFsxX# z#`KbNgt*X~%bPAZEZ~~T^SMLuOsZo29`DnJ9Erl+*A!kVt`O2Oo#_0*;S8tXq85Wj ziQ`?tjtnafX)4;dYBPi!)Kgk2$PzNcH|!`2hZvu?a!yePL&!pr#6H#*iN0G6fgJ(? zf^6QIIxM@L0umaV4GIk{(|i=pq|SHB$y4~@ls3o6#%YHA9hT0y?Hgu0#zaXLaVgf{ zQaAbO)U4n#*=KbEN5^LIw9qIfPl4G5M}B4)wn)10d}3<0U{AVc(Z$+Qtgxnck(rZ2 zE4R|tO#(ZbI7|JSEcQ+D5NNk-sfhPdomeEmV{h6s*+JpVf(K1~3V!;N?_Q4)<j5|6 zC40@K$wHR<%;OG67r!G`XDwMmXC#LtuqoCTDVZeY$+j$IPn=PC)?tokpm57k0Uen> zugYx28=@yS@;LC7wmM}xITxG}@t(OypyjOSOdnl!g=uF*B>iQY8@SBX1acL8(iU-w z-DzB)n;PfFmN?gI=9SE=JO|kmUrk&l#1yXa?Boeojui#j5@tM1xqAit5;@kWx@D_7 z%z0gJ<TvrDf}OZvRCS*u%eADFr}qYNRNstHJ^n_9W1Yq$!*l_$_FGD-4sWIix$ab# zW6}`uOfhWP;mM_A6R2=4d7@Dh4@>BdGPht}N6}X+4CIcOG4a{(@^`Ek<lr=ulK5@Y z<i5mFXU4{_*VNTn97KCrgjkxQ#pV=AI=FD?Y*<mRSktAD%OzmLSokX`sO5kO%i=>K z$1`6tCbFtH2|WEK&Jeo6DMpg<AmdI66JCKmM$7vm7!R#T$Z_f5YtcG&<cJ7Iv83=p zPlm!tQYxHt93sjDR13Zs@V%07n$dJ4Aic-f%YtRIlWm$^1qb6CgC1#3g&CqJWslEl zHqe$ce4<p}@|MSa$yTwZ#>q2QD;Th>GMGE<?GdLL4vs%Hm|2*oE3q^Sv?e@|m}sIU zuv^kb>V0TS0hh|0Wo}J3W~vym=qc269N<y+Q{Z^qTv*iN=G-w`;@F-)H@F(KE*Zb! z>3FX;^U^JAE=EzG+{%CajoK<prdqQXhO&g7*~O4Fc?#?LdYNDWCiSKX3O5`(1X~I{ zg7^>J(sJx%`)JMoW<vNir-;geB@?D`HEo@GF?zWu$L=P{kBrVYg4L(Fop!896Z1`( z;`G34!z53}gEx}qFPp$#_~+2d@H-7Z@+K)MOBxHv7%$Y?#PBGXrAg$Qlk<&>9<Mhl z1eb6-h(0p;uF&^C@<9DPc4kM>re+}xrwv;}I8rvYJZQ}5Xvz|ptsN23Y|!(z_F#vg zLSK;Kbw5p}#%&gowJROotUNtK%u&Q;PyfWtAx%GG&7aPZdZXZzCKbD>P>4xuPV#es zCINphKORnnva77UT>+em^Ol_R@OO*}Ilj}trHCWu;Y6(^4hxhl{JQJ;1@31&cwm#J zP$#rxtw**qN65lELj8svCps^iG|RATZkj9JmBA5m&`Efa!yRFfIm(PjGPkE(vgB0S zwDe#iZ}Q?0m(vDp2csTod=)z~PeIvZL4pI1z``C40cIChj){>RlO<n2P}(XG@Nk~? z6DE#ZZk}7Z1ws_32)%JQ!Z9bSzS*W}gV~if1=dGa{Ht;}q>kJUn^B~>hAlBi^7%AR zj^Dpqq?`?U<WGERnA2G3q&C$=>d0l$9xqSMj>A^ZSo=7R=$|q4Jh;|L!0u8454*lY zM0A_VVwoe;U&VZqFzIObTjCHCAh15VvT0GVK#y*+*OWH-1}!FKC)*C?w9MXT^*l#n zmfZ>T)@jjIcS~~MV#)2)elKk%U>AB^$IVMYrzxf2NHL?Li^gN-RU9n`IG11DRL0n3 zd}N-HDsu~`%9c*6rX75@F09zfDEO{==Cm_HPAv{5&exiL1kJVbGGzJfHuFQDBuDfs zC6*+Pj^(aP6nu6vDCRtJ^LXr7v))7bV7*1dj-RbbttLDnJ03l~t1plypnOoVTj7V( z(Y?hAcF!huE!k?_k$+*v1rs**L*hz_yljQMvmV5;vnU?Yt8dKY=_uc}WZ~2GXB;Ig znr(W-_isp0S{tYsA$myAndun&&2x%Ej(=1<A|makaV2v%E`Ms&v3-}J+DXZ#A7L%t zEfed%2#CEqVz9h}wXy4)Qk2B}1(7mJ>>odD+%m6-ThS?@ZOKQ*kC79nXr3?=apGtX z?D{I&o{-bZam|QdsUYZFB<G{{?=i&-Wjn5~-QeKjDWM-6tu}|f@T#(C2<uwKBOEqX zxgHG#X&Q6YgAP~dPW4<U(UI@E<kCSQj_Th=H=`2kWm|ThS?hEug5%x<?QBD~kBhCI z*>WFrPSAA}VO^|H;jGjlE_Y<%?yw+hj>Cr~yJsbFc$cqSQ7m|b_vWO?ce*_pmy!-^ zcDz@M^f(=|RI%l^#f^-m?E>b4OD7m`Flp&L%5d0`x+e1p&k=sVEnRmSf5>X^vt_3% zOqgb^m&+rNQ?EN&$E8m(ha<_|cA-MurxUDwojV0~95N7BZ1rOZnRwCF-O(oac*m0& z&ISc6ied&G_y4;qiS&f8ly&1f_~WF(bE5=-`B67bEF_L}u3MlN#rnuQ{?*DfJqL$Y z<y8~U*qtffk{G&T`@tP=wtt!(*6J$NdcbmBPLyb8YjL0Bjpq8rE?VjicY@rve$r{W zv2JOX<vE8xKH|oCrmP#|Pcti@NaCoA6iS)E@bS+kmk4%=+l^CpJW%PGy72130xn0< zFgvL}$B5|6OSdjqalB5Qb*+`JkVDPy;{&FSr<)SC?AgM^l+AkSRF=T>FphOGzt|5c zO=Wl4(p0#Ay}_Jff&CJG^@+OI8ISa>4LSCk<I$YHs%1?J1VR$$D7<xu5uD<5+eM5^ zF=nFS4hcsY{oq$6kGNQlpIK?t*YIQM?t&YUY>yay1eYvwakw#eN{3ae!yfy#-Y0V! zJ~#?Vr?R#Sqz3!$<y6?WN!2M!NwcM*m0O$hxIj{L-<mMCV_iMUM-nbf^QdoZWfNQ< za5%ES;GX<q#!P|V94yrbSvyKs@kFs`D^?uNIDLJx!jXbI8S7Zv9!y^;eo1SZb>qz~ zS{6GV$aGZ9x6les;ARv(xiWz1NK;Q_`_4@QkN%4I1if~=!!W_^cqZ?oSB7Vpc}<*V zI7V1C&1ex&5?DI1v2e2P!;Xqp1&O-)#>$^(l{nTZ^y_d51RQ)SZQ|y@v1w^foV399 zcq1p}Nebt7@4V!8_`{j7L@fc9RT8UoR0W>#Kb;fE^Jx1OIpc?pHV1ujr`%}zkucB0 zTR2zohm%~=Pe-PXuSTDZq6Fe^KH5^k&veAC?B_E>W41$jOyAGBF+JLTWs1_#IV~G{ z57f(;Yc=ior79^JbZ-K$gXkHhtJ54dXbUC#%xu}<wY2HQmY~)Le3r+&Gz1jqbX<{Q ze0<e2bw(-6Ax25nt|b=IPAS?=6P*rKJY`XAG3*FkC31*OB7Etwl%KpE(fyiET?zu? z${t5f^B-Z%P-;4?BEb<nQ)PaS1k3g_!E2l>JHqSdEHQME`1*J8$shKa6^l;X>)!Bx zYrW*RzuP<X4R6YW=Aj<e?b&7U+x%$n$G_><eV3(be^S{l{_XG7<a6x0CFefW)IT+F zH2n1D+THKreH%pNg(pS7sjGh~VXXP%MBLuLf2S%dYOLAZ?^Rd-bjG1m#oWc)rd{v9 zIb$#P+uz#lbL*c;OuVD@_P4hC%p{Mr`v-pgJGFFbnad<5*=wIxmuEN363WT#3Qv5s zEa!>hp^$S4>JcrL;i}z=ZVL=KyG?vMI4(~pSi{_Z({}foqPg8kS6;T}|F*sSdij>W zi~l8v<kkObST*J0-2xH4_TSUrRo$8DS6KOVPV9s^EB?g2@qWpeR)6BDyjYE)?S-hN z3`X1CKL_n{*b;K;$DNOdyk9zf$t<0_ck{EQUle$qOjLf`9rJ$4H2I*SV%(>kWkFJz zo8`UtPSNYB4^G^?e^H%g>;lCIug%j#_RY{!aGZEj&SLKry$xHc(jL0*W?eLQ@r><p z{fuvzj6JNT+5WCKjNK5Sv@-5feT;@a)1t1e_g*sHXf+C$nz`~v)9wS2J0G8j+Y~<` zh~wp>?s?}f39s7hpTB2{o`=^`(TA$#jMdMQzG+UIeu??v#*k_IpG3?KY8Einx4b6S z$g;ff-QmXf*IR#Xd03k?HRM%YjWyTa#Eb8Jjnyl|kNwTm>$-Q;Q~#TG;^Z^G_t$aP zH*b2x=*aT^q1UUVXF<N-A!EM52JP$Wr(W1{{qW>_8a#^%6L(mj-D7z7^^}u46+|xY z*nL0fR_cy7{O{~$te&Nzze7#p^tDAv7kT&d{JLHmD9Gx*B6Y26?9z*CJty`_Ja)~{ zeY*O6omsQX!Im)JS)Z*8FMPUoX`PfS=kuoJwqgFRp@*ZDkDdR0cy&@hPu$&>dGGn3 zafYVu{P#3;zj)Q+=KX)|5tGFHD}uw`#s~UF@iH(}Sxo*Qqgo$boqzj;;Qwg0KeF32 zCY-Q6{z>@-t0(i7zTRsdMSLk=YuXh8G_!IA7kbEgMwYF=e*RwNo8)Or<i4qD1~54; zxqI_w<=gypw=dtW*{@Dnb=tyft5rbc%Bm0d*W9^x>)tD$&mU#lChu9pCF|S1o&E6N z#FFVN><^`g|0}Js{n{TSUcYozk!bJnEHTlGA>kHA7hBczrg`|i%88k^@^VaS<<f-p zPkzOP3hTaf`(=0jn8B<mTE0f-KWIsY3r~$-efr@?|L0jUp%bOfb}o-zH)+i!^AG=L zD+coV_p={Ay!!LygZHi1U%mJ+&szV&;tQ!e=iUAIGV}h%YQ8Pj-e)I?Pu=RVyngce z)i?J9buYPaWV6Pz&0Q^q+4cgK93?#4>g1>H_<3?q$a9Yx*`raR<+r2v#x0+m(kI-* zyV&CIp4)cJS}(O0$3FRI5q{S#(<slU_D|g2kl*t=nBHbfu&ex@$C8wC#mT8y^M%8o z?4ZPm-uLBm!<mojUw#pG{fl1I7rkk(dW}!lf6+Vg?x5CcGa-(xs;w8LG+VB1oqK!g zG0yBfK}|KMFnMmJ$SS3O)1EEX2+hA_^KXsb<k>o2uV>HRQ2Y6v?#ZX(UoU#3U7RPS zkpFMdgUf|6st-EK#lyXSd_Avsp3OdDTDWUaW_iah&&YFMBYNLmox)TZ?pnAe-Nr@l zSg`Pn?UnWW=E-h2diICtxt8BYCu^K8S!E|uxzzE2P4LyfKGLaPi+#-e9<8{fdaJnF z`=GN<nrqSQB?a3;S(fRR+OW_2u61?$0l`IrYvV-&!`zNkPCp?g%=@@CAz0b@wrh{i z3L^<+{RCAHMn~gxp?Nn}M?WwK`R@Eb=|Wx{*V3n6Zlat=>!+Esc$O)rsIg@U8o0iF zWV5<UW@qg4qb5#?uY;^U*4fmR*WJ>SpSxk}r>P~Egq`(tXBBS=$uQT93z=3qhe2Fl zb8~t$oBG|ZoA%are=S8O&)MwRv1(WQtZ*-h#o-o$d2Dg#-FL;L^&VB}RNtT+uq=>` zd9sbHxlOB(GW!m%3-t+=%X&Z0*e#_xm8oA-meF|b9UrZOOlq957oY7pb#HdHNAUHH zw?j64Pg=h0`O^jULa%n(skvU@eEDO^1I83*%>#L&cilXtdV}_={JPcjp3zZ#TfgBE ziyKbAb-Gt<YiMGa`!sSVSGmL96^E`IdMi`m!r+noxWDnGKSR0wmi+yV_520y%(I+C z-1#&ZAE;hDxH4?|sV?D)Mfs{X&q&sMxV2YsE9ZrtmdOWXYj1pe9p_YA$(dXC_Qz?r zjNc!!+0|78>RPjx>#v`CU|zh+E{kmjHgeS;zhn!lTjYwBe!C~Abm@?O)%!2A3nTZJ zdGK`|c(BF%p*hdNeS4BSK0f=9{AhLkGRxx^x9UmVYPoQE`UPiedkqz*$-gH!Omg~f z)XwXhvgXizvG4iM$|mzM9yy`>V&VO_K6>RdcG)T2ylSxhbJwM!1n$G<@6Y8wmowu) z#=`utgWl|1ZxXj0SW%t2;;qC=alW?XYu+ZNPA8pT3GO@@xL$ZshTtL&^BB3sE^!Ma zqnFle&$=WUW@UEwW~|BFrN1IAFBcZgJ(9KNV#lFL4lGysEN)(ZG2{0P=5E2#5)a8h z|Gz&iYcsmC@3e?jlvg$hnCdJ3lB%g{WA2!p@MFr}mGhptF6ve2JDgqWvAQyQM~#u` zIdMscQ;KpQCw%Gfn7LKO)+y*xZ%FXAuL{$)rKY>L*IU1`E^SE5jjZ{YXi!uCZQkA5 zBD)<ddLG_Ew$&Gsr_IpXsG|EU;`p+kycMUUJf|A3xn)}YN$~fNxpg!A-46)tHfgz4 z`<ngLo`8zI6+8d048F_z@U%8-ncN?j<rXva{*>6y`6svh@hT5l#=6Exn}@OoUPRAn z=(r|%%Uq^4*<*42JmFgj9e>&xVl7hlTv#Yl&#__2`!ijAU1H90`I60IRaVU@54Qed z&i?Z8=<;x`rA`f3Qd`SK7JfA`)U>nfal4YXW8QL2o%Gg1)8L7=S1aE;?LEoZttqeZ zF^<{auQV+1`T0$c6S)+!f*9?y7xtgGU#Y(8HOt@acZD~uKdf_uz5b3(irS4MjhWB7 zqk_6wZ%C<LEZK1{=gscmc`YW1y1%q%bo22`ZM@1;P-QXej}~*soZIDbtEE1$g)m+e zlJdI5+sXW7Len}!??(()Q`+;zwEK@gXz2RH==`|Be2Ks%3kE*TB_@0mG*dosB)53X zULigAWz##CWs{0$bWCI5nxR{-=#a26>r3V5cWb*=28-T5zVg@_v*5*hW*LaTW)*77 zOH3{_ZfITja8LN{Ns>KZjklYA)LU_wRcPtYr2a?hUg8&PSN^*dx>-ixzuE-ehvh6B z%~6_DV^**G%woFxN_NA!<%?^Tj#PX)Qj*u=QJ?6wWzozdhx6JvR}}^{_k9Umu3F!= z_;F^_)ai>9{!ctJ-)7~_Q@lUkZ<#;!@<-A8FBi1gN=#&I->YbpR;w$fvc+tTMCzkA zr(ga`(wQ0aReSo6dn`|jpM6`ef4zKy+=06@pK>*bO^QD8-C*h$RzU*}G1Iw^_atz% zG`HM8;rS`L%Tux9$lMZ(MJWa46P8~6m>DHE|5|;6z-8V_=7k?7HcgE97y0tL=^EQ; z;dwvg?Zuj2uV~;4$qYFv{K{B~vob&INl5ptKU|NxSDg6nSfI!?BRY#&!l3lHxz)ub zvJ$5vU)I;<?0jFG!;`^#U+hCz*>1zM#{H*nYUefN*E9Z*oq6yT_k-I<yni38N;q*v zd6}GnQj>&x{k66;QcKit{IzfV`BWp`{mfLi><v{mUO^W-a!*K>$#VxESrN2+!8`-S z>w#Z4n-++vtX`;nqV&Kiy|o7lA6)uYE0HvF`hmrF6}FWv-Iv`bcep?2hIGku+n%T| zi`&j^==JYa?{m-$X%b-Ab6|P3U+62jXsIW>4uXl<9x^ZVtp3-Fz1@04vHDC}CetKC zVLj2gQ*V~&crf@KnUK6oaMqFye?<??&^s)j@OpoA=j1DLFYgs=%=6rx%DOT|^J3YP z@VkoZ_Zcjk88maf_0w#pi9bqW4J$sJTw{CVrs3AFrB?dtMUwWDv^yW}V4cSBcGtgq zzcPNy-8Ze0(0?o9S@5G|)A@R#n7EZ(r&Ek}g}3iw*ztS4#v1OLHFH+{_><ci5b>>g z;R?fV0Siy)NzJ|@z%6nrL#=PuOf{RyMU$qmW$*bpC*hqd(~3i}OS@;4*RJ($JMqP7 zi`BFljFt+m8yVLb|NUuwd2L;;%eT<dNq0ZJlvEYX+xB+CdvAB8@PB4$Q9Tct3+wlb zbu=$+lrYNu{PR7Ji!!6L$}gFZs~+avz8WDvEv`g;WpyiC(}AsC1>wK6ni^`&SG3M% zy%g`UN8_Ik>!**;C1+&IhtGT_weHj>*Dk(e*&noB8@}qF`oiS)(elQBuRiNroZnQ~ zf1J5#&00SF7n`_kv+cKt7ss1RzwcCb@!z3epOe2weZxtu^>Kf0o``om)BER<{)FTA zU$x0UO}@P1#~FK>k9WmVHy*Q&iOV@%mtd4MvFYLaTk$4V7Z}gJnXO$QIwd=e?d|G} zXCDGPf3C`wVAm)#|2;c;x8K<#*~O*#H^0e0*6bEM*%`0nlHpm;>>OeJpv_<Zp4|UG zS3Zkp*F@E8%a;_y)r9TRSa4|b>jf9iU-`Oc)@A8_pPgoB-7aq`jjGm6tm?NuF3iiS zq9Z+1TGQjD!EzI^hEC5S<IKd1qOQD05@+^I5~*)lF3-&x%@=lj?oQUbqBXOu9$qeB zeHzRtc++gl)}P1b-}vS`<zY_C(KXH8bE*?m&+)wJe7r+Ur~Z{~c=3hlSMKzR+%0^V z%F%S<q$AhO-6p(Br&lZX1R9BS3K^d}QJ8(=#Q&w;GTr`i37_)Y9IySco6N1|88OGE zN`|k{|Kyv8jUBmP7;;wb6)^1d`d-J=H_InrhepEHkS%PcdvBeVTx1*Z{E<#lXym=6 zw-^FuO|sorkRF%QwQX{J+A_I{3sJk~svXi)7XH+3ZZdCXmFU@+S*ELV_fD9y?e?M* zk2xQim<1<Qr5;fedN<{Q>-(vncQVwv&tYNW;(3&9mZY|&Gq9;HJ8G7i0P{@w4&9mI zO|^>Y;pMYbHyJQ|aLbEM=SfTc&CVOaA*uNFx*OZ#IAhC1-X>1z<=Gz->P2OC>}e^F z>*lln<@~<NS8owd%#X-_(VXWMLN;=8E?jnc6aU5|aSdq)mi|dnUS2qVQ~OpaAvM!q z8EWgd>8o5z<y-%;t>K{Xj{MAp7w)Z`EbC}gT+JAmT_E^0?XT`j|7TkR!@ch@6|`U5 z9dSjCvu<fvuf>$a4zUvVxBd@z9%8RQVr9nEUpgoFV%LVQH6J%S+izFuQ!v`~$m-^r zPm?b;{gwLhUbU!veZhkBzVDA*t84nVVCueaLCp*7bC&-9+TnFO_UELddV3k1-bcJq za{hdBPtHTT8T+Q*ez2mH`FmBjg52xZ8S}z)uPE(Pth%^C=D1m#{*Spf;<XRNh0pLw zEUB*FFE;6t;5z1KY?2}w1+CAWLKx2a91l}5TN%{dqMvhIS*N>st7EU;#maQ^gv7W! zkqK6PPASu$XPa)QoSfhwYu6sJEZw}|eg6869qsFdJ>MAEZ9c<vCHJVI#oSLv^}oB< z+kP(hwORA>{j3Vp|A7y`U8`qA^v6m&`OQM}nd+Ik85kJOFfcF}PF`pzH#tvhHA`uy zS?FY0?Q3Ah=I`18j1ZQ$?rLT*Yw|CHX<)|YDTdk1EYDU1hizsyRb+yQX_yx=%VJv- z%)r3Fz{tSB@OJWcD>+rv4j}`B97r0bqVc6H14D69@?=3n;mN$#A_^ckp|}=Bb-ngv zM{9eqqE!`FPlCL(8ssGuMUgs_1GNk$U$Eu}D?E29fr+1yf#DG&1A{t>LSx;@fm*VY zWo#tC3JW@StxaZTVEDtyz@Uesuw4(VaKE9To?b?PHzSh>Gh{_H$hE82dC2%NFfbfo zK-Xqw1k*P8o(&&3&?bMdkzje-cmXCOql0W5D1cvET1mfQWMHu1WMGg+afQ9v<U(6b Wh%xhQLB^z5Ox|TH&33~Yqz(Wxx4O&# delta 11311 zcmZ2lce}biz?+#xgn@y9gF$CmPw@ULlGE49Ffgo}#K^$Qz`&54pIeZhmzr0iSCO0Z zHa4<Y+I(Bx{P=~J4zHcr?r}r>enfF<v|q^MwJMh9=8B7j?bH@o=^eDmWdFZKJ58p$ z1?#ph@{cK*<kj@_!Gpu?#e5BFA3oc^U$?7zd!m8Puf5ZM*Z*L6`@VJF>)(sYe-{1! zeDwDGEC1~K|9$)XVV8u+V)1qLrFY-A-pkMrea#zxNA&KZ^6y3eUuTs3ee~hO?d|#O zlb1Ay6xBy%1eLG6pmOqS_2GXBA$MYAzpzhl-@m`U{N27b?c$1mFTcF`@<@RDXuT50 z%b81dCvH@ECM_H8<N9IGw|alqd<!F6@o)YAwrw}R{KxD|O?`pMo89X+9^Q28eEaE0 z?$+I{vNI0;y?EAuXI0YXBdtZY#iD&@VlPVeu^o&l?Wzl{nzQxFKZ!?+TRu1)p1h?s z>04UGE$LQA6Fr{OJvG-<(p@KhKKJqca#PkYmzX>8?R%H@?Y|Q*v+3!%eRuTJ>V3l^ zmp+*Od*$`;&yT!WtYUJ_811Aa%)M02Zq=k4yxJC$c*AtNsLbals|&8m-`Q_|Jzen} zi|(?$cjTLQDde-gpLAg6j@L(?g%ny9%$!qsjOpgD>8-|h{Z}4I`gZEUzF%*D+<iIw z&5OR%VLE5MSAY3YWq;=B^A%SzZ>Pn*u&LhqzFwO7>6<rCew_Vpw<e)^i+bawZD;pf z&~5m%YH1VirFkq~x6M8~ZD%<3ar(5FJb~{jAyMYDrtcDsh~kTB-l2Zz(x!`huB<)q z>E)ZpM-OwEc~mQDy}fmY`!174{5_d?8T&Qy%^TDcFKs%x=Zvnyq?&_2m$!e-7Wk&( z5oI=W`c77lzWVdGF79x=HQ4~{A~6Tc?3e6POKdr(Y|DMtn#VZh@#e?o`RC-qHaOmz z>;P6{=J4~9-$Axaf99pBvnv<gW>}hg=B~oK%oSU5P4r8-H*D$ElU`!WITdUG^OR|e zuPMCET(Bj_SigjOfz0+&Hr_|`TD)GneGb~raC&<E=kCqn{I9PoyzyMHCC5m=n0vyW zEb%xqj%pzl-PvbO-(gZoe=DZQduSeu=V`UiMza+neb<+1YKxv#*lNPneCOX&9sTRu zPo`M?Engn8`}5N;XOFHwd&>WEzVG*Cw>bO$9-Jz<_s;uo)zh!G<vomlxBpj7-LG%K zUAOL)Pcr;jQ)Ezo?0Le@wX52G-_nnf$iMCPZ}Vl{w#9uNe8p>?{u5N48u$2H@q(+? zzbts{YU=J=TK|0dlW~Swi0FQ;s-suWUOioF=C8H=<Y|>Yv$drt?vJM2H(I_W(3 zsh`jN=iAMTol|bNWWuY*)6cCwpZ+{sEPHl?`t2uDvtni^8NAuiz$sWS_Fi6B=HeFD zCG(7}_svYbay~z;cJ1>u4i-C3KiV2l-~3$b@HBU=^Tn%-Yu+sM(=ENa=W0<=N%n?& z+K&q^p3^huSbgQhthYynE<3*O*&{i#{q||@IqB=ms*5YO^n8$7V#_$eM4tP9L33s2 zZHFaKgBCd65*CnTdHh~J&p>}8=fwJ}U-qZ0Dfsp~jJdVy9GmTdjOUC+QZX|VCk1=Q zrRM6YAK%obxzkACwrS<!{Y@utFALUTY<wrO{S}j!Lz&)!i~>e+`w83<v(Fqn`&EPc zTGNc<w;m-H-ZU=mj`o@>^<vZ3Y14lA|7iO9w)q>|a(O+!bLZ^pqc+dG`=%t`zp1cr zLjC2xf1Vuv`SR$?{N>`=I*(0iGuNdrFJ=9Gu<1_wvTfJcs*}F{ySRJueZPC9b+&&~ z^U4!^KE6Em^L6?EQ%zf5TE5#=``!KY&aE$h+UEThEUtc?{dbw8g!r8|OX?DC9DnL~ z?$zVZpZnMQ_v`!JD>>(P&i`7(!OUNWgRA?F9$fY1@2mQRm4Ej0_s`$$|K?W2@$}cX zcHF3oI<;To?p_J;%9`V^EN7d0X)mx}9xK(7_#>|H_>SBYWtnfE{oH(Gsj0I4I;Kk| zwZDG6`;lXO@t6<~yYWH(HtD#?C!+W4t?K47O__XdcYpjg!_Au|AA4<<3%4(r(HZ3% zFWYG;xhW$o_~LJq>iV|zUgzWFH*r=T{*!Kgn%PJ@?W}=}Kg(H$xTtr!bI$6BtUWC` zzv!u|!4g;1l$dpKf1@9|$A7;1oU4cX>TAA3seyVfMLDw<e5ii@_T}w<UXL@}zmqEN zntqp8EB!X@mCm!LtJ)Syi(FqCX;YQ#mbN~uexbv%e<eEh$7Y;)D7eeH{&Spudg?2_ z?*AqV{o0DDGg+Uky12sey400!^@d$h&o?fJ`{Nn#Tz$QRqwRi+eHo>*_IAXqy`-FA zD?jt%*@FCKHzrREy)d!1w(#4#izlvW*)rX{{`X$Sh4=p|Gwzl*mTkSrsvn%HYq_E7 z)h6LLzc0+aHec<o*u!XDE=}Rrhppx6*LddK^!%7O@zL6cwfSF6dAbu1cRV}xdAsM; zy`Q7*zBzEtrRCn+mHc}H1-n@;Z29~7-`NALOWv>j__sCw;l35x+hX>s?VBC*sMj;D zP;2L^@YE}-dM?UnM}Jwqzjg0X*(-+SM{8tO8Et*F@kQHb124mnKG)18XO|=~Kbl)K z!D{J*`Xh&TZVTONwY!M-+^p!{EmB3|#^D`-t3LnAE~w|pUng~ALqxg|kDL0=ONDit zHVP^0Wz4_0aGrU3k!nHXss3f#dE?LKUX-8lZo`gUFK1nfG5M0Kd-?TLbI-54zR0({ zw)|1P<@}S}u5X9yWNM9@AFv;N+qAi6#>?lIyQ=f2W!p8?KeJ4$w~n~@gfZ!PTNUrw zX}f<r8)#b`Q*r&gxLD!LuHF0g%#7}8=luG!<o(>8@9&>se{??ZrJia1h6M-HI!)f) z<v%E&vvQ$Tgu$PU`;3e3vi&VSBYFHpbv{?|%#a%b)j67<53E0NN1$EJ_K)EWWsSg) zlertxH8WF#*WZa<tD9AS>WEd)V?EoF12)=!)=KDnPn-2F_*aGbzl@tnXM>DGy#k-! z`#W1;`Z0~@q@4%$oX|+^zZp1f?X9&z(pgg*rv6kdmJ$>9esJ!TT~v%-U3ElJ=px33 zn17GrUL=+E+IOpDIQF#Lx!x9BY*v$d<gdh$h|iw)j6XawOZC-zv+8-NbG^*d?Q@<j z+o3agy{(4cezTDI`3?QtsTbF2Pg8u=ck1-t^8u#Zd2)w(gDdYIpYnERjLy6KH4BUO z1@o%TYD+oZZPg<E^r-Xx%^ByrubJuHU)?6;o4iTcP4-Z)aI*5g^=tR8sGd=I@7&k5 z*Rqz~>pS`RO4rHRobPW3S>9jSCgkh9ss6F6?4jOIj}GPsmmkRpTNHVR-??Y2Jo~#H z7uUFK-XY&6{ra8gZ5z{9f+uX&8=A~g<vX<D{$5`F@3lMl_7-XHJ~eCUj^ERN*RQ`6 zbH9DR_`mo6Q`h}I{J-x1$FnDQAI*1*FJC61!lJg{X12(m<M!X`ZXN!A!+ufd@-oGn zd19eom)EcK-kfpv=`@G5ix>ZFpJZ+J{zlBz`OEY+R^EO8+}!_p&2cF&6W-H((xn{p zTcuyuS>B%~z1w!1`~;cT>zMNWd$*-6ewXvCvN!I-&g7Fnb=g*LeDWvz)!g5A&n{Z^ z&!n_aZ0*jvFZx#9W`@0d->>AwUOV#lZpf_VdVWh|6?QK^=2ZVm$+WESO`ml4O71%m z<+r~Y2P}S<{j9QAuj1kLN^A8U$;F}dvv!?$cGlwHwUTq?YZkg(-tcBeVEYHl9UCR} zcW_Urv&mXh+m`wH%8K8!D&rOl*SxXX;+4IV=k8pdbyu>M{mm0Q8$3Pj;=2@s^$~5W zt<Chm+aJEBv!jw@e(TxUo%O1>FInE-*e2wAc++Dy*+c0MkEJD@yleHCUFG<$<D2F+ zN|ojtpU*C7J}>K&cFv^Cy_t8<ec#2EuO6A)%JnhRnD+2h-`UfD&u;*ylIIDZ)0$3V zxN~Mg(e?{Jx&x9mGo$LSE&b@4JO9=6H7T3FziX>MD)D*x@5_HCS?`}JzI)28ssGO$ zwlp?MJ@iC%@@az`>x*;F?5X1T&R{%UkL9lQed~SN-;Qm+Sf{yOIqt!eS=n{d^!CQd zuZ(Mplb8|sAvCPgv#i@=%TLa^TBVZr*bmfeZTQ@KO`Re7o<1-0jY@N=_?+18Z0Bb) zKAo<7JSFqc6Sw-$Q$3A6V`SGEuGqPK%BBtHvs&++4drysv=RTYX~v#4|B@c}hh%(X z^2u&B;y-#tBs#qK<Eih{ME&pmDY|57ZEOG6VE@zahN1W6_E&G;_Rg(g&b{3GQYT)D z{_uA+Dz2_u`)vN3%bz~)&$Tw4y>)TH^k+XZ3WUY3tDDM3pXfMQ+g5)x)XUdn*<x+a z$v<s;XWi@GW>mX;<?5{7-M0l)pR7+g%@{Im=F+t%<oNC^+^KDK**mzqt~5U@y`o_D z)LlB;O@5y)KM*!`)tjiJvlAuu%ze7=-`6K!_n))h|NhE4*;p;J*OwQ4naUW!^zq|~ zXH3iX%bYmh=s&yLL!R@b%M}CW(~0$xK03?gV}7=;bBI`UD(Rz4yVNS*-QNS=@*FyU z;c0vR)HQB)qO}boudVmoxH8Qu=3K}3XZ-=!>K4ql><#|<e&NSY9A_7w-}C6I!VY^= zEB>#gal0kveT(^itbNmoz?Xkkb)Am9?UK3f58qO^DOQIs^e#4#`8%ONSJn3D|1~@J z|Cm^xw|q~!rLj`<#%-Z<f_ERO_{*X5^xwbJ&o7_LS5JSwT;9IqnfK;7Exmn5c11VH zTe4k~kJ=x3B)Y8BG*?qEzNScZ?c49`&U`KX@U+-z+4IxOXTABW@y54ebGYr)xXzf$ zjj3v-U)Mc|`lVHntP|&-bokur$Db!3TmMPx==5zKK}YNNK8#zNl-8UQX207usr%y3 zjDRQKJiONF=JxBn@6pMQ6Me&9BeCbs^H8U&hjw4sEmK>&)88{H?e5;W|5lpB-}9ZR z+BaXwW~X#(+)us-kJz3ZNjt-6_x9*No9Z})FFkMDR$qv=Dw_3N{P5&L&i&@zD|S_V zdidk&?#bWP<@H|uwXK)Zm#DXknYwAoAszGO&QoW;Jt#9xhbi<M*M2$o-9_FHJh!Y4 zy<_$^jcd&%KN}ZolfR$E7sp<`zu)BTukh=C<1Q@={*<Eoa+=5GNmAaI!aEzk_rH4R z(8p50se9|(A6xI9d0VyJ+V2F@*1Gf6wpFG_XZH!1F<)S2XMW9)Rj%_Prk=sJLS(}6 z<@0ulOfm7<{xYQWuVcj7+0Xg%*PTAR^}+pFtEU)Q8${>`ou2c1=F*p9hI{sv-@WqG zzxl)E<&O97_xJ~V@BdeP|M&jcuiu^BU?e<wRejKtXG>-tT(M*F>}l8U&N*OzYC_>; zDL>Y{n4`0Mx$o%Yw`DHt@yT!YxF^<pc6I$ug)i5`-<zvn&zbXbHv5$|GjE3$Ev}qp zYHn2iH}1by_Kszh-=BJ|{j9m9_4;)KgU>qyp03{(C2l3W^M!Vpa}#q2=ZT$DGOrzp z*dM7;aIb#v_j5Na*S>PyWMnsguk|l0so4D%Hh;doy?t=Q`(2)=9P0~qDy`Jnp|r4s zEB)a%joSJ{f?}bqOTSFDGQU2Z`Ejv>_2u6-Cu^)<#QU139P8(s8u#(2P=LNzVbsbU zR(z{<^|Jn3oz(7}qBO4{P^E`M>4&<{rTgM6dlP=KCjO6m6~5N3*K7LBeM_%M&O9xl zZ29Zaf;*k|8m@6|_Zq+dZ+7LGr+vrLuKMrmCucr?{dn}{@p}H>?(dF1e4e=T@bl#F z`>tE>@mpfAv(CD?;BNfQ<R})kt-nk{Jqn@}o-(dbGVQ$+#4#(tNk>qsK}$(s8B=pZ zSE^$>hoi7tOKDgk!>S1fR;GI~1-K^6?~&ic5R!P%r8$6Q0oU?IDOJS+R_;Zj9|Zy? z+IR^uF)!c>Q<FHZc%xplv1K{aA(lm_7A8nCE#R8&)a}8;5^8XXgPq+$w9%&X3^&87 z0Ovgi6`0hYTW(fjxZsj8ONoU`aUJhO4SvOI&)c%QBw2hqra1|*9{evL+sVUp=*z(? z){9J9B3jwCl-dMWE6C1u;cC!26{T$3QmS~+PM4dPWmUjQgMNuaF=F+Hc5jhs7BJhG z!8=K=N$X&cuq6xskvRg2UL3+5g=;KCSsJwF2ptOE!sH<OMkz?j(V_KbN~ljm!ov+F zht%3R97MeYpG7!yJY2ym(aOOnnz&)gF{cgMEUaP{9Kzz0laH|+iutB_<QZF&e#$Y; z!^$l`5BpBIQOU7e^2pMuipvG+7u7mV);HmBGC8@0tF6JJIx%di>I9aJobGe_#hhn2 z9#POY=qOf5>s=h-V8MRqmPVE`OUMp|AZ_kO?HK{jRXQGfcd``DaPIiNG(<>~{ose- z!xo$@hj_U3UT{46Vsx|itZ3tgvgP*@eN{RxZ#-brC*ktMWzFR|&H=5KZmekn^-Aha z%FnJjMpOy3&AiTYWTuFzV+7B^Ll0L>*)G-;J5lB|!;^q;jVWp-EXRE|PC3c#cq3-w z$ty)nNhf_Kemr8xv7#WE=_1>q6t!6i2W2^K1wBhm5xBN;is#(0vjQ~&%j7b(6bo9D z=Jmw1G;nQiOFXP_;Trctk+uU-Nn6U8j_j=0dn^*k_o!HK;nwFf920b>?YX1fx?y^6 zXwjK-jSsq%<cir63s>j{F&**K44hK^NU_0bqKlYw$Lu8s4hgd+*@|f@pKu6h%}zJD zDiE@;kL$5xj`D*8mp?T8kZPQeu()yKdF2WhsUuC2(fPGSP7EOzJro=jcBCHEoX+Ud za)7D3Uh2?tj!VlJ4hjn_*H?4p@NqWK@+q7%O->-pL5U?Wubwf0Rr|<PK>?Ww-Hw+T z4r&*_>JU}v;X3Bl^1@-oA|D^0MuX{wf^%2|)K@xAI>6bI${xt%&i{BppJIz<2XE;y zi^VO@2HIDWpEb7&9N;{>V<J;i<itCLYb-f7KN57-t9QC_uD~TKTT#NIb0-&*^8&8R znK%7(S~x|f^cy)C6lgjba0GI&^$B_|X4*LW;Np*Qt{lr94rOMkbj<Zsa(=*csGZ|X z!6TL?13L+I_Y9Mk9i541PWP{6SfONl_*}z}yh)mC_bwI)ICy2+^Zx=noSdR|77K*C z1{__(tzhOE`Jw)lA**765(j6KY>R}WM7zpYg*9u1rep~0|9pV2GF7)_D!V&Z=1PT# zXvw{$QH>k4X9&t0wAhv=Wp0saNl&}z;-<;6jzxQ>h(M3-w@j`|f#dpfs*dt@yjRmS znq<g)&`@}l61Re#tAa<OzDbL0?-n_3BiHQ=A&P#*{EvRjXRUuzYakG!Xra-l#1ie@ z>LBLLA=lBSv4U;m&ZbsVj>9+ZiT6k_KGF~^emg};AftQo#pzr}=I!dq6m)Ss@>{~v zTeahUY4Ev~2l)=AEW4;Gt**G>kYyR4BFD!iPmWArND7a=u!3W%z$4FBJzqqQxR%c0 zc2;RWAS$=giHk+6>G78O9}FLR+4#;SvprIGyw$bEti?g}l<r4~=8icQzQ!jU4YY4m zF6?M?5Y;hJ<T_&Oc+gVFVNRL1+T6(sO3_j>*9^?OT(|Hf3#?J?3(9wV!)esS!o_xk zLGV-ulc7UMi@?lQgP9xo^n$n<Mc?go(rZ|dJH=%;hoh*I=0QG}o&ziE%}ywDWIN|_ z1Szchyx>&Z0>?eMt(wyhWeFUcR+u-lWy5~|6^1N_e>CdwpOBPLPYLo|>}V5vaK)4< z4Hj#X;~sQ4{5d2uS>%ou%R^<}V+9|WTDGQo7@cygS$R&i-?6#kg$vgaR@RTZrmAaL zu^+r)w9F;*2jdDQ1Enj?7D>~tWz?T@IFouxcIy$R8%0SfY)c$2Oxy8kUn29v;L<Zm zOIQvmd9b<LhzmHi7}+i8a^RR#5T%<fu3+K(Ml;yRVTOa#>=nu#uNUz4Mo9}i+&4Y* zq>iEshl_EFZioKWm5W83H{?&@d_SXc!%{sbg|>!@C>O3nQ@8~VspYkp$Q}9KWg=AH z!`v}DUL(xoutTeM+`Yd{iEM^KGMhM>^h54gvp-6fTj>$CyZHxOFQ;#EfkKU<(6t1C z>kByFl{yG0z4;_Q<5)vQy0=u+zf&?Tjm9SqSA68=R=Xr6+7zlNW2ll)GvTd_lHd{l zrk1HslUEvS6R3#NYpz%=ojhrdVn@E~4i|}fPyWP*emuop5dteR^cS^$<eYU>u}FYl z-ut!Yb^#@pG!H3xf%&4IGn;ap6<Z1<mPW)EavTfmNYMSPz@+|k&QyiEiu0!8w;C(% za&fy%Y58chHT6)XK)7v?W9S7br=A0gFSoI9q_<tFR5I<k9yC*=tMNyei<YcT<A&|} zlh=yYUvr#s`i_=LZ|eizotwmx1?*QP-`gx;!*Wf?CD4GY$y}wW;-RC=u58t<%?37e zHm=ZY+fXvS%Sznw&IH|=PwyS-P}4P=)AS>6QtK9<P${P!{ms2$RUC!Ffn1!;3JVS? z^|7@?ADiWN&f(7km(?d^JMK4rO4v}w#+149@ug!72kWmHopgF4ai~q9?20hgBlZ56 z2Qy}HH)`_~3kJPlaS)Y^EfG0lT-xK&XUW3sE|A37{Nr!EiqpZ0skaiJ2=vV7Db{0V z`?zwdZ*#NboEKcL7KJM8`?7Ri)-xuS5Q{}pC*K^lS-*V^*H<%%>3_rOZm-(lu~@+3 z_|)9hN*fE#8FEzD7fkVZ%F+@2YDL&QSApAGLky2gcFcd7bZqT1g>TuF2`rI32lc(1 zc!U(@#ZTjS&5&$8K}dW~%SNLuRuX=SD-NA<KWxa6t?e5n9mSrw*XQ!C3yORPk7&xp zFl>ww>zOt^%pqZ|LsTU1qf1-|r+U{rMlAW%&=F?v?z?DPG2bKc!}XeLo?12B*f{l6 zg}mdO%Yo-Z1Voy&dW4tAc4#*RWz0U|q}ZZu#3ruX@i^6Mu3t>!gBg~g#{>oTmx%LO zpLVcm&}<5s!ojh7vQXf1fsXITH%y!(EMVu6w0O+}fkip1R+=*&3E$@8;j7Xru)ZKs z^`V4Q&gqF)PaTMuSlA-Lb4#dRbHfFNN1|C4+<eD=Cz~knCdoG@=<i_I=r`4|J3*Bt zUn2Ksl~9XBpY++S2L%2YeRYaDTBL4pJB*cGd=9hVdtvuft{lY$N|vHt4G|LzUmJvr zIqjL><e6pLA<b~<g~eLO7~8hW1&wYT#vI=60+R)tSQeQW8RTtJl@VMoz;d`=-#~wV zB+Eh3Clg&6nY4D)G#}&OaNIWKVm9-mZ{BVhE<#5t&BJeHNX)yb<-^+KAnH7IDa)Zh z3+EVjIsTb;D_PB^Lw&}|UZH3K`7^?qnTvE;;!im1*n2Q+j7y7i<9?(aJ!jfG$A%jx z^zPfF9do$h`rzJ84~IX~W(6&oF<D@nVEv58Zmt61`&AY@os!<fxS}a?$t@v{GS{RY z&B+2`D?<e4hOH8~qj)@mlU1ojcw&@t!XB%YJe&I*EEE>IOcY6X?#OX92=b6vKS!a( zfNi7KRHqvZk5^rpp|hW{@U@|<hak(NB$m#KpN$p_zAgnbSeO&FCO?@h*!*BxWml*M z`^WmO$tG<ai}%%=Nd8yn^%uEWEy%b3+xkNb|BHPTRck-I@3oY*P0#h|&pvG1VY=`C zn_VZj<hagz^6k*R{Y7VfE@(X`Iq&^?88r>Jd3SgH{&z}n+M{HrqVBuz*UKcUvC7|E zy?y`wA{Ca_(r<w$->;Vmj;PE_Ja_HWFGK0g<qK=;pKhqXETcRrdTDL_Q;lGrlW(LW z?#J)ka;eWFXu;vAy03Y>0l`gceLrgX+?~>E<1*uv<QtZ5gXgPK43BV_s3lHZ#woZx z)kExZ+vFo!E3dqIk|$Dic+vgYseYf=_5MB_BewVS<+wNDhnCHpT>p34qt789I~1Du z3sg%ji<d6@Ep<o!@a+24l0MGY_xoAgoc%B}Uxe-A4ud=MQ}4}s=X>f&j6hfB9s3;3 zw^}h@*}uO(Tk1PSJVv-DH9K(Qi?(>Szq5B~cx6<sUXiK$YL~sl)g>P8Js*{}O#5`T z+<vB`Qn=G<wX>D7bGGf-y5+T7;GvxlR$es@y!zo<$H&hPA+w9y7e3ee-R$ZV8VQ|e zeDNaxKR;qdlyO;4@UPC&KZ?8z3{T7_Gs>yfOaJzlKKV0U`J?@rl|f9lLZ3UT0(W?{ zHbjXOxwOfZcPW+ck^9i~b=~IO$1c47n*aX$jG2Ga%KtWSuMF|#u=#xU`@HvCPyf1Q zf4U;4%R}Am?TRe{u|G^TuU)@(-Rg0UMe9=w?NfJN6#g$;zW?s^@{PZQbMg-OFTWl7 zU&AMEg;8*Ql|_i~+}9g53sX~yoFil=+%b8%VMDb0Os~yBjB9_qikqse{E+RLop<{N zDRHgN%UlmrZFJnVb_YHG+Z^wAC183K@3NN5^5KP1v$B8uUFRS0cX4xf^S`GjFCM*b zoqzS-yD)3L3CiZK8)fbuycl?XaW(6P*~M2UJzaX)WBFv?(<ke<glx7jZ!tc<eDb6j z8`JHDEDTB*cKutxtx{*9dxeuJ{^f}kpYm$g-hNy1=t^?a)_r}GX0QDwD{yj(X5hpx zh3ofR^|Z;!sr}`+H}Lj+PNuKfg6s;nMLB+)SisuyO=v>nhwD3>woBd1uUyU6G++JK zwJT4~ML#+B{8X>?=O^b_zdop+A}r0=azp5lSFeE6E2*bt3kwggjIQYVI^pQ`CWmMD zI`*sHbWnd4JIU4jmCZiC(jfJ`yWj4<tbVlG>WZ`KO=tb9tdE}QbN#dGI3>YTSXE}p z9{>KwpC6CZ+dmogdq38{=oTXqY#h>DZK~#eFUYFvOw05WM=G+JzM8$i-Yt7=M}6%6 zBXcLjnOw@u68dU*-iw(heWliW^<!MY5s8-)WnNwqS#kcWDXYAb;mOChEgE;PHCeIE z;G#&uz12tVFu8qjyHYpv^_B}QmE8x@l$l@ebO>g4zMI+SqhX|>eEOkE0i&OBs=&R9 z$m<94G~OM*chhxu)yb*PxL0~7b(!WfKKc?>|G|gjijG6qCD+KPXOc;~Pkq|xmi9WP z>RX+ig{@`Q^ZvXWLI1dRz1+w;UFz(OXs;`?Q~bqU#f~;CeKh6bX1(Uw?{2)2m6!P| zwaN2X<WbkqyH01P2>p7Yn%8pVz^j`FL_TjZls<ZqLxU-0QE-Gr>d6g>nolGQ9kd)< zQ&(<0mi(qZOJF*e&axi16t#VFQ<+$Ef=XQHe%73B9<SsRd#rcaguB;gn_8aNuWDa7 z=X7n5#oPyd`CM@hVN;rJto^dKPuSMujLiG&;(hEEa~0$lc5mF=`fKL%z+667KC6?L zk^=8Aek|!++PYjO!i8l5+e81xSNw|a>T=ZgH}Otb#5=1=w4R?Ykf~{U4`19CtMI<L z2ZU^opUgV;p!<3r@7-e#mxcM5i@!9yxvaKuo{!V&<#V-ea%9TSD=P?QJEiVnZ9B7! zskTn^ebRlW?-e<ZUS75FONcuAI_93B&ZUFvXO&m^?q9Q9_EEEq!H&0QKS=LN@P8)Z zw5RIF#($xc=lp$f>IrXV{h<q&CogQ*us@;dG&NkWQDNs#Bi5#C#$reBi+x_7Ru;|Y z*fBAD1J~bqMl<gmzw%V><g&KCXKS@iGwSN>x3b-7QI^NFdgsnKkvOXh3E#i+?9IFH zwA)ljKZfV}oT(Yv4RhKrFdI#7k2~ga?~sd}(46;+S>`R4ir#s8_MNAF)?s(+KhBl& z7y7(t#te;pUCO2=D_j<OGBo9}_r!dC5%K#5cemWu?cSn+;eVfs{=JxTeHN!_K~-Ic zVpdecche6gx@-yNZr?R`B^#gnbR)verfqxHbU))v54)98X`4lyPU*#c6e#I;klf00 z*EwKPuS;;=7lpoUq3PATXTPf6+MJbZSzq(*<D&l$e=yJf{o%<YnGFg$g<l^z%2yvL z>tyvbJZfila^1loKhIS&60YannAE=@IPh1dl^lc9oJ#>$-dS2-c+z_3_1D>N&(Hm| zjz9jJ=!>6^#CIJ%SQeN2{m@(a0&A_$N0=Xo-#99LuTi45Tl&F8HP^pws|$EDw;pP- zdZGN!uD(U@&Ze*z0iE~TH>A9K)7f`vv)%mi4$m(A1bMONmtUX%%@uj*MMjs9ut@8x z!k8{)DXV&`Lz8=JdGbVV<z32|Hbc>5M}Xauhy>{m+)PTJg_(kQFMToQYIg`Y>zk6a zX7*o6wO_K@Vv<i6oGP5iCfCrtk&PiG;>7X?j@Pu7SbVKlHcnt>cU(F7-OQ@#j;|Jc zT6(~Q=lC%--OPZ_7Zsf~bDw28T$KELdG+~MGjIJkr}g#znN#9Cmt^hEoJ+duq)~8- z<@PjtbEefiO=})idT*0jY&k)H-p_kXXOj4iYBA+{{XOtEt$w}VjR|M(x<6mLYH1sT z7Q-xN=iC<7kDAIY3tZ}7JJfJ-{(N}n`Hz*GTo_zMyIVi5RBREr^Fu_?$s@1kl!E?2 zg=Rm+(nafhvx-jL;!*v+Aw*9hC(*WDk>_@%_W9kHziTauj4F{={q~4wQ_+!#Iieks ztAy7ad&{(Ko!IBoQl4%GCi*s+hvr`9;j{4CbkqBj?A$Y7Y8U?7wNNe6v3`5_hc?b6 z219|RL0bEQr0)rt^abZD?y#575mxvW%<6O9b;B2B=S5;~)!LMI`<!GE=RM(3KWm9Y z`4@||n?D7nJh2!0xjEf5_GjxW>x;!TReK&;-@Q=arIPifpvv{sn)yekb)IXpU90nU zb=&?riP={7=bu)-`lUt7FM9r!{@K>`8VL%!m(OepVR&jDvLxb7n69(}2cK#0<FyHl zEsZUAPk4NaZc5dTIC8&a$D$<#^%Iv~`*`_^O<k0%Q;zu$-WiAbQ+jT!vg3ZckEOKr z+Aj5fkNVHcZe7v97SgG=SkTu=uw{+;N#j@3Vp%!<xdx>CKCsh(tDquImFLE}7t(h# zCe`zaJl*=me*ZR`nN}OPO1kokD~|70?kRmGZ}hE+=fhiJ2iJ*$I(`iIkHz28zs4N9 z?44n0yP({W!jzS#bvnO@l>PTV^yiO8eE$sYsn;C7{?PEu)#dY2w~#-ZJ9{bD<c12T z);lk+zQ5LbT_Ka#*Krwh$h!>AHs;COE<Y4Fy~D+({uWnFw)d&sPhJ)NnAk6pQ<5$f zrc?DMDX8Xx!(zj44ktr;6d4K{edDVFGxxns5HM%q>OHJoxX}E<kL@eg-&A{<Y~-2r zpl4!%@$0Q;RwcVNJ#gW;xm<dkC)4idDq*FXc1r8)BZbXZ-o31STCsZDn`yS|Carb3 zJvDxc^SAv)KAY=v7kigqyB>RX^TXTw=bry|<J_}l%!`kC%WS*Y=f}p>EFc|P_3H_n z!F}^K&HOuJfwybzZn<UkdCsy^*m!>e|NC<{_yhHS{+5v|xD)WvfqAF>0p`Ml#m>I5 z+kV%l&A#9()zHJUWIyM(KL^}WWUesnjCmc$nVNj|`Zn9|5505u->uL3{h?s?z5ff| zcFs!Pv~IE4?dvQX7I&rp2|DlF;3M^M<(Ai9+Ly!~)~YMpHs2$%dW}xLu{qnS*DLk% zCv3AQd3dCu?d$1Hli7LP{>UU4zIqrCtR__B6U-WN%*}8oS9|~YKr#7H@#MMpKQv4A zU6Fb(o1!AQ?78iQjX4t=9u_}YU;j!rqajWA<liM+v-o#6{|eo*`S%K=;=rJTtXj^x zwX>UFUEq1M<NJ~$<yw!l&Tg~+vuut|P;P0&h6_PwSi1_U9GcFbzbF6a*PcWA=R#a( z{aMhs`H$O7oA$b+bDOuBhK64*^2(PmdU9!zVCd;vnR9tsj%o!xt6@0KcJ^JTw#sV8 z`Wq5QuP+u8kzVA&Zm;vman1wh{3;9e3!64qz3I`NA^Kpsrf{9qGKSFW4IbMUu6t|# zue<bqkI|ggnP;mCCRX#m(Uxr7UHIlYlWT2LhW@WPe47Fbs&s02niY~hDYkxzy;0bH z_-ev2F3C+Uten@Udq}-HT|d+2a9EeP#Glzm6_(f6O;mWQX4pNuy1(1mMscIbDu*Lh zRSr2T_cj<@YOR-N4Zm5sw38{s*D-tHvgm3_C!XD}BKEk=(fFLMr_C}&ExkYASyFuU zqPNR#u4RwgGVSKvuLWmTPx^1*{CMul?=3w`Z#M39WGZ}_#@?kPmptd#MF*Gl89ST~ z-52uuGPNL7x8C8tp&t{2CELTTEfSo98=Wppp1d=aNpZs0Mun3*lI9du?EQ6HN12<Q zLG8)Os#F81>%8WNoH{rb&bKm(_&Dn*r?)_kg?+3PzgR1C{B(n-OD{fr{_4{2lbzo+ zr1e(C{=478<*1QltkN>++-kccg3}q^HtGLlRn#x+U)8=;D9EQi%cnIb_H7))n$I%J zKC(3*R5!SP$8BNlJC*0rOP+mWTV%FQ@x;|-rkCdRWG|KMJ;OA?`L(g66hF)Pn9#%g zOQjdF{SEzHT(SNGbB=68Tf5q+jHb>+(ZI*|?SB0fp2&9ohQP~|t>^r!xX)=mxGsI< zUHnXk+1=Nfmb~1!Kd*JY?d*E-54+cX*#9;#d$;O+ksF)(-*2B%8{d#7wZP{4ZNDs= zS9`;*{Bspzv@r><nl(lD!lBIv^8=T@Ie4!6{ExTh@5>VeUmvqm@i=T3%Cq!zH2+lX zD}D+GRqt^G{x;8+x!%2_$m?v9-&HyH8v^X<&F^B4Jw3aYp|!R*faUT+zT{ndB0ajD zqm~MlEWI24;OLi|TxWh;?{#V3a(G2z?z0K3AGet{9o#!*eZ<fD^{;RJS9p}_{NM4& z@}Kv=U%UQ~8_}(5oopUFxmWud3z(6v17U1-)D2(+3vHgNx0;y`B)NK>hm0Qs1H%D^ z$@BG$CpQ{JLKNIH%4TK(tykUbYo^Eq5i7DNVwMGo?MGX~%D}+Dz{tSB@MAKgjhq5% zpN@e+4kQgz(Rf2<vb~KC*ucs8HWDm98cnq(`|HY1USXpI5j_VM<<|y_?$8#VEM?0N zk<qmUsecKQ(bNg>W@Hj!7GVG_tOfa`pmW#SWM&42Kb#B<dMH-f>Q468Rh+!vRvKc= zJ+Luv44|TXlQr#l6+lMh6_)WxF*7i{U}s=3M=_$!5UQAWvXn9R<bFFIaNtayZwGSG zSCh%R?KB-hMzl8@iTN@!FwB-?VBkbCLdu+hAt^;aDMha&IVZrIl?^1z#lXd2&dk8j IX9eN`0NkNJa{vGU diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v index c6560f7..1d30f66 100755 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v @@ -133,25 +133,19 @@ integer byte_index; reg aw_en; - wire tx_req = tx_reg[8]; // request to transmit - wire tx_ack = tx_tready; // acknowledge when stream ready - - wire rx_req = rx_tvalid; // request to receive - wire rx_ack = !rx_reg[8]; - wire rx_val = rx_reg[8]; + wire tx_empty = !tx_reg[8]; // request to transmit + wire rx_full = rx_reg[8]; - //assign rx_reg[7:0] <= rx_tdata; - // I/O Connections assignments - assign interrupt = ctrl_reg[4] & (!tx_req | rx_req); + assign interrupt = ctrl_reg[4] & (tx_empty | rx_full); // TX stream interface assign tx_tdata = tx_reg[7:0]; - assign tx_tvalid = tx_req; + assign tx_tvalid = tx_reg[8]; // RX stream interface - assign rx_tready = rx_ack; + assign rx_tready = !rx_reg[8]; //AXI Slave assign S_AXI_AWREADY = axi_awready; @@ -257,27 +251,27 @@ always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) - rx_reg <= 0; - else if ((ctrl_reg[1] == 1'b1)) - rx_reg <= 0; - else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) + rx_reg <= 0; + else if ((ctrl_reg[1] == 1'b1)) // RX flush + rx_reg <= 0; + else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // SW test write rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]}; - else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) + else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // Read and clear RX valid pending rx_reg[8] <= 1'b0; - else if (rx_req & rx_ack) // check precedence (rx_req) - rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; + else if (rx_tvalid & rx_tready) //(!rx_reg[8]) // new RX data + rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; // valid rx data (= clear rx_tready inverted bit[8]) end always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) tx_reg <= 0; - else if ((ctrl_reg[0] == 1'b1)) - tx_reg <= 0; - else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) + else if ((ctrl_reg[0] == 1'b1)) // TX flush + tx_reg <= 0; + else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) // Write and set valid pending tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]}; - else if (tx_req & tx_ack) - tx_reg[8] <= 1'b0; + else if (tx_tready & tx_tvalid) //& tx_reg[8]) // clear TX valid pending when req and ack + tx_reg[8] <= 1'b0; // clear valid when TX data acknowledged end always @( posedge S_AXI_ACLK ) @@ -392,7 +386,7 @@ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) 2'h0 : reg_data_out <= rx_reg[7:0]; 2'h1 : reg_data_out <= tx_reg[7:0]; - 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], tx_req, !tx_req, rx_val, rx_val}; + 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_empty, tx_empty, rx_full, rx_full}; 2'h3 : reg_data_out <= ctrl_reg; default : reg_data_out <= 0; endcase diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl new file mode 100644 index 0000000..4804aeb --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml new file mode 100644 index 0000000..6298ed0 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml @@ -0,0 +1,600 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>soclabs.org</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>ft1248x1_to_axi_streamio</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>aresetn</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>aresetn</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>aclk</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>aclk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">txd8:rxd8</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_TOLERANCE_HZ</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">-1</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>txd8</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>txd_tdata8_o</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>txd_tvalid_o</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>txd_tready_i</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>rxd8</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxd_tdata8_i</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxd_tvalid_i</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>rxd_tready_o</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>xilinx_verilogsynthesis</spirit:name> + <spirit:displayName>Verilog Synthesis</spirit:displayName> + <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier> + <spirit:language>verilog</spirit:language> + <spirit:modelName>ft1248x1_to_axi_streamio_v1_0</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>d48af1db</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name> + <spirit:displayName>Verilog Simulation</spirit:displayName> + <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier> + <spirit:language>verilog</spirit:language> + <spirit:modelName>ft1248x1_to_axi_streamio_v1_0</spirit:modelName> + <spirit:fileSetRef> + <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>d48af1db</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>xilinx_xpgui</spirit:name> + <spirit:displayName>UI Layout</spirit:displayName> + <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier> + <spirit:fileSetRef> + <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>6f142aff</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + <spirit:view> + <spirit:name>bd_tcl</spirit:name> + <spirit:displayName>Block Diagram</spirit:displayName> + <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier> + <spirit:fileSetRef> + <spirit:localName>bd_tcl_view_fileset</spirit:localName> + </spirit:fileSetRef> + <spirit:parameters> + <spirit:parameter> + <spirit:name>viewChecksum</spirit:name> + <spirit:value>45a2f450</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>ft_clk_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ft_ssn_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ft_miso_o</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ft_miosio_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ft_miosio_o</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>ft_miosio_z</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>aclk</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>aresetn</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txd_tvalid_o</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txd_tdata8_o</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>txd_tready_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">1</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxd_tready_o</spirit:name> + <spirit:wire> + <spirit:direction>out</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxd_tdata8_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:vector> + <spirit:left spirit:format="long">7</spirit:left> + <spirit:right spirit:format="long">0</spirit:right> + </spirit:vector> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + <spirit:driver> + <spirit:defaultValue spirit:format="long">0</spirit:defaultValue> + </spirit:driver> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>rxd_tvalid_i</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + <spirit:wireTypeDefs> + <spirit:wireTypeDef> + <spirit:typeName>wire</spirit:typeName> + <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef> + <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef> + </spirit:wireTypeDef> + </spirit:wireTypeDefs> + </spirit:wire> + </spirit:port> + </spirit:ports> + <spirit:modelParameters> + <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer"> + <spirit:name>C_rxd8_TDATA_WIDTH</spirit:name> + <spirit:displayName>C rxd8 TDATA WIDTH</spirit:displayName> + <spirit:description>AXI4Stream sink: Data Width</spirit:description> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH" spirit:order="3" spirit:rangeType="long">8</spirit:value> + </spirit:modelParameter> + <spirit:modelParameter spirit:dataType="integer"> + <spirit:name>C_txd8_TDATA_WIDTH</spirit:name> + <spirit:displayName>C txd8 TDATA WIDTH</spirit:displayName> + <spirit:description>Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.</spirit:description> + <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_txd8_TDATA_WIDTH" spirit:order="4" spirit:rangeType="long">8</spirit:value> + </spirit:modelParameter> + </spirit:modelParameters> + </spirit:model> + <spirit:choices> + <spirit:choice> + <spirit:name>choice_list_74b5137e</spirit:name> + <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration> + <spirit:enumeration>ACTIVE_LOW</spirit:enumeration> + </spirit:choice> + <spirit:choice> + <spirit:name>choice_list_d8920bdd</spirit:name> + <spirit:enumeration>8</spirit:enumeration> + </spirit:choice> + </spirit:choices> + <spirit:fileSets> + <spirit:fileSet> + <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name> + <spirit:file> + <spirit:name>hdl/SYNCHRONIZER_EDGES.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>hdl/ft1248x1_to_axi_streamio_v1_0.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + <spirit:userFileType>CHECKSUM_dbb92f62</spirit:userFileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name> + <spirit:file> + <spirit:name>hdl/SYNCHRONIZER_EDGES.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + <spirit:file> + <spirit:name>hdl/ft1248x1_to_axi_streamio_v1_0.v</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>xilinx_xpgui_view_fileset</spirit:name> + <spirit:file> + <spirit:name>xgui/ft1248x1_to_axi_streamio_v1_0.tcl</spirit:name> + <spirit:fileType>tclSource</spirit:fileType> + <spirit:userFileType>CHECKSUM_6f142aff</spirit:userFileType> + <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType> + </spirit:file> + </spirit:fileSet> + <spirit:fileSet> + <spirit:name>bd_tcl_view_fileset</spirit:name> + <spirit:file> + <spirit:name>bd/bd.tcl</spirit:name> + <spirit:fileType>tclSource</spirit:fileType> + </spirit:file> + </spirit:fileSet> + </spirit:fileSets> + <spirit:description>FTDI FT1248 single bit serial to AXI 8-bit stream IO</spirit:description> + <spirit:parameters> + <spirit:parameter> + <spirit:name>C_rxd8_TDATA_WIDTH</spirit:name> + <spirit:displayName>C rxd8 TDATA WIDTH</spirit:displayName> + <spirit:description>AXI4Stream sink: Data Width</spirit:description> + <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_rxd8_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd" spirit:order="3">8</spirit:value> + <spirit:vendorExtensions> + <xilinx:parameterInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_rxd8_TDATA_WIDTH">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:parameterInfo> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>C_txd8_TDATA_WIDTH</spirit:name> + <spirit:displayName>C txd8 TDATA WIDTH</spirit:displayName> + <spirit:description>Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.</spirit:description> + <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_txd8_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd" spirit:order="4">8</spirit:value> + <spirit:vendorExtensions> + <xilinx:parameterInfo> + <xilinx:enablement> + <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_txd8_TDATA_WIDTH">false</xilinx:isEnabled> + </xilinx:enablement> + </xilinx:parameterInfo> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>Component_Name</spirit:name> + <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ft1248x1_to_axi_streamio_v1_0</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:vendorExtensions> + <xilinx:coreExtensions> + <xilinx:supportedFamilies> + <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family> + <xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family> + </xilinx:supportedFamilies> + <xilinx:taxonomies> + <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy> + </xilinx:taxonomies> + <xilinx:displayName>ft1248x1_to_axi_streamio_v1.0</xilinx:displayName> + <xilinx:coreRevision>5</xilinx:coreRevision> + <xilinx:coreCreationDateTime>2023-02-20T10:15:53Z</xilinx:coreCreationDateTime> + <xilinx:tags> + <xilinx:tag xilinx:name="ui.data.coregen.df@428bf478_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@77d2a63f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@401fae27_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@799f76c6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@543230e4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@860c575_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@13b2b016_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1b16e880_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@b115448_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@35f4f12f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@96c629_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@289d8498_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5e6ca2b9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@34c6c438_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2f1c92e2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6bc27418_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6470d1df_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@666070f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4795032_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@214e5d0f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@72c6aa50_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@310b0085_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@7057424_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6cf947f0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2241eee6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@64c33679_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@f32e78b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@524b62d8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@25a5c540_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5b694545_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1756c2fa_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5e55a1f4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@6e825144_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@29f61c2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5d96e1e9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@608fee64_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@12bb2394_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@319424cf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3aac7e77_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@511ec980_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@330b1dd3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@529e8eab_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@dd60893_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@c8742b2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@7621d7af_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@24f3db95_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@22c484f4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1866e24c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5571345d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@46ac3e68_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@56b1d9f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@529ff48f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@757ac0cc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1fcd0999_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@90370b5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@28c4e1ce_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@a3c2c51_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@33cb581b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@36560694_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5a029744_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@649708f3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@40b4275d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2c2b1fd9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2c951206_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@60f53ba_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@62ce2736_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@4869df7e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@366d857f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3143c41e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@a3a24e5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@f50a86e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@16f76b78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@784ca772_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@266cf8b0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5985e9a7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@5b0f2afb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@261184f5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@1ff5947b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@439de9f5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@3103f8a1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@43ce0b7f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@63f6aeb9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@654e1a72_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@428ff7a8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + <xilinx:tag xilinx:name="ui.data.coregen.df@2747214_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag> + </xilinx:tags> + </xilinx:coreExtensions> + <xilinx:packagingInfo> + <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion> + <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6c2025e0"/> + <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c08cf8d4"/> + <xilinx:checksum xilinx:scope="ports" xilinx:value="95a87e81"/> + <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1be3ccaa"/> + <xilinx:checksum xilinx:scope="parameters" xilinx:value="6bebc0ed"/> + <xilinx:targetDRCs> + <xilinx:targetDRC xilinx:tool="ipi"> + <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/> + </xilinx:targetDRC> + </xilinx:targetDRCs> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix new file mode 100644 index 0000000000000000000000000000000000000000..e82fe55bd07f5b2021117a733d5ad768f20a16cc GIT binary patch literal 260 zcmWIWW@gc4U}NB5Sh_?gRI^Fgv5A3!VJ`y%0~><~LvpfSMQ#owg8&0M*t~K5iL-$k z-nv@n&Ya&IYIMaoAjspa_c{NQXS}zEa`6^k-WsrJ`{PZ8=k&cw&z;xyJafidH|T@! znN#{)&6!MDAJ3j~7ToYSD1hO0;psD;TfManO^i0KFzC@g+3&yRM326nrkC%TvuFCv zJIpT~*IgMtaZcu9{!NlOT;eUf<*l;f3<2JZOd`x8INT0#FCzm3!;(f28{(4yZ&o%C RkCB0q!GwW<VHb$Q005UEP7DA5 literal 0 HcmV?d00001 diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v new file mode 100644 index 0000000..35555b6 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v @@ -0,0 +1,40 @@ +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright © 2022, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +module SYNCHRONIZER_EDGES ( + input wire testmode_i + ,input wire clk_i + ,input wire reset_n_i + ,input wire asyn_i + ,output wire syn_o + ,output wire posedge_o + ,output wire negedge_o + ); + +reg sync_stage1; +reg sync_stage2; +reg sync_stage3; + + always @(posedge clk_i or negedge reset_n_i) + if(~reset_n_i) begin + sync_stage1 <= 1'b0; + sync_stage2 <= 1'b0; + sync_stage3 <= 1'b0; + end + else begin + sync_stage1 <= asyn_i; + sync_stage2 <= sync_stage1; + sync_stage3 <= sync_stage2; + end + +assign syn_o = (testmode_i) ? asyn_i : sync_stage2; +assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3); +assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3); + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v new file mode 100644 index 0000000..d4c6ac4 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v @@ -0,0 +1,199 @@ +//----------------------------------------------------------------------------- +// FT1248 1-bit-data to 8-bit AXI-Stream IO +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright (C) 2022-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device) +//----------------------------------------------------------------------------- + + module ft1248x1_to_axi_streamio_v1_0 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + + // Parameters of Axi Stream Bus Interface rxd8 + parameter integer C_rxd8_TDATA_WIDTH = 8, + + // Parameters of Axi Stream Bus Interface txd8 + parameter integer C_txd8_TDATA_WIDTH = 8 + ) + ( + input wire ft_clk_i, // SCLK + input wire ft_ssn_i, // SS_N + output wire ft_miso_o, // MISO +// inout wire ft_miosio_io, // MIOSIO tristate output control + input wire ft_miosio_i, + output wire ft_miosio_o, + output wire ft_miosio_z, +// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO +// +// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated + + input wire aclk, // external primary clock + input wire aresetn, // external reset (active low) + + // Ports of Axi stream Bus Interface TXD + output wire txd_tvalid_o, + output wire [7 : 0] txd_tdata8_o, + input wire txd_tready_i, + + // Ports of Axi stream Bus Interface RXD + output wire rxd_tready_o, + input wire [7 : 0] rxd_tdata8_i, + input wire rxd_tvalid_i + + ); + +//wire ft_clk; +wire ft_clk_rising; +wire ft_clk_falling; + +wire ft_ssn; +//wire ft_ssn_rising; +//wire ft_ssn_falling; + +SYNCHRONIZER_EDGES u_sync_ft_clk ( + .testmode_i(1'b0), + .clk_i(aclk), + .reset_n_i(aresetn), + .asyn_i(ft_clk_i), + .syn_o(), + .posedge_o(ft_clk_rising), + .negedge_o(ft_clk_falling) + ); + +SYNCHRONIZER_EDGES u_sync_ft_ssn ( + .testmode_i(1'b0), + .clk_i(aclk), + .reset_n_i(aresetn), + .asyn_i(ft_ssn_i), + .syn_o(ft_ssn), + .posedge_o( ), + .negedge_o( ) + ); + +//---------------------------------------------- +//-- FT1248 1-bit protocol State Machine +//---------------------------------------------- + +reg [4:0] ft_state; // 17-state for bit-serial +wire [4:0] ft_nextstate = ft_state + 5'b00001; + +// advance state count on rising edge of ft_clk +always @(posedge aclk or negedge aresetn) + if (!aresetn) + ft_state <= 5'b11111; + else if (ft_ssn) // sync reset + ft_state <= 5'b11111; + else if (ft_clk_rising) // loop if multi-data +// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate; + ft_state <= ft_nextstate; + +// 16: bus turnaround (or bit[5]) +// 0 for CMD3 +// 3 for CMD2 +// 5 for CMD1 +// 6 for CMD0 +// 7 for cmd turnaround +// 8 for data bit0 +// 9 for data bit1 +// 10 for data bit2 +// 11 for data bit3 +// 12 for data bit4 +// 13 for data bit5 +// 14 for data bit6 +// 15 for data bit7 + +// capture 7-bit CMD on falling edge of clock (mid-data) +reg [7:0] ft_cmd; +// - valid sample ready after 7th edge (ready RX or TX data phase functionality) +always @(posedge aclk or negedge aresetn) + if (!aresetn) + ft_cmd <= 8'b00000001; + else if (ft_ssn) // sync reset + ft_cmd <= 8'b00000001; + else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase) + ft_cmd <= {ft_cmd[6:0],ft_miosio_i}; + +wire ft_cmd_valid = ft_cmd[7]; +wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0]; +wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0]; + +// tristate enable for miosio (deselected status or serialized data for read command) +wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]); +assign ft_miosio_z = !ft_miosio_e; + +// capture (ft_cmd_txd) serial data out on falling edge of clock +// bit [0] indicated byte valid +reg [7:0] rxd_sr; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + rxd_sr <= 8'b00000000; + else if (ft_ssn) // sync reset + rxd_sr <= 8'b00000000; + else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift + rxd_sr <= {ft_miosio_i, rxd_sr[7:1]}; + +// AXI STREAM handshake interfaces +// TX stream delivers valid FT1248 read data transfer +// 8-bit write port with extra top-bit used as valid qualifer +reg [8:0] txstream; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + txstream <= 9'b000000000; + else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted + txstream[8] <= 1'b0; + else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives + txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]}; + +assign txd_tvalid_o = txstream[8]; +assign txd_tdata8_o = txstream[7:0]; + + +// AXI STREAM handshake interfaces +// RX stream accepts 8-bit data to transfer over FT1248 channel +// 8-bit write port with extra top-bit used as valid qualifer +reg [8:0] rxstream; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + rxstream <= 9'b000000000; + else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data + rxstream[8:0] <= {1'b1,rxd_tdata8_i}; + else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion + rxstream[8] <= 1'b0; +assign rxd_tready_o = !rxstream[8]; // ready until loaded + +// shift TXD on rising edge of clock +reg [7:0] txd_sr; +// rewrite for clocked +always @(posedge aclk or negedge aresetn) + if (!aresetn) + txd_sr <= 8'b00000000; + else if (ft_ssn) // sync reset + txd_sr <= 8'b00000000; + else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111)) + txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000; + else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift + txd_sr <= {1'b0,txd_sr[7:1]}; + + +//FT1248 FIFO status signals + +// ft_miso_o reflects TXF when deselected +assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0]; + +// ft_miso_o reflects RXE when deselected +assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v new file mode 100644 index 0000000..03004be --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ft1248x1_to_axi_streamio_v1_0_rxd8 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v new file mode 100644 index 0000000..28cc34e --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ft1248x1_to_axi_streamio_v1_0_txd8 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip new file mode 100644 index 0000000000000000000000000000000000000000..9da11b5a3446608bfe339577062496b021daa431 GIT binary patch literal 7881 zcmWIWW@Zs#U|`^2_!SruHvePqhZnpI3{Ms^Fz_-kFeK;a7Ubup=9TDG<mSAMjhueV zOnTq@^&cMA9hmmra_&oaiAe=kx7k%<^J-EendVE(zLhrZ->*|_?~R&;Ck4ss-BNr1 zth`cXuh6F7pY`>%{VNV7K4JS8>i??SmhrbnK}>z&)!!!d^@(5VcK&<$JmYO!UQK7y zRjUsh<+(%7_UpyRoc|iXuIjW!Ts$A!`Sa)h>aO%xt+rmcHqSM~+o@5WHStYe*k6Sh zp1S?J=Pp!@J9zL-q0!tk?32<~h&za!J#)$XN!S^i(<_xkCvv^zzTThoLix__f1UzH z=jU&D&+@QTM1lWS;G%Dz7o5`KtX?O3=)>14;fDs|r#n<F<=1^M?NnVLp+8BKU96^X ztp=ZA%udI3GrU4$JU7?+PLBPQ=&jv(b9Tm~;}$9c4>b}uL`M6aRhM|galGzu>#T`C zUrTXM)rt9f>g#H^x~tuHTKV_RnHRD5)zbb`nW7rJug))7+3(zuq*b^lJvuSw!gqW7 zPY;Ci0<Md+lo#yvHfjzw@RHyZ(`&k?JXK?JcI%9D&(0_<X|mjOV_A{<wDp4B_ZL1} zS#T`jw)TyyGhTnO@!nZ&u*82+M#@wD#~UAc$=1~DkiE3=pZo6H*1v?mm{}&oJYV(w z-Q}E5{|YT+??ujU-#-7?--jhO(&yj*o_SJ6I74y=hri*@SGoT)D)U65cO|W!wB~YU zlEo~4yZ*Je+wXTV&a~;9I=9Nj*Uv1%*sXYroL%3<@2xXuCi5pfVSRDBvH8V~W{cWy zn*5J0zFiM;s=M5gTvmTo{~{Lt^v&%TQ!M1~N4#XnDX(|8Pf)qs^Zj*Mb+6>R2Zq0< zK3q~)+g=dVc(3%&BZ=vXf3JV%eet*CPkr{k0_%Bv@7<GMKc0WQYenLY@><2x{-q}^ zAF<4OGD9-|q|<fJGiT>T%s!s+SzOklwf3;cuJ<ox)h>$mteDHT)6UhzLTAqwpW3ZK zXY$)VD{dBBnQ<(`aN6#JbAFu?ioCn_Mx&w0nl$Bk*-uU+OX=SDdZB;1u+<zj^L*<Y zNpG_!IUQg6dQMr;vd0h4&TIQ%t<w7L#+>lewZCWPEY9^@dAZ+WW9YTs&qu;4J{;bC zSl()V>(M=BC0pc-)$L2-yeDs(d)?1U6UOYbyLtU({@H9Fw^dVi?%|So^LEV}4}ZP7 zyqr*>q|GLo5w~|9U9`E`+gM`nua83Rc~^w0m%Z9?@mBNt@0_1MhlS2CEjb;;D}1AV zmc@<!*hiPvm3{vcxq(w~**`l+bq(3BI5XMRuguR>Ux?3nz?43XdrnGEo7b$fS8i@Q z?D^VrQ`hC=PWuwOcF4_pSkcAF-CgpWZ+n;S&Fzz#B0B|l6>BTn1ZO+-emx-btEX41 zIXdl{!=xR?QAuA^Z>@=%5P0ooUXskw2A85YF$=eC*Q`AMVc|*bfVt8-2X`4?$=%c9 zpC{m?UlcCQuhyOKol_lnKg3S$&FpKIM{HM%JXbvMKsK9W&l>UB+f3)Pe)AW8D7KGn z_96jUgL4gExod0oKRGBpBQ3Oyf7PWII}Y@_sjxaY`LWrXz3rQD{gFMl<@-s&Sr3o3 za=$t>@j|k?*>AtI&n6md>7Bs+MMI0lCD7Y`dY%235Rb^@*^&$1<}FtB?KtbRRB_@B zr+d?{`Fg7Te$#d}p{%6+(&e>ZwnoQIHdb<0-Z<sW?tFulAsw25q8ctqr~EcfJn`)O z*_FCcp1XwVnr2T++c4>t&$i8$*Q9=Ldm6Jyl~Jee=avO$@)j)TX*`@D==x7mEIr~% z;>M!I3rcs_S?I0$dsb4yhC#XG#k;3AsdFZ7TzqXp;XIRb7cv@;-A~V$vvA|$WgIt( zPrfMdnIkT=PGRHsPcI}z-}-Ht{rmmmM-AM{?aq()bbM&<{cFBvAG6s!jqKm++$KLy z6iP35@eo*-P;>P&Q~kx=*NPu^@<dygh@Tew`sj|KXj0mqmlDit(k;RtryrO)Gp3BI zpa1#a>j(JSKUa$WnZ7Vk%j<>R*1rl56PV27{_L!|yVL4Z_v<sMk;|07vdfCjWsiAg zDKnSde_QU(RIe?Hk9p3garO82{taj1KYnbXad`1g?TY86JJwz0vzNONbLgVE?>5&; z|Ab9<>*s#?!MsX$t52s{!kmjYeI72nuwp{luSk!Vwi}N>d&{U6UD0{R<azjBS^I;2 zT~Ckfelq`$R<%*Cddu6l-&y%CmtR|bE%-_AnkR?$PrYZly>9lMGxqx$&wM&MW#R-4 z?v<MYLhn`AA3Z3@b+?r3=EL{Gsng;X2`gRyU!-{_;Ck!*81=YmZMll~4W`B2OyK*| zBk@S%!@LYVu^Yz~dp1tqJZbuccXD~hwm+SIVV32|r_C1*J`DBO%W<xsxXf;LPE_2k z(<`se+86lo-Bq7^-oIaEshzqXc6LjilS9i)S8i+J1&=Shac|n&`Rh=P=j$nZTooN! zK3Mg!SaEWAe%ExkFF0?d;hf9|8XG^&nI#=rzH)0(%-?!`nXe+(4=$7um(e{_vT4Pq zpi_MtYUTHu-OcGNJ+t&g!ruMoj`%HW{d-pHWVlt^_VqjK=hSE@1V7uqHmc5f-@=*2 zr~Z}qoHX=NxYbu&;N!ZI@8fc}TVm<%x9(Q2zMAB|cK3u`S2sm$T7PFFlV^%i)Y)&B zKC*4Lf9Ed0od5e|`{TjcHJ=l0UfUbK4b@fiSa<LExv52E&pc*cytsRB_?rH=84G9B zOnzE>Otx00ziw{ruFW#H%@{8_<SkITCYRef<@(O*kCAK7O0pk6&UpA@zTU%m(br_V zr`}<!SC-F@w>sy%Y*Bv7;((<7u48MnudT>1{PersU-<Rs3ai;RccSeJV&3lFc4wo^ zHscL*AE*5}5b%1-DW~9fE%(mns~!4X*)(Ix`nZaS4R<3Jc$O_xKho$Rt#xpRN9OH! z)t@FvuiqLn^Y1Uy=WKiD9Wv2An>TCbR-2CX_u@BP`Y?5O_nDCPZ-xi+mloR;xL^Fl zyKqhXO7rPO)xt9cFNZHWu5b8l^7fght*^b^6LKZ{(c}dQ;!HQ%x3!1gSTDcy?T<VY zKUEn;<tHEe-nYNcJ6`_yx25)rY^UpnRvfR&wER+HrioilmUNydk;Ye4#=D{Y(T;mR z$`2GypDW6JeEG)pR{u7vSpFruz4cSPlvwYA|CbLd{VrNOHKF4DgcS##IkbeVxxQNO zD_@QL<`#~!ExuW)skxqa^j>Ok6wVDVSbWyX^5@}m)vu;MPpkg4iNn)ky=0cn^amHU zKV{^}IoEuYU^}N~d+%-R|G%&PPrY8X`s%@3)-s3J_MW|U+eNpnsA%=$o6Si-gnk_C zlDyRSeb$--*OcE{UGv`6{;lY-<^F$HmR&rPQn~6*@V6(Ar}OmA+PEYw_|FqH)!kvm zy<9UF8ZGMg^m4q-VN<>`Qi18G6N|XR9PdX<m&C35G+#8Ex7STb{LB~KO-yRaoqa;v z=g(pKCOnz@&3D;P_N)?SfhC8f{M_ZYw`(kZIH&CD-q#0>A|5t=_E|EOg>85K<S1_Q zbN^}@C!N~2=18~bEgrX*@p|u$#9TSJIzeEsn_--5^V&6Ah1R;vSR;O+DExKf?rlzc z_-=hyeHwJ3VV|B?Y&pY~ltblHx-<kk8qbwa*_A02>nwFYa8(yiilBClduE1GQ0dh7 z3aU5RwrLddMVy>wk|UvXKk(M1C0bn1S1(;7)audj`Rb)5*&GHx`vfJHC2OcXuL#}P zrm(?s{n9lGyqZSOx3ai6sU2u|uVE_97(3Bo{nBMG7AafKS+6{6S?4Yfm3@mtN`ggG z&$X*g5LsiT^t|CJ<0XX<%lB7OJ-4`Cd{C3WvU}A!hI9U$CN4g%>T{UI7+eoY6xaDI z(DayQI`?zj+!GA1+s>9x&<e=mwU}eR(V<l<Nc5b#{MBnduAvt3x~j2P1r#Q{*9cv+ zDnMzEIqMCERZ9xwR1G@S6whssU6q^_acItWmRT7Bx9%14MR49Qo8WtH@f6j`?{*11 zXJ<8P@i=bv{5xle=b;l%{<eEZishaxOxd?Mq_LBi$MSxKC10$!&pGc-o>)e+=X3kl zF`m4r`200TK*yUKYR_kTGfYU**pt6o#rd*9Ztai0pwLp!u#oom8lt>PlG$_QAFPzh zt?{{6KY!_5e#NeXKfM;MwsKK=RP${jN0H0rCx2{?h@{4Dsm$l%S(3n+xNmWb5tGMT zlfzMVb#gy0@N29UiFP}A=$ClY#MG44ZC5h+D-T`FSf!SA_uOMYb1BiT16Ov-{+gd> zGArrTB1fy-C;sMAu3JPGl)s+oZ!Xo)pewlivQ*8fi!)ZS9Pumn_A{6ARauo&{!8?G zOEV(}bL_JvCS40>@?Et4YQ0>#cTHyB!dG+6Le*t@mz?mJXt9!aief;)^0$XyvN?wc zN=d0tooKQsyKH;-DSvaRy8!}MzWUj_%*iuxxGZ4!#?QWNUY^OS%oR6U=GHB+dzg_k zk-@{_W(AY)B%am+BS-I+70VVC2T8k{$>w|tl8zKgO>*$-o1f9&<~n=&yx_^5Y=zsy zi~TL6LJtZ(St=gT;Ml=u`SNnZx)%;sHzyx7(*2)ut8a=+;Que-V!xyo=@&fw)qQIF zjj}Uu>+K#J{JkV1(0FBf(dy7NUtwLtUqZQIkx|MbD)JKB%`YD5FZ5726sVuPOx|wy ztIQ5N$D>L41q-%5`MgN}P{QWC8BU8FZwI(r-U#`%-*!c`VQ9vS8x#1pZ7T7aZ?`^r za*mEN%fo}$y4LTx>YHh{ZDPmVWh*7xxMlA9xSu&+`nF=`Rtt_jtLN=5^NxR&-eJFF ze)t+bf%1pJ0g)<4>LX9@fBo<1LpJe!p$B$uKG~3a_2Zn23@_&Kvp&<AQakbeujTa& zh%Vuq#X_M8o?KB27#SGMSr`~37#J8bQgZZzBmJB`g8cnFqg;dHU0vK=gZ0YR2K)Ly zHW09V9B&vi&E?fHfjp5dYrUqsIw@Qfj?ub4bJ;z$d8f+EUbX%|eE-4phcza-w^l6Q zT2%1t=U#JTx$nOXn)a(qZJqOli)HCb6Sql+I6Mx@Ot*<-&`t14u6R^@x!K2cMdFfR z2~N30t=8KdCTv2Q0g^ls``_D1Ox_fA&e;3bm4(&+{M|lS-_&4@6M1rQ(G5P{$RI{> z$8DdaKUFPG-LvJxSI&p265nQt960^i#y~~ryYPfQ?sMn=@09S?JSEif^7iK+=U<=x z{P_2iQnQ`)Gkgvvrw6SyzHYEm@Kx%?2={|CQ_}Y;N2qAC=bV>&EX8|k<}0=0%_{{? z<w$EWykfeRV$iiwIz%GhvHrk}V><+djFT&S!ke2NDkOH4$xIKK^trcjVR&??D$~og zf7Yq(*NM^F(;s`{Y^YA?<%zcSJN7oO?*9370W*((<MnohRV(f!CVkivfAyi>#Y-En z&V6jWv~YFe)y_ln3%^fG3cVX5xtBTLT-)x?s<RK5=>~qD)opX|bJWj&4WIX3`Qx^7 z=htAb>MKr}`%ff=#JFDFoNym0Rs%x9lJs}p=Hy^t_$|S}pbU-Gv=T!j6N?JN_>%ni z#EQ)L;*z4&#N5pM_%g$I1HH1X5xK>;&4m8N{O$6!zU)=JN%@rDnp@L7L-)s+<UW!< zJ@?nS#}6G;G8Qi5kmZaFtNQzX`)&r$fK9^c-(GgJBy8M$qxRcDC;j+5+vm%_eo~z? zhyCweMwV#d)NM(LEE2rTQU^aIZ80_5DPk-!chVbye;2fjH(dG2>r!PF?7FZ-E%}0^ z&y$cPoG)08{Sv4XoxF&<TW6Xj&u2*<Wx>-kyFR$9bTb8so?J8G_KImH@~_T3$=YOK zrGMwj#2ulAbC#^uX)fEd_m1C-=l-o`R=342etWbmICtLqqEcJa3wCcD_FsRW|F%S1 zf5F}uz3tqxOD%3(`)QgR-G5}V-P-hUkB#$0)Wjz?{&nkW2wpNdMSIpN%LKEOc^w{3 z(dWcg8VD`@ZT+`g;B++4$Nvx47+n6SG<AZ+r&oF$y?jUKa&fzLU3!=+@a@5Fu`SU7 zbsuc@iyG;3L@V_r>J=GIZcAHcG<_|vXS`Ed;Y9(9OA|7k>sF+&rfJo_?2LJ-b1c$T z;dDTG@_YMiPnTC8{2HBqobP6G3pM$?yCUHI>MO;2)_?qMpwju_Pez3uPrbbC-2KWs z%?)1EO||?SS*%jnzf-KFK;AVf^>Zs@#HtvkXKFo{W(Snk#vg0n|F5V&Au#22)8h}! zT(4RcPkITgj&0vH$>rep#fG1mUR~jx%fYPD7O>HTdtRUW@&?s7i9;)bWdpCiE;*~2 zUtfN<x60Fg&zFtfcAQI=y<YQ>hi%Q<&e8|EEcQNjNv)Mt`~~{IcBabC?cVW4NNDcv z<_UG@kCiv(w|#mPZF_)0;F;j26H}Frp7J@`C2`q}*PCf(L8H5eYvP0Gq`*~Q@;#4C z`}gyxpu!w(!`aI{wh4ExJ8|pu41?<)s}H=nu336>QaOiaQNp~{Gf#vIEVbHo^Tw>x zPP5M3ew+W)HA7i{Wpqh|K4+aScj?^OTu-O*Tnp$s9?>p($jW59Qs~DtH~sGh#(TB3 zowt~8Fybw*6wE!U?Q}ZX*7EijmGz>z5t_D%lCL?PH$UXmzqMGSXi2fdcc)HYpA(L! zrCTDnw07s6Q&sY<+%)UxBbyIf0@hBGp1t|&wU7JlWcFEG|26pa{bOWB&6obihB}9m zrn)ZN+LZJ0?6!%mj{l}C%u43`Vih|l`B;W<NyUkke8#gjO?VL5IIG~4<(i7VWhJxg z&y^}Z&h9*X%&=0|Su1;u<$UY4`5IyKzexB0h^aHaUs-p1rRn>`v&jX1buV*INzW4h zVRM{M&B;#E`0yU_iiwX+zaE_xy>n07>AST@RAn2d2wrvA@O(%2kFHr(d;F$)=q}Ov z$>V*i%P{)p{QBl_iI6`mH6eRe<-4{$O$t}ud*B|w=gDUx8YUsBX0vrC>K$FxF#ncb zmyc6}-42auXPkN#3T5p7aO|5>l6HN)vmeVB%Y>|nnTnOo-Xe1+CM52B@$hVRw5`FU zwvgABx`~%lM85B>nP^(N(NkI_?2hu$lH3pZJ(KrZt%{g*c3Imqt(hEg?+>$_JfSlo zpqM9<CwKOW)8XM));abYm;d;e(e7sbbcO%o@TVFJF1{|hviPE0|Dwn@FPHsfJYRgj zBP`;}@na&dxz^k)>RZd|nB4c5^H=ZA*m;}%rWLQR$lGrCeb)0ezn|WbV^<L>cHVwp zE}UJiP2t&!g@+{KLodu*IivXM#s~L{6OI`R%O4Um_`j=LXvSGbl`EcaXRZvrwrz8| zILq13+^^5nXbEVZRO)^syY|eg&m|7QS^~_>(ZSo+$aOzI|Ng6l$i8-Q)mM7u>+Wn| zlJnar+LLV<+NsDZl5Y2P*Y^5b^QW&j+;(@#yX1eL@>FB^bC*ayRM}VlG&Xfd&vr$< zYpc(xUwgx^m7ghaVZoit(U&v!MI~D*^s-D|#XEK8j0@gu#aaEG{JuU;TFN=AW_;Zc zP<YX3#jlRZJmR+;3?7+pIPu8u>5A^KldDRu9;naV6%+6$<n5&Ls~nq4F5Jq9wqK-m zD==%DyGHl2D?JBaTA1JEE<6}gn=d<&X_YAt$2NnFT`aQYn+|mpgzbH_XxXw8{PQBX z!@Pyh?=7{l58&><b$bmfzrp?MGJWClPRyNq{GZ%?8L;|=(y`EuX}zx&RJHA>?C~u4 zD!$p~XhDTx)5o7TKYp<F5oA3Ya_7V^SHJ(s0ta`niR`Y+nfXyRgZubamL4TP3A=Bb zl_pvmn*~2K3je}%Fip(bXVH4=DF>e)niDQQgT1D~qV#{{1M#=duJCG<K06mxm-WfZ zR%D9&YY~&;0Ipa*j!SjH=PZwkw;#KFVX|}A9xl$gw}0)QbBgC~*ONK(jQ2%e>X^3j z_U~D1_E!eqy*=k+2sfYf{;fLFT{g$h+}JOXwOYifiBXDgS5BQQYwFrx`4T!|=RdBR z^H;q`-^sMCOOA8dW-cGIpjPItqy6g?Sfm=mlysbOXZp<N4f|<)aMhL1o)LRBmg=ng zqb~NCEA>f^-wq+wnmNx)*JxPrc4zPWDqk9Nd+OI^h3ppB|AbX+p7W34!G)tM{gMwH zi(EQEqsl4z!o#zTx?H8w+50Lp${&1;UsfVnvFXl-&y$QDKP>yt+~Izc?{Ddbo11QD zFIZN2Nd2Ns_GX5Mag&Y&+`Vj+JGH*;pnSrA_qThev**N_Syi0!Nx!?^?Z^FV%6(`5 zJ@>ia-=V*|JS(1K%HDOd;Xcisg->gYtSoh{g`L_xxX+p05Bu_8hE0DV+p+^!=10V> zt)6xETa!SjT0_?>-8~;>mfx=o`|9`ohUIRHe@kSimG!T@)FJ=jFZ(8!=hGr{{^#ZW z<wvw6KvM?)wM6nO85tNZu`)2IF)%Pxq?cyu<8MloB<GwBa`ZoBAYr>X{v)f!3&%ZD z`P|BlDGC=m*^_7Os+*#=IChuck<|Zp`9un4_Z*o}5qW9f_kHj8UN1dxc;|#e9IBZt z8^aVOSiOq1j<O%}GU!ul+<8eL*mrtHfVyqEvrb9Nawa1QU-!xF3`Hko7zA&hz8!r^ z;%3Hz->mVT)(p35xAshR$vkmn-tE50*0&oo&#Z7XDt&*~aOTc`j~855|26mSgagIQ z(`|b9BxGzi72pzI%jfgfBW0x<N2Z9Pc2lmoLvO}b2hNanj%N?*2uK{$m}y!$;kMen zgpkiAnG0DCu}+mKXS|o8a!&SPwYx9J@}(D-+?sXe<-L&H)ywv5%vtGVk(7Bo%eCZO znD*&^LJt>Q-L&S?tNy6t<@XNcSDfYXOEf*;enveb!R$-T1C7A$4^?UVCqDW;sk=rq zPG$NBFJbK<p{9ND$L3C(>yooeVryjn`v)__-|xCvxcO)I(m4|>_5Uw1o%N~s%J#@a z(*yr^p51iw{;f41y3Fhu5s|08SSU2$%OY2MW(EdVIR*w!1_p+t6#b+Wy^`ddw-K@a zw+%#U*VP}5y}sNtb=DSj6*-C2=%tS8$Bw9kxT+OqxV%c~>vquiFIzvMf0w66#+}Td z^UO-yxAwpPcy_P5t6_HxN5+ANoH0UehR?V=el%^+{HpBXT2ZZFoFJMpL15jaLa`ZD zijA+M56zW6KXD_ATjadr;?(pEEu9&8VV)13yD&c8C(ORZ<=e-@H3kOPw;$p@>HI(? z=1KF+=SOBdTq?}Q*`EEi+^TThvdO347u0<Hef_2Dw}QYbjrxGTdd+|Hv$g6~g}g%C zQuzer_ZznAIWXHNvFzr)FsqNN^7o3PMlN<)*I&16Zn($vbN3;|p3EnYo-EBe@>@{& znEb;WGt1VAR>x)9JUiZ>EZ}o@|L}6_beC0XsaKn3g>SDF)LJt+V2{c9`nsBF^XnB7 z-vw~)Tsuv}ha>G#(6J|syKTfXw*>0Ua+Y`GGzsHcTbwraiQ5$R64y`szgkp0&nDcT zpb~kosC4I|r0jcFj~Qh)sYte1^l^SQd!147sAnG6)!>gy{3r39?akU?yfkmm;lrwF z<*W2Q>OMQtnek)A?UZZl;<Z+s*x<Xh>+WT-_}gqJ_PI$0bO{7)woF?hz&)>O{>9%n z|J*;5Hu;X!EVqLF%U>8Z`lmgQUw)sjF7Aw8y834MqXu^WjQ{GSecXL3QpdXgs;9D| z^aRPxje3*T&Yq^~XOY<J_4LNfl-#P{(TzIqV%c6j+k58edZyA168SgcobGMU3<_1_ zeYPl9t0>?2n)N1@cZC`{ty1chtJmkLR4V<H{-mYl@#>pdtIu^CKjG`=o@8YxFZPl= zebFq|Wm3kpPhL9<EOO#*igh{0c^>6`vOW6QweZ}$VD_zhuddURT=Ui8Zv5Gd^*`L_ z-Iymo?MC&Zz3OHcpLCvmpT~LS#w_jUXYYw@pT6eT^gUGzx!(8~MKe1lEr0JL9-p%= zkM+t)sq*J1Waei+uljg2?SR%MAFa8uslhj;pZuD3X|ZFS{9WN=O#K@1i(R^EE(Fgs zkl%e|p;M6D$r(W<HfuUt_R@K@WC!QycL1HF#w<%d^W^hv1C+tW4m$DzhYw+tR1 zy}7;oY1hJIJ>hrCo@!pJ<5+j&-Yb)dJYk$FCH3Zu_a+@*_D3?nn~_O`8TY&@0|NsC zBLf4&l12~<WtJ6LE4KbONCQNxFdy#TIEpD)`g;gdUh+ds!Cz#TAsdLT*hd&>EJ17~ jfNUnV(g<PZ2T7!|DZrbR4J5_Nz{(KI$iNUL3*rF)8ac1A literal 0 HcmV?d00001 diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl new file mode 100644 index 0000000..f4b8c38 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl @@ -0,0 +1,35 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + +} + +proc update_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to update C_rxd8_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to validate C_rxd8_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to update C_txd8_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to validate C_txd8_TDATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH { MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_rxd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_txd8_TDATA_WIDTH { MODELPARAM_VALUE.C_txd8_TDATA_WIDTH PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_txd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_txd8_TDATA_WIDTH} +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl index a1a6c43..59baedb 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl @@ -118,9 +118,10 @@ ipx::check_integrity [ipx::current_core] ipx::save_core [ipx::current_core] ipx::check_integrity -quiet -xrt [ipx::current_core] -ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::current_core] +ipx::archive_core $mculib_ip/soclabs.org_user_nanosoc_chip_1.0.zip [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] -close_project -delete +#close_project -delete +close_project set_property ip_repo_paths { ip_repo $mculib_ip} [current_project] update_ip_catalog diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl index 87ae9c2..ac91278 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl @@ -110,6 +110,6 @@ exec mkdir -p $pynqDir exec cp -p $project/export/design_1.bit $pynqDir exec cp -p $project/export/design_1.hwh $pynqDir -exec rm -Rf vivado/ +#exec rm -Rf vivado/ exit 1 diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl index 356404e..e7552e8 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl @@ -1,4 +1,5 @@ ### DMA PL230 rtl source build +set search_path [ concat $search_path ../verilog ] read_verilog ../verilog/pl230_defs.v read_verilog $dma230_vlog/pl230_ahb_ctrl.v read_verilog $dma230_vlog/pl230_apb_regs.v diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl index 4859c7b..1c371ce 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl @@ -46,8 +46,15 @@ if { $bCheckIPs == 1 } { set list_check_ips "\ soclabs.org:user:nanosoc_chip:1.0\ xilinx.com:ip:zynq_ultra_ps_e:3.3\ +soclabs.org:user:ADPcontrol:1.0\ +xilinx.com:ip:ahblite_axi_bridge:3.0\ +xilinx.com:ip:axi_bram_ctrl:4.1\ xilinx.com:ip:axi_gpio:2.0\ +soclabs.org:user:axi_stream_io:1.0\ xilinx.com:ip:axi_uartlite:2.0\ +xilinx.com:ip:axis_data_fifo:2.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +soclabs.org:user:ft1248x1_to_axi_streamio:1.0\ xilinx.com:ip:xlslice:1.0\ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:proc_sys_reset:5.0\ @@ -123,10 +130,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { # Create pins create_bd_pin -dir I -type clk aclk create_bd_pin -dir I -type rst ext_reset_in - create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o - create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z - create_bd_pin -dir O -from 15 -to 0 gpio_tri_i - create_bd_pin -dir I -from 15 -to 0 gpio_tri_o create_bd_pin -dir O -from 0 -to 0 -type rst nrst create_bd_pin -dir O -from 15 -to 0 p0_tri_i create_bd_pin -dir I -from 15 -to 0 p0_tri_o @@ -137,6 +140,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z + create_bd_pin -dir O -from 0 -to 0 swdclk_i + create_bd_pin -dir O -from 0 -to 0 swdio_tri_i + create_bd_pin -dir I swdio_tri_o + create_bd_pin -dir I swdio_tri_z + + # Create instance: ADPcontrol_0, and set properties + set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ] + + # Create instance: ahblite_axi_bridge_0, and set properties + set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.ECC_TYPE {0} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] @@ -154,16 +175,78 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.C_IS_DUAL {1} \ ] $axi_gpio_1 - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] - set_property -dict [ list \ - CONFIG.C_GPIO2_WIDTH {16} \ - CONFIG.C_GPIO_WIDTH {16} \ - CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 + # Create instance: axi_stream_io_0, and set properties + set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ] + + # Create instance: axi_stream_io_1, and set properties + set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ] + + # Create instance: axi_stream_io_2, and set properties + set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ] + + # Create instance: axi_stream_io_3, and set properties + set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ] # Create instance: axi_uartlite_0, and set properties set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \ + ] $axi_uartlite_0 + + # Create instance: axi_uartlite_1, and set properties + set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \ + ] $axi_uartlite_1 + + # Create instance: axis_data_fifo_0, and set properties + set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_0 + + # Create instance: axis_data_fifo_1, and set properties + set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_1 + + # Create instance: axis_data_fifo_2, and set properties + set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_2 + + # Create instance: axis_data_fifo_3, and set properties + set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_3 + + # Create instance: axis_data_fifo_4, and set properties + set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_4 + + # Create instance: blk_mem_gen_0, and set properties + set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ] + set_property -dict [ list \ + CONFIG.Byte_Size {8} \ + CONFIG.EN_SAFETY_CKT {true} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Read_Width_A {32} \ + CONFIG.Read_Width_B {32} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Write_Width_A {32} \ + CONFIG.Write_Width_B {32} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $blk_mem_gen_0 + + # Create instance: ft1248x1_to_axi_stream_0, and set properties + set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ] # Create instance: p1_i_bit15to6, and set properties set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ] @@ -184,6 +267,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.IN4_WIDTH {1} \ CONFIG.IN5_WIDTH {1} \ CONFIG.IN6_WIDTH {10} \ + CONFIG.IN7_WIDTH {1} \ + CONFIG.IN8_WIDTH {8} \ CONFIG.NUM_PORTS {7} \ ] $p1_i_concat @@ -259,6 +344,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.DOUT_WIDTH {1} \ ] $pmoda_i_bit3 + # Create instance: pmoda_i_bit4, and set properties + set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + CONFIG.DOUT_WIDTH {1} \ + ] $pmoda_i_bit4 + + # Create instance: pmoda_i_bit7, and set properties + set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + CONFIG.DOUT_WIDTH {1} \ + ] $pmoda_i_bit7 + # Create instance: pmoda_o_concat8, and set properties set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ] set_property -dict [ list \ @@ -277,7 +380,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { # Create instance: smartconnect_0, and set properties set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ - CONFIG.NUM_MI {4} \ + CONFIG.NUM_MI {8} \ CONFIG.NUM_SI {1} \ ] $smartconnect_0 @@ -291,41 +394,70 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] # Create interface connections + connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE] + connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS] + connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS] + connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8] + connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx] + connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] + connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS] + connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] # Create port connections + connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8] connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout] + connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out] + connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra] + connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka] + connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena] + connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea] + connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina] connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o] connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din] - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o] connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4] - connect_bd_net -net nanosoc_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i] - connect_bd_net -net nanosoc_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i] - connect_bd_net -net nanosoc_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din] - connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i] - connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i] - connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0] + connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx] + connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta] + connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i] + connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i] + connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din] + connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2] + connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0] + connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0] connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3] connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3] - connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1] + connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1] connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout] connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6] connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din] - connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] - connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout] - connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout] + connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din] + connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout] + connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout] + connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout] connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4] + connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4] connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in] # Restore current instance @@ -371,12 +503,12 @@ proc create_root_design { parentCell } { set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ] set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ] - # Create instance: nanosoc_chip_0, and set properties - set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ] - # Create instance: cmsdk_socket create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket + # Create instance: nanosoc_chip_0, and set properties + set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ] + # Create instance: zynq_ultra_ps_e_0, and set properties set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] set_property -dict [ list \ @@ -964,28 +1096,33 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] # Create port connections - connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o] - connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z] - connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o] - connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i] - connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst] - connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i] - connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i] - connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o] - connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z] - connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o] - connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z] + connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i] + connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i] + connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i] + connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i] + connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i] + connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o] + connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z] + connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o] + connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z] connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i] connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z] + connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o] + connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z] connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] # Create address segments assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force - assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force - assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force + assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force + assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force + assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force + assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force # Restore current instance -- GitLab