diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl new file mode 100755 index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml new file mode 100755 index 0000000000000000000000000000000000000000..ae447c2beab6758f44b93cb19ab244bd7312b197 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml @@ -0,0 +1,1348 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>soclabs.org</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>ADPcontrol</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> 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a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v new file mode 100755 index 0000000000000000000000000000000000000000..7b8967c18e34a77bb98084ede844e99853f3e47c --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v @@ -0,0 +1,103 @@ +//----------------------------------------------------------------------------- +// top-level soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + + module ADPcontrol_v1_0 # + ( + // Users to add parameters here + parameter PROMPT_CHAR = "]" + + // User parameters ends + // Do not modify the parameters beyond this line + + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Ports of Axi Slave Bus Interface com_rx + input wire ahb_hclk, + input wire ahb_hresetn, + + output wire com_rx_tready, + input wire [7 : 0] com_rx_tdata, + input wire com_rx_tvalid, + + // Ports of Axi Master Bus Interface com_tx + output wire com_tx_tvalid, + output wire [7 : 0] com_tx_tdata, + input wire com_tx_tready, + + // Ports of Axi Slave Bus Interface stdio_rx + output wire stdio_rx_tready, + input wire [7 : 0] stdio_rx_tdata, + input wire stdio_rx_tvalid, + + // Ports of Axi Master Bus Interface stdio_tx + output wire stdio_tx_tvalid, + output wire [7 : 0] stdio_tx_tdata, + input wire stdio_tx_tready, + + output wire [7 : 0] gpo8, + input wire [7 : 0] gpi8, + + output wire [31:0] ahb_haddr , + output wire [ 2:0] ahb_hburst , + output wire ahb_hmastlock, + output wire [ 3:0] ahb_hprot , + output wire [ 2:0] ahb_hsize , + output wire [ 1:0] ahb_htrans , + output wire [31:0] ahb_hwdata , + output wire ahb_hwrite , + input wire [31:0] ahb_hrdata , + input wire ahb_hready , + input wire ahb_hresp + ); + + // Add user logic here + +ADPmanager + #(.PROMPT_CHAR (PROMPT_CHAR)) + ADPmanager( + .HCLK (ahb_hclk ), + .HRESETn (ahb_hresetn ), + .HADDR32_o (ahb_haddr ), + .HBURST3_o (ahb_hburst ), + .HMASTLOCK_o (ahb_hmastlock ), + .HPROT4_o (ahb_hprot ), + .HSIZE3_o (ahb_hsize ), + .HTRANS2_o (ahb_htrans ), + .HWDATA32_o (ahb_hwdata ), + .HWRITE_o (ahb_hwrite ), + .HRDATA32_i (ahb_hrdata ), + .HREADY_i (ahb_hready ), + .HRESP_i (ahb_hresp ), + .GPO8_o (gpo8 ), + .GPI8_i (gpi8 ), + .COMRX_TREADY_o(com_rx_tready), + .COMRX_TDATA_i(com_rx_tdata), + .COMRX_TVALID_i(com_rx_tvalid), + .STDRX_TREADY_o(stdio_rx_tready), + .STDRX_TDATA_i(stdio_rx_tdata), + .STDRX_TVALID_i(stdio_rx_tvalid), + .COMTX_TVALID_o(com_tx_tvalid), + .COMTX_TDATA_o(com_tx_tdata), + .COMTX_TREADY_i(com_tx_tready), + .STDTX_TVALID_o(stdio_tx_tvalid), + .STDTX_TDATA_o(stdio_tx_tdata), + .STDTX_TREADY_i(stdio_tx_tready) + + ); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v new file mode 100755 index 0000000000000000000000000000000000000000..0e980d36757f551bd13414b0bf8f135a4e6bcafc --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_com_rx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v new file mode 100755 index 0000000000000000000000000000000000000000..ba5f03594fc0075bdc58c0535948374580237a28 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_com_tx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v new file mode 100755 index 0000000000000000000000000000000000000000..30f30e3895ada561f258535ea88f9b012142f738 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_stdio_rx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v new file mode 100755 index 0000000000000000000000000000000000000000..8f4af08975c515e65431d6d12dfe5484ac0cac69 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ADPcontrol_v1_0_stdio_tx # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v new file mode 100755 index 0000000000000000000000000000000000000000..f4747ae3006625177bd065d731cdf0604d7334e9 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPmanager.v @@ -0,0 +1,786 @@ +//----------------------------------------------------------------------------- +// soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + +//`define ADPBASIC 1 + +module ADPmanager // AHB initiator interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] HADDR32_o, + output wire [ 2:0] HBURST3_o, + output wire HMASTLOCK_o, + output wire [ 3:0] HPROT4_o, + output wire [ 2:0] HSIZE3_o, + output wire [ 1:0] HTRANS2_o, + output wire [31:0] HWDATA32_o, + output wire HWRITE_o, + input wire [31:0] HRDATA32_i, + input wire HREADY_i, + input wire HRESP_i, +// COMIO interface + output wire [ 7:0] GPO8_o, + input wire [ 7:0] GPI8_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam BANNERHEX = 32'h50c1ab01; +`else + localparam BANNERHEX = 32'h50c1ab02; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function FNuppercase; +input [7:0] char8; + FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping +`ifdef ADPFSMDESIGN +localparam ADP_WRITEHEX = 6'b000000 ; +localparam ADP_WRITEHEXS = 6'b000001 ; +localparam ADP_WRITEHEX9 = 6'b000010 ; +localparam ADP_WRITEHEX8 = 6'b000011 ; +localparam ADP_WRITEHEX7 = 6'b000100 ; +localparam ADP_WRITEHEX6 = 6'b000101 ; +localparam ADP_WRITEHEX5 = 6'b000110 ; +localparam ADP_WRITEHEX4 = 6'b000111 ; +localparam ADP_WRITEHEX3 = 6'b001000 ; +localparam ADP_WRITEHEX2 = 6'b001001 ; +localparam ADP_WRITEHEX1 = 6'b001010 ; +localparam ADP_WRITEHEX0 = 6'b001011 ; +localparam ADP_LINEACK = 6'b001101 ; +localparam ADP_LINEACK2 = 6'b110010 ; +localparam ADP_PROMPT = 6'b001110 ; +localparam ADP_IOCHK = 6'b001111 ; +localparam ADP_RXCMD = 6'b010000 ; +localparam ADP_RXPARAM = 6'b010010 ; +localparam ADP_ACTION = 6'b010011 ; +localparam ADP_READ = 6'b010001 ; +localparam ADP_SYSCHK = 6'b010100 ; +localparam ADP_STDIN = 6'b010101 ; +localparam ADP_SYSCTL = 6'b010110 ; +localparam ADP_WRITE = 6'b010111 ; +localparam ADP_EXIT = 6'b011000 ; +localparam STD_IOCHK = 6'b011001 ; +localparam STD_RXD1 = 6'b011010 ; +localparam STD_RXD2 = 6'b011011 ; +localparam STD_TXD1 = 6'b011101 ; +localparam STD_TXD2 = 6'b011110 ; +localparam ADP_BCTRL = 6'b011111 ; +localparam ADP_BREADB0 = 6'b100000 ; +localparam ADP_BREADB1 = 6'b100001 ; +localparam ADP_BREADB2 = 6'b100010 ; +localparam ADP_BREADB3 = 6'b100011 ; +localparam ADP_BWRITE = 6'b100100 ; +localparam ADP_POLL = 6'b100101 ; +localparam ADP_POLL1 = 6'b100110 ; +localparam ADP_POLL2 = 6'b100111 ; +localparam ADP_ZCTRL = 6'b101110 ; +localparam ADP_ZWRITE = 6'b101111 ; +localparam ADP_ECHOCMD = 6'b110000 ; +localparam ADP_ECHOCMDSP = 6'b110001 ; +localparam ADP_UNKNOWN = 6'b101000 ; +localparam ADP_STDOUT = 6'b101010 ; +localparam ADP_STDOUT1 = 6'b101011 ; +localparam ADP_STDOUT2 = 6'b101100 ; +localparam ADP_STDOUT3 = 6'b101101 ; +reg [5:0] adp_state ; +`else +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000 +localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001 +localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010 +localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011 +localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100 +localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101 +localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110 +localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111 +localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000 +localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001 +localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010 +localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011 +localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001101 +localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b110010 +localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110 +localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111 +localparam ADP_RXCMD = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000 +localparam ADP_RXPARAM = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010010 +localparam ADP_ACTION = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010011 +localparam ADP_READ = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010001 +localparam ADP_SYSCHK = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100 +localparam ADP_STDIN = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101 +localparam ADP_SYSCTL = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110 +localparam ADP_WRITE = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111 +localparam ADP_EXIT = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000 +localparam STD_IOCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001 +localparam STD_RXD1 = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010 +localparam STD_RXD2 = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011 +localparam STD_TXD1 = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011101 +localparam STD_TXD2 = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011110 +localparam ADP_BCTRL = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011111 +localparam ADP_BREADB0 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b100000 +localparam ADP_BREADB1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100001 +localparam ADP_BREADB2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100010 +localparam ADP_BREADB3 = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100011 +localparam ADP_BWRITE = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100100 +localparam ADP_POLL = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100101 +localparam ADP_POLL1 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100110 +localparam ADP_POLL2 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100111 +localparam ADP_ZCTRL = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b101110 +localparam ADP_ZWRITE = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101111 +localparam ADP_ECHOCMD = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b110000 +localparam ADP_ECHOCMDSP = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b110001 +localparam ADP_UNKNOWN = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101000 +localparam ADP_STDOUT = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101010 +localparam ADP_STDOUT1 = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101011 +localparam ADP_STDOUT2 = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101100 +localparam ADP_STDOUT3 = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101101 +reg [47:0] adp_state ; +`endif + +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + +assign GPO8_o = adp_sys[7:0]; + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign HADDR32_o = adp_addr; +assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign HMASTLOCK_o = 1'b0; +assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign HWDATA32_o = adp_bus_data; +assign HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +reg [31:0] adp_count; +reg adp_count_dec ; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) +// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_down_zero_next; // param about to be zero +input [31:0] counter; + FNcount_down_zero_next = !(|counter[31:1]); +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= BANNERHEX; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; +`ifndef ADPBASIC + adp_count <= 0; + adp_count_dec<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; +`endif + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; +`ifndef ADPBASIC + adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param-- + adp_count_dec<= 0; +`endif + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) + begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) + begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) + begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end + else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end +// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param + else begin adp_cmd <= com_rx_byte; adp_param <= 32'hffffffff; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) +`ifndef ADPBASIC + begin adp_count <= adp_param; adp_state <= ADP_ACTION; end // parameter complete on EOL +`else + begin adp_state <= ADP_ACTION; end // parameter complete on EOL +`endif + else + begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter + if (FNexit(com_rx_byte)) + adp_state <= STD_IOCHK; + else if (FNvalid_cmd(adp_cmd) == CMD_A) + begin if (adp_param == 32'hffffffff) adp_param <= adp_addr; else adp_addr <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin + if (adp_param[31:8] == 0) // report GPO + begin adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 1) // clear bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 2) // set bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 3) // overwrite bits in GPO + begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else // 4 etc, report GPO + begin adp_state <= ADP_SYSCTL; end + end + else if (FNvalid_cmd(adp_cmd) == CMD_R) + begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else if (FNvalid_cmd(adp_cmd) == CMD_S) + begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) + begin adp_bus_data <= adp_param; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) + begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_B) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_BCTRL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_M) + begin if (adp_param == 32'hffffffff) adp_param <= adp_mask; else adp_mask <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_P) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_V) + begin if (adp_param == 32'hffffffff) adp_param <= adp_val; else adp_val <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_Z) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_ZCTRL; // non-zero count +`endif + else + begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; end + else begin ADP_BUSWRITEINC_next(); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; ADP_txchar_next("R"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_count_dec <=1; end + ADP_POLL2: + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_ZCTRL; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + if (com_tx_done) adp_state <= STD_IOCHK; + else com_tx_req <= 1; // extend stream request if not ready + + ADP_SYSCHK: // check STDIN fifo + begin // no upper flags so STDIN char + if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end + ADP_STDIN: // push char into STDIN + if (std_tx_done) begin adp_bus_data <= adp_param[7:0]; ADP_txchar_next("S"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else std_tx_req <= 1; // extend + + ADP_SYSCTL: // read current status - and report in hex + begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + + ADP_ECHOCMD: // output command and (param) data + begin adp_state <= ADP_ECHOCMDSP; ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param; end // output command char + ADP_ECHOCMDSP: // output command space and (bus) data + if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space char + else com_tx_req <= 1; // extend + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output "0" hex prefix + + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end else com_tx_req <= 1; // extend + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end + end else com_tx_req <= 1; // extend + ADP_LINEACK2: // CR + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default error + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .HADDR32_o (ahb_haddr ), +// .HBURST3_o (ahb_hburst ), +// .HMASTLOCK_o (ahb_hmastlock ), +// .HPROT4_o (ahb_hprot ), +// .HSIZE3_o (ahb_hsize ), +// .HTRANS2_o (ahb_htrans ), +// .HWDATA32_o (ahb_hwdata ), +// .HWRITE_o (ahb_hwrite ), +// .HRDATA32_i (ahb_hrdata ), +// .HREADY_i (ahb_hready ), +// .HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip new file mode 100644 index 0000000000000000000000000000000000000000..5ae9d96e74bbcd831a65923ed1cbf388a7dc8b62 Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip differ diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v new file mode 100755 index 0000000000000000000000000000000000000000..7b8967c18e34a77bb98084ede844e99853f3e47c --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v @@ -0,0 +1,103 @@ +//----------------------------------------------------------------------------- +// top-level soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + + module ADPcontrol_v1_0 # + ( + // Users to add parameters here + parameter PROMPT_CHAR = "]" + + // User parameters ends + // Do not modify the parameters beyond this line + + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Ports of Axi Slave Bus Interface com_rx + input wire ahb_hclk, + input wire ahb_hresetn, + + output wire com_rx_tready, + input wire [7 : 0] com_rx_tdata, + input wire com_rx_tvalid, + + // Ports of Axi Master Bus Interface com_tx + output wire com_tx_tvalid, + output wire [7 : 0] com_tx_tdata, + input wire com_tx_tready, + + // Ports of Axi Slave Bus Interface stdio_rx + output wire stdio_rx_tready, + input wire [7 : 0] stdio_rx_tdata, + input wire stdio_rx_tvalid, + + // Ports of Axi Master Bus Interface stdio_tx + output wire stdio_tx_tvalid, + output wire [7 : 0] stdio_tx_tdata, + input wire stdio_tx_tready, + + output wire [7 : 0] gpo8, + input wire [7 : 0] gpi8, + + output wire [31:0] ahb_haddr , + output wire [ 2:0] ahb_hburst , + output wire ahb_hmastlock, + output wire [ 3:0] ahb_hprot , + output wire [ 2:0] ahb_hsize , + output wire [ 1:0] ahb_htrans , + output wire [31:0] ahb_hwdata , + output wire ahb_hwrite , + input wire [31:0] ahb_hrdata , + input wire ahb_hready , + input wire ahb_hresp + ); + + // Add user logic here + +ADPmanager + #(.PROMPT_CHAR (PROMPT_CHAR)) + ADPmanager( + .HCLK (ahb_hclk ), + .HRESETn (ahb_hresetn ), + .HADDR32_o (ahb_haddr ), + .HBURST3_o (ahb_hburst ), + .HMASTLOCK_o (ahb_hmastlock ), + .HPROT4_o (ahb_hprot ), + .HSIZE3_o (ahb_hsize ), + .HTRANS2_o (ahb_htrans ), + .HWDATA32_o (ahb_hwdata ), + .HWRITE_o (ahb_hwrite ), + .HRDATA32_i (ahb_hrdata ), + .HREADY_i (ahb_hready ), + .HRESP_i (ahb_hresp ), + .GPO8_o (gpo8 ), + .GPI8_i (gpi8 ), + .COMRX_TREADY_o(com_rx_tready), + .COMRX_TDATA_i(com_rx_tdata), + .COMRX_TVALID_i(com_rx_tvalid), + .STDRX_TREADY_o(stdio_rx_tready), + .STDRX_TDATA_i(stdio_rx_tdata), + .STDRX_TVALID_i(stdio_rx_tvalid), + .COMTX_TVALID_o(com_tx_tvalid), + .COMTX_TDATA_o(com_tx_tdata), + .COMTX_TREADY_i(com_tx_tready), + .STDTX_TVALID_o(stdio_tx_tvalid), + .STDTX_TDATA_o(stdio_tx_tdata), + .STDTX_TREADY_i(stdio_tx_tready) + + ); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v new file mode 100755 index 0000000000000000000000000000000000000000..f4747ae3006625177bd065d731cdf0604d7334e9 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v @@ -0,0 +1,786 @@ +//----------------------------------------------------------------------------- +// soclabs ASCII Debug Protocol controller +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright � 2021-2, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + + +//`define ADPBASIC 1 + +module ADPmanager // AHB initiator interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] HADDR32_o, + output wire [ 2:0] HBURST3_o, + output wire HMASTLOCK_o, + output wire [ 3:0] HPROT4_o, + output wire [ 2:0] HSIZE3_o, + output wire [ 1:0] HTRANS2_o, + output wire [31:0] HWDATA32_o, + output wire HWRITE_o, + input wire [31:0] HRDATA32_i, + input wire HREADY_i, + input wire HRESP_i, +// COMIO interface + output wire [ 7:0] GPO8_o, + input wire [ 7:0] GPI8_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam BANNERHEX = 32'h50c1ab01; +`else + localparam BANNERHEX = 32'h50c1ab02; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function FNuppercase; +input [7:0] char8; + FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping +`ifdef ADPFSMDESIGN +localparam ADP_WRITEHEX = 6'b000000 ; +localparam ADP_WRITEHEXS = 6'b000001 ; +localparam ADP_WRITEHEX9 = 6'b000010 ; +localparam ADP_WRITEHEX8 = 6'b000011 ; +localparam ADP_WRITEHEX7 = 6'b000100 ; +localparam ADP_WRITEHEX6 = 6'b000101 ; +localparam ADP_WRITEHEX5 = 6'b000110 ; +localparam ADP_WRITEHEX4 = 6'b000111 ; +localparam ADP_WRITEHEX3 = 6'b001000 ; +localparam ADP_WRITEHEX2 = 6'b001001 ; +localparam ADP_WRITEHEX1 = 6'b001010 ; +localparam ADP_WRITEHEX0 = 6'b001011 ; +localparam ADP_LINEACK = 6'b001101 ; +localparam ADP_LINEACK2 = 6'b110010 ; +localparam ADP_PROMPT = 6'b001110 ; +localparam ADP_IOCHK = 6'b001111 ; +localparam ADP_RXCMD = 6'b010000 ; +localparam ADP_RXPARAM = 6'b010010 ; +localparam ADP_ACTION = 6'b010011 ; +localparam ADP_READ = 6'b010001 ; +localparam ADP_SYSCHK = 6'b010100 ; +localparam ADP_STDIN = 6'b010101 ; +localparam ADP_SYSCTL = 6'b010110 ; +localparam ADP_WRITE = 6'b010111 ; +localparam ADP_EXIT = 6'b011000 ; +localparam STD_IOCHK = 6'b011001 ; +localparam STD_RXD1 = 6'b011010 ; +localparam STD_RXD2 = 6'b011011 ; +localparam STD_TXD1 = 6'b011101 ; +localparam STD_TXD2 = 6'b011110 ; +localparam ADP_BCTRL = 6'b011111 ; +localparam ADP_BREADB0 = 6'b100000 ; +localparam ADP_BREADB1 = 6'b100001 ; +localparam ADP_BREADB2 = 6'b100010 ; +localparam ADP_BREADB3 = 6'b100011 ; +localparam ADP_BWRITE = 6'b100100 ; +localparam ADP_POLL = 6'b100101 ; +localparam ADP_POLL1 = 6'b100110 ; +localparam ADP_POLL2 = 6'b100111 ; +localparam ADP_ZCTRL = 6'b101110 ; +localparam ADP_ZWRITE = 6'b101111 ; +localparam ADP_ECHOCMD = 6'b110000 ; +localparam ADP_ECHOCMDSP = 6'b110001 ; +localparam ADP_UNKNOWN = 6'b101000 ; +localparam ADP_STDOUT = 6'b101010 ; +localparam ADP_STDOUT1 = 6'b101011 ; +localparam ADP_STDOUT2 = 6'b101100 ; +localparam ADP_STDOUT3 = 6'b101101 ; +reg [5:0] adp_state ; +`else +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000 +localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001 +localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010 +localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011 +localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100 +localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101 +localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110 +localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111 +localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000 +localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001 +localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010 +localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011 +localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001101 +localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b110010 +localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110 +localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111 +localparam ADP_RXCMD = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000 +localparam ADP_RXPARAM = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010010 +localparam ADP_ACTION = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010011 +localparam ADP_READ = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010001 +localparam ADP_SYSCHK = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100 +localparam ADP_STDIN = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101 +localparam ADP_SYSCTL = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110 +localparam ADP_WRITE = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111 +localparam ADP_EXIT = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000 +localparam STD_IOCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001 +localparam STD_RXD1 = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010 +localparam STD_RXD2 = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011 +localparam STD_TXD1 = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011101 +localparam STD_TXD2 = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011110 +localparam ADP_BCTRL = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011111 +localparam ADP_BREADB0 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b100000 +localparam ADP_BREADB1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100001 +localparam ADP_BREADB2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100010 +localparam ADP_BREADB3 = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100011 +localparam ADP_BWRITE = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100100 +localparam ADP_POLL = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100101 +localparam ADP_POLL1 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100110 +localparam ADP_POLL2 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100111 +localparam ADP_ZCTRL = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b101110 +localparam ADP_ZWRITE = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101111 +localparam ADP_ECHOCMD = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b110000 +localparam ADP_ECHOCMDSP = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b110001 +localparam ADP_UNKNOWN = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101000 +localparam ADP_STDOUT = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101010 +localparam ADP_STDOUT1 = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101011 +localparam ADP_STDOUT2 = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101100 +localparam ADP_STDOUT3 = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101101 +reg [47:0] adp_state ; +`endif + +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + +assign GPO8_o = adp_sys[7:0]; + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign HADDR32_o = adp_addr; +assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign HMASTLOCK_o = 1'b0; +assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign HWDATA32_o = adp_bus_data; +assign HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +reg [31:0] adp_count; +reg adp_count_dec ; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) +// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_down_zero_next; // param about to be zero +input [31:0] counter; + FNcount_down_zero_next = !(|counter[31:1]); +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= BANNERHEX; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; +`ifndef ADPBASIC + adp_count <= 0; + adp_count_dec<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; +`endif + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; +`ifndef ADPBASIC + adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param-- + adp_count_dec<= 0; +`endif + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) + begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) + begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) + begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end + else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end +// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param + else begin adp_cmd <= com_rx_byte; adp_param <= 32'hffffffff; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) +`ifndef ADPBASIC + begin adp_count <= adp_param; adp_state <= ADP_ACTION; end // parameter complete on EOL +`else + begin adp_state <= ADP_ACTION; end // parameter complete on EOL +`endif + else + begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter + if (FNexit(com_rx_byte)) + adp_state <= STD_IOCHK; + else if (FNvalid_cmd(adp_cmd) == CMD_A) + begin if (adp_param == 32'hffffffff) adp_param <= adp_addr; else adp_addr <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin + if (adp_param[31:8] == 0) // report GPO + begin adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 1) // clear bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 2) // set bits in GPO + begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else if (adp_param[31:8] == 3) // overwrite bits in GPO + begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end + else // 4 etc, report GPO + begin adp_state <= ADP_SYSCTL; end + end + else if (FNvalid_cmd(adp_cmd) == CMD_R) + begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else if (FNvalid_cmd(adp_cmd) == CMD_S) + begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) + begin adp_bus_data <= adp_param; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) + begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_B) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_BCTRL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_M) + begin if (adp_param == 32'hffffffff) adp_param <= adp_mask; else adp_mask <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_P) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_V) + begin if (adp_param == 32'hffffffff) adp_param <= adp_val; else adp_val <= adp_param; + adp_state <= ADP_ECHOCMD; end + else if (FNvalid_cmd(adp_cmd) == CMD_Z) + if (FNcount_down_zero_next(adp_param)) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_ZCTRL; // non-zero count +`endif + else + begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; end + else begin ADP_BUSWRITEINC_next(); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; ADP_txchar_next("R"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_count_dec <=1; end + ADP_POLL2: + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_ZCTRL; end + end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + if (com_tx_done) adp_state <= STD_IOCHK; + else com_tx_req <= 1; // extend stream request if not ready + + ADP_SYSCHK: // check STDIN fifo + begin // no upper flags so STDIN char + if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end + ADP_STDIN: // push char into STDIN + if (std_tx_done) begin adp_bus_data <= adp_param[7:0]; ADP_txchar_next("S"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + else std_tx_req <= 1; // extend + + ADP_SYSCTL: // read current status - and report in hex + begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); com_tx_req <= 1; adp_state <= ADP_ECHOCMDSP; end + + ADP_ECHOCMD: // output command and (param) data + begin adp_state <= ADP_ECHOCMDSP; ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param; end // output command char + ADP_ECHOCMDSP: // output command space and (bus) data + if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space char + else com_tx_req <= 1; // extend + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output "0" hex prefix + + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt + end else com_tx_req <= 1; // extend + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end + end else com_tx_req <= 1; // extend + ADP_LINEACK2: // CR + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default error + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .HADDR32_o (ahb_haddr ), +// .HBURST3_o (ahb_hburst ), +// .HMASTLOCK_o (ahb_hmastlock ), +// .HPROT4_o (ahb_hprot ), +// .HSIZE3_o (ahb_hsize ), +// .HTRANS2_o (ahb_htrans ), +// .HWDATA32_o (ahb_hwdata ), +// .HWRITE_o (ahb_hwrite ), +// .HRDATA32_i (ahb_hrdata ), +// .HREADY_i (ahb_hready ), +// .HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v new file mode 100755 index 0000000000000000000000000000000000000000..c2caf1521648331612a7936d021eaa20c62d91d3 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmaster.v @@ -0,0 +1,728 @@ +/* +* ASCII Debug COntroller +* A joint work commissioned on behalf of SoC Labs. +* +* Contributors +* +* David Flynn (d.w.flynn@soton.ac.uk) +* +* Copyright © 2021, SoC Labs (www.soclabs.org) +*/ + +//`define ADPBASIC 1 + +module ADPmaster // bus master interface + #(parameter PROMPT_CHAR = "]" + ) + ( input wire HCLK, + input wire HRESETn, + output wire [31:0] M_HADDR32_o, + output wire [ 2:0] M_HBURST3_o, + output wire M_HMASTLOCK_o, + output wire [ 3:0] M_HPROT4_o, + output wire [ 2:0] M_HSIZE3_o, + output wire [ 1:0] M_HTRANS2_o, + output wire [31:0] M_HWDATA32_o, + output wire M_HWRITE_o, + input wire [31:0] M_HRDATA32_i, + input wire M_HREADY_i, + input wire M_HRESP_i, +// input wire COM_RXE_i, + input wire [ 7:0] COMRX_TDATA_i, + input wire COMRX_TVALID_i, + output wire COMRX_TREADY_o, +// input wire COM_TXF_i, + output wire [ 7:0] COMTX_TDATA_o, + output wire COMTX_TVALID_o, + input wire COMTX_TREADY_i, +// STDIO interface +// input wire STDOUT_RXE_i, + input wire [ 7:0] STDRX_TDATA_i, + input wire STDRX_TVALID_i, + output wire STDRX_TREADY_o, +// input wire STDIN_TXF_i + output wire [ 7:0] STDTX_TDATA_o, + output wire STDTX_TVALID_o, + input wire STDTX_TREADY_i +); + +wire COM_RXE_i = !COMRX_TVALID_i; +wire COM_TXF_i = !COMTX_TREADY_i; + +//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o; +//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o; + + +wire STD_TXF_i = !STDTX_TREADY_i; +wire STD_RXE_i = !STDRX_TVALID_i; + +`ifdef ADPBASIC + localparam ADP_ID= 32'hADB0DF03; +`else + localparam ADP_ID= 32'hADC0DF03; +`endif + +localparam CMD_bad = 4'b0000; +localparam CMD_A = 4'b0001; // set address +`ifndef ADPBASIC +localparam CMD_B = 4'b1000; // Binary upload (wordocunt) from addr++ +localparam CMD_M = 4'b1010; // set read mask +localparam CMD_P = 4'b1011; // Poll hardware (count) +localparam CMD_V = 4'b1100; // match value +localparam CMD_Z = 4'b1101; // Zero-fill (wordocunt) from addr++ +`endif +localparam CMD_C = 4'b1001; // Control +localparam CMD_R = 4'b0010; // read word, addr++ +localparam CMD_S = 4'b0011; // Status/STDIN +localparam CMD_W = 4'b0100; // write word, addr++ +localparam CMD_X = 4'b0101; // exit + + +function FNvalid_adp_entry; // Escape char +input [7:0] char8; + FNvalid_adp_entry = (char8[7:0] == 8'h1b); +endfunction + +function [3:0] FNvalid_cmd; +input [7:0] char8; +case (char8[7:0]) +"A": FNvalid_cmd = CMD_A; +"a": FNvalid_cmd = CMD_A; +"R": FNvalid_cmd = CMD_R; +"r": FNvalid_cmd = CMD_R; +"S": FNvalid_cmd = CMD_S; +"s": FNvalid_cmd = CMD_S; +"W": FNvalid_cmd = CMD_W; +"w": FNvalid_cmd = CMD_W; +"X": FNvalid_cmd = CMD_X; +"x": FNvalid_cmd = CMD_X; +`ifndef ADPBASIC +"B": FNvalid_cmd = CMD_B; +"b": FNvalid_cmd = CMD_B; +"C": FNvalid_cmd = CMD_C; +"c": FNvalid_cmd = CMD_C; +"M": FNvalid_cmd = CMD_M; +"m": FNvalid_cmd = CMD_M; +"P": FNvalid_cmd = CMD_P; +"p": FNvalid_cmd = CMD_P; +"V": FNvalid_cmd = CMD_V; +"v": FNvalid_cmd = CMD_V; +"Z": FNvalid_cmd = CMD_Z; +"z": FNvalid_cmd = CMD_Z; +`endif +default: + FNvalid_cmd = 0; +endcase +endfunction + +function FNvalid_space; // space or tab char +input [7:0] char8; + FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09)); +endfunction + +function FNnull; // space or tab char +input [7:0] char8; + FNnull = (char8[7:0] == 8'h00); +endfunction + +function FNexit; // EOF +input [7:0] char8; + FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00)); +endfunction + +function FNvalid_EOL; // CR or LF +input [7:0] char8; + FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d)); +endfunction + +function [63:0] FNBuild_param64_hexdigit; +input [63:0] param64; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64 +" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64 +"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64 +"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000}; +"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001}; +"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010}; +"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011}; +"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100}; +"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101}; +"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110}; +"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111}; +"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000}; +"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001}; +"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010}; +"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011}; +"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100}; +"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101}; +"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110}; +"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111}; +default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged +endcase +endfunction + +function [63:0] FNBuild_param64_byte; +input [63:0] param64; +input [7:0] byte; + FNBuild_param64_byte = {byte[7:0], param64[63:08]}; +endfunction + +function [31:0] FNBuild_param32_hexdigit; +input [31:0] param32; +input [7:0] char8; +case (char8[7:0]) +"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32 +" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32 +"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32 +"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000}; +"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001}; +"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010}; +"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011}; +"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100}; +"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101}; +"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110}; +"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111}; +"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000}; +"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001}; +"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010}; +"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011}; +"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100}; +"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101}; +"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110}; +"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111}; +default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged +endcase +endfunction + +function [31:0] FNBuild_param32_byte; +input [31:0] param32; +input [7:0] byte; + FNBuild_param32_byte = {byte[7:0], param32[31:08]}; +endfunction + + + +function [7:0] FNmap_hex_digit; +input [3:0] nibble; +case (nibble[3:0]) +4'b0000: FNmap_hex_digit = "0"; +4'b0001: FNmap_hex_digit = "1"; +4'b0010: FNmap_hex_digit = "2"; +4'b0011: FNmap_hex_digit = "3"; +4'b0100: FNmap_hex_digit = "4"; +4'b0101: FNmap_hex_digit = "5"; +4'b0110: FNmap_hex_digit = "6"; +4'b0111: FNmap_hex_digit = "7"; +4'b1000: FNmap_hex_digit = "8"; +4'b1001: FNmap_hex_digit = "9"; +4'b1010: FNmap_hex_digit = "a"; +4'b1011: FNmap_hex_digit = "b"; +4'b1100: FNmap_hex_digit = "c"; +4'b1101: FNmap_hex_digit = "d"; +4'b1110: FNmap_hex_digit = "e"; +4'b1111: FNmap_hex_digit = "f"; +default: FNmap_hex_digit = "0"; +endcase +endfunction + + +// as per Vivado synthesis mapping + +//localparam ADP_WRITEHEX = 6'b000000 ; +//localparam ADP_WRITEHEXS = 6'b000001 ; +//localparam ADP_WRITEHEX9 = 6'b000010 ; +//localparam ADP_WRITEHEX8 = 6'b000011 ; +//localparam ADP_WRITEHEX7 = 6'b000100 ; +//localparam ADP_WRITEHEX6 = 6'b000101 ; +//localparam ADP_WRITEHEX5 = 6'b000110 ; +//localparam ADP_WRITEHEX4 = 6'b000111 ; +//localparam ADP_WRITEHEX3 = 6'b001000 ; +//localparam ADP_WRITEHEX2 = 6'b001001 ; +//localparam ADP_WRITEHEX1 = 6'b001010 ; +//localparam ADP_WRITEHEX0 = 6'b001011 ; +//localparam ADP_READEOL = 6'b001100 ; +//localparam ADP_LINEACK = 6'b001101 ; +//localparam ADP_PROMPT = 6'b001110 ; +//localparam ADP_IOCHK = 6'b001111 ; +//localparam ADP_RXCMD = 6'b010000 ; +//localparam ADP_READ = 6'b010001 ; +//localparam ADP_RXPARAM = 6'b010010 ; +//localparam ADP_ACTION = 6'b010011 ; +//localparam ADP_SYSCHK = 6'b010100 ; +//localparam ADP_STDIN = 6'b010101 ; +//localparam ADP_STAT = 6'b010110 ; +//localparam ADP_WRITE = 6'b010111 ; +//localparam ADP_EXIT = 6'b011000 ; +//localparam STD_IOCHK = 6'b011001 ; +//localparam STD_RXD1 = 6'b011010 ; +//localparam STD_RXD2 = 6'b011011 ; +//localparam STD_TXD1 = 6'b011101 ; +//localparam STD_TXD2 = 6'b011110 ; +//localparam ADP_BCTRL = 6'b011111 ; +//localparam ADP_BREADB0 = 6'b100000 ; +//localparam ADP_BREADB1 = 6'b100001 ; +//localparam ADP_BREADB2 = 6'b100010 ; +//localparam ADP_BREADB3 = 6'b100011 ; +//localparam ADP_BWRITE = 6'b100100 ; +//localparam ADP_POLL = 6'b100101 ; +//localparam ADP_POLL1 = 6'b100110 ; +//localparam ADP_POLL2 = 6'b100111 ; +//localparam ADP_UNKNOWN = 6'b101000 ; +//localparam ADP_STDOUT = 6'b101010 ; +//localparam ADP_STDOUT1 = 6'b101011 ; +//localparam ADP_STDOUT2 = 6'b101100 ; +//localparam ADP_STDOUT3 = 6'b101101 ; +//localparam ADP_ZCTRL = 6'b101110 ; +//localparam ADP_ZWRITE = 6'b101111 ; +// one-hot encoded explicitly +localparam ADP_WRITEHEX = 46'b0000000000000000000000000000000000000000000001 ; +localparam ADP_WRITEHEXS = 46'b0000000000000000000000000000000000000000000010 ; +localparam ADP_WRITEHEX9 = 46'b0000000000000000000000000000000000000000000100 ; +localparam ADP_WRITEHEX8 = 46'b0000000000000000000000000000000000000000001000 ; +localparam ADP_WRITEHEX7 = 46'b0000000000000000000000000000000000000000010000 ; +localparam ADP_WRITEHEX6 = 46'b0000000000000000000000000000000000000000100000 ; +localparam ADP_WRITEHEX5 = 46'b0000000000000000000000000000000000000001000000 ; +localparam ADP_WRITEHEX4 = 46'b0000000000000000000000000000000000000010000000 ; +localparam ADP_WRITEHEX3 = 46'b0000000000000000000000000000000000000100000000 ; +localparam ADP_WRITEHEX2 = 46'b0000000000000000000000000000000000001000000000 ; +localparam ADP_WRITEHEX1 = 46'b0000000000000000000000000000000000010000000000 ; +localparam ADP_WRITEHEX0 = 46'b0000000000000000000000000000000000100000000000 ; +localparam ADP_READEOL = 46'b0000000000000000000000000000000001000000000000 ; +localparam ADP_LINEACK = 46'b0000000000000000000000000000000010000000000000 ; +localparam ADP_PROMPT = 46'b0000000000000000000000000000000100000000000000 ; +localparam ADP_IOCHK = 46'b0000000000000000000000000000001000000000000000 ; +localparam ADP_RXCMD = 46'b0000000000000000000000000000010000000000000000 ; +localparam ADP_READ = 46'b0000000000000000000000000000100000000000000000 ; +localparam ADP_RXPARAM = 46'b0000000000000000000000000001000000000000000000 ; +localparam ADP_ACTION = 46'b0000000000000000000000000010000000000000000000 ; +localparam ADP_SYSCHK = 46'b0000000000000000000000000100000000000000000000 ; +localparam ADP_STDIN = 46'b0000000000000000000000001000000000000000000000 ; +localparam ADP_STAT = 46'b0000000000000000000000010000000000000000000000 ; +localparam ADP_WRITE = 46'b0000000000000000000000100000000000000000000000 ; +localparam ADP_EXIT = 46'b0000000000000000000001000000000000000000000000 ; +localparam STD_IOCHK = 46'b0000000000000000000010000000000000000000000000 ; +localparam STD_RXD1 = 46'b0000000000000000000100000000000000000000000000 ; +localparam STD_RXD2 = 46'b0000000000000000001000000000000000000000000000 ; +localparam STD_TXD1 = 46'b0000000000000000010000000000000000000000000000 ; +localparam STD_TXD2 = 46'b0000000000000000100000000000000000000000000000 ; +localparam ADP_BCTRL = 46'b0000000000000001000000000000000000000000000000 ; +localparam ADP_BREADB0 = 46'b0000000000000010000000000000000000000000000000 ; +localparam ADP_BREADB1 = 46'b0000000000000100000000000000000000000000000000 ; +localparam ADP_BREADB2 = 46'b0000000000001000000000000000000000000000000000 ; +localparam ADP_BREADB3 = 46'b0000000000010000000000000000000000000000000000 ; +localparam ADP_BWRITE = 46'b0000000000100000000000000000000000000000000000 ; +localparam ADP_POLL = 46'b0000000001000000000000000000000000000000000000 ; +localparam ADP_POLL1 = 46'b0000000010000000000000000000000000000000000000 ; +localparam ADP_POLL2 = 46'b0000000100000000000000000000000000000000000000 ; +localparam ADP_ZCTRL = 46'b0000001000000000000000000000000000000000000000 ; +localparam ADP_ZWRITE = 46'b0000010000000000000000000000000000000000000000 ; +localparam ADP_UNKNOWN = 46'b0000100000000000000000000000000000000000000000 ; +localparam ADP_STDOUT = 46'b0001000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT1 = 46'b0010000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT2 = 46'b0100000000000000000000000000000000000000000000 ; +localparam ADP_STDOUT3 = 46'b1000000000000000000000000000000000000000000000 ; + +reg [45:0] adp_state ; +reg [31:0] adp_bus_data; +reg banner ; +reg com_tx_req ; +reg [7:0] com_tx_byte ; +reg com_rx_ack ; +reg std_tx_req ; +reg [ 7:0] std_tx_byte; +reg std_rx_ack ; +reg adp_bus_req ; +reg adp_bus_write ; +reg [7:0] adp_cmd ; +reg [31:0] adp_param ; +reg adp_param_dec ; +reg [31:0] adp_addr ; +reg adp_addr_inc; +reg [31:0] adp_sys ; + + +// ADP RX stream +wire com_rx_req = COMRX_TVALID_i; +wire [ 7:0] com_rx_byte = COMRX_TDATA_i; +assign COMRX_TREADY_o = com_rx_ack; +// ADP TX stream +wire com_tx_ack = COMTX_TREADY_i; +assign COMTX_TDATA_o = com_tx_byte; +assign COMTX_TVALID_o = com_tx_req; +// STD RX stream (from STDOUT) +wire std_rx_req = STDRX_TVALID_i; +wire [ 7:0] std_rx_byte = STDRX_TDATA_i; +assign STDRX_TREADY_o = std_rx_ack; +// STD TX stream (to STDIN) +wire std_tx_ack = STDTX_TREADY_i; +assign STDTX_TDATA_o = std_tx_byte; +assign STDTX_TVALID_o = std_tx_req; + +//AMBA AHB master as "stream" interface +reg ahb_dphase; +wire ahb_aphase = adp_bus_req & !ahb_dphase; +wire adp_bus_ack = ahb_dphase & M_HREADY_i; +// control pipe +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) + ahb_dphase <= 0; + else if (M_HREADY_i) + ahb_dphase <= (ahb_aphase); + +assign M_HADDR32_o = adp_addr; +assign M_HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer; +assign M_HMASTLOCK_o = 1'b0; +assign M_HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1}; +assign M_HSIZE3_o[2:0] = {1'b0, 2'b10}; +assign M_HTRANS2_o = {ahb_aphase,1'b0}; // non-seq +assign M_HWDATA32_o = adp_bus_data; +assign M_HWRITE_o = adp_bus_write; + + +`ifndef ADPBASIC +//reg [63:0] adp_bctrl64; +reg [31:0] adp_bctrl; +reg [31:0] adp_val; +reg [31:0] adp_mask; +reg [31:0] adp_poll; +wire adp_delay_done; +wire adp_bctrl_done; +wire adp_bctrl_zero; +wire poll2_loop_next; +`endif + +// ADP_control flags in the 'C' control field +wire adp_disable; +wire adp_stdin_wait; + +// commnon interface handshake terms +wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o; +wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i; +wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o; +wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i; +wire adp_bus_done = (adp_bus_req & adp_bus_ack); + +// common task to set up for next state +task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner) + begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end +endtask +task ADP_PROMPT_next; // prepare prompt TX + begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end +endtask +task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion +input[31:0] data; + begin adp_bus_req <=1; adp_bus_write <=1; adp_bus_data <= data; adp_addr_inc <=1; end +endtask +task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion + begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end +endtask + +task ADP_hexdigit_next; // output nibble +input [3:0] nibble; + begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end +endtask +task ADP_txchar_next; // output char +input [7:0] byte; + begin com_tx_req<= 1; com_tx_byte <= byte; end +endtask + +task com_rx_nxt; com_rx_ack <=1; endtask + +function FNcount_zero_next; // param about to be zero +input [31:0] counter; + FNcount_zero_next = (counter[31:0] == 32'h00000001); +endfunction + +function FNcount_zero; // param about to be zero +input [31:0] counter; + FNcount_zero = (counter[31:0] == 32'h0000000); // exactly 0 +endfunction + +always @(posedge HCLK or negedge HRESETn) + if(!HRESETn) begin + adp_state <= ADP_WRITEHEX ; + adp_bus_data <= 32'h50c1ab01; + banner <= 1; // start-up HEX message + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_cmd <= 0; + adp_param <= 0; + adp_param_dec<= 0; + adp_addr <= 0; + adp_addr_inc <= 0; + adp_bus_write<= 0; + adp_val <= 0; + adp_mask <= 0; + adp_sys <= 0; + + end else begin // default states + adp_state <= adp_state; // default to hold current state + com_tx_req <= 0; // default no TX req + com_rx_ack <= 0; // default no RX ack + std_tx_req <= 0; // default no TX req + std_rx_ack <= 0; // default no RX ack + adp_bus_req <= 0; // default no bus transaction + adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++ + adp_addr_inc <= 0; + adp_param <= (adp_param_dec & adp_bus_done & (|adp_param)) ? adp_param - 1 : adp_param; // param-- + adp_param_dec<= 0; + + case (adp_state) +// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>> + STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN +// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy + STD_TXD1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end + else std_rx_ack <= 1; // extend + STD_TXD2: // output char to ADP channel + if (com_tx_done) begin adp_state <= STD_IOCHK; end + else com_tx_req <= 1; // extend + STD_RXD1: // read rx char and check for ADP entry else STDIN ** + if (com_rx_done) begin + if (FNvalid_adp_entry(com_rx_byte)) begin adp_state <= ADP_LINEACK; end // ADP prompt + else if (std_tx_ack) begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end + else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked + end else com_rx_ack <= 1; // extend + STD_RXD2: // get STD in char + if (std_tx_done) begin adp_state <= STD_IOCHK; end + else std_tx_req <= 1; // extend + +// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>> + ADP_PROMPT: // transition after reset deassertion + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // extend + + ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back + if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end +// else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end + +// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>> + ADP_STDOUT: // output "<" + if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end + else com_tx_req <= 1; // extend stream request if not ready + ADP_STDOUT1: // get STD out char + if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end + else std_rx_ack <= 1; // else extend + ADP_STDOUT2: // output char + if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end + else com_tx_req <= 1; // else extend + ADP_STDOUT3: // output ">" + if (com_tx_done) begin adp_state <= ADP_IOCHK; end + else com_tx_req <= 1; // else extend + +// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>> + ADP_RXCMD: // read and save ADP command + if (com_rx_done) begin + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit + else if (FNvalid_EOL(com_rx_byte)) ADP_LINEACK_next(); // dummy command + else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command + else if (FNvalid_cmd(com_rx_byte) == CMD_R) begin ADP_BUSREADINC_next(); adp_state <= ADP_READ; end // no param + else begin adp_cmd <= com_rx_byte; adp_param <= 0; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter + end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_RXPARAM: // read and build hex parameter + if (com_rx_done) begin // RX byte + if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit + else if (FNvalid_EOL(com_rx_byte)) adp_state <= ADP_ACTION; // paremeter complete on EOL + else begin adp_param <= FNBuild_param32_hexdigit(adp_param, com_rx_byte); com_rx_ack <= 1; end // build parameter + end + else com_rx_ack <= 1; + + ADP_ACTION: // parse command and action with parameter +// if (FNexit(adp_cmd)) adp_state <= STD_IOCHK; + if (FNvalid_cmd(adp_cmd) == CMD_A) begin adp_addr <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_C) begin adp_sys <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_S) begin adp_state <= ADP_SYSCHK; end + else if (FNvalid_cmd(adp_cmd) == CMD_W) begin ADP_BUSWRITEINC_next(adp_param); adp_state <= ADP_WRITE; end + else if (FNvalid_cmd(adp_cmd) == CMD_X) begin adp_state <= ADP_EXIT; end +`ifndef ADPBASIC + else if (FNvalid_cmd(adp_cmd) == CMD_M) begin adp_mask <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_V) begin adp_val <= adp_param; ADP_LINEACK_next(); end + else if (FNvalid_cmd(adp_cmd) == CMD_B) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_BCTRL; end // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_P) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_POLL; end // non-zero count + else if (FNvalid_cmd(adp_cmd) == CMD_Z) begin if (FNcount_zero(adp_param)) ADP_LINEACK_next(); else adp_state <= ADP_ZCTRL; end // non-zero count +`endif + else begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; com_tx_req <= 1; end // unrecognised/invald + +// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>> + + ADP_WRITE: // perform bus write at current address pointer (and auto increment) + if (adp_bus_done) begin ADP_LINEACK_next(); end + else begin ADP_BUSWRITEINC_next(adp_param); end // extend request + + ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex + if (adp_bus_done) begin adp_bus_data <= M_HRDATA32_i; adp_state <= ADP_WRITEHEX; end + else begin ADP_BUSREADINC_next(); end // extend request + +`ifndef ADPBASIC + +// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>> + ADP_BCTRL: // set control value + begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end // read next 4 bytes + ADP_BREADB0: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_BREADB1; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB1: // read raw binary byte + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_BREADB2; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB2: // read raw binary byte 0 + if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_BREADB3; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BREADB3: // read raw binary byte 0 + if (com_rx_done) + begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next({adp_bus_data[31:8],com_rx_byte[7:0]}); adp_param_dec <= 1; adp_state <= ADP_BWRITE; end + else com_rx_ack <= 1; // extend stream request if not ready + ADP_BWRITE: // Write word to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_zero_next(adp_param)) ADP_LINEACK_next(); else begin com_rx_ack <= 1; adp_state <= ADP_BREADB0; end + end else begin ADP_BUSWRITEINC_next(adp_bus_data); adp_param_dec <= 1; end // extend request + +// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>> + ADP_POLL: // set poll value + begin adp_bus_req <= 1; adp_bus_write <= 0; adp_param_dec <=1; adp_state <= ADP_POLL1; end + ADP_POLL1: // wait for read data, no addr++ + if (adp_bus_done) begin adp_bus_data <= M_HRDATA32_i; adp_param_dec <=1; adp_state <= ADP_POLL2; end + else begin adp_bus_req <= 1; adp_param_dec <=1; end + ADP_POLL2: + if (FNcount_zero(adp_param)) ADP_LINEACK_next(); // timeout + else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) adp_state <= ADP_WRITEHEX; // exact match + else adp_state <= ADP_POLL; + +// >>>>>>>>>>>>>>>> ADP ZERO MEMORY >>>>>>>>>>>>>>>>>>>>>> + ADP_ZCTRL: // set control value + begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; adp_state <= ADP_ZWRITE; end + ADP_ZWRITE: // Write zero to Addr++ + if (adp_bus_done) begin // auto address++, count-- + if (FNcount_zero_next(adp_param)) ADP_LINEACK_next(); else begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; end + end else begin ADP_BUSWRITEINC_next(32'h0); adp_param_dec <= 1; end // extend request +`endif + + // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>> + + ADP_UNKNOWN: // output "?" + if (com_tx_done) begin ADP_LINEACK_next(); end + else com_tx_req <= 1; // extend stream request if not ready + + ADP_EXIT: // exit ADP mode + adp_state <= STD_IOCHK; + + ADP_SYSCHK: // check STDIN fifo + if (adp_param[31:8] == 0) begin // no upper flags so STDIN char + std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; + end else begin adp_sys <= adp_sys ^ adp_param; adp_state <= ADP_STAT; end + ADP_STDIN: // push char into STDIN + if(std_tx_done) ADP_LINEACK_next(); + else std_tx_req <= 1; // extend + ADP_STAT: // read current status - and report in hex + begin adp_bus_data <= adp_sys; adp_state <= ADP_WRITEHEX; end + + ADP_WRITEHEX: // output hex word with prefix + begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(" "); end // output space prefix + ADP_WRITEHEXS: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX9: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix + else com_tx_req <= 1; // extend + ADP_WRITEHEX8: + if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7 + else com_tx_req <= 1; // extend + ADP_WRITEHEX7: // output hex nibble 7 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6 + else com_tx_req <= 1; // extend + ADP_WRITEHEX6: // output hex nibble 6 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5 + else com_tx_req <= 1; // extend + ADP_WRITEHEX5: // output hex nibble 5 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4 + else com_tx_req <= 1; // extend + ADP_WRITEHEX4: // output hex nibble 4 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3 + else com_tx_req <= 1; // extend + ADP_WRITEHEX3: // output hex nibble 3 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2 + else com_tx_req <= 1; // extend + ADP_WRITEHEX2: // output hex nibble 2 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1 + else com_tx_req <= 1; // extend + ADP_WRITEHEX1: // output hex nibble 1 + if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0 + else com_tx_req <= 1; // extend + ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack + if (com_tx_done) begin + if (banner) begin ADP_LINEACK_next(); end + else begin adp_state <= ADP_READEOL; com_rx_ack <= 1'b1; end // discard any param + end else com_tx_req <= 1; // extend + + ADP_READEOL: // read flush until EOL + if (com_rx_done) begin // RX byte + if (FNvalid_EOL(com_rx_byte)) begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // parameter complete on EOL + else com_rx_ack <= 1; + end else com_rx_ack <= 1; + + ADP_LINEACK: // write EOLN + if (com_tx_done) begin + if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end + else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end + end else com_tx_req <= 1; // extend + + default: + begin ADP_txchar_next("!"); adp_state <= ADP_UNKNOWN; end // default to hold state + endcase + end + +endmodule + +////AHBLITE_ADPMASTER instancing +//ADPmaster +// #(.PROMPT_CHAR ("]")) +// ADPmaster( +// .HCLK (ahb_hclk ), +// .HRESETn (ahb_hrestn ), +// .M_HADDR32_o (ahb_haddr ), +// .M_HBURST3_o (ahb_hburst ), +// .M_HMASTLOCK_o (ahb_hmastlock ), +// .M_HPROT4_o (ahb_hprot ), +// .M_HSIZE3_o (ahb_hsize ), +// .M_HTRANS2_o (ahb_htrans ), +// .M_HWDATA32_o (ahb_hwdata ), +// .M_HWRITE_o (ahb_hwrite ), +// .M_HRDATA32_i (ahb_hrdata ), +// .M_HREADY_i (ahb_hready ), +// .M_HRESP_i (ahb_hresp ), + +// .COMRX_TREADY_o(com_rx_tready), +// .COMRX_TDATA_i(com_rx_tdata), +// .COMRX_TVALID_i(com_rx_tvalid), +// .STDRX_TREADY_o(std_rx_tready), +// .STDRX_TDATA_i(std_rx_tdata), +// .STDRX_TVALID_i(std_rx_tvalid), +// .COMTX_TVALID_o(com_tx_tvalid), +// .COMTX_TDATA_o(com_tx_tdata), +// .COMTX_TREADY_i(com_tx_tready), +// .STDTX_TVALID_o(std_tx_tvalid), +// .STDTX_TDATA_o(std_tx_tdata), +// .STDTX_TREADY_i(std_tx_tready) + +// ); diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl new file mode 100755 index 0000000000000000000000000000000000000000..7b1f3777d50c30180f5ec02a105f6d4280b0d604 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl @@ -0,0 +1,24 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to update PROMPT_CHAR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to validate PROMPT_CHAR + return true +} + + +proc update_MODELPARAM_VALUE.PROMPT_CHAR { MODELPARAM_VALUE.PROMPT_CHAR PARAM_VALUE.PROMPT_CHAR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PROMPT_CHAR}] ${MODELPARAM_VALUE.PROMPT_CHAR} +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml index afd116f0e666806de4d0ff0d7f50a99ebd8d756e..5696e415cb8e30efb4743373a5ca6747614422b3 100755 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml @@ -381,7 +381,7 @@ <spirit:parameters> <spirit:parameter> <spirit:name>viewChecksum</spirit:name> - <spirit:value>fc7589fa</spirit:value> + <spirit:value>4d515fed</spirit:value> </spirit:parameter> </spirit:parameters> </spirit:view> @@ -397,7 +397,7 @@ <spirit:parameters> <spirit:parameter> <spirit:name>viewChecksum</spirit:name> - <spirit:value>fc7589fa</spirit:value> + <spirit:value>4d515fed</spirit:value> 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b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip differ diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v index c6560f7d9f7273274985938b456c1f1479797a92..1d30f66be79c030e3aedc8b1e2e5c5095e974158 100755 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v @@ -133,25 +133,19 @@ integer byte_index; reg aw_en; - wire tx_req = tx_reg[8]; // request to transmit - wire tx_ack = tx_tready; // acknowledge when stream ready - - wire rx_req = rx_tvalid; // request to receive - wire rx_ack = !rx_reg[8]; - wire rx_val = rx_reg[8]; + wire tx_empty = !tx_reg[8]; // request to transmit + wire rx_full = rx_reg[8]; - //assign rx_reg[7:0] <= rx_tdata; - // I/O Connections assignments - assign interrupt = ctrl_reg[4] & (!tx_req | rx_req); + assign interrupt = ctrl_reg[4] & (tx_empty | rx_full); // TX stream interface assign tx_tdata = tx_reg[7:0]; - assign tx_tvalid = tx_req; + assign tx_tvalid = tx_reg[8]; // RX stream interface - assign rx_tready = rx_ack; + assign rx_tready = !rx_reg[8]; //AXI Slave assign S_AXI_AWREADY = axi_awready; @@ -257,27 +251,27 @@ always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) - rx_reg <= 0; - else if ((ctrl_reg[1] == 1'b1)) - rx_reg <= 0; - else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) + rx_reg <= 0; + else if ((ctrl_reg[1] == 1'b1)) // RX flush + rx_reg <= 0; + else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // SW test write rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]}; - else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) + else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // Read and clear RX valid pending rx_reg[8] <= 1'b0; - else if (rx_req & rx_ack) // check precedence (rx_req) - rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; + else if (rx_tvalid & rx_tready) //(!rx_reg[8]) // new RX data + rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; // valid rx data (= clear rx_tready inverted bit[8]) end always @( posedge S_AXI_ACLK ) begin if ( S_AXI_ARESETN == 1'b0 ) tx_reg <= 0; - else if ((ctrl_reg[0] == 1'b1)) - tx_reg <= 0; - else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) + else if ((ctrl_reg[0] == 1'b1)) // TX flush + tx_reg <= 0; + else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) // Write and set valid pending tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]}; - else if (tx_req & tx_ack) - tx_reg[8] <= 1'b0; + else if (tx_tready & tx_tvalid) //& tx_reg[8]) // clear TX valid pending when req and ack + tx_reg[8] <= 1'b0; // clear valid when TX data acknowledged end always @( posedge S_AXI_ACLK ) @@ -392,7 +386,7 @@ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) 2'h0 : reg_data_out <= rx_reg[7:0]; 2'h1 : reg_data_out <= tx_reg[7:0]; - 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], tx_req, !tx_req, rx_val, rx_val}; + 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_empty, tx_empty, rx_full, rx_full}; 2'h3 : reg_data_out <= ctrl_reg; default : reg_data_out <= 0; endcase diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl new file mode 100644 index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. 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xilinx:value="true"/> + </xilinx:targetDRC> + </xilinx:targetDRCs> + </xilinx:packagingInfo> + </spirit:vendorExtensions> +</spirit:component> diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix new file mode 100644 index 0000000000000000000000000000000000000000..e82fe55bd07f5b2021117a733d5ad768f20a16cc Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix differ diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v new file mode 100644 index 0000000000000000000000000000000000000000..35555b6fff93bcd08e9fe78363bf33ce83cd00ac --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v @@ -0,0 +1,40 @@ +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright © 2022, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +module SYNCHRONIZER_EDGES ( + input wire testmode_i + ,input wire clk_i + ,input wire reset_n_i + ,input wire asyn_i + ,output wire syn_o + ,output wire posedge_o + ,output wire negedge_o + ); + +reg sync_stage1; +reg sync_stage2; +reg sync_stage3; + + always @(posedge clk_i or negedge reset_n_i) + if(~reset_n_i) begin + sync_stage1 <= 1'b0; + sync_stage2 <= 1'b0; + sync_stage3 <= 1'b0; + end + else begin + sync_stage1 <= asyn_i; + sync_stage2 <= sync_stage1; + sync_stage3 <= sync_stage2; + end + +assign syn_o = (testmode_i) ? asyn_i : sync_stage2; +assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3); +assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3); + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v new file mode 100644 index 0000000000000000000000000000000000000000..d4c6ac43f831366160672a8ea31e669f207c4e48 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v @@ -0,0 +1,199 @@ +//----------------------------------------------------------------------------- +// FT1248 1-bit-data to 8-bit AXI-Stream IO +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Flynn (d.w.flynn@soton.ac.uk) +// +// Copyright (C) 2022-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device) +//----------------------------------------------------------------------------- + + module ft1248x1_to_axi_streamio_v1_0 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + + // Parameters of Axi Stream Bus Interface rxd8 + parameter integer C_rxd8_TDATA_WIDTH = 8, + + // Parameters of Axi Stream Bus Interface txd8 + parameter integer C_txd8_TDATA_WIDTH = 8 + ) + ( + input wire ft_clk_i, // SCLK + input wire ft_ssn_i, // SS_N + output wire ft_miso_o, // MISO +// inout wire ft_miosio_io, // MIOSIO tristate output control + input wire ft_miosio_i, + output wire ft_miosio_o, + output wire ft_miosio_z, +// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO +// +// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated + + input wire aclk, // external primary clock + input wire aresetn, // external reset (active low) + + // Ports of Axi stream Bus Interface TXD + output wire txd_tvalid_o, + output wire [7 : 0] txd_tdata8_o, + input wire txd_tready_i, + + // Ports of Axi stream Bus Interface RXD + output wire rxd_tready_o, + input wire [7 : 0] rxd_tdata8_i, + input wire rxd_tvalid_i + + ); + +//wire ft_clk; +wire ft_clk_rising; +wire ft_clk_falling; + +wire ft_ssn; +//wire ft_ssn_rising; +//wire ft_ssn_falling; + +SYNCHRONIZER_EDGES u_sync_ft_clk ( + .testmode_i(1'b0), + .clk_i(aclk), + .reset_n_i(aresetn), + .asyn_i(ft_clk_i), + .syn_o(), + .posedge_o(ft_clk_rising), + .negedge_o(ft_clk_falling) + ); + +SYNCHRONIZER_EDGES u_sync_ft_ssn ( + .testmode_i(1'b0), + .clk_i(aclk), + .reset_n_i(aresetn), + .asyn_i(ft_ssn_i), + .syn_o(ft_ssn), + .posedge_o( ), + .negedge_o( ) + ); + +//---------------------------------------------- +//-- FT1248 1-bit protocol State Machine +//---------------------------------------------- + +reg [4:0] ft_state; // 17-state for bit-serial +wire [4:0] ft_nextstate = ft_state + 5'b00001; + +// advance state count on rising edge of ft_clk +always @(posedge aclk or negedge aresetn) + if (!aresetn) + ft_state <= 5'b11111; + else if (ft_ssn) // sync reset + ft_state <= 5'b11111; + else if (ft_clk_rising) // loop if multi-data +// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate; + ft_state <= ft_nextstate; + +// 16: bus turnaround (or bit[5]) +// 0 for CMD3 +// 3 for CMD2 +// 5 for CMD1 +// 6 for CMD0 +// 7 for cmd turnaround +// 8 for data bit0 +// 9 for data bit1 +// 10 for data bit2 +// 11 for data bit3 +// 12 for data bit4 +// 13 for data bit5 +// 14 for data bit6 +// 15 for data bit7 + +// capture 7-bit CMD on falling edge of clock (mid-data) +reg [7:0] ft_cmd; +// - valid sample ready after 7th edge (ready RX or TX data phase functionality) +always @(posedge aclk or negedge aresetn) + if (!aresetn) + ft_cmd <= 8'b00000001; + else if (ft_ssn) // sync reset + ft_cmd <= 8'b00000001; + else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase) + ft_cmd <= {ft_cmd[6:0],ft_miosio_i}; + +wire ft_cmd_valid = ft_cmd[7]; +wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0]; +wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0]; + +// tristate enable for miosio (deselected status or serialized data for read command) +wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]); +assign ft_miosio_z = !ft_miosio_e; + +// capture (ft_cmd_txd) serial data out on falling edge of clock +// bit [0] indicated byte valid +reg [7:0] rxd_sr; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + rxd_sr <= 8'b00000000; + else if (ft_ssn) // sync reset + rxd_sr <= 8'b00000000; + else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift + rxd_sr <= {ft_miosio_i, rxd_sr[7:1]}; + +// AXI STREAM handshake interfaces +// TX stream delivers valid FT1248 read data transfer +// 8-bit write port with extra top-bit used as valid qualifer +reg [8:0] txstream; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + txstream <= 9'b000000000; + else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted + txstream[8] <= 1'b0; + else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives + txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]}; + +assign txd_tvalid_o = txstream[8]; +assign txd_tdata8_o = txstream[7:0]; + + +// AXI STREAM handshake interfaces +// RX stream accepts 8-bit data to transfer over FT1248 channel +// 8-bit write port with extra top-bit used as valid qualifer +reg [8:0] rxstream; +always @(posedge aclk or negedge aresetn) + if (!aresetn) + rxstream <= 9'b000000000; + else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data + rxstream[8:0] <= {1'b1,rxd_tdata8_i}; + else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion + rxstream[8] <= 1'b0; +assign rxd_tready_o = !rxstream[8]; // ready until loaded + +// shift TXD on rising edge of clock +reg [7:0] txd_sr; +// rewrite for clocked +always @(posedge aclk or negedge aresetn) + if (!aresetn) + txd_sr <= 8'b00000000; + else if (ft_ssn) // sync reset + txd_sr <= 8'b00000000; + else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111)) + txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000; + else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift + txd_sr <= {1'b0,txd_sr[7:1]}; + + +//FT1248 FIFO status signals + +// ft_miso_o reflects TXF when deselected +assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0]; + +// ft_miso_o reflects RXE when deselected +assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111); + + +endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v new file mode 100644 index 0000000000000000000000000000000000000000..03004bea96fe4c5e9ea0984b905d5f7a4b91d771 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v @@ -0,0 +1,167 @@ + +`timescale 1 ns / 1 ps + + module ft1248x1_to_axi_streamio_v1_0_rxd8 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // AXI4Stream sink: Data Width + parameter integer C_S_AXIS_TDATA_WIDTH = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // AXI4Stream sink: Clock + input wire S_AXIS_ACLK, + // AXI4Stream sink: Reset + input wire S_AXIS_ARESETN, + // Ready to accept data in + output wire S_AXIS_TREADY, + // Data in + input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, + // Byte qualifier + input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, + // Indicates boundary of last packet + input wire S_AXIS_TLAST, + // Data is in valid + input wire S_AXIS_TVALID + ); + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // Total number of input data. + localparam NUMBER_OF_INPUT_WORDS = 8; + // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1); + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 1'b0, // This is the initial/idle state + + WRITE_FIFO = 1'b1; // In this state FIFO is written with the + // input stream data S_AXIS_TDATA + wire axis_tready; + // State variable + reg mst_exec_state; + // FIFO implementation signals + genvar byte_index; + // FIFO write enable + wire fifo_wren; + // FIFO full flag + reg fifo_full_flag; + // FIFO write pointer + reg [bit_num-1:0] write_pointer; + // sink has accepted all the streaming data and stored in FIFO + reg writes_done; + // I/O Connections assignments + + assign S_AXIS_TREADY = axis_tready; + // Control state machine implementation + always @(posedge S_AXIS_ACLK) + begin + if (!S_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + end + else + case (mst_exec_state) + IDLE: + // The sink starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if (S_AXIS_TVALID) + begin + mst_exec_state <= WRITE_FIFO; + end + else + begin + mst_exec_state <= IDLE; + end + WRITE_FIFO: + // When the sink has accepted all the streaming input data, + // the interface swiches functionality to a streaming master + if (writes_done) + begin + mst_exec_state <= IDLE; + end + else + begin + // The sink accepts and stores tdata + // into FIFO + mst_exec_state <= WRITE_FIFO; + end + + endcase + end + // AXI Streaming Sink + // + // The example design sink is always ready to accept the S_AXIS_TDATA until + // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1)); + + always@(posedge S_AXIS_ACLK) + begin + if(!S_AXIS_ARESETN) + begin + write_pointer <= 0; + writes_done <= 1'b0; + end + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) + begin + if (fifo_wren) + begin + // write pointer is incremented after every write to the FIFO + // when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= 1'b0; + end + if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST) + begin + // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= 1'b1; + end + end + end + + // FIFO write enable generation + assign fifo_wren = S_AXIS_TVALID && axis_tready; + + // FIFO Implementation + generate + for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1) + begin:FIFO_GEN + + reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1]; + + // Streaming input data is stored in FIFO + + always @( posedge S_AXIS_ACLK ) + begin + if (fifo_wren)// && S_AXIS_TSTRB[byte_index]) + begin + stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8]; + end + end + end + endgenerate + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v new file mode 100644 index 0000000000000000000000000000000000000000..28cc34eafd0d52416bcfd2c8472fcda1245cd9a6 --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v @@ -0,0 +1,228 @@ + +`timescale 1 ns / 1 ps + + module ft1248x1_to_axi_streamio_v1_0_txd8 # + ( + // Users to add parameters here + + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = 8; + + // function called clogb2 that returns an integer which has the + // value of the ceiling of the log base 2. + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + parameter [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + //if ( count == 0 ) + // begin + mst_exec_state <= INIT_COUNTER; + // end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 1; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= read_pointer + 32'b1; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip new file mode 100644 index 0000000000000000000000000000000000000000..9da11b5a3446608bfe339577062496b021daa431 Binary files /dev/null and b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip differ diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f4b8c38737c46cbcd6d7a1adc43b9844e6b2e07f --- /dev/null +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl @@ -0,0 +1,35 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + +} + +proc update_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to update C_rxd8_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to validate C_rxd8_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to update C_txd8_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to validate C_txd8_TDATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH { MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH PARAM_VALUE.C_rxd8_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_rxd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_txd8_TDATA_WIDTH { MODELPARAM_VALUE.C_txd8_TDATA_WIDTH PARAM_VALUE.C_txd8_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_txd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_txd8_TDATA_WIDTH} +} + diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl index a1a6c43b84f099075b5f79214628984e8427a264..59baedbdea1dc8fa83d4525e6067114f604c5da4 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl @@ -118,9 +118,10 @@ ipx::check_integrity [ipx::current_core] ipx::save_core [ipx::current_core] ipx::check_integrity -quiet -xrt [ipx::current_core] -ipx::archive_core $mculib_ip/soclabs.org_user_cmsdk_mcu_chip_1.0.zip [ipx::current_core] +ipx::archive_core $mculib_ip/soclabs.org_user_nanosoc_chip_1.0.zip [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] -close_project -delete +#close_project -delete +close_project set_property ip_repo_paths { ip_repo $mculib_ip} [current_project] update_ip_catalog diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl index 87ae9c21ccbc94e23c06ccd881d73e19637f74ff..ac912781c4d37afbb52b0070e3b35f90506f7ad2 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl @@ -110,6 +110,6 @@ exec mkdir -p $pynqDir exec cp -p $project/export/design_1.bit $pynqDir exec cp -p $project/export/design_1.hwh $pynqDir -exec rm -Rf vivado/ +#exec rm -Rf vivado/ exit 1 diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl index 356404ee9e0d2ee8a3e21d54b13fae19b9421c6d..e7552e8defdc092fb7f8dea7606a683a2e55dea9 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/scripts/rtl_source_dma230.tcl @@ -1,4 +1,5 @@ ### DMA PL230 rtl source build +set search_path [ concat $search_path ../verilog ] read_verilog ../verilog/pl230_defs.v read_verilog $dma230_vlog/pl230_ahb_ctrl.v read_verilog $dma230_vlog/pl230_apb_regs.v diff --git a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl index 4859c7bf4bbd640cadb922491a7de25c57e547e4..1c371ce955932e2bb0f599980de721b9bf6feb7f 100644 --- a/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl +++ b/Cortex-M0/nanosoc/systems/mcu/fpga_imp/target_fpga_zcu104/design_1.tcl @@ -46,8 +46,15 @@ if { $bCheckIPs == 1 } { set list_check_ips "\ soclabs.org:user:nanosoc_chip:1.0\ xilinx.com:ip:zynq_ultra_ps_e:3.3\ +soclabs.org:user:ADPcontrol:1.0\ +xilinx.com:ip:ahblite_axi_bridge:3.0\ +xilinx.com:ip:axi_bram_ctrl:4.1\ xilinx.com:ip:axi_gpio:2.0\ +soclabs.org:user:axi_stream_io:1.0\ xilinx.com:ip:axi_uartlite:2.0\ +xilinx.com:ip:axis_data_fifo:2.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +soclabs.org:user:ft1248x1_to_axi_streamio:1.0\ xilinx.com:ip:xlslice:1.0\ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:proc_sys_reset:5.0\ @@ -123,10 +130,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { # Create pins create_bd_pin -dir I -type clk aclk create_bd_pin -dir I -type rst ext_reset_in - create_bd_pin -dir O -from 15 -to 0 gpio2_tri_o - create_bd_pin -dir I -from 15 -to 0 gpio2_tri_z - create_bd_pin -dir O -from 15 -to 0 gpio_tri_i - create_bd_pin -dir I -from 15 -to 0 gpio_tri_o create_bd_pin -dir O -from 0 -to 0 -type rst nrst create_bd_pin -dir O -from 15 -to 0 p0_tri_i create_bd_pin -dir I -from 15 -to 0 p0_tri_o @@ -137,6 +140,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z + create_bd_pin -dir O -from 0 -to 0 swdclk_i + create_bd_pin -dir O -from 0 -to 0 swdio_tri_i + create_bd_pin -dir I swdio_tri_o + create_bd_pin -dir I swdio_tri_z + + # Create instance: ADPcontrol_0, and set properties + set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ] + + # Create instance: ahblite_axi_bridge_0, and set properties + set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.ECC_TYPE {0} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_0 # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] @@ -154,16 +175,78 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.C_IS_DUAL {1} \ ] $axi_gpio_1 - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] - set_property -dict [ list \ - CONFIG.C_GPIO2_WIDTH {16} \ - CONFIG.C_GPIO_WIDTH {16} \ - CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 + # Create instance: axi_stream_io_0, and set properties + set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ] + + # Create instance: axi_stream_io_1, and set properties + set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ] + + # Create instance: axi_stream_io_2, and set properties + set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ] + + # Create instance: axi_stream_io_3, and set properties + set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ] # Create instance: axi_uartlite_0, and set properties set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \ + ] $axi_uartlite_0 + + # Create instance: axi_uartlite_1, and set properties + set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ] + set_property -dict [ list \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \ + ] $axi_uartlite_1 + + # Create instance: axis_data_fifo_0, and set properties + set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_0 + + # Create instance: axis_data_fifo_1, and set properties + set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_1 + + # Create instance: axis_data_fifo_2, and set properties + set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_2 + + # Create instance: axis_data_fifo_3, and set properties + set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_3 + + # Create instance: axis_data_fifo_4, and set properties + set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ] + set_property -dict [ list \ + CONFIG.FIFO_DEPTH {64} \ + ] $axis_data_fifo_4 + + # Create instance: blk_mem_gen_0, and set properties + set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ] + set_property -dict [ list \ + CONFIG.Byte_Size {8} \ + CONFIG.EN_SAFETY_CKT {true} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Read_Width_A {32} \ + CONFIG.Read_Width_B {32} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Write_Width_A {32} \ + CONFIG.Write_Width_B {32} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $blk_mem_gen_0 + + # Create instance: ft1248x1_to_axi_stream_0, and set properties + set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ] # Create instance: p1_i_bit15to6, and set properties set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ] @@ -184,6 +267,8 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.IN4_WIDTH {1} \ CONFIG.IN5_WIDTH {1} \ CONFIG.IN6_WIDTH {10} \ + CONFIG.IN7_WIDTH {1} \ + CONFIG.IN8_WIDTH {8} \ CONFIG.NUM_PORTS {7} \ ] $p1_i_concat @@ -259,6 +344,24 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { CONFIG.DOUT_WIDTH {1} \ ] $pmoda_i_bit3 + # Create instance: pmoda_i_bit4, and set properties + set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + CONFIG.DOUT_WIDTH {1} \ + ] $pmoda_i_bit4 + + # Create instance: pmoda_i_bit7, and set properties + set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + CONFIG.DOUT_WIDTH {1} \ + ] $pmoda_i_bit7 + # Create instance: pmoda_o_concat8, and set properties set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ] set_property -dict [ list \ @@ -277,7 +380,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { # Create instance: smartconnect_0, and set properties set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ - CONFIG.NUM_MI {4} \ + CONFIG.NUM_MI {8} \ CONFIG.NUM_SI {1} \ ] $smartconnect_0 @@ -291,41 +394,70 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } { set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] # Create interface connections + connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE] + connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS] + connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS] + connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8] + connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx] + connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] + connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS] + connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] # Create port connections + connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8] connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout] + connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out] + connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra] + connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka] + connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena] + connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea] + connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina] connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o] connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din] - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins gpio2_tri_o] [get_bd_pins axi_gpio_2/gpio2_io_o] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins gpio_tri_i] [get_bd_pins axi_gpio_2/gpio_io_o] connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4] - connect_bd_net -net nanosoc_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i] - connect_bd_net -net nanosoc_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i] - connect_bd_net -net nanosoc_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din] - connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins gpio_tri_o] [get_bd_pins axi_gpio_2/gpio_io_i] - connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins gpio2_tri_z] [get_bd_pins axi_gpio_2/gpio2_io_i] - connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In4] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net const1 [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net ftclk_o [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0] + connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx] + connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta] + connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i] + connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i] + connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din] + connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2] + connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0] + connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0] connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3] connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3] - connect_bd_net -net ftssn_n [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1] + connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1] connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout] connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6] connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din] - connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] - connect_bd_net -net pmoda_i_bit2_Dout [get_bd_pins p1_i_concat/In0] [get_bd_pins pmoda_i_bit2/Dout] - connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins p1_i_concat/In2] [get_bd_pins pmoda_i_bit3/Dout] + connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din] + connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout] + connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout] + connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout] connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4] + connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4] connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in] # Restore current instance @@ -371,12 +503,12 @@ proc create_root_design { parentCell } { set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ] set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ] - # Create instance: nanosoc_chip_0, and set properties - set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ] - # Create instance: cmsdk_socket create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket + # Create instance: nanosoc_chip_0, and set properties + set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ] + # Create instance: zynq_ultra_ps_e_0, and set properties set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] set_property -dict [ list \ @@ -964,28 +1096,33 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] # Create port connections - connect_bd_net -net nanosoc_chip_0_swdio_o [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/gpio_tri_o] - connect_bd_net -net nanosoc_chip_0_swdio_z [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/gpio2_tri_z] - connect_bd_net -net cmsdk_socket_gpio2_tri_o [get_bd_pins nanosoc_chip_0/swdclk_i] [get_bd_pins cmsdk_socket/gpio2_tri_o] - connect_bd_net -net cmsdk_socket_gpio_tri_i [get_bd_pins nanosoc_chip_0/swdio_i] [get_bd_pins cmsdk_socket/gpio_tri_i] - connect_bd_net -net cmsdk_socket_nrst [get_bd_pins nanosoc_chip_0/nrst_i] [get_bd_pins cmsdk_socket/nrst] - connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins nanosoc_chip_0/p0_i] [get_bd_pins cmsdk_socket/p0_tri_i] - connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins nanosoc_chip_0/p1_i] [get_bd_pins cmsdk_socket/p1_tri_i] - connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o] - connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z] - connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o] - connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z] + connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i] + connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i] + connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i] + connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i] + connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i] + connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o] + connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z] + connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o] + connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z] connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i] connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z] + connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o] + connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z] connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o] - connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] - connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] # Create address segments assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force - assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_2/S_AXI/Reg] -force - assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force + assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force + assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force + assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force + assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force # Restore current instance