From 8eb0e232b51e470c5b91a2b7aa68e4d8589185e0 Mon Sep 17 00:00:00 2001 From: dwn1c21 <d.newbrook@soton.ac.uk> Date: Sun, 30 Apr 2023 17:11:36 +0000 Subject: [PATCH] Fix pathes in build_mcu_fpga_pynq_zcu104.tcl --- .../scripts/build_mcu_fpga_pynq_zcu104.tcl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/system/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/system/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl index ac91278..3b97a5c 100644 --- a/system/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl +++ b/system/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl @@ -6,7 +6,7 @@ ### ### David Flynn (d.w.flynn@soton.ac.uk) ### -### Copyright � 2022, SoC Labs (www.soclabs.org) +### Copyright 2022, SoC Labs (www.soclabs.org) ###----------------------------------------------------------------------------- # # developed & tested using vivado_version 2021.1 @@ -62,14 +62,14 @@ read_verilog $importDir/design_1_wrapper.v source $importDir/design_1.tcl create_root_design "" -add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../verilog/pl230_defs.v} -set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] -set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] -set_property is_global_include true [get_files ../verilog/pl230_defs.v] +add_files -norecurse -scan_for_includes {../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../defines/pl230_defs.v} +set_property is_global_include true [get_files ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] +set_property is_global_include true [get_files ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] +set_property is_global_include true [get_files ../defines/pl230_defs.v] -set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] -set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] -set_property file_type {Verilog Header} [get_files ../verilog/pl230_defs.v] +set_property file_type {Verilog Header} [get_files ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v] +set_property file_type {Verilog Header} [get_files ../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v] +set_property file_type {Verilog Header} [get_files ../defines/pl230_defs.v] add_files $importDir/fpga_pinmap.xdc -- GitLab