diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index 50149406eacd4b343d56b6f27dd5a640404f3810..f319e99bdf29e36371759b9cac30e1e004e63cd2 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -57,7 +57,6 @@ source scripts/rtl_source_soclabs_ip.tcl
 #source scripts/rtl_source_fpga_ip.tcl
 
 # soclabs modified mcu system 
-set_property verilog_define {NOEXP} [current_fileset]
 
 set soc_vlog ../src
 read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
diff --git a/system/makefile b/system/makefile
index a2e8dfa8ab94884610891a78b3b0623df71258c1..28313d87195e954443a915bb0e724ced1df03b6b 100644
--- a/system/makefile
+++ b/system/makefile
@@ -81,9 +81,15 @@ BOOTROM_HEX       ?= $(NANOSOC_TECH_DIR)/system/testcodes/bootloader/$(BOOTLOADE
 BOOTROM_BUILD_DIR ?= $(PROJ_SYS_DIR)/bootrom
 
 
+NANSOC_EXPANSION_REGION ?= yes
+
 # Simulator Defines
 DEFINES_VC  += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC 
 
+ifeq ($(NANSOC_EXPANSION_REGION),yes)
+	DEFINES_VC += +define+NANSOC_EXPANSION_REGION
+endif
+
 # Simulator Command file to specify RTL source files
 TBENCH_VC   ?= -f $(PROJECT_DIR)/flist/project/system.flist
 
@@ -94,6 +100,7 @@ SIMULATOR   = xm
 # Directory to put simulation files
 SIM_DIR ?= 
 
+
 ifeq ($(SIM_DIR),)
 # Defaultly put simulation files in simulation directory with c code testname
 SIM_DIR = $(PROJECT_DIR)/simulate/sim/$(TESTNAME)
diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v
index b8012b558958674ed7c25eb02b0907184274436b..52f2a9105d659001546e844730220414b7540779 100644
--- a/system/src/verilog/nanosoc_chip.v
+++ b/system/src/verilog/nanosoc_chip.v
@@ -841,7 +841,7 @@ localparam    CORTEX_M0 = 1;
 // Expansion Region "exp" instance
 //----------------------------------------
 
-`ifdef NOEXP
+`ifdef NANSOC_EXPANSION_REGION
 nanosoc_exp #(.ADDRWIDTH(29)
 ) u_nanosoc_exp (
   .HCLK        (HCLK),