diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
index fb2712d2cabcc05959b092c88c1f91bab9809612..7520bf717d9ca9b91101233d0e9c9fb0b51eab1c 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix.xml
@@ -44,9 +44,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__SOCDEBUG_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -198,9 +198,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_0_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -351,9 +351,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__DMAC_1_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -504,9 +504,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__CPU_0_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -654,12 +654,12 @@
<!--Master interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__BOOTROM</spirit:name>
- <spirit:description>Master port _BOOTROM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0</spirit:name>
+ <spirit:description>Master port _BOOTROM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__BOOTROM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__BOOTROM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -686,7 +686,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_BOOTROM</spirit:name>
+ <spirit:name>HSEL_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -694,7 +694,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_BOOTROM</spirit:name>
+ <spirit:name>HADDR_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -702,7 +702,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_BOOTROM</spirit:name>
+ <spirit:name>HTRANS_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -710,7 +710,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_BOOTROM</spirit:name>
+ <spirit:name>HWRITE_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -718,7 +718,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_BOOTROM</spirit:name>
+ <spirit:name>HSIZE_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -726,7 +726,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_BOOTROM</spirit:name>
+ <spirit:name>HBURST_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -734,18 +734,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_BOOTROM</spirit:name>
+ <spirit:name>HPROT_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_BOOTROM unmapped -->
+ <!-- HMASTER_BOOTROM_0 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_BOOTROM</spirit:name>
+ <spirit:name>HWDATA_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -753,7 +753,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_BOOTROM</spirit:name>
+ <spirit:name>HMASTLOCK_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -761,7 +761,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_BOOTROM</spirit:name>
+ <spirit:name>HREADYMUX_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -771,7 +771,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_BOOTROM</spirit:name>
+ <spirit:name>HRDATA_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -779,7 +779,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_BOOTROM</spirit:name>
+ <spirit:name>HREADYOUT_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -787,7 +787,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_BOOTROM</spirit:name>
+ <spirit:name>HRESP_BOOTROM_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -798,12 +798,12 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__IMEM</spirit:name>
- <spirit:description>Master port _IMEM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0</spirit:name>
+ <spirit:description>Master port _IMEM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__IMEM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__IMEM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -830,7 +830,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_IMEM</spirit:name>
+ <spirit:name>HSEL_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -838,7 +838,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_IMEM</spirit:name>
+ <spirit:name>HADDR_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -846,7 +846,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_IMEM</spirit:name>
+ <spirit:name>HTRANS_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -854,7 +854,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_IMEM</spirit:name>
+ <spirit:name>HWRITE_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -862,7 +862,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_IMEM</spirit:name>
+ <spirit:name>HSIZE_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -870,7 +870,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_IMEM</spirit:name>
+ <spirit:name>HBURST_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -878,18 +878,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_IMEM</spirit:name>
+ <spirit:name>HPROT_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_IMEM unmapped -->
+ <!-- HMASTER_IMEM_0 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_IMEM</spirit:name>
+ <spirit:name>HWDATA_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -897,7 +897,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_IMEM</spirit:name>
+ <spirit:name>HMASTLOCK_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -905,7 +905,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_IMEM</spirit:name>
+ <spirit:name>HREADYMUX_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -915,7 +915,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_IMEM</spirit:name>
+ <spirit:name>HRDATA_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -923,7 +923,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_IMEM</spirit:name>
+ <spirit:name>HREADYOUT_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -931,7 +931,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_IMEM</spirit:name>
+ <spirit:name>HRESP_IMEM_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -942,12 +942,12 @@
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__DMEM</spirit:name>
- <spirit:description>Master port _DMEM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0</spirit:name>
+ <spirit:description>Master port _DMEM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__DMEM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__DMEM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -974,7 +974,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_DMEM</spirit:name>
+ <spirit:name>HSEL_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -982,7 +982,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMEM</spirit:name>
+ <spirit:name>HADDR_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -990,7 +990,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMEM</spirit:name>
+ <spirit:name>HTRANS_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -998,7 +998,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMEM</spirit:name>
+ <spirit:name>HWRITE_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1006,7 +1006,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMEM</spirit:name>
+ <spirit:name>HSIZE_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1014,7 +1014,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMEM</spirit:name>
+ <spirit:name>HBURST_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1022,18 +1022,18 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMEM</spirit:name>
+ <spirit:name>HPROT_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- <!-- HMASTER_DMEM unmapped -->
+ <!-- HMASTER_DMEM_0 unmapped -->
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMEM</spirit:name>
+ <spirit:name>HWDATA_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1041,7 +1041,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMEM</spirit:name>
+ <spirit:name>HMASTLOCK_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1049,7 +1049,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_DMEM</spirit:name>
+ <spirit:name>HREADYMUX_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -1059,7 +1059,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMEM</spirit:name>
+ <spirit:name>HRDATA_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1067,7 +1067,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_DMEM</spirit:name>
+ <spirit:name>HREADYOUT_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -1075,7 +1075,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMEM</spirit:name>
+ <spirit:name>HRESP_DMEM_0</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
@@ -2171,18 +2171,18 @@
<spirit:addressSpaces>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__BOOTROM_AS</spirit:name>
- <spirit:description>_BOOTROM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_AS</spirit:name>
+ <spirit:description>_BOOTROM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_BOOTROM_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_BOOTROM_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x10000000_0x1fffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2191,18 +2191,18 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__IMEM_AS</spirit:name>
- <spirit:description>_IMEM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_AS</spirit:name>
+ <spirit:description>_IMEM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_IMEM_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_IMEM_0_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_IMEM_0x20000000_0x2fffffff</spirit:name>
+ <spirit:name>_IMEM_0_0x20000000_0x2fffffff</spirit:name>
<spirit:addressOffset>0x20000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2211,13 +2211,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__DMEM_AS</spirit:name>
- <spirit:description>_DMEM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_AS</spirit:name>
+ <spirit:description>_DMEM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_DMEM_0x30000000_0x3fffffff</spirit:name>
+ <spirit:name>_DMEM_0_0x30000000_0x3fffffff</spirit:name>
<spirit:addressOffset>0x30000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2338,24 +2338,24 @@
<spirit:name>AHBLiteTarget_Slave__SOCDEBUG_MM</spirit:name>
<spirit:description>_SOCDEBUG memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2411,10 +2411,10 @@
<spirit:memoryRemap spirit:state="remap_0">
<spirit:name>AHBLiteTarget_Slave__SOCDEBUG_remap_0_remap_MM</spirit:name>
<spirit:description>_SOCDEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2422,10 +2422,10 @@
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__SOCDEBUG_remap_n0_remap_MM</spirit:name>
<spirit:description>_SOCDEBUG remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2436,31 +2436,31 @@
<spirit:name>AHBLiteTarget_Slave__DMAC_0_MM</spirit:name>
<spirit:description>_DMAC_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2512,31 +2512,31 @@
<spirit:name>AHBLiteTarget_Slave__DMAC_1_MM</spirit:name>
<spirit:description>_DMAC_1 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2588,24 +2588,24 @@
<spirit:name>AHBLiteTarget_Slave__CPU_0_MM</spirit:name>
<spirit:description>_CPU_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2661,10 +2661,10 @@
<spirit:memoryRemap spirit:state="remap_0">
<spirit:name>AHBLiteTarget_Slave__CPU_0_remap_0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2672,10 +2672,10 @@
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteTarget_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -3142,7 +3142,7 @@
<!-- Input signals of Master interfaces -->
<spirit:port>
- <spirit:name>HRDATA_BOOTROM</spirit:name>
+ <spirit:name>HRDATA_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3152,13 +3152,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_BOOTROM</spirit:name>
+ <spirit:name>HREADYOUT_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_BOOTROM</spirit:name>
+ <spirit:name>HRESP_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3168,7 +3168,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_IMEM</spirit:name>
+ <spirit:name>HRDATA_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3178,13 +3178,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_IMEM</spirit:name>
+ <spirit:name>HREADYOUT_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_IMEM</spirit:name>
+ <spirit:name>HRESP_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3194,7 +3194,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMEM</spirit:name>
+ <spirit:name>HRDATA_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3204,13 +3204,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_DMEM</spirit:name>
+ <spirit:name>HREADYOUT_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMEM</spirit:name>
+ <spirit:name>HRESP_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -3420,13 +3420,13 @@
<!-- Output signals of Master interfaces -->
<spirit:port>
- <spirit:name>HSEL_BOOTROM</spirit:name>
+ <spirit:name>HSEL_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_BOOTROM</spirit:name>
+ <spirit:name>HADDR_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3436,7 +3436,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_BOOTROM</spirit:name>
+ <spirit:name>HTRANS_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3446,13 +3446,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_BOOTROM</spirit:name>
+ <spirit:name>HWRITE_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_BOOTROM</spirit:name>
+ <spirit:name>HSIZE_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3462,7 +3462,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_BOOTROM</spirit:name>
+ <spirit:name>HBURST_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3472,7 +3472,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_BOOTROM</spirit:name>
+ <spirit:name>HPROT_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3482,7 +3482,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_BOOTROM</spirit:name>
+ <spirit:name>HMASTER_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3492,7 +3492,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_BOOTROM</spirit:name>
+ <spirit:name>HWDATA_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3502,25 +3502,25 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_BOOTROM</spirit:name>
+ <spirit:name>HMASTLOCK_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_BOOTROM</spirit:name>
+ <spirit:name>HREADYMUX_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_IMEM</spirit:name>
+ <spirit:name>HSEL_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_IMEM</spirit:name>
+ <spirit:name>HADDR_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3530,7 +3530,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_IMEM</spirit:name>
+ <spirit:name>HTRANS_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3540,13 +3540,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_IMEM</spirit:name>
+ <spirit:name>HWRITE_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_IMEM</spirit:name>
+ <spirit:name>HSIZE_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3556,7 +3556,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_IMEM</spirit:name>
+ <spirit:name>HBURST_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3566,7 +3566,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_IMEM</spirit:name>
+ <spirit:name>HPROT_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3576,7 +3576,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_IMEM</spirit:name>
+ <spirit:name>HMASTER_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3586,7 +3586,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_IMEM</spirit:name>
+ <spirit:name>HWDATA_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3596,25 +3596,25 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_IMEM</spirit:name>
+ <spirit:name>HMASTLOCK_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_IMEM</spirit:name>
+ <spirit:name>HREADYMUX_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_DMEM</spirit:name>
+ <spirit:name>HSEL_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMEM</spirit:name>
+ <spirit:name>HADDR_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3624,7 +3624,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMEM</spirit:name>
+ <spirit:name>HTRANS_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3634,13 +3634,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMEM</spirit:name>
+ <spirit:name>HWRITE_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMEM</spirit:name>
+ <spirit:name>HSIZE_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3650,7 +3650,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMEM</spirit:name>
+ <spirit:name>HBURST_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3660,7 +3660,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMEM</spirit:name>
+ <spirit:name>HPROT_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3670,7 +3670,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTER_DMEM</spirit:name>
+ <spirit:name>HMASTER_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3680,7 +3680,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMEM</spirit:name>
+ <spirit:name>HWDATA_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3690,13 +3690,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMEM</spirit:name>
+ <spirit:name>HMASTLOCK_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_DMEM</spirit:name>
+ <spirit:name>HREADYMUX_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
@@ -4513,15 +4513,15 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
@@ -4553,15 +4553,15 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
index e2f7c6b2210615c3ec5eb2d2d4e853cb95735e58..70ebb8b4673d320ae9421bb1702f0a6a63d737a5 100644
--- a/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
+++ b/system/nanosoc_busmatrix/ipxact/nanosoc_busmatrix/nanosoc_busmatrix_lite.xml
@@ -44,9 +44,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__SOCDEBUG_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -175,9 +175,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_0_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -305,9 +305,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__DMAC_1_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -435,9 +435,9 @@
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__CPU_0_MM"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM" spirit:opaque="true"/>
- <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__IMEM_0" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__DMEM_0" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__SYSIO" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_L" spirit:opaque="true"/>
<spirit:bridge spirit:masterRef="AHBLiteTarget_Master__EXPRAM_H" spirit:opaque="true"/>
@@ -562,12 +562,12 @@
<!--Master interfaces -->
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__BOOTROM</spirit:name>
- <spirit:description>Master port _BOOTROM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0</spirit:name>
+ <spirit:description>Master port _BOOTROM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__BOOTROM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__BOOTROM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -594,7 +594,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_BOOTROM</spirit:name>
+ <spirit:name>HSEL_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -602,7 +602,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_BOOTROM</spirit:name>
+ <spirit:name>HADDR_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -610,7 +610,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_BOOTROM</spirit:name>
+ <spirit:name>HTRANS_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -618,7 +618,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_BOOTROM</spirit:name>
+ <spirit:name>HWRITE_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -626,7 +626,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_BOOTROM</spirit:name>
+ <spirit:name>HSIZE_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -634,7 +634,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_BOOTROM</spirit:name>
+ <spirit:name>HBURST_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -642,7 +642,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_BOOTROM</spirit:name>
+ <spirit:name>HPROT_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -650,7 +650,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_BOOTROM</spirit:name>
+ <spirit:name>HWDATA_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -658,7 +658,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_BOOTROM</spirit:name>
+ <spirit:name>HMASTLOCK_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -666,7 +666,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_BOOTROM</spirit:name>
+ <spirit:name>HREADYMUX_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -676,7 +676,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_BOOTROM</spirit:name>
+ <spirit:name>HRDATA_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -684,7 +684,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_BOOTROM</spirit:name>
+ <spirit:name>HREADYOUT_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -692,19 +692,19 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_BOOTROM</spirit:name>
+ <spirit:name>HRESP_BOOTROM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__IMEM</spirit:name>
- <spirit:description>Master port _IMEM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0</spirit:name>
+ <spirit:description>Master port _IMEM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__IMEM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__IMEM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -731,7 +731,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_IMEM</spirit:name>
+ <spirit:name>HSEL_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -739,7 +739,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_IMEM</spirit:name>
+ <spirit:name>HADDR_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -747,7 +747,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_IMEM</spirit:name>
+ <spirit:name>HTRANS_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -755,7 +755,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_IMEM</spirit:name>
+ <spirit:name>HWRITE_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -763,7 +763,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_IMEM</spirit:name>
+ <spirit:name>HSIZE_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -771,7 +771,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_IMEM</spirit:name>
+ <spirit:name>HBURST_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -779,7 +779,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_IMEM</spirit:name>
+ <spirit:name>HPROT_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -787,7 +787,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_IMEM</spirit:name>
+ <spirit:name>HWDATA_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -795,7 +795,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_IMEM</spirit:name>
+ <spirit:name>HMASTLOCK_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -803,7 +803,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_IMEM</spirit:name>
+ <spirit:name>HREADYMUX_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -813,7 +813,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_IMEM</spirit:name>
+ <spirit:name>HRDATA_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -821,7 +821,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_IMEM</spirit:name>
+ <spirit:name>HREADYOUT_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -829,19 +829,19 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_IMEM</spirit:name>
+ <spirit:name>HRESP_IMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>AHBLiteTarget_Master__DMEM</spirit:name>
- <spirit:description>Master port _DMEM</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0</spirit:name>
+ <spirit:description>Master port _DMEM_0</spirit:description>
<spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
<spirit:master>
- <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__DMEM_AS"/>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__DMEM_0_AS"/>
</spirit:master>
<spirit:portMaps>
@@ -868,7 +868,7 @@
<spirit:name>HSELx</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSEL_DMEM</spirit:name>
+ <spirit:name>HSEL_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -876,7 +876,7 @@
<spirit:name>HADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HADDR_DMEM</spirit:name>
+ <spirit:name>HADDR_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -884,7 +884,7 @@
<spirit:name>HTRANS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HTRANS_DMEM</spirit:name>
+ <spirit:name>HTRANS_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -892,7 +892,7 @@
<spirit:name>HWRITE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWRITE_DMEM</spirit:name>
+ <spirit:name>HWRITE_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -900,7 +900,7 @@
<spirit:name>HSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HSIZE_DMEM</spirit:name>
+ <spirit:name>HSIZE_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -908,7 +908,7 @@
<spirit:name>HBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HBURST_DMEM</spirit:name>
+ <spirit:name>HBURST_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -916,7 +916,7 @@
<spirit:name>HPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HPROT_DMEM</spirit:name>
+ <spirit:name>HPROT_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -924,7 +924,7 @@
<spirit:name>HWDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HWDATA_DMEM</spirit:name>
+ <spirit:name>HWDATA_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -932,7 +932,7 @@
<spirit:name>HMASTLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HMASTLOCK_DMEM</spirit:name>
+ <spirit:name>HMASTLOCK_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -940,7 +940,7 @@
<spirit:name>HREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYMUX_DMEM</spirit:name>
+ <spirit:name>HREADYMUX_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
@@ -950,7 +950,7 @@
<spirit:name>HRDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRDATA_DMEM</spirit:name>
+ <spirit:name>HRDATA_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -958,7 +958,7 @@
<spirit:name>HREADYOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HREADYOUT_DMEM</spirit:name>
+ <spirit:name>HREADYOUT_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
@@ -966,7 +966,7 @@
<spirit:name>HRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>HRESP_DMEM</spirit:name>
+ <spirit:name>HRESP_DMEM_0</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
@@ -2009,18 +2009,18 @@
<spirit:addressSpaces>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__BOOTROM_AS</spirit:name>
- <spirit:description>_BOOTROM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_AS</spirit:name>
+ <spirit:description>_BOOTROM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_BOOTROM_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_BOOTROM_0x10000000_0x1fffffff</spirit:name>
+ <spirit:name>_BOOTROM_0_0x10000000_0x1fffffff</spirit:name>
<spirit:addressOffset>0x10000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2029,18 +2029,18 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__IMEM_AS</spirit:name>
- <spirit:description>_IMEM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_AS</spirit:name>
+ <spirit:description>_IMEM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_IMEM_0x00000000_0x0fffffff</spirit:name>
+ <spirit:name>_IMEM_0_0x00000000_0x0fffffff</spirit:name>
<spirit:addressOffset>0x00000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
<spirit:segment>
- <spirit:name>_IMEM_0x20000000_0x2fffffff</spirit:name>
+ <spirit:name>_IMEM_0_0x20000000_0x2fffffff</spirit:name>
<spirit:addressOffset>0x20000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2049,13 +2049,13 @@
</spirit:addressSpace>
<spirit:addressSpace>
- <spirit:name>AHBLiteTarget_Master__DMEM_AS</spirit:name>
- <spirit:description>_DMEM address space</spirit:description>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_AS</spirit:name>
+ <spirit:description>_DMEM_0 address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:segments>
<spirit:segment>
- <spirit:name>_DMEM_0x30000000_0x3fffffff</spirit:name>
+ <spirit:name>_DMEM_0_0x30000000_0x3fffffff</spirit:name>
<spirit:addressOffset>0x30000000</spirit:addressOffset>
<spirit:range>0x010000000</spirit:range>
</spirit:segment>
@@ -2176,24 +2176,24 @@
<spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_MM</spirit:name>
<spirit:description>_SOCDEBUG memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2249,10 +2249,10 @@
<spirit:memoryRemap spirit:state="remap_0">
<spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_remap_0_remap_MM</spirit:name>
<spirit:description>_SOCDEBUG remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2260,10 +2260,10 @@
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__SOCDEBUG_remap_n0_remap_MM</spirit:name>
<spirit:description>_SOCDEBUG remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2274,31 +2274,31 @@
<spirit:name>AHBLiteInitiator_Slave__DMAC_0_MM</spirit:name>
<spirit:description>_DMAC_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2350,31 +2350,31 @@
<spirit:name>AHBLiteInitiator_Slave__DMAC_1_MM</spirit:name>
<spirit:description>_DMAC_1 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2426,24 +2426,24 @@
<spirit:name>AHBLiteInitiator_Slave__CPU_0_MM</spirit:name>
<spirit:description>_CPU_0 memory map</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x10000000_0x1fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x10000000_0x1fffffff">
<!-- Address_region 0x10000000-0x1fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x10000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x10000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x20000000_0x2fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x20000000_0x2fffffff">
<!-- Address_region 0x20000000-0x2fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x20000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x20000000</spirit:baseAddress>
</spirit:subspaceMap>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM"
- spirit:segmentRef="_DMEM_0x30000000_0x3fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__DMEM_0"
+ spirit:segmentRef="_DMEM_0_0x30000000_0x3fffffff">
<!-- Address_region 0x30000000-0x3fffffff -->
- <spirit:name>AHBLiteTarget_Master__DMEM_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__DMEM_0_0x30000000_0_state_always_SM</spirit:name>
<spirit:baseAddress>0x30000000</spirit:baseAddress>
</spirit:subspaceMap>
@@ -2499,10 +2499,10 @@
<spirit:memoryRemap spirit:state="remap_0">
<spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM"
- spirit:segmentRef="_IMEM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__IMEM_0"
+ spirit:segmentRef="_IMEM_0_0x00000000_0x0fffffff">
<!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__IMEM_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__IMEM_0_0x00000000_0_state_remap_0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2510,10 +2510,10 @@
<spirit:memoryRemap spirit:state="remap_n0">
<spirit:name>AHBLiteInitiator_Slave__CPU_0_remap_n0_remap_MM</spirit:name>
<spirit:description>_CPU_0 remap_n0 remap</spirit:description>
- <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM"
- spirit:segmentRef="_BOOTROM_0x00000000_0x0fffffff">
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__BOOTROM_0"
+ spirit:segmentRef="_BOOTROM_0_0x00000000_0x0fffffff">
<!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
- <spirit:name>AHBLiteTarget_Master__BOOTROM_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:name>AHBLiteTarget_Master__BOOTROM_0_0x00000000_0_state_remap_n0_SM</spirit:name>
<spirit:baseAddress>0x00000000</spirit:baseAddress>
</spirit:subspaceMap>
</spirit:memoryRemap>
@@ -2876,7 +2876,7 @@
<!-- Input signals of Master interfaces -->
<spirit:port>
- <spirit:name>HRDATA_BOOTROM</spirit:name>
+ <spirit:name>HRDATA_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2886,19 +2886,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_BOOTROM</spirit:name>
+ <spirit:name>HREADYOUT_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_BOOTROM</spirit:name>
+ <spirit:name>HRESP_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_IMEM</spirit:name>
+ <spirit:name>HRDATA_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2908,19 +2908,19 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_IMEM</spirit:name>
+ <spirit:name>HREADYOUT_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_IMEM</spirit:name>
+ <spirit:name>HRESP_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRDATA_DMEM</spirit:name>
+ <spirit:name>HRDATA_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
@@ -2930,13 +2930,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYOUT_DMEM</spirit:name>
+ <spirit:name>HREADYOUT_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HRESP_DMEM</spirit:name>
+ <spirit:name>HRESP_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
</spirit:wire>
@@ -3114,13 +3114,13 @@
<!-- Output signals of Master interfaces -->
<spirit:port>
- <spirit:name>HSEL_BOOTROM</spirit:name>
+ <spirit:name>HSEL_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_BOOTROM</spirit:name>
+ <spirit:name>HADDR_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3130,7 +3130,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_BOOTROM</spirit:name>
+ <spirit:name>HTRANS_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3140,13 +3140,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_BOOTROM</spirit:name>
+ <spirit:name>HWRITE_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_BOOTROM</spirit:name>
+ <spirit:name>HSIZE_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3156,7 +3156,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_BOOTROM</spirit:name>
+ <spirit:name>HBURST_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3166,7 +3166,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_BOOTROM</spirit:name>
+ <spirit:name>HPROT_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3176,7 +3176,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_BOOTROM</spirit:name>
+ <spirit:name>HWDATA_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3186,25 +3186,25 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_BOOTROM</spirit:name>
+ <spirit:name>HMASTLOCK_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_BOOTROM</spirit:name>
+ <spirit:name>HREADYMUX_BOOTROM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_IMEM</spirit:name>
+ <spirit:name>HSEL_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_IMEM</spirit:name>
+ <spirit:name>HADDR_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3214,7 +3214,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_IMEM</spirit:name>
+ <spirit:name>HTRANS_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3224,13 +3224,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_IMEM</spirit:name>
+ <spirit:name>HWRITE_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_IMEM</spirit:name>
+ <spirit:name>HSIZE_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3240,7 +3240,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_IMEM</spirit:name>
+ <spirit:name>HBURST_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3250,7 +3250,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_IMEM</spirit:name>
+ <spirit:name>HPROT_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3260,7 +3260,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_IMEM</spirit:name>
+ <spirit:name>HWDATA_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3270,25 +3270,25 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_IMEM</spirit:name>
+ <spirit:name>HMASTLOCK_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_IMEM</spirit:name>
+ <spirit:name>HREADYMUX_IMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSEL_DMEM</spirit:name>
+ <spirit:name>HSEL_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HADDR_DMEM</spirit:name>
+ <spirit:name>HADDR_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3298,7 +3298,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HTRANS_DMEM</spirit:name>
+ <spirit:name>HTRANS_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3308,13 +3308,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWRITE_DMEM</spirit:name>
+ <spirit:name>HWRITE_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HSIZE_DMEM</spirit:name>
+ <spirit:name>HSIZE_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3324,7 +3324,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HBURST_DMEM</spirit:name>
+ <spirit:name>HBURST_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3334,7 +3334,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HPROT_DMEM</spirit:name>
+ <spirit:name>HPROT_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3344,7 +3344,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HWDATA_DMEM</spirit:name>
+ <spirit:name>HWDATA_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
@@ -3354,13 +3354,13 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HMASTLOCK_DMEM</spirit:name>
+ <spirit:name>HMASTLOCK_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>HREADYMUX_DMEM</spirit:name>
+ <spirit:name>HREADYMUX_DMEM_0</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
</spirit:wire>
@@ -4095,15 +4095,15 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
@@ -4135,15 +4135,15 @@
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
- <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v</spirit:name>
+ <spirit:name>../../verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v</spirit:name>
<spirit:fileType>verilogSource-2001</spirit:fileType>
</spirit:file>
<spirit:file>
diff --git a/system/nanosoc_busmatrix/logs/nanosoc.log b/system/nanosoc_busmatrix/logs/nanosoc.log
index 68f64e8cce3a5c2d8a55fc58e239ee5e542a3a66..1f19b5e72b08704298662c4245c2ef89b8f873b3 100644
--- a/system/nanosoc_busmatrix/logs/nanosoc.log
+++ b/system/nanosoc_busmatrix/logs/nanosoc.log
@@ -14,7 +14,7 @@
=
= BuildBusMatrix.pl
=
-= Run Date : 04/06/2023 13:16:41
+= Run Date : 12/06/2023 11:01:02
==============================================================
Script accepted the following parameters:
@@ -26,10 +26,10 @@ Script accepted the following parameters:
- Architecture type : 'ahb2'
- Arbitration scheme : 'burst'
- Address map : user defined
- - Connectivity mapping : _SOCDEBUG -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
- _DMAC_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
- _DMAC_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
- _CPU_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
+ - Connectivity mapping : _SOCDEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+ _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+ _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+ _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE
- Connectivity type : sparse
- Routing data width : 32
- Routing address width : 32
@@ -56,8 +56,8 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_0.v' file...
-Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMA_1.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v' file...
+Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_SOCDEBUG.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v' file...
Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v' file...
@@ -75,36 +75,36 @@ Deleting the '/home/dam1n19/accelerator-project/nanosoc_tech/system/nanosoc_busm
Creating the bus matrix variant...
- - Rendering 'nanosoc_busmatrix_lite.xml'
- - Rendering 'nanosoc_busmatrix_default_slave.v'
- - Rendering 'nanosoc_arbiter_IMEM.v'
+ - Rendering 'nanosoc_target_output_BOOTROM_0.v'
+ - Rendering 'nanosoc_target_output_SYSIO.v'
+ - Rendering 'nanosoc_target_output_EXPRAM_L.v'
+ - Rendering 'nanosoc_busmatrix_lite.v'
- Rendering 'nanosoc_matrix_decode_DMAC_0.v'
- - Rendering 'nanosoc_target_output_BOOTROM.v'
- - Rendering 'nanosoc_arbiter_BOOTROM.v'
- - Rendering 'nanosoc_target_output_SYSTABLE.v'
- Rendering 'nanosoc_target_output_EXP_2.v'
- - Rendering 'nanosoc_inititator_input.v'
- - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
- - Rendering 'nanosoc_target_output_IMEM.v'
- - Rendering 'nanosoc_target_output_EXPRAM_L.v'
- - Rendering 'nanosoc_arbiter_SYSTABLE.v'
+ - Rendering 'nanosoc_arbiter_SYSIO.v'
+ - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
+ - Rendering 'nanosoc_arbiter_BOOTROM_0.v'
+ - Rendering 'nanosoc_arbiter_EXP_1.v'
+ - Rendering 'nanosoc_arbiter_DMEM_0.v'
- Rendering 'nanosoc_target_output_EXP_1.v'
- - Rendering 'nanosoc_target_output_DMEM.v'
- - Rendering 'nanosoc_target_output_EXP_0.v'
- Rendering 'nanosoc_matrix_decode_CPU_0.v'
- - Rendering 'nanosoc_matrix_decode_SOCDEBUG.v'
- - Rendering 'nanosoc_arbiter_SYSIO.v'
- - Rendering 'nanosoc_arbiter_EXP_2.v'
+ - Rendering 'nanosoc_inititator_input.v'
- Rendering 'nanosoc_arbiter_EXP_0.v'
- - Rendering 'nanosoc_arbiter_EXPRAM_L.v'
- - Rendering 'nanosoc_busmatrix.xml'
+ - Rendering 'nanosoc_busmatrix_lite.xml'
+ - Rendering 'nanosoc_busmatrix_default_slave.v'
+ - Rendering 'nanosoc_matrix_decode_SOCDEBUG.v'
+ - Rendering 'nanosoc_target_output_EXP_0.v'
- Rendering 'nanosoc_target_output_EXPRAM_H.v'
- - Rendering 'nanosoc_arbiter_EXP_1.v'
- - Rendering 'nanosoc_busmatrix_lite.v'
- - Rendering 'nanosoc_busmatrix.v'
+ - Rendering 'nanosoc_target_output_SYSTABLE.v'
+ - Rendering 'nanosoc_target_output_DMEM_0.v'
+ - Rendering 'nanosoc_arbiter_EXP_2.v'
+ - Rendering 'nanosoc_matrix_decode_DMAC_1.v'
+ - Rendering 'nanosoc_arbiter_SYSTABLE.v'
- Rendering 'nanosoc_arbiter_EXPRAM_H.v'
- - Rendering 'nanosoc_arbiter_DMEM.v'
- - Rendering 'nanosoc_target_output_SYSIO.v'
+ - Rendering 'nanosoc_target_output_IMEM_0.v'
+ - Rendering 'nanosoc_busmatrix.v'
+ - Rendering 'nanosoc_arbiter_IMEM_0.v'
+ - Rendering 'nanosoc_busmatrix.xml'
Done!
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
index 6746db1d35847e62779caa7e92d7edd13268437f..850c0bccd60e389146d4d5d9ada76dd3ba8092f2 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_arbiter_BOOTROM (
+module nanosoc_arbiter_BOOTROM_0 (
// Common AHB signals
HCLK ,
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
index 9d473c706c70e35b87e6ee88f2b0635cd42fbced..e2559ef58dfb6eb30868b759eb77d350e435cbda 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_arbiter_DMEM (
+module nanosoc_arbiter_DMEM_0 (
// Common AHB signals
HCLK ,
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
index b69a7d194b452fa1d73f8a791f70acca9768a2c4..7e3ec3846216af3a7076d6660ab27fc38e92184a 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_arbiter_IMEM (
+module nanosoc_arbiter_IMEM_0 (
// Common AHB signals
HCLK ,
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
index baa99937bbaf742b3cc3a30787d8837be0753e51..7ab092a3d2fccce715e873de882c152bf52a8c3d 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
@@ -35,10 +35,10 @@
// - Routing data width of 32 bits,
// - Arbiter type 'burst',
// - Connectivity mapping:
-// _SOCDEBUG -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
-// _DMAC_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
-// _DMAC_1 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
-// _CPU_0 -> _BOOTROM, _IMEM, _DMEM, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+// _SOCDEBUG -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
+// _DMAC_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+// _DMAC_1 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H,
+// _CPU_0 -> _BOOTROM_0, _IMEM_0, _DMEM_0, _SYSIO, _EXP_0, _EXP_1, _EXP_2, _EXPRAM_L, _EXPRAM_H, _SYSTABLE,
// - Connectivity type 'sparse'.
//
//------------------------------------------------------------------------------
@@ -107,19 +107,19 @@ module nanosoc_busmatrix (
HREADY_CPU_0,
// Output port MI0 (inputs from slave 0)
- HRDATA_BOOTROM,
- HREADYOUT_BOOTROM,
- HRESP_BOOTROM,
+ HRDATA_BOOTROM_0,
+ HREADYOUT_BOOTROM_0,
+ HRESP_BOOTROM_0,
// Output port MI1 (inputs from slave 1)
- HRDATA_IMEM,
- HREADYOUT_IMEM,
- HRESP_IMEM,
+ HRDATA_IMEM_0,
+ HREADYOUT_IMEM_0,
+ HRESP_IMEM_0,
// Output port MI2 (inputs from slave 2)
- HRDATA_DMEM,
- HREADYOUT_DMEM,
- HRESP_DMEM,
+ HRDATA_DMEM_0,
+ HREADYOUT_DMEM_0,
+ HRESP_DMEM_0,
// Output port MI3 (inputs from slave 3)
HRDATA_SYSIO,
@@ -162,43 +162,43 @@ module nanosoc_busmatrix (
// Output port MI0 (outputs to slave 0)
- HSEL_BOOTROM,
- HADDR_BOOTROM,
- HTRANS_BOOTROM,
- HWRITE_BOOTROM,
- HSIZE_BOOTROM,
- HBURST_BOOTROM,
- HPROT_BOOTROM,
- HMASTER_BOOTROM,
- HWDATA_BOOTROM,
- HMASTLOCK_BOOTROM,
- HREADYMUX_BOOTROM,
+ HSEL_BOOTROM_0,
+ HADDR_BOOTROM_0,
+ HTRANS_BOOTROM_0,
+ HWRITE_BOOTROM_0,
+ HSIZE_BOOTROM_0,
+ HBURST_BOOTROM_0,
+ HPROT_BOOTROM_0,
+ HMASTER_BOOTROM_0,
+ HWDATA_BOOTROM_0,
+ HMASTLOCK_BOOTROM_0,
+ HREADYMUX_BOOTROM_0,
// Output port MI1 (outputs to slave 1)
- HSEL_IMEM,
- HADDR_IMEM,
- HTRANS_IMEM,
- HWRITE_IMEM,
- HSIZE_IMEM,
- HBURST_IMEM,
- HPROT_IMEM,
- HMASTER_IMEM,
- HWDATA_IMEM,
- HMASTLOCK_IMEM,
- HREADYMUX_IMEM,
+ HSEL_IMEM_0,
+ HADDR_IMEM_0,
+ HTRANS_IMEM_0,
+ HWRITE_IMEM_0,
+ HSIZE_IMEM_0,
+ HBURST_IMEM_0,
+ HPROT_IMEM_0,
+ HMASTER_IMEM_0,
+ HWDATA_IMEM_0,
+ HMASTLOCK_IMEM_0,
+ HREADYMUX_IMEM_0,
// Output port MI2 (outputs to slave 2)
- HSEL_DMEM,
- HADDR_DMEM,
- HTRANS_DMEM,
- HWRITE_DMEM,
- HSIZE_DMEM,
- HBURST_DMEM,
- HPROT_DMEM,
- HMASTER_DMEM,
- HWDATA_DMEM,
- HMASTLOCK_DMEM,
- HREADYMUX_DMEM,
+ HSEL_DMEM_0,
+ HADDR_DMEM_0,
+ HTRANS_DMEM_0,
+ HWRITE_DMEM_0,
+ HSIZE_DMEM_0,
+ HBURST_DMEM_0,
+ HPROT_DMEM_0,
+ HMASTER_DMEM_0,
+ HWDATA_DMEM_0,
+ HMASTLOCK_DMEM_0,
+ HREADYMUX_DMEM_0,
// Output port MI3 (outputs to slave 3)
HSEL_SYSIO,
@@ -381,19 +381,19 @@ module nanosoc_busmatrix (
input HREADY_CPU_0; // Transfer done
// Output port MI0 (inputs from slave 0)
- input [31:0] HRDATA_BOOTROM; // Read data bus
- input HREADYOUT_BOOTROM; // HREADY feedback
- input [1:0] HRESP_BOOTROM; // Transfer response
+ input [31:0] HRDATA_BOOTROM_0; // Read data bus
+ input HREADYOUT_BOOTROM_0; // HREADY feedback
+ input [1:0] HRESP_BOOTROM_0; // Transfer response
// Output port MI1 (inputs from slave 1)
- input [31:0] HRDATA_IMEM; // Read data bus
- input HREADYOUT_IMEM; // HREADY feedback
- input [1:0] HRESP_IMEM; // Transfer response
+ input [31:0] HRDATA_IMEM_0; // Read data bus
+ input HREADYOUT_IMEM_0; // HREADY feedback
+ input [1:0] HRESP_IMEM_0; // Transfer response
// Output port MI2 (inputs from slave 2)
- input [31:0] HRDATA_DMEM; // Read data bus
- input HREADYOUT_DMEM; // HREADY feedback
- input [1:0] HRESP_DMEM; // Transfer response
+ input [31:0] HRDATA_DMEM_0; // Read data bus
+ input HREADYOUT_DMEM_0; // HREADY feedback
+ input [1:0] HRESP_DMEM_0; // Transfer response
// Output port MI3 (inputs from slave 3)
input [31:0] HRDATA_SYSIO; // Read data bus
@@ -436,43 +436,43 @@ module nanosoc_busmatrix (
// Output port MI0 (outputs to slave 0)
- output HSEL_BOOTROM; // Slave Select
- output [31:0] HADDR_BOOTROM; // Address bus
- output [1:0] HTRANS_BOOTROM; // Transfer type
- output HWRITE_BOOTROM; // Transfer direction
- output [2:0] HSIZE_BOOTROM; // Transfer size
- output [2:0] HBURST_BOOTROM; // Burst type
- output [3:0] HPROT_BOOTROM; // Protection control
- output [3:0] HMASTER_BOOTROM; // Master select
- output [31:0] HWDATA_BOOTROM; // Write data
- output HMASTLOCK_BOOTROM; // Locked Sequence
- output HREADYMUX_BOOTROM; // Transfer done
+ output HSEL_BOOTROM_0; // Slave Select
+ output [31:0] HADDR_BOOTROM_0; // Address bus
+ output [1:0] HTRANS_BOOTROM_0; // Transfer type
+ output HWRITE_BOOTROM_0; // Transfer direction
+ output [2:0] HSIZE_BOOTROM_0; // Transfer size
+ output [2:0] HBURST_BOOTROM_0; // Burst type
+ output [3:0] HPROT_BOOTROM_0; // Protection control
+ output [3:0] HMASTER_BOOTROM_0; // Master select
+ output [31:0] HWDATA_BOOTROM_0; // Write data
+ output HMASTLOCK_BOOTROM_0; // Locked Sequence
+ output HREADYMUX_BOOTROM_0; // Transfer done
// Output port MI1 (outputs to slave 1)
- output HSEL_IMEM; // Slave Select
- output [31:0] HADDR_IMEM; // Address bus
- output [1:0] HTRANS_IMEM; // Transfer type
- output HWRITE_IMEM; // Transfer direction
- output [2:0] HSIZE_IMEM; // Transfer size
- output [2:0] HBURST_IMEM; // Burst type
- output [3:0] HPROT_IMEM; // Protection control
- output [3:0] HMASTER_IMEM; // Master select
- output [31:0] HWDATA_IMEM; // Write data
- output HMASTLOCK_IMEM; // Locked Sequence
- output HREADYMUX_IMEM; // Transfer done
+ output HSEL_IMEM_0; // Slave Select
+ output [31:0] HADDR_IMEM_0; // Address bus
+ output [1:0] HTRANS_IMEM_0; // Transfer type
+ output HWRITE_IMEM_0; // Transfer direction
+ output [2:0] HSIZE_IMEM_0; // Transfer size
+ output [2:0] HBURST_IMEM_0; // Burst type
+ output [3:0] HPROT_IMEM_0; // Protection control
+ output [3:0] HMASTER_IMEM_0; // Master select
+ output [31:0] HWDATA_IMEM_0; // Write data
+ output HMASTLOCK_IMEM_0; // Locked Sequence
+ output HREADYMUX_IMEM_0; // Transfer done
// Output port MI2 (outputs to slave 2)
- output HSEL_DMEM; // Slave Select
- output [31:0] HADDR_DMEM; // Address bus
- output [1:0] HTRANS_DMEM; // Transfer type
- output HWRITE_DMEM; // Transfer direction
- output [2:0] HSIZE_DMEM; // Transfer size
- output [2:0] HBURST_DMEM; // Burst type
- output [3:0] HPROT_DMEM; // Protection control
- output [3:0] HMASTER_DMEM; // Master select
- output [31:0] HWDATA_DMEM; // Write data
- output HMASTLOCK_DMEM; // Locked Sequence
- output HREADYMUX_DMEM; // Transfer done
+ output HSEL_DMEM_0; // Slave Select
+ output [31:0] HADDR_DMEM_0; // Address bus
+ output [1:0] HTRANS_DMEM_0; // Transfer type
+ output HWRITE_DMEM_0; // Transfer direction
+ output [2:0] HSIZE_DMEM_0; // Transfer size
+ output [2:0] HBURST_DMEM_0; // Burst type
+ output [3:0] HPROT_DMEM_0; // Protection control
+ output [3:0] HMASTER_DMEM_0; // Master select
+ output [31:0] HWDATA_DMEM_0; // Write data
+ output HMASTLOCK_DMEM_0; // Locked Sequence
+ output HREADYMUX_DMEM_0; // Transfer done
// Output port MI3 (outputs to slave 3)
output HSEL_SYSIO; // Slave Select
@@ -669,55 +669,55 @@ module nanosoc_busmatrix (
wire [1:0] HRESP_CPU_0; // Transfer response
// Output Port MI0
- wire HSEL_BOOTROM; // Slave Select
- wire [31:0] HADDR_BOOTROM; // Address bus
- wire [1:0] HTRANS_BOOTROM; // Transfer type
- wire HWRITE_BOOTROM; // Transfer direction
- wire [2:0] HSIZE_BOOTROM; // Transfer size
- wire [2:0] HBURST_BOOTROM; // Burst type
- wire [3:0] HPROT_BOOTROM; // Protection control
- wire [3:0] HMASTER_BOOTROM; // Master select
- wire [31:0] HWDATA_BOOTROM; // Write data
- wire HMASTLOCK_BOOTROM; // Locked Sequence
- wire HREADYMUX_BOOTROM; // Transfer done
-
- wire [31:0] HRDATA_BOOTROM; // Read data bus
- wire HREADYOUT_BOOTROM; // HREADY feedback
- wire [1:0] HRESP_BOOTROM; // Transfer response
+ wire HSEL_BOOTROM_0; // Slave Select
+ wire [31:0] HADDR_BOOTROM_0; // Address bus
+ wire [1:0] HTRANS_BOOTROM_0; // Transfer type
+ wire HWRITE_BOOTROM_0; // Transfer direction
+ wire [2:0] HSIZE_BOOTROM_0; // Transfer size
+ wire [2:0] HBURST_BOOTROM_0; // Burst type
+ wire [3:0] HPROT_BOOTROM_0; // Protection control
+ wire [3:0] HMASTER_BOOTROM_0; // Master select
+ wire [31:0] HWDATA_BOOTROM_0; // Write data
+ wire HMASTLOCK_BOOTROM_0; // Locked Sequence
+ wire HREADYMUX_BOOTROM_0; // Transfer done
+
+ wire [31:0] HRDATA_BOOTROM_0; // Read data bus
+ wire HREADYOUT_BOOTROM_0; // HREADY feedback
+ wire [1:0] HRESP_BOOTROM_0; // Transfer response
// Output Port MI1
- wire HSEL_IMEM; // Slave Select
- wire [31:0] HADDR_IMEM; // Address bus
- wire [1:0] HTRANS_IMEM; // Transfer type
- wire HWRITE_IMEM; // Transfer direction
- wire [2:0] HSIZE_IMEM; // Transfer size
- wire [2:0] HBURST_IMEM; // Burst type
- wire [3:0] HPROT_IMEM; // Protection control
- wire [3:0] HMASTER_IMEM; // Master select
- wire [31:0] HWDATA_IMEM; // Write data
- wire HMASTLOCK_IMEM; // Locked Sequence
- wire HREADYMUX_IMEM; // Transfer done
-
- wire [31:0] HRDATA_IMEM; // Read data bus
- wire HREADYOUT_IMEM; // HREADY feedback
- wire [1:0] HRESP_IMEM; // Transfer response
+ wire HSEL_IMEM_0; // Slave Select
+ wire [31:0] HADDR_IMEM_0; // Address bus
+ wire [1:0] HTRANS_IMEM_0; // Transfer type
+ wire HWRITE_IMEM_0; // Transfer direction
+ wire [2:0] HSIZE_IMEM_0; // Transfer size
+ wire [2:0] HBURST_IMEM_0; // Burst type
+ wire [3:0] HPROT_IMEM_0; // Protection control
+ wire [3:0] HMASTER_IMEM_0; // Master select
+ wire [31:0] HWDATA_IMEM_0; // Write data
+ wire HMASTLOCK_IMEM_0; // Locked Sequence
+ wire HREADYMUX_IMEM_0; // Transfer done
+
+ wire [31:0] HRDATA_IMEM_0; // Read data bus
+ wire HREADYOUT_IMEM_0; // HREADY feedback
+ wire [1:0] HRESP_IMEM_0; // Transfer response
// Output Port MI2
- wire HSEL_DMEM; // Slave Select
- wire [31:0] HADDR_DMEM; // Address bus
- wire [1:0] HTRANS_DMEM; // Transfer type
- wire HWRITE_DMEM; // Transfer direction
- wire [2:0] HSIZE_DMEM; // Transfer size
- wire [2:0] HBURST_DMEM; // Burst type
- wire [3:0] HPROT_DMEM; // Protection control
- wire [3:0] HMASTER_DMEM; // Master select
- wire [31:0] HWDATA_DMEM; // Write data
- wire HMASTLOCK_DMEM; // Locked Sequence
- wire HREADYMUX_DMEM; // Transfer done
-
- wire [31:0] HRDATA_DMEM; // Read data bus
- wire HREADYOUT_DMEM; // HREADY feedback
- wire [1:0] HRESP_DMEM; // Transfer response
+ wire HSEL_DMEM_0; // Slave Select
+ wire [31:0] HADDR_DMEM_0; // Address bus
+ wire [1:0] HTRANS_DMEM_0; // Transfer type
+ wire HWRITE_DMEM_0; // Transfer direction
+ wire [2:0] HSIZE_DMEM_0; // Transfer size
+ wire [2:0] HBURST_DMEM_0; // Burst type
+ wire [3:0] HPROT_DMEM_0; // Protection control
+ wire [3:0] HMASTER_DMEM_0; // Master select
+ wire [31:0] HWDATA_DMEM_0; // Write data
+ wire HMASTLOCK_DMEM_0; // Locked Sequence
+ wire HREADYMUX_DMEM_0; // Transfer done
+
+ wire [31:0] HRDATA_DMEM_0; // Read data bus
+ wire HREADYOUT_DMEM_0; // HREADY feedback
+ wire [1:0] HRESP_DMEM_0; // Transfer response
// Output Port MI3
wire HSEL_SYSIO; // Slave Select
@@ -1055,9 +1055,9 @@ module nanosoc_busmatrix (
wire i_sel3to9; // Routing selection signal
wire i_active3to9; // Active signal
- wire i_hready_mux__bootrom; // Internal HREADYMUXM for MI0
- wire i_hready_mux__imem; // Internal HREADYMUXM for MI1
- wire i_hready_mux__dmem; // Internal HREADYMUXM for MI2
+ wire i_hready_mux__bootrom_0; // Internal HREADYMUXM for MI0
+ wire i_hready_mux__imem_0; // Internal HREADYMUXM for MI1
+ wire i_hready_mux__dmem_0; // Internal HREADYMUXM for MI2
wire i_hready_mux__sysio; // Internal HREADYMUXM for MI3
wire i_hready_mux__expram_l; // Internal HREADYMUXM for MI4
wire i_hready_mux__expram_h; // Internal HREADYMUXM for MI5
@@ -1261,21 +1261,21 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI0
.active_dec0 (i_active0to0),
- .readyout_dec0 (i_hready_mux__bootrom),
- .resp_dec0 (HRESP_BOOTROM),
- .rdata_dec0 (HRDATA_BOOTROM),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
// Control/Response for Output Stage MI1
.active_dec1 (i_active0to1),
- .readyout_dec1 (i_hready_mux__imem),
- .resp_dec1 (HRESP_IMEM),
- .rdata_dec1 (HRDATA_IMEM),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active0to2),
- .readyout_dec2 (i_hready_mux__dmem),
- .resp_dec2 (HRESP_DMEM),
- .rdata_dec2 (HRDATA_DMEM),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active0to3),
@@ -1353,21 +1353,21 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI0
.active_dec0 (i_active1to0),
- .readyout_dec0 (i_hready_mux__bootrom),
- .resp_dec0 (HRESP_BOOTROM),
- .rdata_dec0 (HRDATA_BOOTROM),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
// Control/Response for Output Stage MI1
.active_dec1 (i_active1to1),
- .readyout_dec1 (i_hready_mux__imem),
- .resp_dec1 (HRESP_IMEM),
- .rdata_dec1 (HRDATA_IMEM),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active1to2),
- .readyout_dec2 (i_hready_mux__dmem),
- .resp_dec2 (HRESP_DMEM),
- .rdata_dec2 (HRDATA_DMEM),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active1to3),
@@ -1438,21 +1438,21 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI0
.active_dec0 (i_active2to0),
- .readyout_dec0 (i_hready_mux__bootrom),
- .resp_dec0 (HRESP_BOOTROM),
- .rdata_dec0 (HRDATA_BOOTROM),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
// Control/Response for Output Stage MI1
.active_dec1 (i_active2to1),
- .readyout_dec1 (i_hready_mux__imem),
- .resp_dec1 (HRESP_IMEM),
- .rdata_dec1 (HRDATA_IMEM),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active2to2),
- .readyout_dec2 (i_hready_mux__dmem),
- .resp_dec2 (HRESP_DMEM),
- .rdata_dec2 (HRDATA_DMEM),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active2to3),
@@ -1526,21 +1526,21 @@ module nanosoc_busmatrix (
// Control/Response for Output Stage MI0
.active_dec0 (i_active3to0),
- .readyout_dec0 (i_hready_mux__bootrom),
- .resp_dec0 (HRESP_BOOTROM),
- .rdata_dec0 (HRDATA_BOOTROM),
+ .readyout_dec0 (i_hready_mux__bootrom_0),
+ .resp_dec0 (HRESP_BOOTROM_0),
+ .rdata_dec0 (HRDATA_BOOTROM_0),
// Control/Response for Output Stage MI1
.active_dec1 (i_active3to1),
- .readyout_dec1 (i_hready_mux__imem),
- .resp_dec1 (HRESP_IMEM),
- .rdata_dec1 (HRDATA_IMEM),
+ .readyout_dec1 (i_hready_mux__imem_0),
+ .resp_dec1 (HRESP_IMEM_0),
+ .rdata_dec1 (HRDATA_IMEM_0),
// Control/Response for Output Stage MI2
.active_dec2 (i_active3to2),
- .readyout_dec2 (i_hready_mux__dmem),
- .resp_dec2 (HRESP_DMEM),
- .rdata_dec2 (HRDATA_DMEM),
+ .readyout_dec2 (i_hready_mux__dmem_0),
+ .resp_dec2 (HRESP_DMEM_0),
+ .rdata_dec2 (HRDATA_DMEM_0),
// Control/Response for Output Stage MI3
.active_dec3 (i_active3to3),
@@ -1604,7 +1604,7 @@ module nanosoc_busmatrix (
// Output stage for MI0
- nanosoc_target_output_BOOTROM u_nanosoc_target_output_bootrom_0 (
+ nanosoc_target_output_BOOTROM_0 u_nanosoc_target_output_bootrom_0_0 (
// Common AHB signals
.HCLK (HCLK),
@@ -1663,7 +1663,7 @@ module nanosoc_busmatrix (
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_BOOTROM),
+ .HREADYOUTM (HREADYOUT_BOOTROM_0),
.active_op0 (i_active0to0),
.active_op1 (i_active1to0),
@@ -1671,26 +1671,26 @@ module nanosoc_busmatrix (
.active_op3 (i_active3to0),
// Slave Address/Control Signals
- .HSELM (HSEL_BOOTROM),
- .HADDRM (HADDR_BOOTROM),
- .HTRANSM (HTRANS_BOOTROM),
- .HWRITEM (HWRITE_BOOTROM),
- .HSIZEM (HSIZE_BOOTROM),
- .HBURSTM (HBURST_BOOTROM),
- .HPROTM (HPROT_BOOTROM),
- .HMASTERM (HMASTER_BOOTROM),
- .HMASTLOCKM (HMASTLOCK_BOOTROM),
- .HREADYMUXM (i_hready_mux__bootrom),
- .HWDATAM (HWDATA_BOOTROM)
+ .HSELM (HSEL_BOOTROM_0),
+ .HADDRM (HADDR_BOOTROM_0),
+ .HTRANSM (HTRANS_BOOTROM_0),
+ .HWRITEM (HWRITE_BOOTROM_0),
+ .HSIZEM (HSIZE_BOOTROM_0),
+ .HBURSTM (HBURST_BOOTROM_0),
+ .HPROTM (HPROT_BOOTROM_0),
+ .HMASTERM (HMASTER_BOOTROM_0),
+ .HMASTLOCKM (HMASTLOCK_BOOTROM_0),
+ .HREADYMUXM (i_hready_mux__bootrom_0),
+ .HWDATAM (HWDATA_BOOTROM_0)
);
// Drive output with internal version
- assign HREADYMUX_BOOTROM = i_hready_mux__bootrom;
+ assign HREADYMUX_BOOTROM_0 = i_hready_mux__bootrom_0;
// Output stage for MI1
- nanosoc_target_output_IMEM u_nanosoc_target_output_imem_1 (
+ nanosoc_target_output_IMEM_0 u_nanosoc_target_output_imem_0_1 (
// Common AHB signals
.HCLK (HCLK),
@@ -1749,7 +1749,7 @@ module nanosoc_busmatrix (
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_IMEM),
+ .HREADYOUTM (HREADYOUT_IMEM_0),
.active_op0 (i_active0to1),
.active_op1 (i_active1to1),
@@ -1757,26 +1757,26 @@ module nanosoc_busmatrix (
.active_op3 (i_active3to1),
// Slave Address/Control Signals
- .HSELM (HSEL_IMEM),
- .HADDRM (HADDR_IMEM),
- .HTRANSM (HTRANS_IMEM),
- .HWRITEM (HWRITE_IMEM),
- .HSIZEM (HSIZE_IMEM),
- .HBURSTM (HBURST_IMEM),
- .HPROTM (HPROT_IMEM),
- .HMASTERM (HMASTER_IMEM),
- .HMASTLOCKM (HMASTLOCK_IMEM),
- .HREADYMUXM (i_hready_mux__imem),
- .HWDATAM (HWDATA_IMEM)
+ .HSELM (HSEL_IMEM_0),
+ .HADDRM (HADDR_IMEM_0),
+ .HTRANSM (HTRANS_IMEM_0),
+ .HWRITEM (HWRITE_IMEM_0),
+ .HSIZEM (HSIZE_IMEM_0),
+ .HBURSTM (HBURST_IMEM_0),
+ .HPROTM (HPROT_IMEM_0),
+ .HMASTERM (HMASTER_IMEM_0),
+ .HMASTLOCKM (HMASTLOCK_IMEM_0),
+ .HREADYMUXM (i_hready_mux__imem_0),
+ .HWDATAM (HWDATA_IMEM_0)
);
// Drive output with internal version
- assign HREADYMUX_IMEM = i_hready_mux__imem;
+ assign HREADYMUX_IMEM_0 = i_hready_mux__imem_0;
// Output stage for MI2
- nanosoc_target_output_DMEM u_nanosoc_target_output_dmem_2 (
+ nanosoc_target_output_DMEM_0 u_nanosoc_target_output_dmem_0_2 (
// Common AHB signals
.HCLK (HCLK),
@@ -1835,7 +1835,7 @@ module nanosoc_busmatrix (
.held_tran_op3 (i_held_tran3),
// Slave read data and response
- .HREADYOUTM (HREADYOUT_DMEM),
+ .HREADYOUTM (HREADYOUT_DMEM_0),
.active_op0 (i_active0to2),
.active_op1 (i_active1to2),
@@ -1843,22 +1843,22 @@ module nanosoc_busmatrix (
.active_op3 (i_active3to2),
// Slave Address/Control Signals
- .HSELM (HSEL_DMEM),
- .HADDRM (HADDR_DMEM),
- .HTRANSM (HTRANS_DMEM),
- .HWRITEM (HWRITE_DMEM),
- .HSIZEM (HSIZE_DMEM),
- .HBURSTM (HBURST_DMEM),
- .HPROTM (HPROT_DMEM),
- .HMASTERM (HMASTER_DMEM),
- .HMASTLOCKM (HMASTLOCK_DMEM),
- .HREADYMUXM (i_hready_mux__dmem),
- .HWDATAM (HWDATA_DMEM)
+ .HSELM (HSEL_DMEM_0),
+ .HADDRM (HADDR_DMEM_0),
+ .HTRANSM (HTRANS_DMEM_0),
+ .HWRITEM (HWRITE_DMEM_0),
+ .HSIZEM (HSIZE_DMEM_0),
+ .HBURSTM (HBURST_DMEM_0),
+ .HPROTM (HPROT_DMEM_0),
+ .HMASTERM (HMASTER_DMEM_0),
+ .HMASTLOCKM (HMASTLOCK_DMEM_0),
+ .HREADYMUXM (i_hready_mux__dmem_0),
+ .HWDATAM (HWDATA_DMEM_0)
);
// Drive output with internal version
- assign HREADYMUX_DMEM = i_hready_mux__dmem;
+ assign HREADYMUX_DMEM_0 = i_hready_mux__dmem_0;
// Output stage for MI3
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
index 1a00f814071f9a6452df7f78d39b10de221fa218..68a8cf55783a678d7cd57f299ab3a8d644c9daba 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
@@ -80,19 +80,19 @@ module nanosoc_busmatrix_lite (
HMASTLOCK_CPU_0,
// Output port MI0 (inputs from slave 0)
- HRDATA_BOOTROM,
- HREADYOUT_BOOTROM,
- HRESP_BOOTROM,
+ HRDATA_BOOTROM_0,
+ HREADYOUT_BOOTROM_0,
+ HRESP_BOOTROM_0,
// Output port MI1 (inputs from slave 1)
- HRDATA_IMEM,
- HREADYOUT_IMEM,
- HRESP_IMEM,
+ HRDATA_IMEM_0,
+ HREADYOUT_IMEM_0,
+ HRESP_IMEM_0,
// Output port MI2 (inputs from slave 2)
- HRDATA_DMEM,
- HREADYOUT_DMEM,
- HRESP_DMEM,
+ HRDATA_DMEM_0,
+ HREADYOUT_DMEM_0,
+ HRESP_DMEM_0,
// Output port MI3 (inputs from slave 3)
HRDATA_SYSIO,
@@ -135,40 +135,40 @@ module nanosoc_busmatrix_lite (
// Output port MI0 (outputs to slave 0)
- HSEL_BOOTROM,
- HADDR_BOOTROM,
- HTRANS_BOOTROM,
- HWRITE_BOOTROM,
- HSIZE_BOOTROM,
- HBURST_BOOTROM,
- HPROT_BOOTROM,
- HWDATA_BOOTROM,
- HMASTLOCK_BOOTROM,
- HREADYMUX_BOOTROM,
+ HSEL_BOOTROM_0,
+ HADDR_BOOTROM_0,
+ HTRANS_BOOTROM_0,
+ HWRITE_BOOTROM_0,
+ HSIZE_BOOTROM_0,
+ HBURST_BOOTROM_0,
+ HPROT_BOOTROM_0,
+ HWDATA_BOOTROM_0,
+ HMASTLOCK_BOOTROM_0,
+ HREADYMUX_BOOTROM_0,
// Output port MI1 (outputs to slave 1)
- HSEL_IMEM,
- HADDR_IMEM,
- HTRANS_IMEM,
- HWRITE_IMEM,
- HSIZE_IMEM,
- HBURST_IMEM,
- HPROT_IMEM,
- HWDATA_IMEM,
- HMASTLOCK_IMEM,
- HREADYMUX_IMEM,
+ HSEL_IMEM_0,
+ HADDR_IMEM_0,
+ HTRANS_IMEM_0,
+ HWRITE_IMEM_0,
+ HSIZE_IMEM_0,
+ HBURST_IMEM_0,
+ HPROT_IMEM_0,
+ HWDATA_IMEM_0,
+ HMASTLOCK_IMEM_0,
+ HREADYMUX_IMEM_0,
// Output port MI2 (outputs to slave 2)
- HSEL_DMEM,
- HADDR_DMEM,
- HTRANS_DMEM,
- HWRITE_DMEM,
- HSIZE_DMEM,
- HBURST_DMEM,
- HPROT_DMEM,
- HWDATA_DMEM,
- HMASTLOCK_DMEM,
- HREADYMUX_DMEM,
+ HSEL_DMEM_0,
+ HADDR_DMEM_0,
+ HTRANS_DMEM_0,
+ HWRITE_DMEM_0,
+ HSIZE_DMEM_0,
+ HBURST_DMEM_0,
+ HPROT_DMEM_0,
+ HWDATA_DMEM_0,
+ HMASTLOCK_DMEM_0,
+ HREADYMUX_DMEM_0,
// Output port MI3 (outputs to slave 3)
HSEL_SYSIO,
@@ -331,19 +331,19 @@ module nanosoc_busmatrix_lite (
input HMASTLOCK_CPU_0; // Locked Sequence
// Output port MI0 (inputs from slave 0)
- input [31:0] HRDATA_BOOTROM; // Read data bus
- input HREADYOUT_BOOTROM; // HREADY feedback
- input HRESP_BOOTROM; // Transfer response
+ input [31:0] HRDATA_BOOTROM_0; // Read data bus
+ input HREADYOUT_BOOTROM_0; // HREADY feedback
+ input HRESP_BOOTROM_0; // Transfer response
// Output port MI1 (inputs from slave 1)
- input [31:0] HRDATA_IMEM; // Read data bus
- input HREADYOUT_IMEM; // HREADY feedback
- input HRESP_IMEM; // Transfer response
+ input [31:0] HRDATA_IMEM_0; // Read data bus
+ input HREADYOUT_IMEM_0; // HREADY feedback
+ input HRESP_IMEM_0; // Transfer response
// Output port MI2 (inputs from slave 2)
- input [31:0] HRDATA_DMEM; // Read data bus
- input HREADYOUT_DMEM; // HREADY feedback
- input HRESP_DMEM; // Transfer response
+ input [31:0] HRDATA_DMEM_0; // Read data bus
+ input HREADYOUT_DMEM_0; // HREADY feedback
+ input HRESP_DMEM_0; // Transfer response
// Output port MI3 (inputs from slave 3)
input [31:0] HRDATA_SYSIO; // Read data bus
@@ -386,40 +386,40 @@ module nanosoc_busmatrix_lite (
// Output port MI0 (outputs to slave 0)
- output HSEL_BOOTROM; // Slave Select
- output [31:0] HADDR_BOOTROM; // Address bus
- output [1:0] HTRANS_BOOTROM; // Transfer type
- output HWRITE_BOOTROM; // Transfer direction
- output [2:0] HSIZE_BOOTROM; // Transfer size
- output [2:0] HBURST_BOOTROM; // Burst type
- output [3:0] HPROT_BOOTROM; // Protection control
- output [31:0] HWDATA_BOOTROM; // Write data
- output HMASTLOCK_BOOTROM; // Locked Sequence
- output HREADYMUX_BOOTROM; // Transfer done
+ output HSEL_BOOTROM_0; // Slave Select
+ output [31:0] HADDR_BOOTROM_0; // Address bus
+ output [1:0] HTRANS_BOOTROM_0; // Transfer type
+ output HWRITE_BOOTROM_0; // Transfer direction
+ output [2:0] HSIZE_BOOTROM_0; // Transfer size
+ output [2:0] HBURST_BOOTROM_0; // Burst type
+ output [3:0] HPROT_BOOTROM_0; // Protection control
+ output [31:0] HWDATA_BOOTROM_0; // Write data
+ output HMASTLOCK_BOOTROM_0; // Locked Sequence
+ output HREADYMUX_BOOTROM_0; // Transfer done
// Output port MI1 (outputs to slave 1)
- output HSEL_IMEM; // Slave Select
- output [31:0] HADDR_IMEM; // Address bus
- output [1:0] HTRANS_IMEM; // Transfer type
- output HWRITE_IMEM; // Transfer direction
- output [2:0] HSIZE_IMEM; // Transfer size
- output [2:0] HBURST_IMEM; // Burst type
- output [3:0] HPROT_IMEM; // Protection control
- output [31:0] HWDATA_IMEM; // Write data
- output HMASTLOCK_IMEM; // Locked Sequence
- output HREADYMUX_IMEM; // Transfer done
+ output HSEL_IMEM_0; // Slave Select
+ output [31:0] HADDR_IMEM_0; // Address bus
+ output [1:0] HTRANS_IMEM_0; // Transfer type
+ output HWRITE_IMEM_0; // Transfer direction
+ output [2:0] HSIZE_IMEM_0; // Transfer size
+ output [2:0] HBURST_IMEM_0; // Burst type
+ output [3:0] HPROT_IMEM_0; // Protection control
+ output [31:0] HWDATA_IMEM_0; // Write data
+ output HMASTLOCK_IMEM_0; // Locked Sequence
+ output HREADYMUX_IMEM_0; // Transfer done
// Output port MI2 (outputs to slave 2)
- output HSEL_DMEM; // Slave Select
- output [31:0] HADDR_DMEM; // Address bus
- output [1:0] HTRANS_DMEM; // Transfer type
- output HWRITE_DMEM; // Transfer direction
- output [2:0] HSIZE_DMEM; // Transfer size
- output [2:0] HBURST_DMEM; // Burst type
- output [3:0] HPROT_DMEM; // Protection control
- output [31:0] HWDATA_DMEM; // Write data
- output HMASTLOCK_DMEM; // Locked Sequence
- output HREADYMUX_DMEM; // Transfer done
+ output HSEL_DMEM_0; // Slave Select
+ output [31:0] HADDR_DMEM_0; // Address bus
+ output [1:0] HTRANS_DMEM_0; // Transfer type
+ output HWRITE_DMEM_0; // Transfer direction
+ output [2:0] HSIZE_DMEM_0; // Transfer size
+ output [2:0] HBURST_DMEM_0; // Burst type
+ output [3:0] HPROT_DMEM_0; // Protection control
+ output [31:0] HWDATA_DMEM_0; // Write data
+ output HMASTLOCK_DMEM_0; // Locked Sequence
+ output HREADYMUX_DMEM_0; // Transfer done
// Output port MI3 (outputs to slave 3)
output HSEL_SYSIO; // Slave Select
@@ -596,52 +596,52 @@ module nanosoc_busmatrix_lite (
wire HRESP_CPU_0; // Transfer response
// Output Port MI0
- wire HSEL_BOOTROM; // Slave Select
- wire [31:0] HADDR_BOOTROM; // Address bus
- wire [1:0] HTRANS_BOOTROM; // Transfer type
- wire HWRITE_BOOTROM; // Transfer direction
- wire [2:0] HSIZE_BOOTROM; // Transfer size
- wire [2:0] HBURST_BOOTROM; // Burst type
- wire [3:0] HPROT_BOOTROM; // Protection control
- wire [31:0] HWDATA_BOOTROM; // Write data
- wire HMASTLOCK_BOOTROM; // Locked Sequence
- wire HREADYMUX_BOOTROM; // Transfer done
-
- wire [31:0] HRDATA_BOOTROM; // Read data bus
- wire HREADYOUT_BOOTROM; // HREADY feedback
- wire HRESP_BOOTROM; // Transfer response
+ wire HSEL_BOOTROM_0; // Slave Select
+ wire [31:0] HADDR_BOOTROM_0; // Address bus
+ wire [1:0] HTRANS_BOOTROM_0; // Transfer type
+ wire HWRITE_BOOTROM_0; // Transfer direction
+ wire [2:0] HSIZE_BOOTROM_0; // Transfer size
+ wire [2:0] HBURST_BOOTROM_0; // Burst type
+ wire [3:0] HPROT_BOOTROM_0; // Protection control
+ wire [31:0] HWDATA_BOOTROM_0; // Write data
+ wire HMASTLOCK_BOOTROM_0; // Locked Sequence
+ wire HREADYMUX_BOOTROM_0; // Transfer done
+
+ wire [31:0] HRDATA_BOOTROM_0; // Read data bus
+ wire HREADYOUT_BOOTROM_0; // HREADY feedback
+ wire HRESP_BOOTROM_0; // Transfer response
// Output Port MI1
- wire HSEL_IMEM; // Slave Select
- wire [31:0] HADDR_IMEM; // Address bus
- wire [1:0] HTRANS_IMEM; // Transfer type
- wire HWRITE_IMEM; // Transfer direction
- wire [2:0] HSIZE_IMEM; // Transfer size
- wire [2:0] HBURST_IMEM; // Burst type
- wire [3:0] HPROT_IMEM; // Protection control
- wire [31:0] HWDATA_IMEM; // Write data
- wire HMASTLOCK_IMEM; // Locked Sequence
- wire HREADYMUX_IMEM; // Transfer done
-
- wire [31:0] HRDATA_IMEM; // Read data bus
- wire HREADYOUT_IMEM; // HREADY feedback
- wire HRESP_IMEM; // Transfer response
+ wire HSEL_IMEM_0; // Slave Select
+ wire [31:0] HADDR_IMEM_0; // Address bus
+ wire [1:0] HTRANS_IMEM_0; // Transfer type
+ wire HWRITE_IMEM_0; // Transfer direction
+ wire [2:0] HSIZE_IMEM_0; // Transfer size
+ wire [2:0] HBURST_IMEM_0; // Burst type
+ wire [3:0] HPROT_IMEM_0; // Protection control
+ wire [31:0] HWDATA_IMEM_0; // Write data
+ wire HMASTLOCK_IMEM_0; // Locked Sequence
+ wire HREADYMUX_IMEM_0; // Transfer done
+
+ wire [31:0] HRDATA_IMEM_0; // Read data bus
+ wire HREADYOUT_IMEM_0; // HREADY feedback
+ wire HRESP_IMEM_0; // Transfer response
// Output Port MI2
- wire HSEL_DMEM; // Slave Select
- wire [31:0] HADDR_DMEM; // Address bus
- wire [1:0] HTRANS_DMEM; // Transfer type
- wire HWRITE_DMEM; // Transfer direction
- wire [2:0] HSIZE_DMEM; // Transfer size
- wire [2:0] HBURST_DMEM; // Burst type
- wire [3:0] HPROT_DMEM; // Protection control
- wire [31:0] HWDATA_DMEM; // Write data
- wire HMASTLOCK_DMEM; // Locked Sequence
- wire HREADYMUX_DMEM; // Transfer done
-
- wire [31:0] HRDATA_DMEM; // Read data bus
- wire HREADYOUT_DMEM; // HREADY feedback
- wire HRESP_DMEM; // Transfer response
+ wire HSEL_DMEM_0; // Slave Select
+ wire [31:0] HADDR_DMEM_0; // Address bus
+ wire [1:0] HTRANS_DMEM_0; // Transfer type
+ wire HWRITE_DMEM_0; // Transfer direction
+ wire [2:0] HSIZE_DMEM_0; // Transfer size
+ wire [2:0] HBURST_DMEM_0; // Burst type
+ wire [3:0] HPROT_DMEM_0; // Protection control
+ wire [31:0] HWDATA_DMEM_0; // Write data
+ wire HMASTLOCK_DMEM_0; // Locked Sequence
+ wire HREADYMUX_DMEM_0; // Transfer done
+
+ wire [31:0] HRDATA_DMEM_0; // Read data bus
+ wire HREADYOUT_DMEM_0; // HREADY feedback
+ wire HRESP_DMEM_0; // Transfer response
// Output Port MI3
wire HSEL_SYSIO; // Slave Select
@@ -767,12 +767,12 @@ module nanosoc_busmatrix_lite (
wire [1:0] i_hresp_DMAC_1;
wire [1:0] i_hresp_CPU_0;
- wire [3:0] i_hmaster_BOOTROM;
- wire [1:0] i_hresp_BOOTROM;
- wire [3:0] i_hmaster_IMEM;
- wire [1:0] i_hresp_IMEM;
- wire [3:0] i_hmaster_DMEM;
- wire [1:0] i_hresp_DMEM;
+ wire [3:0] i_hmaster_BOOTROM_0;
+ wire [1:0] i_hresp_BOOTROM_0;
+ wire [3:0] i_hmaster_IMEM_0;
+ wire [1:0] i_hresp_IMEM_0;
+ wire [3:0] i_hmaster_DMEM_0;
+ wire [1:0] i_hresp_DMEM_0;
wire [3:0] i_hmaster_SYSIO;
wire [1:0] i_hresp_SYSIO;
wire [3:0] i_hmaster_EXPRAM_L;
@@ -805,9 +805,9 @@ module nanosoc_busmatrix_lite (
assign HRESP_CPU_0 = i_hresp_CPU_0[0];
- assign i_hresp_BOOTROM = {{1{tie_low}}, HRESP_BOOTROM};
- assign i_hresp_IMEM = {{1{tie_low}}, HRESP_IMEM};
- assign i_hresp_DMEM = {{1{tie_low}}, HRESP_DMEM};
+ assign i_hresp_BOOTROM_0 = {{1{tie_low}}, HRESP_BOOTROM_0};
+ assign i_hresp_IMEM_0 = {{1{tie_low}}, HRESP_IMEM_0};
+ assign i_hresp_DMEM_0 = {{1{tie_low}}, HRESP_DMEM_0};
assign i_hresp_SYSIO = {{1{tie_low}}, HRESP_SYSIO};
assign i_hresp_EXPRAM_L = {{1{tie_low}}, HRESP_EXPRAM_L};
assign i_hresp_EXPRAM_H = {{1{tie_low}}, HRESP_EXPRAM_H};
@@ -888,52 +888,52 @@ module nanosoc_busmatrix_lite (
// Output port MI0 signals
- .HSEL_BOOTROM (HSEL_BOOTROM),
- .HADDR_BOOTROM (HADDR_BOOTROM),
- .HTRANS_BOOTROM (HTRANS_BOOTROM),
- .HWRITE_BOOTROM (HWRITE_BOOTROM),
- .HSIZE_BOOTROM (HSIZE_BOOTROM),
- .HBURST_BOOTROM (HBURST_BOOTROM),
- .HPROT_BOOTROM (HPROT_BOOTROM),
- .HWDATA_BOOTROM (HWDATA_BOOTROM),
- .HMASTER_BOOTROM (i_hmaster_BOOTROM),
- .HMASTLOCK_BOOTROM (HMASTLOCK_BOOTROM),
- .HREADYMUX_BOOTROM (HREADYMUX_BOOTROM),
- .HRDATA_BOOTROM (HRDATA_BOOTROM),
- .HREADYOUT_BOOTROM (HREADYOUT_BOOTROM),
- .HRESP_BOOTROM (i_hresp_BOOTROM),
+ .HSEL_BOOTROM_0 (HSEL_BOOTROM_0),
+ .HADDR_BOOTROM_0 (HADDR_BOOTROM_0),
+ .HTRANS_BOOTROM_0 (HTRANS_BOOTROM_0),
+ .HWRITE_BOOTROM_0 (HWRITE_BOOTROM_0),
+ .HSIZE_BOOTROM_0 (HSIZE_BOOTROM_0),
+ .HBURST_BOOTROM_0 (HBURST_BOOTROM_0),
+ .HPROT_BOOTROM_0 (HPROT_BOOTROM_0),
+ .HWDATA_BOOTROM_0 (HWDATA_BOOTROM_0),
+ .HMASTER_BOOTROM_0 (i_hmaster_BOOTROM_0),
+ .HMASTLOCK_BOOTROM_0 (HMASTLOCK_BOOTROM_0),
+ .HREADYMUX_BOOTROM_0 (HREADYMUX_BOOTROM_0),
+ .HRDATA_BOOTROM_0 (HRDATA_BOOTROM_0),
+ .HREADYOUT_BOOTROM_0 (HREADYOUT_BOOTROM_0),
+ .HRESP_BOOTROM_0 (i_hresp_BOOTROM_0),
// Output port MI1 signals
- .HSEL_IMEM (HSEL_IMEM),
- .HADDR_IMEM (HADDR_IMEM),
- .HTRANS_IMEM (HTRANS_IMEM),
- .HWRITE_IMEM (HWRITE_IMEM),
- .HSIZE_IMEM (HSIZE_IMEM),
- .HBURST_IMEM (HBURST_IMEM),
- .HPROT_IMEM (HPROT_IMEM),
- .HWDATA_IMEM (HWDATA_IMEM),
- .HMASTER_IMEM (i_hmaster_IMEM),
- .HMASTLOCK_IMEM (HMASTLOCK_IMEM),
- .HREADYMUX_IMEM (HREADYMUX_IMEM),
- .HRDATA_IMEM (HRDATA_IMEM),
- .HREADYOUT_IMEM (HREADYOUT_IMEM),
- .HRESP_IMEM (i_hresp_IMEM),
+ .HSEL_IMEM_0 (HSEL_IMEM_0),
+ .HADDR_IMEM_0 (HADDR_IMEM_0),
+ .HTRANS_IMEM_0 (HTRANS_IMEM_0),
+ .HWRITE_IMEM_0 (HWRITE_IMEM_0),
+ .HSIZE_IMEM_0 (HSIZE_IMEM_0),
+ .HBURST_IMEM_0 (HBURST_IMEM_0),
+ .HPROT_IMEM_0 (HPROT_IMEM_0),
+ .HWDATA_IMEM_0 (HWDATA_IMEM_0),
+ .HMASTER_IMEM_0 (i_hmaster_IMEM_0),
+ .HMASTLOCK_IMEM_0 (HMASTLOCK_IMEM_0),
+ .HREADYMUX_IMEM_0 (HREADYMUX_IMEM_0),
+ .HRDATA_IMEM_0 (HRDATA_IMEM_0),
+ .HREADYOUT_IMEM_0 (HREADYOUT_IMEM_0),
+ .HRESP_IMEM_0 (i_hresp_IMEM_0),
// Output port MI2 signals
- .HSEL_DMEM (HSEL_DMEM),
- .HADDR_DMEM (HADDR_DMEM),
- .HTRANS_DMEM (HTRANS_DMEM),
- .HWRITE_DMEM (HWRITE_DMEM),
- .HSIZE_DMEM (HSIZE_DMEM),
- .HBURST_DMEM (HBURST_DMEM),
- .HPROT_DMEM (HPROT_DMEM),
- .HWDATA_DMEM (HWDATA_DMEM),
- .HMASTER_DMEM (i_hmaster_DMEM),
- .HMASTLOCK_DMEM (HMASTLOCK_DMEM),
- .HREADYMUX_DMEM (HREADYMUX_DMEM),
- .HRDATA_DMEM (HRDATA_DMEM),
- .HREADYOUT_DMEM (HREADYOUT_DMEM),
- .HRESP_DMEM (i_hresp_DMEM),
+ .HSEL_DMEM_0 (HSEL_DMEM_0),
+ .HADDR_DMEM_0 (HADDR_DMEM_0),
+ .HTRANS_DMEM_0 (HTRANS_DMEM_0),
+ .HWRITE_DMEM_0 (HWRITE_DMEM_0),
+ .HSIZE_DMEM_0 (HSIZE_DMEM_0),
+ .HBURST_DMEM_0 (HBURST_DMEM_0),
+ .HPROT_DMEM_0 (HPROT_DMEM_0),
+ .HWDATA_DMEM_0 (HWDATA_DMEM_0),
+ .HMASTER_DMEM_0 (i_hmaster_DMEM_0),
+ .HMASTLOCK_DMEM_0 (HMASTLOCK_DMEM_0),
+ .HREADYMUX_DMEM_0 (HREADYMUX_DMEM_0),
+ .HRDATA_DMEM_0 (HRDATA_DMEM_0),
+ .HREADYOUT_DMEM_0 (HREADYOUT_DMEM_0),
+ .HRESP_DMEM_0 (i_hresp_DMEM_0),
// Output port MI3 signals
.HSEL_SYSIO (HSEL_SYSIO),
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
index bcb53414167d2c3ae5fb64a4947533e107125c0a..d8f6faa12de9f41fe2e523e6f1c3f42ce9be1749 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_target_output_BOOTROM (
+module nanosoc_target_output_BOOTROM_0 (
// Common AHB signals
HCLK,
@@ -311,7 +311,7 @@ module nanosoc_target_output_BOOTROM (
assign req_port3 = held_tran_op3 & sel_op3;
// Arbiter instance for resolving requests to this output stage
- nanosoc_arbiter_BOOTROM u_output_arb (
+ nanosoc_arbiter_BOOTROM_0 u_output_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
index 8ff767274fb2a9cb2ae101e4da05d3de2a97e89f..e06782c3c5bb7e27fafcd09541cfaecdabd7f178 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_target_output_DMEM (
+module nanosoc_target_output_DMEM_0 (
// Common AHB signals
HCLK,
@@ -311,7 +311,7 @@ module nanosoc_target_output_DMEM (
assign req_port3 = held_tran_op3 & sel_op3;
// Arbiter instance for resolving requests to this output stage
- nanosoc_arbiter_DMEM u_output_arb (
+ nanosoc_arbiter_DMEM_0 u_output_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
similarity index 99%
rename from system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v
rename to system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
index 79261e07c0e08a5bec186a78dbfc0312cc60301f..b369f495bc2a930c3d4e1ceabdd53eee88cee5a9 100644
--- a/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM.v
+++ b/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
@@ -32,7 +32,7 @@
-module nanosoc_target_output_IMEM (
+module nanosoc_target_output_IMEM_0 (
// Common AHB signals
HCLK,
@@ -311,7 +311,7 @@ module nanosoc_target_output_IMEM (
assign req_port3 = held_tran_op3 & sel_op3;
// Arbiter instance for resolving requests to this output stage
- nanosoc_arbiter_IMEM u_output_arb (
+ nanosoc_arbiter_IMEM_0 u_output_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/system/nanosoc_busmatrix/xml/nanosoc.xml b/system/nanosoc_busmatrix/xml/nanosoc.xml
index b55e1f81e23a6049d356a133def753ef86791cde..417b2a9c2fe7738f8b7a51dc3e8cb3aca7d9c4c2 100644
--- a/system/nanosoc_busmatrix/xml/nanosoc.xml
+++ b/system/nanosoc_busmatrix/xml/nanosoc.xml
@@ -62,9 +62,9 @@
<!-- Slave interface definitions -->
<slave_interface name="_SOCDEBUG">
- <sparse_connect interface="_BOOTROM"/>
- <sparse_connect interface="_IMEM"/>
- <sparse_connect interface="_DMEM"/>
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
<sparse_connect interface="_EXP_0"/>
<sparse_connect interface="_EXP_1"/>
@@ -72,10 +72,10 @@
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
<sparse_connect interface="_SYSTABLE"/>
- <address_region interface="_BOOTROM" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
- <address_region interface="_BOOTROM" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_IMEM" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_DMEM" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
<address_region interface="_EXP_0" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
<address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
@@ -83,23 +83,23 @@
<address_region interface="_EXP_1" mem_lo='a0000000' mem_hi='bfffffff' remapping='none'/>
<address_region interface="_EXP_2" mem_lo='c0000000' mem_hi='dfffffff' remapping='none'/>
<address_region interface="_SYSTABLE" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
- <remap_region interface="_IMEM" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ <remap_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
</slave_interface>
<slave_interface name="_DMAC_0">
- <sparse_connect interface="_BOOTROM"/>
- <sparse_connect interface="_IMEM"/>
- <sparse_connect interface="_DMEM"/>
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
<sparse_connect interface="_EXP_0"/>
<sparse_connect interface="_EXP_1"/>
<sparse_connect interface="_EXP_2"/>
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
- <address_region interface="_IMEM" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_IMEM" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_DMEM" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
<address_region interface="_EXP_0" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
<address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
@@ -109,19 +109,19 @@
</slave_interface>
<slave_interface name="_DMAC_1">
- <sparse_connect interface="_BOOTROM"/>
- <sparse_connect interface="_IMEM"/>
- <sparse_connect interface="_DMEM"/>
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
<sparse_connect interface="_EXP_0"/>
<sparse_connect interface="_EXP_1"/>
<sparse_connect interface="_EXP_2"/>
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
- <address_region interface="_IMEM" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
- <address_region interface="_BOOTROM" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_IMEM" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_DMEM" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
<address_region interface="_EXP_0" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
<address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
@@ -131,9 +131,9 @@
</slave_interface>
<slave_interface name="_CPU_0">
- <sparse_connect interface="_BOOTROM"/>
- <sparse_connect interface="_IMEM"/>
- <sparse_connect interface="_DMEM"/>
+ <sparse_connect interface="_BOOTROM_0"/>
+ <sparse_connect interface="_IMEM_0"/>
+ <sparse_connect interface="_DMEM_0"/>
<sparse_connect interface="_SYSIO"/>
<sparse_connect interface="_EXP_0"/>
<sparse_connect interface="_EXP_1"/>
@@ -141,10 +141,10 @@
<sparse_connect interface="_EXPRAM_L"/>
<sparse_connect interface="_EXPRAM_H"/>
<sparse_connect interface="_SYSTABLE"/>
- <address_region interface="_BOOTROM" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
- <address_region interface="_BOOTROM" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
- <address_region interface="_IMEM" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
- <address_region interface="_DMEM" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
+ <address_region interface="_BOOTROM_0" mem_lo='00000000' mem_hi='0fffffff' remapping='move'/>
+ <address_region interface="_BOOTROM_0" mem_lo='10000000' mem_hi='1fffffff' remapping='none'/>
+ <address_region interface="_IMEM_0" mem_lo='20000000' mem_hi='2fffffff' remapping='none'/>
+ <address_region interface="_DMEM_0" mem_lo='30000000' mem_hi='3fffffff' remapping='none'/>
<address_region interface="_SYSIO" mem_lo='40000000' mem_hi='5fffffff' remapping='none'/>
<address_region interface="_EXP_0" mem_lo='60000000' mem_hi='7fffffff' remapping='none'/>
<address_region interface="_EXPRAM_L" mem_lo='80000000' mem_hi='8fffffff' remapping='none'/>
@@ -152,14 +152,14 @@
<address_region interface="_EXP_1" mem_lo='a0000000' mem_hi='bfffffff' remapping='none'/>
<address_region interface="_EXP_2" mem_lo='c0000000' mem_hi='dfffffff' remapping='none'/>
<address_region interface="_SYSTABLE" mem_lo='f0000000' mem_hi='f003ffff' remapping='none'/>
- <remap_region interface="_IMEM" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
+ <remap_region interface="_IMEM_0" mem_lo='00000000' mem_hi='0fffffff' bit='0'/>
</slave_interface>
<!-- Master interface definitions -->
- <master_interface name="_BOOTROM"/>
- <master_interface name="_IMEM"/>
- <master_interface name="_DMEM"/>
+ <master_interface name="_BOOTROM_0"/>
+ <master_interface name="_IMEM_0"/>
+ <master_interface name="_DMEM_0"/>
<master_interface name="_SYSIO"/>
<master_interface name="_EXPRAM_L"/>
<master_interface name="_EXPRAM_H"/>
diff --git a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
index e8d033eaee6c32a60cabd7348fab0fd40e335b6e..0765e09a70ab9a189244449752d81477ac3453bd 100644
--- a/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+++ b/system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
@@ -181,6 +181,9 @@ module nanosoc_interconnect #(
// Instantiate DMA_0 - DMA230
+ //--------------------------------
+ // DMAC_1
+ //--------------------------------
// Instantiate DMA_1 - Not Implemented
//--------------------------------
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v
deleted file mode 100644
index b5e2b43253484f0f00a9b86e677918fe9805f54b..0000000000000000000000000000000000000000
--- a/system/nanosoc_managers/cortexm0/verilog/nanosoc_cortexm0_control.v
+++ /dev/null
@@ -1,144 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Cortex-M0 Reset and Power Control Module
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_cortexm0_control #(
- parameter CLKGATE_PRESENT = 0
-)(
- // Input Clocks and Resets
- input wire FCLK, // Free running clock
- input wire SYSRESETn, // System Reset
- input wire SCANENABLE, // Scan Mode Enable
- input wire TESTMODE, // Test Mode Enable (Override Synchronisers)
-
- // Generated Clocks and Resets
- output wire SCLK, // System clock
- output wire HCLK, // AHB Clock
- output wire HRESETn, // AHB Reset
- output wire PORESETn, // Power on reset
- output wire DCLK, // Debug clock
- output wire DBGRESETn, // Debug reset
-
- // System Reset Request
- input wire NANOSOC_RESETREQ, // System Reset Request
-
- // Power Management Control Signals
- input wire PMUENABLE, // PMU NEable from System Register
- input wire WAKEUP, // Wakeup Signaling from Core
- input wire SLEEPDEEP, // Debug Power Up Request
- input wire GATEHCLK, // Control Signal from Core to Control Clock Gating of HCLK
-
- // Power Management Request signals
- input wire CDBGPWRUPREQ, // Core Debug Power Up Request
- output wire WICENREQ, // WIC enable request from PMU
- output wire SLEEPHOLDREQn, // Core Sleep Hold Request
- output wire PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
- output wire CCTRLRESETREQ, // Core Control System Reset Request
-
- // Power Management Ackowledge signals
- input wire WICENACK, // Wake-on-Interrupt Enable ACK from Core
- input wire SLEEPHOLDACKn, // Sleep Hold Acknowledgement
- output wire CDBGPWRUPACK // Core Debug Power Up Acknowledge
-);
-
- // -------------------------------
- // Cortex-M0 Control System Reset Req
- // -------------------------------
- wire HRESETREQ;
- wire PMUHRESETREQ;
-
- assign CCTRLRESETREQ = PMUHRESETREQ | HRESETREQ;
-
- // -------------------------------
- // NanoSoC Power Down Detection
- // -------------------------------
- // System Power Down Signals
- wire SYSPWRDOWN;
- wire SYSPWRDOWNACK;
-
- // Debug Power Down Signals
- wire DBGPWRDOWN;
- wire DBGPWRDOWNACK;
-
- // In this example system, power control takes place immediately.
- // In a real circuit you might need to add delays in the next two
- // signal assignments for correct operation.
- assign SYSPWRDOWNACK = SYSPWRDOWN;
- assign DBGPWRDOWNACK = DBGPWRDOWN;
-
- // -------------------------------
- // NanoSoC Power Management Unit
- // -------------------------------
- // Connectivity - Clock Generation
- wire HCLKG; // Gated HCLK
- wire DCLKG; // Gated DCLK
- wire SCLKG; // Gated SCLK
-
- assign HCLK = (CLKGATE_PRESENT==0) ? FCLK : HCLKG;
- assign DCLK = (CLKGATE_PRESENT==0) ? FCLK : DCLKG;
- assign SCLK = (CLKGATE_PRESENT==0) ? FCLK : SCLKG;
-
- // Power Management Unit Instantiation
- cortexm0_pmu u_cortexm0_pmu (
- // Power Management Unit Inputs
- .FCLK (FCLK),
- .PORESETn (PORESETn),
- .HRESETREQ (NANOSOC_RESETREQ), // from Cores / Watchdog / Debug Controller
- .PMUENABLE (PMUENABLE), // from System Controller
- .WICENACK (WICENACK), // from WIC in integration
-
- .WAKEUP (WAKEUP), // from WIC in integration
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
-
- .SLEEPDEEP (SLEEPDEEP),
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .GATEHCLK (GATEHCLK),
- .SYSPWRDOWNACK (SYSPWRDOWNACK),
- .DBGPWRDOWNACK (DBGPWRDOWNACK),
- .CGBYPASS (TESTMODE),
-
- // Power Management Unit Outputs
- .HCLK (HCLKG),
- .DCLK (DCLKG),
- .SCLK (SCLKG),
- .WICENREQ (WICENREQ),
- .CDBGPWRUPACK (CDBGPWRUPACK),
- .SYSISOLATEn ( ),
- .SYSRETAINn ( ),
- .SYSPWRDOWN (SYSPWRDOWN),
- .DBGISOLATEn ( ),
- .DBGPWRDOWN (DBGPWRDOWN),
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ)
- );
-
- // -------------------------------
- // Reset Control
- // -------------------------------
- cortexm0_rst_ctl u_rst_ctl (
- // Inputs
- .GLOBALRESETn (SYSRESETn),
- .FCLK (FCLK),
- .HCLK (HCLKG), // TODO: Why are theses Gated?
- .DCLK (DCLKG), // TODO: Why are theses Gated?
- .SYSRESETREQ (NANOSOC_RESETREQ),
- .PMUHRESETREQ (PMUHRESETREQ),
- .PMUDBGRESETREQ (PMUDBGRESETREQ),
- .RSTBYPASS (TESTMODE),
- .SE (SCANENABLE),
-
- // Outputs
- .PORESETn (PORESETn),
- .HRESETn (HRESETn),
- .DBGRESETn (DBGRESETn),
- .HRESETREQ (HRESETREQ)
- );
-endmodule
\ No newline at end of file
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
deleted file mode 100644
index da16b48a697e75323081e641a658ff9100cde74b..0000000000000000000000000000000000000000
--- a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_cortexm0.v
+++ /dev/null
@@ -1,280 +0,0 @@
-//-----------------------------------------------------------------------------
-// NanoSoC Cortex-M0 AHB Manager
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : System level design for the example Cortex-M0 system
-//-----------------------------------------------------------------------------
-
-module nanosoc_manager_cortexm0 #(
- parameter CLKGATE_PRESENT = 0,
- parameter BE = 0, // 1: Big endian 0: little endian
- parameter BKPT = 4, // Number of breakpoint comparators
- parameter DBG = 1, // Debug configuration
- parameter NUMIRQ = 32, // NUM of IRQ
- parameter SMUL = 0, // Multiplier configuration
- parameter SYST = 1, // SysTick
- parameter WIC = 1, // Wake-up interrupt controller support
- parameter WICLINES = 34, // Supported WIC lines
- parameter WPT = 2, // Number of DWT comparators
- parameter RESET_ALL_REGS = 0, // Do not reset all registers
- parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
-)(
- // Input Clocks and Resets
- input wire FCLK, // Free running clock
- input wire SYSRESETn, // System Reset
- input wire SCANENABLE, // Scan Mode Enable
- input wire TESTMODE, // Test Mode Enable (Override Synchronisers)
-
- // System Reset Request Signals
- input wire NANOSOC_RESETREQ, // System Request from System Managers
- output wire CCTRLRESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
-
- // Generated Clocks and Resets
- output wire HCLK, // AHB Clock
- output wire SCLK, // System clock
- output wire HRESETn, // AHB and System reset
- output wire PORESETn, // Power on reset
- output wire DCLK, // Debug clock
- output wire DBGRESETn, // Debug reset
-
- // Power Management Signals
- input wire PMUENABLE, // Power Management Enable
- output wire PMUDBGRESETREQ, // Power Management Debug Reset Req
-
- // AHB Lite port
- output wire [31:0] HADDR, // Address bus
- output wire [1:0] HTRANS, // Transfer type
- output wire HWRITE, // Transfer direction
- output wire [2:0] HSIZE, // Transfer size
- output wire [2:0] HBURST, // Burst type
- output wire [3:0] HPROT, // Protection control
- output wire [31:0] HWDATA, // Write data
- output wire HMASTLOCK, // Locked Sequence
- input wire [31:0] HRDATA, // Read data bus
- input wire HREADY, // HREADY feedback
- input wire HRESP, // Transfer response
-
- // Sideband CPU signalling
- input wire NMI, // Non-Maskable Interrupt request
- input wire [31:0] IRQ, // Maskable Interrupt requests
- output wire TXEV, // Send Event (SEV) output
- input wire RXEV, // Receive Event input
- output wire SLEEPING, // Processor status - sleeping
- output wire SLEEPDEEP, // Processor status - deep sleep
- output wire LOCKUP, // Wake up request from WIC
- output wire SYSRESETREQ, // System reset request
-
- // Serial-Wire Debug
- input wire SWDI, // SWD data input
- input wire SWCLK, // SWD clock
- output wire SWDO, // SWD data output
- output wire SWDOEN // SWD data output enable
-);
-
- // ---------------------------------------------------
- // Cortex-M0 Power Management and Reset Control Unit
- // ---------------------------------------------------
- // Cortex-M0 Control to Core Connectivity
- wire GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
- wire WAKEUP; // Wake-up Signaling from Core
- wire CDBGPWRUPREQ; // Core Debug Power Up Request
- wire CDBGPWRUPACK; // Core Debug Power Up Acknowledge
- wire WICENREQ; // WIC enable request from PMU
- wire WICENACK; // Wake-on-Interrupt Enable ACK from Core
- wire SLEEPHOLDREQn; // Core Sleep Hold Request
- wire SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
-
- // Cortex-M0 Control Instantiation
- nanosoc_cortexm0_control #(
- .CLKGATE_PRESENT(CLKGATE_PRESENT)
- ) u_cpu_control (
- // Input Clocks and Resets
- .FCLK (FCLK), // Free running clock
- .SYSRESETn (SYSRESETn), // System Reset
- .SCANENABLE (SCANENABLE), // Scan Mode Enable
- .TESTMODE (TESTMODE), // Test Mode Enable (Override Synchronisers)
-
- // Generated Clocks and Resets
- .SCLK (SCLK), // System clock
- .HCLK (HCLK), // AHB Clock
- .HRESETn (HRESETn), // AHB Reset
- .PORESETn (PORESETn), // Power on reset
- .DCLK (DCLK), // Debug clock
- .DBGRESETn (DBGRESETn), // Debug reset
-
- // System Reset Request
- .NANOSOC_RESETREQ (NANOSOC_RESETREQ), // System Reset Request
-
- // Power Management Control Signals
- .PMUENABLE (PMUENABLE), // PMU Enable from System Register
- .WAKEUP (WAKEUP), // Wake-up Signaling from Core
- .SLEEPDEEP (SLEEPDEEP), // Debug Power Up Request
- .GATEHCLK (GATEHCLK), // Control Signal from Core to Control CLock Gating of HCLK
-
- // Power Management Request signals
- .CDBGPWRUPREQ (CDBGPWRUPREQ), // Core Debug Power Up Request
- .WICENREQ (WICENREQ), // WIC enable request from PMU
- .SLEEPHOLDREQn (SLEEPHOLDREQn), // Core Sleep Hold Request
- .PMUDBGRESETREQ (PMUDBGRESETREQ), // Power Management Unit Debug Reset Request
- .CCTRLRESETREQ (CCTRLRESETREQ), // Core Control System Reset Request
-
- // Power Management Ackowledge signals
- .WICENACK (WICENACK), // Wake-on-Interrupt Enable ACK from Core
- .SLEEPHOLDACKn (SLEEPHOLDACKn), // Sleep Hold Acknowledgement
- .CDBGPWRUPACK (CDBGPWRUPACK) // Core Debug Power Up Acknowledge
- );
-
- // -------------------------------
- // SysTick signals
- // -------------------------------
- // SysTick Timer Signals
- wire STCLKEN;
- wire [25:0] STCALIB;
-
- // SysTick Control Instantiation
- nanosoc_cortexm0_stclkctrl #(
- .DIV_RATIO (18'd01000)
- ) u_stclkctrl (
- .FCLK (FCLK),
- .SYSRESETn (SYSRESETn),
-
- .STCLKEN (STCLKEN),
- .STCALIB (STCALIB)
- );
-
- // -------------------------------
- // Cortex-M0 CPU Instantiation
- // -------------------------------
- // Processor status
- wire [2:0] CODEHINTDE;
- wire SPECHTRANS;
- wire CODENSEQ;
- wire SHAREABLE;
-
- // Cortex-M0 Logic Instantiation
- CORTEXM0INTEGRATION #(
- .ACG (CLKGATE_PRESENT), // Architectural clock gating
- .BE (BE), // Big-endian
- .BKPT (BKPT), // Number of breakpoint comparators
- .DBG (DBG), // Debug configuration
- .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
- .NUMIRQ (NUMIRQ), // Number of Interrupts
- .RAR (RESET_ALL_REGS), // Reset All Registers
- .SMUL (SMUL), // Multiplier configuration
- .SYST (SYST), // SysTick
- .WIC (WIC), // Wake-up interrupt controller support
- .WICLINES (WICLINES), // Supported WIC lines
- .WPT (WPT) // Number of DWT comparators
- ) u_cortex_m0_integration (
- // System inputs
- .FCLK (FCLKG), // FCLK
- .SCLK (SCLKG), // SCLK generated from PMU
- .HCLK (HCLKG), // HCLK generated from PMU
- .DCLK (DCLKG), // DCLK generated from PMU
- .PORESETn (PORESETn),
- .HRESETn (HRESETn),
- .DBGRESETn (DBGRESETn),
- .RSTBYPASS (RSTBYPASS),
- .SE (SCANENABLE),
-
- // Power management inputs
- .SLEEPHOLDREQn (SLEEPHOLDREQn),
- .WICENREQ (WICENREQ),
- .CDBGPWRUPACK (CDBGPWRUPACK),
-
- // Power management outputs
- .SLEEPHOLDACKn (SLEEPHOLDACKn),
- .WICENACK (WICENACK),
- .CDBGPWRUPREQ (CDBGPWRUPREQ),
-
- .WAKEUP (WAKEUP),
- .WICSENSE ( ),
- .GATEHCLK (GATEHCLK),
- .SYSRESETREQ (SYSRESETREQ),
-
- // System bus
- .HADDR (HADDR),
- .HTRANS (HTRANS),
- .HSIZE (HSIZE),
- .HBURST (HBURST),
- .HPROT (HPROT),
- .HMASTLOCK (HMASTLOCK),
- .HWRITE (HWRITE),
- .HWDATA (HWDATA),
- .HRDATA (HRDATA),
- .HREADY (HREADY),
- .HRESP (HRESP),
- .HMASTER ( ),
-
- .CODEHINTDE (CODEHINTDE),
- .SPECHTRANS (SPECHTRANS),
- .CODENSEQ (CODENSEQ),
-
- // Interrupts
- .IRQ (IRQ[31:0]),
- .NMI (NMI),
- .IRQLATENCY (8'h00),
-
- .ECOREVNUM (28'h0),
-
- // Systick
- .STCLKEN (STCLKEN),
- .STCALIB (STCALIB),
-
- // Debug - JTAG or Serial wire
- .nTRST (1'b1),
- .SWDITMS (SWDI),
- .SWCLKTCK (SWCLK),
- .TDI (1'b0),
- .TDO ( ),
- .nTDOEN ( ),
- .SWDO (SWDO),
- .SWDOEN (SWDOEN),
-
- .DBGRESTART (1'b0), // Unused - Multi-Core synchronous restart from halt
- .DBGRESTARTED ( ), // Unused - Multi-Core synchronous restart from halt
-
- // Event communication
- .TXEV (TXEV),
- .RXEV (RXEV),
- .EDBGRQ (1'b0), // Unused - Multi-Core synchronous halt request
-
- // Status output
- .HALTED ( ),
- .LOCKUP (LOCKUP),
- .SLEEPING (SLEEPING),
- .SLEEPDEEP (SLEEPDEEP)
- );
-
-endmodule
diff --git a/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_slcorem0 b/system/nanosoc_managers/cortexm0/verilog/nanosoc_manager_slcorem0
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/system/nanosoc_managers/cortexm0/verilog/slcorem0.v b/system/nanosoc_managers/cortexm0/verilog/slcorem0.v
new file mode 100644
index 0000000000000000000000000000000000000000..14dc32dc024dff3d2ab867159a1be360fff39a97
--- /dev/null
+++ b/system/nanosoc_managers/cortexm0/verilog/slcorem0.v
@@ -0,0 +1,264 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 - Basic Cortex-M0 CPU Subsystem
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module slcorem0 #(
+ parameter CLKGATE_PRESENT = 0,
+ parameter BE = 0, // 1: Big endian 0: little endian
+ parameter BKPT = 4, // Number of breakpoint comparators
+ parameter DBG = 1, // Debug configuration
+ parameter NUMIRQ = 32, // NUM of IRQ
+ parameter SMUL = 0, // Multiplier configuration
+ parameter SYST = 1, // SysTick
+ parameter WIC = 1, // Wake-up interrupt controller support
+ parameter WICLINES = 34, // Supported WIC lines
+ parameter WPT = 2, // Number of DWT comparators
+ parameter RESET_ALL_REGS = 0, // Do not reset all registers
+ parameter INCLUDE_JTAG = 0 // Do not Include JTAG feature
+)(
+ // System Input Clocks and Resets
+ input wire SYS_FCLK, // Free running clock
+ input wire SYS_SYSRESETn, // System Reset
+ input wire SYS_SCANENABLE, // Scan Mode Enable
+ input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // System Reset Request Signals
+ input wire SYS_SYSRESETREQ, // System Request from System Managers
+ output wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
+
+ // Generated Clocks and Resets
+ output wire SYS_PORESETn, // System Power On Reset
+ output wire SYS_HCLK, // AHB Clock
+ output wire SYS_HRESETn, // AHB and System reset
+
+ // Power Management Signals
+ input wire SYS_PMUENABLE, // Power Management Enable
+ output wire SYS_PMUDBGRESETREQ, // Power Management Debug Reset Req
+
+ // AHB Lite port
+ output wire [31:0] HADDR, // Address bus
+ output wire [1:0] HTRANS, // Transfer type
+ output wire HWRITE, // Transfer direction
+ output wire [2:0] HSIZE, // Transfer size
+ output wire [2:0] HBURST, // Burst type
+ output wire [3:0] HPROT, // Protection control
+ output wire [31:0] HWDATA, // Write data
+ output wire HMASTLOCK, // Locked Sequence
+ input wire [31:0] HRDATA, // Read data bus
+ input wire HREADY, // HREADY feedback
+ input wire HRESP, // Transfer response
+
+ // Sideband CPU signalling
+ input wire CORE_NMI, // Non-Maskable Interrupt request
+ input wire [31:0] CORE_IRQ, // Maskable Interrupt requests
+ output wire CORE_TXEV, // Send Event (SEV) output
+ input wire CORE_RXEV, // Receive Event input
+ output wire CORE_LOCKUP, // Wake up request from WIC
+ output wire CORE_SYSRESETREQ, // System reset request
+
+ output wire CORE_SLEEPING, // Processor status - sleeping
+ output wire CORE_SLEEPDEEP, // Processor status - deep sleep
+
+ // Serial-Wire Debug
+ input wire CORE_SWDI, // SWD data input
+ input wire CORE_SWCLK, // SWD clock
+ output wire CORE_SWDO, // SWD data output
+ output wire CORE_SWDOEN // SWD data output enable
+);
+
+ // ---------------------------------------------------
+ // Cortex-M0 Power Management and Reset Control Unit
+ // ---------------------------------------------------
+ // Cortex-M0 Control to Core Connectivity
+ wire CORE_GATEHCLK; // Control Signal from CPU to Control CLock Gating of HCLK
+ wire CORE_WAKEUP; // Wake-up Signaling from Core
+ wire CORE_CDBGPWRUPREQ; // Core Debug Power Up Request
+ wire CORE_CDBGPWRUPACK; // Core Debug Power Up Acknowledge
+ wire CORE_WICENREQ; // WIC enable request from PMU
+ wire CORE_WICENACK; // Wake-on-Interrupt Enable ACK from Core
+ wire CORE_SLEEPHOLDREQn; // Core Sleep Hold Request
+ wire CORE_SLEEPHOLDACKn; // Core Sleep Hold Acknowledgement
+
+ // Internal Clock Signals
+ wire CORE_HCLK; // AHB Clock
+ wire CORE_HRESETn; // AHB and System reset
+ wire CORE_SCLK; // System clock
+ wire CORE_DCLK; // Debug clock
+ wire CORE_DBGRESETn; // Debug reset
+
+ // Cortex-M0 Control Instantiation
+ slcorem0_prmu #(
+ .CLKGATE_PRESENT(CLKGATE_PRESENT)
+ ) u_core_prmu (
+ // Input Clocks and Resets
+ .SYS_FCLK (SYS_FCLK), // Free running clock
+ .SYS_SYSRESETn (SYS_SYSRESETn), // System Reset
+ .SYS_SCANENABLE (SYS_SCANENABLE), // Scan Mode Enable
+ .SYS_TESTMODE (SYS_TESTMODE), // Test Mode Enable (Override Synchronisers)
+
+ // Core Generated Clocks and Resets
+ .CORE_SCLK (CORE_SCLK), // Core-Subsystem clock
+ .CORE_HCLK (CORE_HCLK), // Core AHB Clock
+ .CORE_HRESETn (CORE_HRESETn), // Core AHB Reset
+ .CORE_DCLK (CORE_DCLK), // Core Debug clock
+ .CORE_DBGRESETn (CORE_DBGRESETn), // Core Debug reset
+
+ // System Generated Clocks and Resets
+ .SYS_HCLK (SYS_HCLK), // System AHB Clock
+ .SYS_HRESETn (SYS_HRESETn), // System AHB Reset
+ .SYS_PORESETn (SYS_PORESETn), // System Power on reset
+
+ // System Reset Request
+ .SYS_SYSRESETREQ (SYS_SYSRESETREQ), // System Reset Request
+
+ // Power Management Control Signals
+ .SYS_PMUENABLE (SYS_PMUENABLE), // PMU Enable from System Register
+ .CORE_WAKEUP (CORE_WAKEUP), // Wake-up Signaling from Core
+ .CORE_SLEEPDEEP (CORE_SLEEPDEEP), // Debug Power Up Request
+ .CORE_GATEHCLK (CORE_GATEHCLK), // Control Signal from Core to Control Clock Gating of HCLK
+
+ // Power Management Request signals
+ .CORE_CDBGPWRUPREQ (CORE_CDBGPWRUPREQ), // Core Debug Power Up Request
+ .CORE_WICENREQ (CORE_WICENREQ), // Core WIC enable request from PMU
+ .CORE_SLEEPHOLDREQn (CORE_SLEEPHOLDREQn), // Core Sleep Hold Request
+
+ .SYS_PRMURESETREQ (SYS_PRMURESETREQ), // Core Control System Reset Request
+ .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ), // Core Power Management Unit Debug Reset Request
+
+ // Power Management Ackowledge signals
+ .CORE_WICENACK (CORE_WICENACK), // Wake-on-Interrupt Enable ACK from Core
+ .CORE_SLEEPHOLDACKn (CORE_SLEEPHOLDACKn), // Sleep Hold Acknowledgement
+ .CORE_CDBGPWRUPACK (CORE_CDBGPWRUPACK) // Core Debug Power Up Acknowledge
+ );
+
+ // -------------------------------
+ // SysTick signals
+ // -------------------------------
+ // SysTick Timer Signals
+ wire CORE_STCLKEN;
+ wire [25:0] CORE_STCALIB;
+
+ // SysTick Control Instantiation
+ nanosoc_cortexm0_stclkctrl #(
+ .DIV_RATIO (18'd01000)
+ ) u_stclkctrl (
+ .FCLK (SYS_FCLK),
+ .SYSRESETn (SYS_SYSRESETn),
+
+ .STCLKEN (CORE_STCLKEN),
+ .STCALIB (CORE_STCALIB)
+ );
+
+ // -------------------------------
+ // Cortex-M0 CPU Instantiation
+ // -------------------------------
+ // Processor status
+ wire [2:0] CORE_CODEHINTDE;
+ wire CORE_SPECHTRANS;
+ wire CORE_CODENSEQ;
+ wire CORE_SHAREABLE;
+
+ // Cortex-M0 Logic Instantiation
+ CORTEXM0INTEGRATION #(
+ .ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT) // Number of DWT comparators
+ ) u_cortex_m0_integration (
+ // System inputs
+ .FCLK (SYS_FCLK), // FCLK
+ .SCLK (CORE_SCLK), // SCLK generated from PMU
+ .HCLK (CORE_HCLK), // HCLK generated from PMU
+ .DCLK (CORE_DCLK), // DCLK generated from PMU
+ .PORESETn (SYS_PORESETn),
+ .HRESETn (CORE_HRESETn),
+ .DBGRESETn (CORE_DBGRESETn),
+ .RSTBYPASS (SYS_TESTMODE),
+ .SE (SYS_SCANENABLE),
+
+ // Power management inputs
+ .SLEEPHOLDREQn (CORE_SLEEPHOLDREQn),
+ .WICENREQ (CORE_WICENREQ),
+ .CDBGPWRUPACK (CORE_CDBGPWRUPACK),
+
+ // Power management outputs
+ .SLEEPHOLDACKn (CORE_SLEEPHOLDACKn),
+ .WICENACK (CORE_WICENACK),
+ .CDBGPWRUPREQ (CORE_CDBGPWRUPREQ),
+
+ .WAKEUP (CORE_WAKEUP),
+ .WICSENSE ( ),
+ .GATEHCLK (CORE_GATEHCLK),
+ .SYSRESETREQ (CORE_SYSRESETREQ),
+
+ // System bus
+ .HADDR (HADDR),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HBURST (HBURST),
+ .HPROT (HPROT),
+ .HMASTLOCK (HMASTLOCK),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HRDATA (HRDATA),
+ .HREADY (HREADY),
+ .HRESP (HRESP),
+ .HMASTER ( ),
+
+ .CODEHINTDE (CORE_CODEHINTDE),
+ .SPECHTRANS (CORE_SPECHTRANS),
+ .CODENSEQ (CORE_CODENSEQ),
+
+ // Interrupts
+ .IRQ (CORE_IRQ[31:0]),
+ .NMI (CORE_NMI),
+ .IRQLATENCY (8'h00),
+
+ .ECOREVNUM (28'h0),
+
+ // Systick
+ .STCLKEN (CORE_STCLKEN),
+ .STCALIB (CORE_STCALIB),
+
+ // Debug - JTAG or Serial wire
+ .nTRST (1'b1),
+ .SWDITMS (CORE_SWDI),
+ .SWCLKTCK (CORE_SWCLK),
+ .TDI (1'b0),
+ .TDO ( ),
+ .nTDOEN ( ),
+ .SWDO (CORE_SWDO),
+ .SWDOEN (CORE_SWDOEN),
+
+ .DBGRESTART (1'b0), // Unused - Multi-Core synchronous restart from halt
+ .DBGRESTARTED ( ), // Unused - Multi-Core synchronous restart from halt
+
+ // Event communication
+ .TXEV (CORE_TXEV),
+ .RXEV (CORE_RXEV),
+ .EDBGRQ (1'b0), // Unused - Multi-Core synchronous halt request
+
+ // Status output - TODO: Map into APB Register Block
+ .HALTED ( ),
+ .LOCKUP (CORE_LOCKUP),
+ .SLEEPING (CORE_SLEEPING),
+ .SLEEPDEEP (CORE_SLEEPDEEP)
+ );
+
+endmodule
diff --git a/system/nanosoc_managers/cortexm0/verilog/slcorem0_prmu.v b/system/nanosoc_managers/cortexm0/verilog/slcorem0_prmu.v
new file mode 100644
index 0000000000000000000000000000000000000000..27dfb73749660732d7e794a793d0b2ea6176b79f
--- /dev/null
+++ b/system/nanosoc_managers/cortexm0/verilog/slcorem0_prmu.v
@@ -0,0 +1,155 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 PRMU - Cortex-M0 CPU Power and Reset Management Unit
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module slcorem0_prmu #(
+ parameter CLKGATE_PRESENT = 0
+)(
+ // Input Clocks and Resets
+ input wire SYS_FCLK, // Free running clock
+ input wire SYS_SYSRESETn, // System Reset
+ input wire SYS_SCANENABLE, // Scan Mode Enable
+ input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // Generated Clocks and Resets
+ output wire CORE_SCLK, // System clock
+ output wire CORE_HCLK, // AHB Clock
+ output wire CORE_HRESETn, // AHB Reset
+ output wire CORE_DCLK, // Debug clock
+ output wire CORE_DBGRESETn, // Debug reset
+
+ output wire SYS_HCLK, // Power on reset
+ output wire SYS_HRESETn, // Power on reset
+ output wire SYS_PORESETn, // Power on reset
+
+ // System Reset Request
+ input wire SYS_SYSRESETREQ, // System Reset Request
+
+ // Power Management Control Signals
+ input wire SYS_PMUENABLE, // PMU Enable from System Register
+ input wire CORE_WAKEUP, // Wakeup Signaling from Core
+ input wire CORE_SLEEPDEEP, // Debug Power Up Request
+ input wire CORE_GATEHCLK, // Control Signal from Core to Control Clock Gating of HCLK
+
+ // Power Management Request signals
+ input wire CORE_CDBGPWRUPREQ, // Core Debug Power Up Request
+ output wire CORE_WICENREQ, // WIC enable request from PMU
+ output wire CORE_SLEEPHOLDREQn, // Core Sleep Hold Request
+
+ // System Reset Request Signals
+ output wire SYS_PRMURESETREQ, // Power and Reset Management System Reset Request
+ output wire SYS_PMUDBGRESETREQ, // Power Management Unit Debug Reset Request
+
+ // Power Management Ackowledge signals
+ input wire CORE_WICENACK, // Wake-on-Interrupt Enable ACK from Core
+ input wire CORE_SLEEPHOLDACKn, // Sleep Hold Acknowledgement
+ output wire CORE_CDBGPWRUPACK // Core Debug Power Up Acknowledge
+);
+
+ // -------------------------------
+ // Cortex-M0 Control System Reset Req
+ // -------------------------------
+ wire CORE_RSTCTLHRESETREQ;
+ wire CORE_PMUHRESETREQ;
+
+ assign SYS_PRMURESETREQ = CORE_PMUHRESETREQ | CORE_RSTCTLHRESETREQ;
+
+ // -------------------------------
+ // Core Power Down Detection
+ // -------------------------------
+ // System Power Down Signals
+ wire CORE_SYSPWRDOWN;
+ wire CORE_SYSPWRDOWNACK;
+
+ // Debug Power Down Signals
+ wire CORE_DBGPWRDOWN;
+ wire CORE_DBGPWRDOWNACK;
+
+ // In this example system, power control takes place immediately.
+ // In a real circuit you might need to add delays in the next two
+ // signal assignments for correct operation.
+ assign CORE_SYSPWRDOWNACK = CORE_SYSPWRDOWN;
+ assign CORE_DBGPWRDOWNACK = CORE_DBGPWRDOWN;
+
+ // -------------------------------
+ // Core Power Management Unit
+ // -------------------------------
+ // Connectivity - Clock Generation
+ wire CORE_HCLKG; // Gated Core HCLK
+ wire CORE_DCLKG; // Gated Core DCLK
+ wire CORE_SCLKG; // Gated Core SCLK
+
+ assign CORE_HCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_HCLKG;
+ assign CORE_DCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_DCLKG;
+ assign CORE_SCLK = (CLKGATE_PRESENT==0) ? SYS_FCLK : CORE_SCLKG;
+
+ // System HCLK needs to be assigned to System Free-running Clock
+ // so other managers can still access bus when CPU is sleeping
+ assign SYS_HCLK = SYS_FCLK;
+
+ // Power Management Unit Instantiation
+ cortexm0_pmu u_cortexm0_pmu (
+ // Power Management Unit Inputs
+ .FCLK (SYS_FCLK),
+ .PORESETn (SYS_PORESETn),
+ .HRESETREQ (SYS_SYSRESETREQ), // from Cores / Watchdog / Debug Controller
+ .PMUENABLE (SYS_PMUENABLE), // from System Controller
+ .WICENACK (CORE_WICENACK), // from WIC in integration
+
+ .WAKEUP (CORE_WAKEUP), // from WIC in integration
+ .CDBGPWRUPREQ (CORE_CDBGPWRUPREQ),
+
+ .SLEEPDEEP (CORE_SLEEPDEEP),
+ .SLEEPHOLDACKn (CORE_SLEEPHOLDACKn),
+ .GATEHCLK (CORE_GATEHCLK),
+ .SYSPWRDOWNACK (CORE_SYSPWRDOWNACK),
+ .DBGPWRDOWNACK (CORE_DBGPWRDOWNACK),
+ .CGBYPASS (SYS_TESTMODE),
+
+ // Power Management Unit Outputs
+ .HCLK (CORE_HCLKG),
+ .DCLK (CORE_DCLKG),
+ .SCLK (CORE_SCLKG),
+ .WICENREQ (CORE_WICENREQ),
+ .CDBGPWRUPACK (CORE_CDBGPWRUPACK),
+ .SYSISOLATEn ( ),
+ .SYSRETAINn ( ),
+ .SYSPWRDOWN (CORE_SYSPWRDOWN),
+ .DBGISOLATEn ( ),
+ .DBGPWRDOWN (CORE_DBGPWRDOWN),
+ .SLEEPHOLDREQn (CORE_SLEEPHOLDREQn),
+ .PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
+ .PMUHRESETREQ (CORE_PMUHRESETREQ)
+ );
+
+ // -------------------------------
+ // Reset Control
+ // -------------------------------
+ slcorem0_rst_ctl u_rst_ctl (
+ // Inputs
+ .SYS_GLOBALRESETn (SYS_SYSRESETn),
+ .SYS_FCLK (SYS_FCLK),
+ .SYS_HCLK (SYS_HCLK),
+ .CORE_HCLK (CORE_HCLK),
+ .CORE_DCLK (CORE_DCLK),
+ .SYS_SYSRESETREQ (SYS_SYSRESETREQ),
+ .CORE_PMUHRESETREQ (CORE_PMUHRESETREQ),
+ .SYS_PMUDBGRESETREQ (SYS_PMUDBGRESETREQ),
+ .SYS_RSTBYPASS (SYS_TESTMODE),
+ .SYS_SE (SYS_SCANENABLE),
+
+ // Outputs
+ .SYS_HRESETREQ (CORE_RSTCTLHRESETREQ),
+ .SYS_PORESETn (SYS_PORESETn),
+ .SYS_HRESETn (SYS_HRESETn),
+ .CORE_HRESETn (CORE_HRESETn),
+ .CORE_DBGRESETn (CORE_DBGRESETn)
+ );
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_managers/cortexm0/verilog/slcorem0_rst_ctl.v b/system/nanosoc_managers/cortexm0/verilog/slcorem0_rst_ctl.v
new file mode 100644
index 0000000000000000000000000000000000000000..dbdea34c82524e46a33526b6f35c6f92ec945746
--- /dev/null
+++ b/system/nanosoc_managers/cortexm0/verilog/slcorem0_rst_ctl.v
@@ -0,0 +1,138 @@
+//-----------------------------------------------------------------------------
+// SoCLabs SLCore-M0 Reset Control - Cortex-M0 Reset Control
+// - Added additional reset synchroniser to allow for synchronisation of both
+// Core and System versions of HRESETn (system works when CPU is powered down)
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+// (C) COPYRIGHT 2009 ARM Limited.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+// SVN Information
+//
+// Checked In : $Date: 2009-03-21 16:43:18 +0000 (Sat, 21 Mar 2009) $
+//
+// Revision : $Revision: 104871 $
+//
+// Release Information : Cortex-M0-AT510-r0p0-00rel0
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// CORTEX-M0 EXAMPLE RESET CONTROLLER
+// This module is designed as an example reset controller for the Cortex-M0
+// // processor It takes a global reset that can be asynchronously asserted
+// and generates from it synchronously asserted and deasserted resets based
+// on synchronous reset requests
+// This module is intended to interface to the example PMU provided (cortexm0_pmu.v)
+// You can modify this module to suit your requirements
+//-----------------------------------------------------------------------------
+
+module slcorem0_rst_ctl
+ (/*AUTOARG*/
+ // Outputs
+ SYS_PORESETn, SYS_HRESETn, CORE_HRESETn, CORE_DBGRESETn, SYS_HRESETREQ,
+ // Inputs
+ SYS_GLOBALRESETn, SYS_FCLK, CORE_HCLK, CORE_DCLK, SYS_HCLK, SYS_SYSRESETREQ,
+ CORE_PMUHRESETREQ, SYS_PMUDBGRESETREQ, SYS_RSTBYPASS, SYS_SE
+ );
+
+ input SYS_GLOBALRESETn; // Global asynchronous reset
+ input SYS_FCLK; // System Free running clock
+ input SYS_HCLK; // AHB clock (connect to HCLK of non-cortex m0 devices)
+ input CORE_HCLK; // AHB clock (connect to HCLK of CORTEXM0INTEGRATION)
+ input CORE_DCLK; // Debug clock (connect to DCLK of CORTEXM0INTEGRATION)
+ input SYS_SYSRESETREQ; // Synchronous (to HCLK) request for HRESETn from system
+ input CORE_PMUHRESETREQ; // Synchronous (to CORE_HCLK) request for HRESETn from PMU
+ input SYS_PMUDBGRESETREQ; // Synchronous (to CORE_DCLK) request for DBGRESETn from PMU
+ input SYS_RSTBYPASS; // Reset synchroniser bypass (for DFT)
+ input SYS_SE; // Scan Enable (for DFT)
+
+ output SYS_HRESETREQ; // Synchronous (to FCLK) indication of HRESET request
+ output SYS_PORESETn; // Connect to PORESETn of CORTEXM0INTEGRATION
+ output SYS_HRESETn; // Connect to HRESETn of AHB System
+ output CORE_HRESETn; // Connect to HRESETn of CORTEXM0INTEGRATION
+ output CORE_DBGRESETn; // Connect to DBGRESETn of CORTEXM0INTEGRATION
+
+ // Sample synchronous requests to assert HRESETn
+ // Sources:
+ // 1 - System (SYSRESETREQ)
+ // 2 - PMU (PMUHRESETREQ)
+ wire h_reset_req_in = SYS_SYSRESETREQ | CORE_PMUHRESETREQ;
+
+ cm0_rst_send_set u_hreset_req
+ (.RSTn (SYS_PORESETn),
+ .CLK (SYS_FCLK),
+ .RSTREQIN (h_reset_req_in),
+ .RSTREQOUT (SYS_HRESETREQ)
+ );
+
+ // Sample synchronous requests to assert DBGRESETn
+ wire dbg_reset_req_sync;
+
+ cm0_rst_send_set u_dbgreset_req
+ (.RSTn (SYS_PORESETn),
+ .CLK (SYS_FCLK),
+ .RSTREQIN (SYS_PMUDBGRESETREQ),
+ .RSTREQOUT (dbg_reset_req_sync)
+ );
+
+ // --------------------
+ // Reset synchronisers
+ // --------------------
+
+ cm0_rst_sync u_sys_poresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (1'b0),
+ .CLK (SYS_FCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (SYS_PORESETn)
+ );
+
+ cm0_rst_sync u_sys_hresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (SYS_HRESETREQ),
+ .CLK (SYS_HCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (SYS_HRESETn)
+ );
+
+ cm0_rst_sync u_core_hresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (SYS_HRESETREQ),
+ .CLK (CORE_HCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (CORE_HRESETn)
+ );
+
+ cm0_rst_sync u_core_dbgresetn_sync
+ (.RSTINn (SYS_GLOBALRESETn),
+ .RSTREQ (dbg_reset_req_sync),
+ .CLK (CORE_DCLK),
+ .SE (SYS_SE),
+ .RSTBYPASS (SYS_RSTBYPASS),
+ .RSTOUTn (CORE_DBGRESETn)
+ );
+
+endmodule // cortexm0_rst_ctl
+
+
+
diff --git a/system/nanosoc_regions/bootrom/verilog/nanosoc_ahb_bootrom.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v
similarity index 100%
rename from system/nanosoc_regions/bootrom/verilog/nanosoc_ahb_bootrom.v
rename to system/nanosoc_regions/bootrom_0/verilog/nanosoc_ahb_bootrom.v
diff --git a/system/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
similarity index 98%
rename from system/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v
rename to system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
index 94ce02faf33658abbd0c384f3eee81a6f6448cbe..7459a0a6e74359e6e1ca21f99ab6dcb1928c7e19 100644
--- a/system/nanosoc_regions/bootrom/verilog/nanosoc_region_bootrom.v
+++ b/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
@@ -11,7 +11,7 @@
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module nanosoc_region_bootrom #(
+module nanosoc_region_bootrom_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter BOOTROM_ADDR_W = 10 // Size of Bootrom (Based on Address Width) - Default 1KB
diff --git a/system/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
similarity index 98%
rename from system/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v
rename to system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
index 95b106e45f50c7252bcb1572c9a440fc110d3b0b..afdf9b884de03304248a313a06965f4568af3876 100644
--- a/system/nanosoc_regions/dmem/verilog/nanosoc_region_dmem.v
+++ b/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
@@ -10,7 +10,7 @@
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module nanosoc_region_dmem #(
+module nanosoc_region_dmem_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter DMEM_RAM_ADDR_W = 14, // Width of DMEM RAM Address - Default 16KB
diff --git a/system/nanosoc_regions/imem/verilog/nanosoc_region_imem.v b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
similarity index 98%
rename from system/nanosoc_regions/imem/verilog/nanosoc_region_imem.v
rename to system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
index 11ce6a6125778ed76c800c6630e747d21376a293..52a8a46bf366623c4e7bb53d90b76464ffeade07 100644
--- a/system/nanosoc_regions/imem/verilog/nanosoc_region_imem.v
+++ b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
@@ -11,7 +11,7 @@
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module nanosoc_region_imem #(
+module nanosoc_region_imem_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
index 2c484541bf8a348be1c68d136f02bc2cb7aaf09b..532e6721cc4e2254f3085ca15015966b4cb96aa9 100644
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -148,7 +148,7 @@ module nanosoc_region_sysio #(
// AHB address decode
- nanosoc_sys_ahb_decode #(
+ nanosoc_sysio_decode #(
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1),
.BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
@@ -243,8 +243,7 @@ module nanosoc_region_sysio #(
// -------------------------------
// System ROM Table
// -------------------------------
- nanosoc_ahb_cs_rom_table
- #(//.JEPID (),
+ nanosoc_ahb_cs_rom_table #(//.JEPID (),
//.JEPCONTINUATION (),
//.PARTNUMBER (),
//.REVISION (),
@@ -278,9 +277,9 @@ module nanosoc_region_sysio #(
// Peripherals
// -------------------------------
- nanosoc_mcu_sysctrl #(
+ nanosoc_sysctrl #(
.BE (BE)
- ) u_nanosoc_mcu_sysctrl (
+ ) u_nanosoc_sysctrl (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
@@ -377,7 +376,7 @@ module nanosoc_region_sysio #(
);
// APB subsystem for timers, UARTs
- nanosoc_apb_subsystem #(
+ nanosoc_sysio_apb_ss #(
.APB_EXT_PORT12_ENABLE (1),
.APB_EXT_PORT13_ENABLE (1),
.APB_EXT_PORT14_ENABLE (1),
@@ -392,7 +391,7 @@ module nanosoc_region_sysio #(
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
- ) u_nanosoc_apb_subsystem (
+ ) u_nanosoc_sysio_apb_ss (
// AHB interface for AHB to APB bridge
.HCLK (HCLK),
diff --git a/system/nanosoc_regions/sysio/verilog/nanosoc_apb_subsystem.v b/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
similarity index 99%
rename from system/nanosoc_regions/sysio/verilog/nanosoc_apb_subsystem.v
rename to system/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
index e3e46d37b66c56d86faaee04e022e4107db3ac21..124d342120bd4013f87b6382476ba94328f004db 100755
--- a/system/nanosoc_regions/sysio/verilog/nanosoc_apb_subsystem.v
+++ b/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
@@ -34,7 +34,7 @@
//-----------------------------------------------------------------------------
// Abstract : APB sub system
//-----------------------------------------------------------------------------
-module nanosoc_apb_subsystem #(
+module nanosoc_sysio_apb_ss #(
// Enable setting for APB extension ports
// By default, all four extension ports are not used.
// This can be overriden by parameters at instantiations.
diff --git a/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
new file mode 100644
index 0000000000000000000000000000000000000000..8c796e132aa82406ef99029fc4c920d1625da9b5
--- /dev/null
+++ b/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
@@ -0,0 +1,286 @@
+//-----------------------------------------------------------------------------
+// NanoSoC CPU Subsystem - Contains CPU Core, Memory and Clock and Reset Control
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.masptone@soton.ac.uk)
+//
+// Copyright (C) 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_ss_cpu #(
+ // System Parameters
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+
+ // CPU Parameters
+ parameter CLKGATE_PRESENT = 0,
+ parameter BE = 0, // 1: Big endian 0: little endian
+ parameter BKPT = 4, // Number of breakpoint comparators
+ parameter DBG = 1, // Debug configuration
+ parameter NUMIRQ = 32, // NUM of IRQ
+ parameter SMUL = 0, // Multiplier configuration
+ parameter SYST = 1, // SysTick
+ parameter WIC = 1, // Wake-up interrupt controller support
+ parameter WICLINES = 34, // Supported WIC lines
+ parameter WPT = 2, // Number of DWT comparators
+ parameter RESET_ALL_REGS = 0, // Do not reset all registers
+ parameter INCLUDE_JTAG = 0, // Do not Include JTAG feature
+
+ // Bootrom 0 Parameters
+ parameter BOOTROM_ADDR_W = 10, // Size of Bootrom (Based on Address Width) - Default 1KB
+
+ // IMEM 0 Parameters
+ parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
+ parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
+ parameter IMEM_RAM_FPGA_IMG = "image.hex", // Image to Preload into SRAM
+
+ // DMEM 0 Parameters
+ parameter DMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
+ parameter DMEM_RAM_DATA_W = 32 // Width of IMEM RAM Data Bus - Default 32 bits
+)(
+ // System Input Clocks and Resets
+ input wire SYS_FCLK, // Free running clock
+ input wire SYS_SYSRESETn, // System Reset
+ input wire SYS_SCANENABLE, // Scan Mode Enable
+ input wire SYS_TESTMODE, // Test Mode Enable (Override Synchronisers)
+
+ // System Reset Request Signals
+ input wire SYS_SYSRESETREQ, // System Request from System Managers
+ output wire SYS_PRMURESETREQ, // CPU Control Reset Request (PMU and Reset Unit)
+
+ // Generated Clocks and Resets
+ output wire SYS_PORESETn, // System Power On Reset
+ output wire SYS_HCLK, // AHB Clock
+ output wire SYS_HRESETn, // AHB and System reset
+
+ // Power Management Signals
+ input wire SYS_PMUENABLE, // Power Management Enable
+ output wire SYS_PMUDBGRESETREQ, // Power Management Debug Reset Req
+
+ // CPU 0 AHB Lite port
+ output wire [31:0] CPU_0_HADDR, // Address bus
+ output wire [1:0] CPU_0_HTRANS, // Transfer type
+ output wire CPU_0_HWRITE, // Transfer direction
+ output wire [2:0] CPU_0_HSIZE, // Transfer size
+ output wire [2:0] CPU_0_HBURST, // Burst type
+ output wire [3:0] CPU_0_HPROT, // Protection control
+ output wire [31:0] CPU_0_HWDATA, // Write data
+ output wire CPU_0_HMASTLOCK, // Locked Sequence
+ input wire [31:0] CPU_0_HRDATA, // Read data bus
+ input wire CPU_0_HREADY, // HREADY feedback
+ input wire CPU_0_HRESP, // Transfer response
+
+ // Bootrom 0 AHB Lite port
+ input wire [31:0] BOOTROM_0_HADDR, // Address bus
+ input wire [1:0] BOOTROM_0_HTRANS, // Transfer type
+ input wire BOOTROM_0_HWRITE, // Transfer direction
+ input wire [2:0] BOOTROM_0_HSIZE, // Transfer size
+ input wire [2:0] BOOTROM_0_HBURST, // Burst type
+ input wire [3:0] BOOTROM_0_HPROT, // Protection control
+ input wire [31:0] BOOTROM_0_HWDATA, // Write data
+ input wire BOOTROM_0_HMASTLOCK, // Locked Sequence
+ output wire [31:0] BOOTROM_0_HRDATA, // Read data bus
+ output wire BOOTROM_0_HREADY, // HREADY feedback
+ output wire BOOTROM_0_HRESP, // Transfer response
+
+ // IMEM 0 AHB Lite port
+ input wire [31:0] IMEM_0_HADDR, // Address bus
+ input wire [1:0] IMEM_0_HTRANS, // Transfer type
+ input wire IMEM_0_HWRITE, // Transfer direction
+ input wire [2:0] IMEM_0_HSIZE, // Transfer size
+ input wire [2:0] IMEM_0_HBURST, // Burst type
+ input wire [3:0] IMEM_0_HPROT, // Protection control
+ input wire [31:0] IMEM_0_HWDATA, // Write data
+ input wire IMEM_0_HMASTLOCK, // Locked Sequence
+ output wire [31:0] IMEM_0_HRDATA, // Read data bus
+ output wire IMEM_0_HREADY, // HREADY feedback
+ output wire IMEM_0_HRESP, // Transfer response
+
+ // DMEM 0 AHB Lite port
+ input wire [31:0] DMEM_0_HADDR, // Address bus
+ input wire [1:0] DMEM_0_HTRANS, // Transfer type
+ input wire DMEM_0_HWRITE, // Transfer direction
+ input wire [2:0] DMEM_0_HSIZE, // Transfer size
+ input wire [2:0] DMEM_0_HBURST, // Burst type
+ input wire [3:0] DMEM_0_HPROT, // Protection control
+ input wire [31:0] DMEM_0_HWDATA, // Write data
+ input wire DMEM_0_HMASTLOCK, // Locked Sequence
+ output wire [31:0] DMEM_0_HRDATA, // Read data bus
+ output wire DMEM_0_HREADY, // HREADY feedback
+ output wire DMEM_0_HRESP, // Transfer response
+
+ // CPU Sideband signalling
+ input wire CPU_0_NMI, // Non-Maskable Interrupt request
+ input wire [31:0] CPU_0_IRQ, // Maskable Interrupt requests
+ output wire CPU_0_TXEV, // Send Event (SEV) output
+ input wire CPU_0_RXEV, // Receive Event input
+ output wire CPU_0_LOCKUP, // Wake up request from WIC
+ output wire CPU_0_SYSRESETREQ, // System reset request
+
+ output wire CPU_0_SLEEPING, // Processor status - sleeping
+ output wire CPU_0_SLEEPDEEP, // Processor status - deep sleep
+
+ // Serial-Wire Debug
+ input wire CPU_0_SWDI, // SWD data input
+ input wire CPU_0_SWCLK, // SWD clock
+ output wire CPU_0_SWDO, // SWD data output
+ output wire CPU_0_SWDOEN // SWD data output enable
+);
+ // -------------------------------
+ // CPU Core 0 Instantiation
+ // -------------------------------
+ slcorem0 #(
+ .ACG (CLKGATE_PRESENT), // Architectural clock gating
+ .BE (BE), // Big-endian
+ .BKPT (BKPT), // Number of breakpoint comparators
+ .DBG (DBG), // Debug configuration
+ .JTAGnSW (INCLUDE_JTAG), // Debug port interface: JTAGnSW
+ .NUMIRQ (NUMIRQ), // Number of Interrupts
+ .RAR (RESET_ALL_REGS), // Reset All Registers
+ .SMUL (SMUL), // Multiplier configuration
+ .SYST (SYST), // SysTick
+ .WIC (WIC), // Wake-up interrupt controller support
+ .WICLINES (WICLINES), // Supported WIC lines
+ .WPT (WPT) // Number of DWT comparators
+ ) u_manager_cpu_0 (
+ // System Input Clocks and Resets
+ .SYS_FCLK(SYS_FCLK),
+ .SYS_SYSRESETn(SYS_SYSRESETn),
+ .SYS_SCANENABLE(SYS_SCANENABLE),
+ .SYS_TESTMODE(SYS_TESTMODE),
+
+ // System Reset Request Signals
+ .SYS_SYSRESETREQ(SYS_SYSRESETREQ),
+ .SYS_PRMURESETREQ(SYS_PRMURESETREQ),
+
+ // Generated Clocks and Resets
+ .SYS_PORESETn(SYS_PORESETn),
+ .SYS_HCLK(SYS_HCLK),
+ .SYS_HRESETn(SYS_HRESETn),
+
+ // Power Management Signals
+ .SYS_PMUENABLE(SYS_PMUENABLE),
+ .SYS_PMUDBGRESETREQ(SYS_PMUDBGRESETREQ),
+
+ // AHB Lite port
+ .HADDR(CPU_0_HADDR),
+ .HTRANS(CPU_0_HTRANS),
+ .HWRITE(CPU_0_HWRITE),
+ .HSIZE(CPU_0_HSIZE),
+ .HBURST(CPU_0_HBURST),
+ .HPROT(CPU_0_HPROT),
+ .HWDATA(CPU_0_HWDATA),
+ .HMASTLOCK(CPU_0_HMASTLOCK),
+ .HRDATA(CPU_0_HRDATA),
+ .HREADY(CPU_0_HREADY),
+ .HRESP(CPU_0_HRESP),
+
+ // Sideband CPU signalling
+ .CORE_NMI(CPU_0_NMI),
+ .CORE_IRQ(CPU_0_IRQ),
+ .CORE_TXEV(CPU_0_TXEV),
+ .CORE_RXEV(CPU_0_RXEV),
+ .CORE_LOCKUP(CPU_0_LOCKUP),
+ .CORE_SYSRESETREQ(CPU_0_SYSRESETREQ),
+
+ .CORE_SLEEPING(CPU_0_SLEEPING),
+ .CORE_SLEEPDEEP(CPU_0_SLEEPDEEP),
+
+ // Serial-Wire Debug
+ .CORE_SWDI(CPU_0_SWDI),
+ .CORE_SWCLK(CPU_0_SWCLK),
+ .CORE_SWDO(CPU_0_SWDO),
+ .CORE_SWDOEN(CPU_0_SWDOEN)
+ );
+
+ // ----------------------------------
+ // CPU 0 Bootrom Region Instantiation
+ // ----------------------------------
+ nanosoc_region_bootrom_0 #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .BOOTROM_ADDR_W (BOOTROM_ADDR_W)
+ ) u_region_bootrom_0 (
+ // Clock and Reset
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
+
+ // AHB connection to Initiator
+ .HSEL(BOOTROM_0_HSEL),
+ .HADDR(BOOTROM_0_HADDR),
+ .HTRANS(BOOTROM_0_HTRANS),
+ .HSIZE(BOOTROM_0_HSIZE),
+ .HPROT(BOOTROM_0_HPROT),
+ .HWRITE(BOOTROM_0_HWRITE),
+ .HREADY(BOOTROM_0_HREADY),
+ .HWDATA(BOOTROM_0_HWDATA),
+
+ // Outputs
+ .HREADYOUT(BOOTROM_0_HREADYOUT),
+ .HRESP(BOOTROM_0_HRESP),
+ .HRDATA(BOOTROM_0_HRDATA)
+ );
+
+ // -----------------------------------------------
+ // CPU 0 Instruction Memory Region Instantiation
+ // -----------------------------------------------
+ nanosoc_region_imem_0 #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .IMEM_RAM_ADDR_W (IMEM_RAM_ADDR_W),
+ .IMEM_RAM_DATA_W (IMEM_RAM_DATA_W),
+ .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG)
+ ) u_region_imem_0 (
+ // Clock and Reset
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
+
+ // AHB connection to Initiator
+ .HSEL(IMEM_0_HSEL),
+ .HADDR(IMEM_0_HADDR),
+ .HTRANS(IMEM_0_HTRANS),
+ .HSIZE(IMEM_0_HSIZE),
+ .HPROT(IMEM_0_HPROT),
+ .HWRITE(IMEM_0_HWRITE),
+ .HREADY(IMEM_0_HREADY),
+ .HWDATA(IMEM_0_HWDATA),
+
+ // Outputs
+ .HREADYOUT(IMEM_0_HREADYOUT),
+ .HRESP(IMEM_0_HRESP),
+ .HRDATA(IMEM_0_HRDATA)
+ );
+
+ // ---------------------------------------
+ // CPU 0 Data Memory Region Instantiation
+ // ---------------------------------------
+ nanosoc_region_dmem_0 #(
+ .SYS_ADDR_W (SYS_ADDR_W),
+ .SYS_DATA_W (SYS_DATA_W),
+ .DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
+ .DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
+ ) u_region_dmem_0 (
+ // Clock and Reset
+ .HCLK(SYS_HCLK),
+ .HRESETn(SYS_HRESETn),
+
+ // AHB connection to Initiator
+ .HSEL(DMEM_0_HSEL),
+ .HADDR(DMEM_0_HADDR),
+ .HTRANS(DMEM_0_HTRANS),
+ .HSIZE(DMEM_0_HSIZE),
+ .HPROT(DMEM_0_HPROT),
+ .HWRITE(DMEM_0_HWRITE),
+ .HREADY(DMEM_0_HREADY),
+ .HWDATA(DMEM_0_HWDATA),
+
+ // Outputs
+ .HREADYOUT(DMEM_0_HREADYOUT),
+ .HRESP(DMEM_0_HRESP),
+ .HRDATA(DMEM_0_HRDATA)
+ );
+
+
+endmodule
\ No newline at end of file