diff --git a/fpga/targets/pynq_kr260/fpga_pinmap.xdc b/fpga/targets/pynq_kr260/fpga_pinmap.xdc
index 480bfc2ecc2c5211fc038e1c425e14cb80519a10..991f7e485706a0cb06354f6afe1d738e1c814034 100644
--- a/fpga/targets/pynq_kr260/fpga_pinmap.xdc
+++ b/fpga/targets/pynq_kr260/fpga_pinmap.xdc
@@ -7,30 +7,38 @@
######################## PMOD 1 Upper ########################
set_property PACKAGE_PIN H12 [get_ports {PMOD0_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_0}]
+set_property PULLDOWN true [get_ports {PMOD0_0}];
set_property PACKAGE_PIN E10 [get_ports {PMOD0_1}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_1}]
+set_property PULLDOWN true [get_ports {PMOD0_1}];
set_property PACKAGE_PIN D10 [get_ports {PMOD0_2}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_2}]
+set_property PULLUP true [get_ports {PMOD0_2}];
set_property PACKAGE_PIN C11 [get_ports {PMOD0_3}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_3}]
+set_property PULLUP true [get_ports {PMOD0_3}];
######################## PMOD 1 Lower ########################
set_property PACKAGE_PIN B10 [get_ports {PMOD0_4}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_4}]
+set_property PULLUP true [get_ports {PMOD0_4}];
set_property PACKAGE_PIN E12 [get_ports {PMOD0_5}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_5}]
+set_property PULLUP true [get_ports {PMOD0_5}];
set_property PACKAGE_PIN D11 [get_ports {PMOD0_6}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_6}]
+set_property PULLUP true [get_ports {PMOD0_6}];
set_property PACKAGE_PIN B11 [get_ports {PMOD0_7}]
set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_7}]
+set_property PULLUP true [get_ports {PMOD0_7}];
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
## ######################## PMOD 2 Upper ########################
## set_property PACKAGE_PIN J11 [get_ports {PMOD1_0}]
diff --git a/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
index 61eebfbfa5714f66ab88ee0a835fab5d4361b4da..e11d1a3b2d3163c7ce02f80b20c77e398e2c36be 100644
--- a/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_kr260/vivado_script/2021_1/nanosoc_design.tcl
@@ -17,18 +17,24 @@ proc get_script_folder {} {
variable script_folder
set script_folder [_tcl::get_script_folder]
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2021.1
-set current_vivado_version [version -short]
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
- puts ""
- catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
- return 1
-}
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
################################################################
# START
@@ -37,6 +43,86 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# To test this script, run the following commands from Vivado Tcl console:
# source extio8x4_io_script.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
@@ -46,16 +132,15 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
soclabs.org:user:nanosoc_chip:1.0\
xilinx.com:ip:xlconstant:1.1\
-xilinx.com:ip:zynq_ultra_ps_e:3.3\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
-soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:smartconnect:1.0\
-xilinx.com:ip:util_reduced_logic:2.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:util_vector_logic:2.0\
"
@@ -144,178 +229,473 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_0
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
# Create instance: axi_gpio_1, and set properties
set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_1
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
# Create instance: axi_stream_io_0, and set properties
set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {64} \
- ] $axis_data_fifo_0
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
- # Create instance: extio8x4_axis_target_0, and set properties
- set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
- # Create instance: p1_extio_concat_o, and set properties
- set p1_extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_o ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_o
-
- # Create instance: p1_extio_concat_z, and set properties
- set p1_extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_z ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_z
-
- # Create instance: p1_o_bit0_ioreq1, and set properties
- set p1_o_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit0_ioreq1 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {0} \
- CONFIG.DIN_TO {0} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit0_ioreq1
-
- # Create instance: p1_o_bit1_ioreq2, and set properties
- set p1_o_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1_ioreq2 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {1} \
- CONFIG.DIN_TO {1} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit1_ioreq2
-
- # Create instance: p1_o_bit3_iodatata4, and set properties
- set p1_o_bit3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3_iodatata4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {6} \
- CONFIG.DIN_TO {3} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {4} \
- ] $p1_o_bit3_iodatata4
-
- # Create instance: pmoda_i_bit4, and set properties
- set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {4} \
- CONFIG.DIN_TO {4} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit4
-
- # Create instance: pmoda_i_bit7, and set properties
- set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {7} \
- CONFIG.DIN_TO {7} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit7
-
- # Create instance: pmoda_z_concat8, and set properties
- set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
- set_property -dict [ list \
- CONFIG.NUM_PORTS {8} \
- ] $pmoda_z_concat8
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
- set_property -dict [ list \
- CONFIG.NUM_MI {3} \
- CONFIG.NUM_SI {1} \
- ] $smartconnect_0
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
- # Create instance: util_reduced_logic_0, and set properties
- set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ]
- # Create instance: util_vector_logic_0, and set properties
- set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
- # Create instance: xlconcat_0, and set properties
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {8} \
- CONFIG.IN1_WIDTH {8} \
- ] $xlconcat_0
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
# Create instance: xlconst_zero, and set properties
set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconst_zero
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
- # Create instance: xlconst_zerox8, and set properties
- set xlconst_zerox8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox8 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {8} \
- ] $xlconst_zerox8
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
# Create instance: xlconstant_1, and set properties
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
# Create interface connections
connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
- connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
- connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
- connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
- connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconst_zero/dout]
- connect_bd_net -net const1 [get_bd_pins p1_extio_concat_z/In0] [get_bd_pins p1_extio_concat_z/In1] [get_bd_pins xlconstant_1/dout]
- connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins p1_extio_concat_z/In3]
- connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout] [get_bd_pins xlconcat_0/In0]
- connect_bd_net -net p1_extio_concat_z_dout [get_bd_pins pmoda_tri_z] [get_bd_pins p1_extio_concat_z/dout]
- connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins p1_o_bit0_ioreq1/Dout]
- connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins p1_o_bit1_ioreq2/Dout]
- connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins p1_o_bit3_iodatata4/Dout]
- connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i]
- connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
- connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
- connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
- connect_bd_net -net xlconcat_0_dout [get_bd_pins p1_tri_i] [get_bd_pins xlconcat_0/dout]
- connect_bd_net -net xlconst_zerox8_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconst_zerox8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -328,6 +708,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
proc create_root_design { parentCell } {
variable script_folder
+ variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
@@ -367,1536 +748,1023 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
# Create instance: xlconstant_zero, and set properties
set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconstant_zero
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
# Create instance: xlconstant_zerox4, and set properties
set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {4} \
- ] $xlconstant_zerox4
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
# Create instance: zynq_ultra_ps_e_0, and set properties
- set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
- set_property -dict [ list \
- CONFIG.CAN0_BOARD_INTERFACE {custom} \
- CONFIG.CAN1_BOARD_INTERFACE {custom} \
- CONFIG.CSU_BOARD_INTERFACE {custom} \
- CONFIG.DP_BOARD_INTERFACE {custom} \
- CONFIG.GEM0_BOARD_INTERFACE {custom} \
- CONFIG.GEM1_BOARD_INTERFACE {custom} \
- CONFIG.GEM2_BOARD_INTERFACE {custom} \
- CONFIG.GEM3_BOARD_INTERFACE {custom} \
- CONFIG.GPIO_BOARD_INTERFACE {custom} \
- CONFIG.IIC0_BOARD_INTERFACE {custom} \
- CONFIG.IIC1_BOARD_INTERFACE {custom} \
- CONFIG.NAND_BOARD_INTERFACE {custom} \
- CONFIG.PCIE_BOARD_INTERFACE {custom} \
- CONFIG.PJTAG_BOARD_INTERFACE {custom} \
- CONFIG.PMU_BOARD_INTERFACE {custom} \
- CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
- CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
- CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
- CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
- CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
- CONFIG.PSU_IMPORT_BOARD_PRESET {} \
- CONFIG.PSU_MIO_0_DIRECTION {out} \
- CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_0_POLARITY {Default} \
- CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_0_SLEW {fast} \
- CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_10_POLARITY {Default} \
- CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_10_SLEW {fast} \
- CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_11_POLARITY {Default} \
- CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_11_SLEW {fast} \
- CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_12_POLARITY {Default} \
- CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_12_SLEW {fast} \
- CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_13_POLARITY {Default} \
- CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_13_SLEW {fast} \
- CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_14_POLARITY {Default} \
- CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_14_SLEW {fast} \
- CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_15_POLARITY {Default} \
- CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_15_SLEW {fast} \
- CONFIG.PSU_MIO_16_DIRECTION {inout} \
- CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_16_POLARITY {Default} \
- CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_16_SLEW {fast} \
- CONFIG.PSU_MIO_17_DIRECTION {inout} \
- CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_17_POLARITY {Default} \
- CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_17_SLEW {fast} \
- CONFIG.PSU_MIO_18_DIRECTION {in} \
- CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_18_POLARITY {Default} \
- CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_18_SLEW {fast} \
- CONFIG.PSU_MIO_19_DIRECTION {out} \
- CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_19_POLARITY {Default} \
- CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_19_SLEW {fast} \
- CONFIG.PSU_MIO_1_DIRECTION {inout} \
- CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_1_POLARITY {Default} \
- CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_1_SLEW {fast} \
- CONFIG.PSU_MIO_20_DIRECTION {out} \
- CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_20_POLARITY {Default} \
- CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_20_SLEW {fast} \
- CONFIG.PSU_MIO_21_DIRECTION {in} \
- CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_21_POLARITY {Default} \
- CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_21_SLEW {fast} \
- CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_22_POLARITY {Default} \
- CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_22_SLEW {fast} \
- CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_23_POLARITY {Default} \
- CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_23_SLEW {fast} \
- CONFIG.PSU_MIO_24_DIRECTION {out} \
- CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_24_POLARITY {Default} \
- CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_24_SLEW {fast} \
- CONFIG.PSU_MIO_25_DIRECTION {in} \
- CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_25_POLARITY {Default} \
- CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_25_SLEW {fast} \
- CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_26_POLARITY {Default} \
- CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_26_SLEW {fast} \
- CONFIG.PSU_MIO_27_DIRECTION {out} \
- CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_27_POLARITY {Default} \
- CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_27_SLEW {fast} \
- CONFIG.PSU_MIO_28_DIRECTION {in} \
- CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_28_POLARITY {Default} \
- CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_28_SLEW {fast} \
- CONFIG.PSU_MIO_29_DIRECTION {out} \
- CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_29_POLARITY {Default} \
- CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_29_SLEW {fast} \
- CONFIG.PSU_MIO_2_DIRECTION {inout} \
- CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_2_POLARITY {Default} \
- CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_2_SLEW {fast} \
- CONFIG.PSU_MIO_30_DIRECTION {in} \
- CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_30_POLARITY {Default} \
- CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_30_SLEW {fast} \
- CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_31_POLARITY {Default} \
- CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_31_SLEW {fast} \
- CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_32_POLARITY {Default} \
- CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_32_SLEW {fast} \
- CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_33_POLARITY {Default} \
- CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_33_SLEW {fast} \
- CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_34_POLARITY {Default} \
- CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_34_SLEW {fast} \
- CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_35_POLARITY {Default} \
- CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_35_SLEW {fast} \
- CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_36_POLARITY {Default} \
- CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_36_SLEW {fast} \
- CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_37_POLARITY {Default} \
- CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_37_SLEW {fast} \
- CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_38_POLARITY {Default} \
- CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_38_SLEW {fast} \
- CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_39_POLARITY {Default} \
- CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_39_SLEW {fast} \
- CONFIG.PSU_MIO_3_DIRECTION {inout} \
- CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_3_POLARITY {Default} \
- CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_3_SLEW {fast} \
- CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_40_POLARITY {Default} \
- CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_40_SLEW {fast} \
- CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_41_POLARITY {Default} \
- CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_41_SLEW {fast} \
- CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_42_POLARITY {Default} \
- CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_42_SLEW {fast} \
- CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_43_POLARITY {Default} \
- CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_43_SLEW {fast} \
- CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_44_POLARITY {Default} \
- CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_44_SLEW {fast} \
- CONFIG.PSU_MIO_45_DIRECTION {in} \
- CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_45_POLARITY {Default} \
- CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_45_SLEW {fast} \
- CONFIG.PSU_MIO_46_DIRECTION {inout} \
- CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_46_POLARITY {Default} \
- CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_46_SLEW {fast} \
- CONFIG.PSU_MIO_47_DIRECTION {inout} \
- CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_47_POLARITY {Default} \
- CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_47_SLEW {fast} \
- CONFIG.PSU_MIO_48_DIRECTION {inout} \
- CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_48_POLARITY {Default} \
- CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_48_SLEW {fast} \
- CONFIG.PSU_MIO_49_DIRECTION {inout} \
- CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_49_POLARITY {Default} \
- CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_49_SLEW {fast} \
- CONFIG.PSU_MIO_4_DIRECTION {inout} \
- CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_4_POLARITY {Default} \
- CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_4_SLEW {fast} \
- CONFIG.PSU_MIO_50_DIRECTION {inout} \
- CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_50_POLARITY {Default} \
- CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_50_SLEW {fast} \
- CONFIG.PSU_MIO_51_DIRECTION {out} \
- CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_51_POLARITY {Default} \
- CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_51_SLEW {fast} \
- CONFIG.PSU_MIO_52_DIRECTION {in} \
- CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_52_POLARITY {Default} \
- CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_52_SLEW {fast} \
- CONFIG.PSU_MIO_53_DIRECTION {in} \
- CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_53_POLARITY {Default} \
- CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_53_SLEW {fast} \
- CONFIG.PSU_MIO_54_DIRECTION {inout} \
- CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_54_POLARITY {Default} \
- CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_54_SLEW {fast} \
- CONFIG.PSU_MIO_55_DIRECTION {in} \
- CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_55_POLARITY {Default} \
- CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_55_SLEW {fast} \
- CONFIG.PSU_MIO_56_DIRECTION {inout} \
- CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_56_POLARITY {Default} \
- CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_56_SLEW {fast} \
- CONFIG.PSU_MIO_57_DIRECTION {inout} \
- CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_57_POLARITY {Default} \
- CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_57_SLEW {fast} \
- CONFIG.PSU_MIO_58_DIRECTION {out} \
- CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_58_POLARITY {Default} \
- CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_58_SLEW {fast} \
- CONFIG.PSU_MIO_59_DIRECTION {inout} \
- CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_59_POLARITY {Default} \
- CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_59_SLEW {fast} \
- CONFIG.PSU_MIO_5_DIRECTION {out} \
- CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_5_POLARITY {Default} \
- CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_5_SLEW {fast} \
- CONFIG.PSU_MIO_60_DIRECTION {inout} \
- CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_60_POLARITY {Default} \
- CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_60_SLEW {fast} \
- CONFIG.PSU_MIO_61_DIRECTION {inout} \
- CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_61_POLARITY {Default} \
- CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_61_SLEW {fast} \
- CONFIG.PSU_MIO_62_DIRECTION {inout} \
- CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_62_POLARITY {Default} \
- CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_62_SLEW {fast} \
- CONFIG.PSU_MIO_63_DIRECTION {inout} \
- CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_63_POLARITY {Default} \
- CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_63_SLEW {fast} \
- CONFIG.PSU_MIO_64_DIRECTION {out} \
- CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_64_POLARITY {Default} \
- CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_64_SLEW {fast} \
- CONFIG.PSU_MIO_65_DIRECTION {out} \
- CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_65_POLARITY {Default} \
- CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_65_SLEW {fast} \
- CONFIG.PSU_MIO_66_DIRECTION {out} \
- CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_66_POLARITY {Default} \
- CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_66_SLEW {fast} \
- CONFIG.PSU_MIO_67_DIRECTION {out} \
- CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_67_POLARITY {Default} \
- CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_67_SLEW {fast} \
- CONFIG.PSU_MIO_68_DIRECTION {out} \
- CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_68_POLARITY {Default} \
- CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_68_SLEW {fast} \
- CONFIG.PSU_MIO_69_DIRECTION {out} \
- CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_69_POLARITY {Default} \
- CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_69_SLEW {fast} \
- CONFIG.PSU_MIO_6_DIRECTION {out} \
- CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_6_POLARITY {Default} \
- CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_6_SLEW {fast} \
- CONFIG.PSU_MIO_70_DIRECTION {in} \
- CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_70_POLARITY {Default} \
- CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_70_SLEW {fast} \
- CONFIG.PSU_MIO_71_DIRECTION {in} \
- CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_71_POLARITY {Default} \
- CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_71_SLEW {fast} \
- CONFIG.PSU_MIO_72_DIRECTION {in} \
- CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_72_POLARITY {Default} \
- CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_72_SLEW {fast} \
- CONFIG.PSU_MIO_73_DIRECTION {in} \
- CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_73_POLARITY {Default} \
- CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_73_SLEW {fast} \
- CONFIG.PSU_MIO_74_DIRECTION {in} \
- CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_74_POLARITY {Default} \
- CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_74_SLEW {fast} \
- CONFIG.PSU_MIO_75_DIRECTION {in} \
- CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_75_POLARITY {Default} \
- CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_75_SLEW {fast} \
- CONFIG.PSU_MIO_76_DIRECTION {out} \
- CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_76_POLARITY {Default} \
- CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_76_SLEW {fast} \
- CONFIG.PSU_MIO_77_DIRECTION {inout} \
- CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_77_POLARITY {Default} \
- CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_77_SLEW {fast} \
- CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_7_POLARITY {Default} \
- CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_7_SLEW {fast} \
- CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_8_POLARITY {Default} \
- CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_8_SLEW {fast} \
- CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_9_POLARITY {Default} \
- CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_9_SLEW {fast} \
- CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
-SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
-1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
-1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
-3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
-3}\
- CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
- CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
- CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
- CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
- CONFIG.PSU_SMC_CYCLE_T0 {NA} \
- CONFIG.PSU_SMC_CYCLE_T1 {NA} \
- CONFIG.PSU_SMC_CYCLE_T2 {NA} \
- CONFIG.PSU_SMC_CYCLE_T3 {NA} \
- CONFIG.PSU_SMC_CYCLE_T4 {NA} \
- CONFIG.PSU_SMC_CYCLE_T5 {NA} \
- CONFIG.PSU_SMC_CYCLE_T6 {NA} \
- CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
- CONFIG.PSU_VALUE_SILVERSION {3} \
- CONFIG.PSU__ACPU0__POWER__ON {1} \
- CONFIG.PSU__ACPU1__POWER__ON {1} \
- CONFIG.PSU__ACPU2__POWER__ON {0} \
- CONFIG.PSU__ACPU3__POWER__ON {0} \
- CONFIG.PSU__ACTUAL__IP {1} \
- CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
- CONFIG.PSU__AFI0_COHERENCY {0} \
- CONFIG.PSU__AFI1_COHERENCY {0} \
- CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
- CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
- CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {38} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
- CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
- CONFIG.PSU__CSU_COHERENCY {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__AL {0} \
- CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
- CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
- CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
- CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
- CONFIG.PSU__DDRC__CL {15} \
- CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
- CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
- CONFIG.PSU__DDRC__COMPONENTS {Components} \
- CONFIG.PSU__DDRC__CWL {14} \
- CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
- CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
- CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
- CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
- CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
- CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
- CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
- CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
- CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
- CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
- CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
- CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
- CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
- CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
- CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
- CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
- CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
- CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
- CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
- CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
- CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
- CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
- CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
- CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
- CONFIG.PSU__DDRC__ECC {Disabled} \
- CONFIG.PSU__DDRC__ECC_SCRUB {0} \
- CONFIG.PSU__DDRC__ENABLE {1} \
- CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
- CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
- CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
- CONFIG.PSU__DDRC__FGRM {1X} \
- CONFIG.PSU__DDRC__FREQ_MHZ {1} \
- CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
- CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LP_ASR {manual normal} \
- CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
- CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
- CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
- CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
- CONFIG.PSU__DDRC__PLL_BYPASS {0} \
- CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
- CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
- CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
- CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
- CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
- CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
- CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
- CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
- CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
- CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
- CONFIG.PSU__DDRC__T_FAW {30.0} \
- CONFIG.PSU__DDRC__T_RAS_MIN {33} \
- CONFIG.PSU__DDRC__T_RC {47.06} \
- CONFIG.PSU__DDRC__T_RCD {15} \
- CONFIG.PSU__DDRC__T_RP {15} \
- CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
- CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
- CONFIG.PSU__DDRC__VREF {1} \
- CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
- CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
- CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
- CONFIG.PSU__DEVICE_TYPE {CG} \
- CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
- CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DLL__ISUSED {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
- CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
- CONFIG.PSU__DP__REF_CLK_FREQ {27} \
- CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
- CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
- CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET0__PTP__ENABLE {0} \
- CONFIG.PSU__ENET0__TSU__ENABLE {0} \
- CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET1__PTP__ENABLE {0} \
- CONFIG.PSU__ENET1__TSU__ENABLE {0} \
- CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET2__PTP__ENABLE {0} \
- CONFIG.PSU__ENET2__TSU__ENABLE {0} \
- CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
- CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
- CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
- CONFIG.PSU__ENET3__PTP__ENABLE {0} \
- CONFIG.PSU__ENET3__TSU__ENABLE {0} \
- CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
- CONFIG.PSU__EN_EMIO_TRACE {0} \
- CONFIG.PSU__EP__IP {0} \
- CONFIG.PSU__EXPAND__CORESIGHT {0} \
- CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
- CONFIG.PSU__EXPAND__GIC {0} \
- CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
- CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
- CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
- CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__FPGA_PL0_ENABLE {1} \
- CONFIG.PSU__FPGA_PL1_ENABLE {0} \
- CONFIG.PSU__FPGA_PL2_ENABLE {0} \
- CONFIG.PSU__FPGA_PL3_ENABLE {0} \
- CONFIG.PSU__FP__POWER__ON {1} \
- CONFIG.PSU__FTM__CTI_IN_0 {0} \
- CONFIG.PSU__FTM__CTI_IN_1 {0} \
- CONFIG.PSU__FTM__CTI_IN_2 {0} \
- CONFIG.PSU__FTM__CTI_IN_3 {0} \
- CONFIG.PSU__FTM__CTI_OUT_0 {0} \
- CONFIG.PSU__FTM__CTI_OUT_1 {0} \
- CONFIG.PSU__FTM__CTI_OUT_2 {0} \
- CONFIG.PSU__FTM__CTI_OUT_3 {0} \
- CONFIG.PSU__FTM__GPI {0} \
- CONFIG.PSU__FTM__GPO {0} \
- CONFIG.PSU__GEM0_COHERENCY {0} \
- CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM1_COHERENCY {0} \
- CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM2_COHERENCY {0} \
- CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM3_COHERENCY {0} \
- CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM__TSU__ENABLE {0} \
- CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
- CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
- CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
- CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
- CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
- CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
- CONFIG.PSU__GPU_PP0__POWER__ON {0} \
- CONFIG.PSU__GPU_PP1__POWER__ON {0} \
- CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__GT__LINK_SPEED {HBR} \
- CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
- CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
- CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
- CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
- CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
- CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
- CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
- CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
- CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
- CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
- CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
- CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
- CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
- CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
- CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
- CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
- CONFIG.PSU__L2_BANK0__POWER__ON {1} \
- CONFIG.PSU__LPDMA0_COHERENCY {0} \
- CONFIG.PSU__LPDMA1_COHERENCY {0} \
- CONFIG.PSU__LPDMA2_COHERENCY {0} \
- CONFIG.PSU__LPDMA3_COHERENCY {0} \
- CONFIG.PSU__LPDMA4_COHERENCY {0} \
- CONFIG.PSU__LPDMA5_COHERENCY {0} \
- CONFIG.PSU__LPDMA6_COHERENCY {0} \
- CONFIG.PSU__LPDMA7_COHERENCY {0} \
- CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
- CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
- CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__NAND_COHERENCY {0} \
- CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
- CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
- CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
- CONFIG.PSU__NUM_FABRIC_RESETS {1} \
- CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
- CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
- CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
- CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
- CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
- CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
- CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
- CONFIG.PSU__PCIE__BAR0_64BIT {0} \
- CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR0_VAL {} \
- CONFIG.PSU__PCIE__BAR1_64BIT {0} \
- CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR1_VAL {} \
- CONFIG.PSU__PCIE__BAR2_64BIT {0} \
- CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR2_VAL {} \
- CONFIG.PSU__PCIE__BAR3_64BIT {0} \
- CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR3_VAL {} \
- CONFIG.PSU__PCIE__BAR4_64BIT {0} \
- CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR4_VAL {} \
- CONFIG.PSU__PCIE__BAR5_64BIT {0} \
- CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR5_VAL {} \
- CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
- CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
- CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
- CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
- CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
- CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
- CONFIG.PSU__PCIE__DEVICE_ID {} \
- CONFIG.PSU__PCIE__ECRC_CHECK {0} \
- CONFIG.PSU__PCIE__ECRC_ERR {0} \
- CONFIG.PSU__PCIE__ECRC_GEN {0} \
- CONFIG.PSU__PCIE__EROM_ENABLE {0} \
- CONFIG.PSU__PCIE__EROM_VAL {} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
- CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
- CONFIG.PSU__PCIE__INTX_GENERATION {0} \
- CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
- CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
- CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
- CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
- CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MULTIHEADER {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
- CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
- CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
- CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
- CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
- CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
- CONFIG.PSU__PCIE__REVISION_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
- CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
- CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
- CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
- CONFIG.PSU__PCIE__VENDOR_ID {} \
- CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PL_CLK0_BUF {TRUE} \
- CONFIG.PSU__PL_CLK1_BUF {FALSE} \
- CONFIG.PSU__PL_CLK2_BUF {FALSE} \
- CONFIG.PSU__PL_CLK3_BUF {FALSE} \
- CONFIG.PSU__PL__POWER__ON {1} \
- CONFIG.PSU__PMU_COHERENCY {0} \
- CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
- CONFIG.PSU__PMU__GPI0__ENABLE {0} \
- CONFIG.PSU__PMU__GPI1__ENABLE {0} \
- CONFIG.PSU__PMU__GPI2__ENABLE {0} \
- CONFIG.PSU__PMU__GPI3__ENABLE {0} \
- CONFIG.PSU__PMU__GPI4__ENABLE {0} \
- CONFIG.PSU__PMU__GPI5__ENABLE {0} \
- CONFIG.PSU__PMU__GPO0__ENABLE {0} \
- CONFIG.PSU__PMU__GPO1__ENABLE {0} \
- CONFIG.PSU__PMU__GPO2__ENABLE {0} \
- CONFIG.PSU__PMU__GPO3__ENABLE {0} \
- CONFIG.PSU__PMU__GPO4__ENABLE {0} \
- CONFIG.PSU__PMU__GPO5__ENABLE {0} \
- CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
- CONFIG.PSU__PRESET_APPLIED {1} \
- CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__DEBUG {0} \
- CONFIG.PSU__PROTECTION__ENABLE {0} \
- CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
-SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
-SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |\
-SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
-subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
- CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
-Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
- CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
- CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
- CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
- CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
- CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
- CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
- CONFIG.PSU__QSPI_COHERENCY {0} \
- CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
- CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
- CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
- CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
- CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
- CONFIG.PSU__REPORT__DBGLOG {0} \
- CONFIG.PSU__RPU_COHERENCY {0} \
- CONFIG.PSU__RPU__POWER__ON {1} \
- CONFIG.PSU__SATA__LANE0__ENABLE {0} \
- CONFIG.PSU__SATA__LANE1__ENABLE {1} \
- CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
- CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
- CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
- CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
- CONFIG.PSU__SD0_COHERENCY {0} \
- CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SD0__RESET__ENABLE {0} \
- CONFIG.PSU__SD1_COHERENCY {0} \
- CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
- CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
- CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
- CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
- CONFIG.PSU__SD1__RESET__ENABLE {0} \
- CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
- CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
- CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
- CONFIG.PSU__TCM0A__POWER__ON {1} \
- CONFIG.PSU__TCM0B__POWER__ON {1} \
- CONFIG.PSU__TCM1A__POWER__ON {1} \
- CONFIG.PSU__TCM1B__POWER__ON {1} \
- CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
- CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
- CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRISTATE__INVERTED {1} \
- CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
- CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
- CONFIG.PSU__UART0__BAUD_RATE {115200} \
- CONFIG.PSU__UART0__MODEM__ENABLE {0} \
- CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
- CONFIG.PSU__UART1__BAUD_RATE {115200} \
- CONFIG.PSU__UART1__MODEM__ENABLE {0} \
- CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
- CONFIG.PSU__USB0_COHERENCY {0} \
- CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
- CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
- CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
- CONFIG.PSU__USB0__RESET__ENABLE {0} \
- CONFIG.PSU__USB1_COHERENCY {0} \
- CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB1__RESET__ENABLE {0} \
- CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
- CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
- CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
- CONFIG.PSU__USE__ADMA {0} \
- CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__AUDIO {0} \
- CONFIG.PSU__USE__CLK {0} \
- CONFIG.PSU__USE__CLK0 {0} \
- CONFIG.PSU__USE__CLK1 {0} \
- CONFIG.PSU__USE__CLK2 {0} \
- CONFIG.PSU__USE__CLK3 {0} \
- CONFIG.PSU__USE__CROSS_TRIGGER {0} \
- CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
- CONFIG.PSU__USE__DEBUG__TEST {0} \
- CONFIG.PSU__USE__EVENT_RPU {0} \
- CONFIG.PSU__USE__FABRIC__RST {1} \
- CONFIG.PSU__USE__FTM {0} \
- CONFIG.PSU__USE__GDMA {0} \
- CONFIG.PSU__USE__IRQ {0} \
- CONFIG.PSU__USE__IRQ0 {1} \
- CONFIG.PSU__USE__IRQ1 {0} \
- CONFIG.PSU__USE__M_AXI_GP0 {0} \
- CONFIG.PSU__USE__M_AXI_GP1 {0} \
- CONFIG.PSU__USE__M_AXI_GP2 {1} \
- CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
- CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__RST0 {0} \
- CONFIG.PSU__USE__RST1 {0} \
- CONFIG.PSU__USE__RST2 {0} \
- CONFIG.PSU__USE__RST3 {0} \
- CONFIG.PSU__USE__RTC {0} \
- CONFIG.PSU__USE__STM {0} \
- CONFIG.PSU__USE__S_AXI_ACE {0} \
- CONFIG.PSU__USE__S_AXI_ACP {0} \
- CONFIG.PSU__USE__S_AXI_GP0 {0} \
- CONFIG.PSU__USE__S_AXI_GP1 {0} \
- CONFIG.PSU__USE__S_AXI_GP2 {0} \
- CONFIG.PSU__USE__S_AXI_GP3 {0} \
- CONFIG.PSU__USE__S_AXI_GP4 {0} \
- CONFIG.PSU__USE__S_AXI_GP5 {0} \
- CONFIG.PSU__USE__S_AXI_GP6 {0} \
- CONFIG.PSU__USE__USB3_0_HUB {0} \
- CONFIG.PSU__USE__USB3_1_HUB {0} \
- CONFIG.PSU__USE__VIDEO {0} \
- CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
- CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
- CONFIG.QSPI_BOARD_INTERFACE {custom} \
- CONFIG.SATA_BOARD_INTERFACE {custom} \
- CONFIG.SD0_BOARD_INTERFACE {custom} \
- CONFIG.SD1_BOARD_INTERFACE {custom} \
- CONFIG.SPI0_BOARD_INTERFACE {custom} \
- CONFIG.SPI1_BOARD_INTERFACE {custom} \
- CONFIG.SUBPRESET1 {Custom} \
- CONFIG.SUBPRESET2 {Custom} \
- CONFIG.SWDT0_BOARD_INTERFACE {custom} \
- CONFIG.SWDT1_BOARD_INTERFACE {custom} \
- CONFIG.TRACE_BOARD_INTERFACE {custom} \
- CONFIG.TTC0_BOARD_INTERFACE {custom} \
- CONFIG.TTC1_BOARD_INTERFACE {custom} \
- CONFIG.TTC2_BOARD_INTERFACE {custom} \
- CONFIG.TTC3_BOARD_INTERFACE {custom} \
- CONFIG.UART0_BOARD_INTERFACE {custom} \
- CONFIG.UART1_BOARD_INTERFACE {custom} \
- CONFIG.USB0_BOARD_INTERFACE {custom} \
- CONFIG.USB1_BOARD_INTERFACE {custom} \
- ] $zynq_ultra_ps_e_0
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
# Create interface connections
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
@@ -1907,50 +1775,40 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
- connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
- connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
- connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
- connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
- connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
- connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
- connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
- connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
- connect_bd_net -net xlconstant_zero_dout [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins xlconstant_zero/dout]
- connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins nanosoc_chip_0/bist_in] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins xlconstant_zerox4/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
# Create address segments
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
+ validate_bd_design
+ save_bd_design
}
# End of create_root_design()
+##################################################################
+# MAIN FLOW
+##################################################################
+#create_root_design ""
-proc available_tcl_procs { } {
- puts "##################################################################"
- puts "# Available Tcl procedures to recreate hierarchical blocks:"
- puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
- puts "# create_root_design"
- puts "#"
- puts "#"
- puts "# The following procedures will create hiearchical blocks with addressing "
- puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
- puts "# will not be handled outside those blocks:"
- puts "#"
- puts "# create_root_design"
- puts "#"
- puts "##################################################################"
-}
-available_tcl_procs
diff --git a/fpga/targets/pynq_kr260/vivado_script/2024_1/nanosoc_design.tcl b/fpga/targets/pynq_kr260/vivado_script/2024_1/nanosoc_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1ce92fac68668e843afa76c1c4a755e0cd465278
--- /dev/null
+++ b/fpga/targets/pynq_kr260/vivado_script/2024_1/nanosoc_design.tcl
@@ -0,0 +1,1812 @@
+
+################################################################
+# This is a generated script based on design: extio8x4_io
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
+
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source extio8x4_io_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
+
+ # Create instance: xlconst_zero, and set properties
+ set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
+ # Create instance: xlconstant_zero, and set properties
+ set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
+
+ # Create instance: xlconstant_zerox4, and set properties
+ set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+#create_root_design ""
diff --git a/fpga/targets/pynq_kv260/fpga_pinmap.xdc b/fpga/targets/pynq_kv260/fpga_pinmap.xdc
index fe0b9409e70db477c32e589bf9601eacb36621a3..6ed980ebc29507ef1fd8253e17da6e680c3f7aad 100644
--- a/fpga/targets/pynq_kv260/fpga_pinmap.xdc
+++ b/fpga/targets/pynq_kv260/fpga_pinmap.xdc
@@ -4,6 +4,45 @@
## ##
##################################################################################
+
+######################## PMOD 1 Upper ########################
+set_property PACKAGE_PIN H12 [get_ports {PMOD0_0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_0}]
+set_property PULLDOWN true [get_ports {PMOD0_0}];
+
+set_property PACKAGE_PIN E10 [get_ports {PMOD0_1}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_1}]
+set_property PULLDOWN true [get_ports {PMOD0_1}];
+
+set_property PACKAGE_PIN D10 [get_ports {PMOD0_2}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_2}]
+set_property PULLUP true [get_ports {PMOD0_2}];
+
+set_property PACKAGE_PIN C11 [get_ports {PMOD0_3}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_3}]
+set_property PULLUP true [get_ports {PMOD0_3}];
+
+######################## PMOD 1 Lower ########################
+set_property PACKAGE_PIN B10 [get_ports {PMOD0_4}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_4}]
+set_property PULLUP true [get_ports {PMOD0_4}];
+
+set_property PACKAGE_PIN E12 [get_ports {PMOD0_5}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_5}]
+set_property PULLUP true [get_ports {PMOD0_5}];
+
+set_property PACKAGE_PIN D11 [get_ports {PMOD0_6}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_6}]
+set_property PULLUP true [get_ports {PMOD0_6}];
+
+set_property PACKAGE_PIN B11 [get_ports {PMOD0_7}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_7}]
+set_property PULLUP true [get_ports {PMOD0_7}];
+
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+######################## KV260 camera ########################
+
# PCAM MIPI ISP
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_p}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {mipi_phy_if_isp_clk_n}]
@@ -17,21 +56,6 @@ set_property PACKAGE_PIN G11 [get_ports iic_scl_io]
set_property PACKAGE_PIN F10 [get_ports iic_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports iic_*]
-# PMOD
-set_property PACKAGE_PIN B11 [get_ports "pmod[7]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L10P_AD10P_45
-set_property PACKAGE_PIN D11 [get_ports "pmod[6]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L8N_HDGC_45
-set_property PACKAGE_PIN E12 [get_ports "pmod[5]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L8P_HDGC_45
-set_property PACKAGE_PIN B10 [get_ports "pmod[4]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L9N_AD11N_45
-set_property PACKAGE_PIN C11 [get_ports "pmod[3]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L9P_AD11P_45
-set_property PACKAGE_PIN D10 [get_ports "pmod[2]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L7N_HDGC_45
-set_property PACKAGE_PIN E10 [get_ports "pmod[1]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L7P_HDGC_45
-set_property PACKAGE_PIN H12 [get_ports "pmod[0]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L4N_AD12N_45
-set_property IOSTANDARD LVCMOS33 [get_ports pmod[*]]
-set_property PULLUP true [get_ports {pmod[2]}];
-set_property PULLUP true [get_ports {pmod[3]}];
-set_property PULLUP true [get_ports {pmod[6]}];
-set_property PULLUP true [get_ports {pmod[7]}];
-
# Digilent PCAM 5C MIPI Camera Enable
set_property PACKAGE_PIN F11 [get_ports "cam_gpio_tri_o[0]"] ;# Bank 45 VCCO - som240_1_b13 - IO_L6N_HDGC_45
set_property IOSTANDARD LVCMOS33 [get_ports cam_gpio_tri_o[*]]
diff --git a/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
index f2d56de3df0c66c47498306ab1179db9adce0866..1ce92fac68668e843afa76c1c4a755e0cd465278 100644
--- a/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_kv260/vivado_script/2021_1/nanosoc_design.tcl
@@ -17,18 +17,24 @@ proc get_script_folder {} {
variable script_folder
set script_folder [_tcl::get_script_folder]
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2021.1
-set current_vivado_version [version -short]
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
- puts ""
- catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
- return 1
-}
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
################################################################
# START
@@ -37,6 +43,86 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# To test this script, run the following commands from Vivado Tcl console:
# source extio8x4_io_script.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
@@ -46,15 +132,16 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
soclabs.org:user:nanosoc_chip:1.0\
xilinx.com:ip:xlconstant:1.1\
-xilinx.com:ip:zynq_ultra_ps_e:3.3\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
-soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
"
set list_ips_missing ""
@@ -142,172 +229,473 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_0
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
# Create instance: axi_gpio_1, and set properties
set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_1
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
# Create instance: axi_stream_io_0, and set properties
set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {64} \
- ] $axis_data_fifo_0
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
- # Create instance: extio8x4_axis_target_0, and set properties
- set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
- # Create instance: p1_extio_concat_o, and set properties
- set p1_extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_o ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_o
-
- # Create instance: p1_extio_concat_z, and set properties
- set p1_extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_z ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_z
-
- # Create instance: p1_o_bit0_ioreq1, and set properties
- set p1_o_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit0_ioreq1 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {0} \
- CONFIG.DIN_TO {0} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit0_ioreq1
-
- # Create instance: p1_o_bit1_ioreq2, and set properties
- set p1_o_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1_ioreq2 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {1} \
- CONFIG.DIN_TO {1} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit1_ioreq2
-
- # Create instance: p1_o_bit3_iodatata4, and set properties
- set p1_o_bit3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3_iodatata4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {6} \
- CONFIG.DIN_TO {3} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {4} \
- ] $p1_o_bit3_iodatata4
-
- # Create instance: pmoda_i_bit4, and set properties
- set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {4} \
- CONFIG.DIN_TO {4} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit4
-
- # Create instance: pmoda_i_bit7, and set properties
- set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {7} \
- CONFIG.DIN_TO {7} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit7
-
- # Create instance: pmoda_z_concat8, and set properties
- set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
- set_property -dict [ list \
- CONFIG.NUM_PORTS {8} \
- ] $pmoda_z_concat8
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
- set_property -dict [ list \
- CONFIG.NUM_MI {3} \
- CONFIG.NUM_SI {1} \
- ] $smartconnect_0
-
- # Create instance: xlconcat_0, and set properties
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {8} \
- CONFIG.IN1_WIDTH {8} \
- ] $xlconcat_0
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
# Create instance: xlconst_zero, and set properties
set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconst_zero
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
- # Create instance: xlconst_zerox8, and set properties
- set xlconst_zerox8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox8 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {8} \
- ] $xlconst_zerox8
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
# Create instance: xlconstant_1, and set properties
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
# Create interface connections
connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
- connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
- connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
- connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
- connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconst_zero/dout]
- connect_bd_net -net const1 [get_bd_pins p1_extio_concat_z/In0] [get_bd_pins p1_extio_concat_z/In1] [get_bd_pins xlconstant_1/dout]
- connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins p1_extio_concat_z/In3]
- connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout] [get_bd_pins xlconcat_0/In0]
- connect_bd_net -net p1_extio_concat_z_dout [get_bd_pins pmoda_tri_z] [get_bd_pins p1_extio_concat_z/dout]
- connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins p1_o_bit0_ioreq1/Dout]
- connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins p1_o_bit1_ioreq2/Dout]
- connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins p1_o_bit3_iodatata4/Dout]
- connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i]
- connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
- connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
- connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
- connect_bd_net -net xlconcat_0_dout [get_bd_pins p1_tri_i] [get_bd_pins xlconcat_0/dout]
- connect_bd_net -net xlconst_zerox8_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconst_zerox8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -320,6 +708,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
proc create_root_design { parentCell } {
variable script_folder
+ variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
@@ -359,1536 +748,1023 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
# Create instance: xlconstant_zero, and set properties
set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconstant_zero
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
# Create instance: xlconstant_zerox4, and set properties
set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {4} \
- ] $xlconstant_zerox4
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
# Create instance: zynq_ultra_ps_e_0, and set properties
- set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
- set_property -dict [ list \
- CONFIG.CAN0_BOARD_INTERFACE {custom} \
- CONFIG.CAN1_BOARD_INTERFACE {custom} \
- CONFIG.CSU_BOARD_INTERFACE {custom} \
- CONFIG.DP_BOARD_INTERFACE {custom} \
- CONFIG.GEM0_BOARD_INTERFACE {custom} \
- CONFIG.GEM1_BOARD_INTERFACE {custom} \
- CONFIG.GEM2_BOARD_INTERFACE {custom} \
- CONFIG.GEM3_BOARD_INTERFACE {custom} \
- CONFIG.GPIO_BOARD_INTERFACE {custom} \
- CONFIG.IIC0_BOARD_INTERFACE {custom} \
- CONFIG.IIC1_BOARD_INTERFACE {custom} \
- CONFIG.NAND_BOARD_INTERFACE {custom} \
- CONFIG.PCIE_BOARD_INTERFACE {custom} \
- CONFIG.PJTAG_BOARD_INTERFACE {custom} \
- CONFIG.PMU_BOARD_INTERFACE {custom} \
- CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
- CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
- CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
- CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
- CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
- CONFIG.PSU_IMPORT_BOARD_PRESET {} \
- CONFIG.PSU_MIO_0_DIRECTION {out} \
- CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_0_POLARITY {Default} \
- CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_0_SLEW {fast} \
- CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_10_POLARITY {Default} \
- CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_10_SLEW {fast} \
- CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_11_POLARITY {Default} \
- CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_11_SLEW {fast} \
- CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_12_POLARITY {Default} \
- CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_12_SLEW {fast} \
- CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_13_POLARITY {Default} \
- CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_13_SLEW {fast} \
- CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_14_POLARITY {Default} \
- CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_14_SLEW {fast} \
- CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_15_POLARITY {Default} \
- CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_15_SLEW {fast} \
- CONFIG.PSU_MIO_16_DIRECTION {inout} \
- CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_16_POLARITY {Default} \
- CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_16_SLEW {fast} \
- CONFIG.PSU_MIO_17_DIRECTION {inout} \
- CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_17_POLARITY {Default} \
- CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_17_SLEW {fast} \
- CONFIG.PSU_MIO_18_DIRECTION {in} \
- CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_18_POLARITY {Default} \
- CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_18_SLEW {fast} \
- CONFIG.PSU_MIO_19_DIRECTION {out} \
- CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_19_POLARITY {Default} \
- CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_19_SLEW {fast} \
- CONFIG.PSU_MIO_1_DIRECTION {inout} \
- CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_1_POLARITY {Default} \
- CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_1_SLEW {fast} \
- CONFIG.PSU_MIO_20_DIRECTION {out} \
- CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_20_POLARITY {Default} \
- CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_20_SLEW {fast} \
- CONFIG.PSU_MIO_21_DIRECTION {in} \
- CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_21_POLARITY {Default} \
- CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_21_SLEW {fast} \
- CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_22_POLARITY {Default} \
- CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_22_SLEW {fast} \
- CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_23_POLARITY {Default} \
- CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_23_SLEW {fast} \
- CONFIG.PSU_MIO_24_DIRECTION {out} \
- CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_24_POLARITY {Default} \
- CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_24_SLEW {fast} \
- CONFIG.PSU_MIO_25_DIRECTION {in} \
- CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_25_POLARITY {Default} \
- CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_25_SLEW {fast} \
- CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_26_POLARITY {Default} \
- CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_26_SLEW {fast} \
- CONFIG.PSU_MIO_27_DIRECTION {out} \
- CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_27_POLARITY {Default} \
- CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_27_SLEW {fast} \
- CONFIG.PSU_MIO_28_DIRECTION {in} \
- CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_28_POLARITY {Default} \
- CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_28_SLEW {fast} \
- CONFIG.PSU_MIO_29_DIRECTION {out} \
- CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_29_POLARITY {Default} \
- CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_29_SLEW {fast} \
- CONFIG.PSU_MIO_2_DIRECTION {inout} \
- CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_2_POLARITY {Default} \
- CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_2_SLEW {fast} \
- CONFIG.PSU_MIO_30_DIRECTION {in} \
- CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_30_POLARITY {Default} \
- CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_30_SLEW {fast} \
- CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_31_POLARITY {Default} \
- CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_31_SLEW {fast} \
- CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_32_POLARITY {Default} \
- CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_32_SLEW {fast} \
- CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_33_POLARITY {Default} \
- CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_33_SLEW {fast} \
- CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_34_POLARITY {Default} \
- CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_34_SLEW {fast} \
- CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_35_POLARITY {Default} \
- CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_35_SLEW {fast} \
- CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_36_POLARITY {Default} \
- CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_36_SLEW {fast} \
- CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_37_POLARITY {Default} \
- CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_37_SLEW {fast} \
- CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_38_POLARITY {Default} \
- CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_38_SLEW {fast} \
- CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_39_POLARITY {Default} \
- CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_39_SLEW {fast} \
- CONFIG.PSU_MIO_3_DIRECTION {inout} \
- CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_3_POLARITY {Default} \
- CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_3_SLEW {fast} \
- CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_40_POLARITY {Default} \
- CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_40_SLEW {fast} \
- CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_41_POLARITY {Default} \
- CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_41_SLEW {fast} \
- CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_42_POLARITY {Default} \
- CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_42_SLEW {fast} \
- CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_43_POLARITY {Default} \
- CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_43_SLEW {fast} \
- CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_44_POLARITY {Default} \
- CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_44_SLEW {fast} \
- CONFIG.PSU_MIO_45_DIRECTION {in} \
- CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_45_POLARITY {Default} \
- CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_45_SLEW {fast} \
- CONFIG.PSU_MIO_46_DIRECTION {inout} \
- CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_46_POLARITY {Default} \
- CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_46_SLEW {fast} \
- CONFIG.PSU_MIO_47_DIRECTION {inout} \
- CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_47_POLARITY {Default} \
- CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_47_SLEW {fast} \
- CONFIG.PSU_MIO_48_DIRECTION {inout} \
- CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_48_POLARITY {Default} \
- CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_48_SLEW {fast} \
- CONFIG.PSU_MIO_49_DIRECTION {inout} \
- CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_49_POLARITY {Default} \
- CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_49_SLEW {fast} \
- CONFIG.PSU_MIO_4_DIRECTION {inout} \
- CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_4_POLARITY {Default} \
- CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_4_SLEW {fast} \
- CONFIG.PSU_MIO_50_DIRECTION {inout} \
- CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_50_POLARITY {Default} \
- CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_50_SLEW {fast} \
- CONFIG.PSU_MIO_51_DIRECTION {out} \
- CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_51_POLARITY {Default} \
- CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_51_SLEW {fast} \
- CONFIG.PSU_MIO_52_DIRECTION {in} \
- CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_52_POLARITY {Default} \
- CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_52_SLEW {fast} \
- CONFIG.PSU_MIO_53_DIRECTION {in} \
- CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_53_POLARITY {Default} \
- CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_53_SLEW {fast} \
- CONFIG.PSU_MIO_54_DIRECTION {inout} \
- CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_54_POLARITY {Default} \
- CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_54_SLEW {fast} \
- CONFIG.PSU_MIO_55_DIRECTION {in} \
- CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_55_POLARITY {Default} \
- CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_55_SLEW {fast} \
- CONFIG.PSU_MIO_56_DIRECTION {inout} \
- CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_56_POLARITY {Default} \
- CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_56_SLEW {fast} \
- CONFIG.PSU_MIO_57_DIRECTION {inout} \
- CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_57_POLARITY {Default} \
- CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_57_SLEW {fast} \
- CONFIG.PSU_MIO_58_DIRECTION {out} \
- CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_58_POLARITY {Default} \
- CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_58_SLEW {fast} \
- CONFIG.PSU_MIO_59_DIRECTION {inout} \
- CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_59_POLARITY {Default} \
- CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_59_SLEW {fast} \
- CONFIG.PSU_MIO_5_DIRECTION {out} \
- CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_5_POLARITY {Default} \
- CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_5_SLEW {fast} \
- CONFIG.PSU_MIO_60_DIRECTION {inout} \
- CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_60_POLARITY {Default} \
- CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_60_SLEW {fast} \
- CONFIG.PSU_MIO_61_DIRECTION {inout} \
- CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_61_POLARITY {Default} \
- CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_61_SLEW {fast} \
- CONFIG.PSU_MIO_62_DIRECTION {inout} \
- CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_62_POLARITY {Default} \
- CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_62_SLEW {fast} \
- CONFIG.PSU_MIO_63_DIRECTION {inout} \
- CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_63_POLARITY {Default} \
- CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_63_SLEW {fast} \
- CONFIG.PSU_MIO_64_DIRECTION {out} \
- CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_64_POLARITY {Default} \
- CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_64_SLEW {fast} \
- CONFIG.PSU_MIO_65_DIRECTION {out} \
- CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_65_POLARITY {Default} \
- CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_65_SLEW {fast} \
- CONFIG.PSU_MIO_66_DIRECTION {out} \
- CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_66_POLARITY {Default} \
- CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_66_SLEW {fast} \
- CONFIG.PSU_MIO_67_DIRECTION {out} \
- CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_67_POLARITY {Default} \
- CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_67_SLEW {fast} \
- CONFIG.PSU_MIO_68_DIRECTION {out} \
- CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_68_POLARITY {Default} \
- CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_68_SLEW {fast} \
- CONFIG.PSU_MIO_69_DIRECTION {out} \
- CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_69_POLARITY {Default} \
- CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_69_SLEW {fast} \
- CONFIG.PSU_MIO_6_DIRECTION {out} \
- CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_6_POLARITY {Default} \
- CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_6_SLEW {fast} \
- CONFIG.PSU_MIO_70_DIRECTION {in} \
- CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_70_POLARITY {Default} \
- CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_70_SLEW {fast} \
- CONFIG.PSU_MIO_71_DIRECTION {in} \
- CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_71_POLARITY {Default} \
- CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_71_SLEW {fast} \
- CONFIG.PSU_MIO_72_DIRECTION {in} \
- CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_72_POLARITY {Default} \
- CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_72_SLEW {fast} \
- CONFIG.PSU_MIO_73_DIRECTION {in} \
- CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_73_POLARITY {Default} \
- CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_73_SLEW {fast} \
- CONFIG.PSU_MIO_74_DIRECTION {in} \
- CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_74_POLARITY {Default} \
- CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_74_SLEW {fast} \
- CONFIG.PSU_MIO_75_DIRECTION {in} \
- CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_75_POLARITY {Default} \
- CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_75_SLEW {fast} \
- CONFIG.PSU_MIO_76_DIRECTION {out} \
- CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_76_POLARITY {Default} \
- CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_76_SLEW {fast} \
- CONFIG.PSU_MIO_77_DIRECTION {inout} \
- CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_77_POLARITY {Default} \
- CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_77_SLEW {fast} \
- CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_7_POLARITY {Default} \
- CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_7_SLEW {fast} \
- CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_8_POLARITY {Default} \
- CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_8_SLEW {fast} \
- CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_9_POLARITY {Default} \
- CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_9_SLEW {fast} \
- CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
-SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
-1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
-1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
-3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
-3}\
- CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
- CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
- CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
- CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
- CONFIG.PSU_SMC_CYCLE_T0 {NA} \
- CONFIG.PSU_SMC_CYCLE_T1 {NA} \
- CONFIG.PSU_SMC_CYCLE_T2 {NA} \
- CONFIG.PSU_SMC_CYCLE_T3 {NA} \
- CONFIG.PSU_SMC_CYCLE_T4 {NA} \
- CONFIG.PSU_SMC_CYCLE_T5 {NA} \
- CONFIG.PSU_SMC_CYCLE_T6 {NA} \
- CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
- CONFIG.PSU_VALUE_SILVERSION {3} \
- CONFIG.PSU__ACPU0__POWER__ON {1} \
- CONFIG.PSU__ACPU1__POWER__ON {1} \
- CONFIG.PSU__ACPU2__POWER__ON {0} \
- CONFIG.PSU__ACPU3__POWER__ON {0} \
- CONFIG.PSU__ACTUAL__IP {1} \
- CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
- CONFIG.PSU__AFI0_COHERENCY {0} \
- CONFIG.PSU__AFI1_COHERENCY {0} \
- CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
- CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
- CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {38} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
- CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
- CONFIG.PSU__CSU_COHERENCY {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__AL {0} \
- CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
- CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
- CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
- CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
- CONFIG.PSU__DDRC__CL {15} \
- CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
- CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
- CONFIG.PSU__DDRC__COMPONENTS {Components} \
- CONFIG.PSU__DDRC__CWL {14} \
- CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
- CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
- CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
- CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
- CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
- CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
- CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
- CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
- CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
- CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
- CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
- CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
- CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
- CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
- CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
- CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
- CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
- CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
- CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
- CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
- CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
- CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
- CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
- CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
- CONFIG.PSU__DDRC__ECC {Disabled} \
- CONFIG.PSU__DDRC__ECC_SCRUB {0} \
- CONFIG.PSU__DDRC__ENABLE {1} \
- CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
- CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
- CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
- CONFIG.PSU__DDRC__FGRM {1X} \
- CONFIG.PSU__DDRC__FREQ_MHZ {1} \
- CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
- CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LP_ASR {manual normal} \
- CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
- CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
- CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
- CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
- CONFIG.PSU__DDRC__PLL_BYPASS {0} \
- CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
- CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
- CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
- CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
- CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
- CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
- CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
- CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
- CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
- CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
- CONFIG.PSU__DDRC__T_FAW {30.0} \
- CONFIG.PSU__DDRC__T_RAS_MIN {33} \
- CONFIG.PSU__DDRC__T_RC {47.06} \
- CONFIG.PSU__DDRC__T_RCD {15} \
- CONFIG.PSU__DDRC__T_RP {15} \
- CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
- CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
- CONFIG.PSU__DDRC__VREF {1} \
- CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
- CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
- CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
- CONFIG.PSU__DEVICE_TYPE {CG} \
- CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
- CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DLL__ISUSED {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
- CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
- CONFIG.PSU__DP__REF_CLK_FREQ {27} \
- CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
- CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
- CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET0__PTP__ENABLE {0} \
- CONFIG.PSU__ENET0__TSU__ENABLE {0} \
- CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET1__PTP__ENABLE {0} \
- CONFIG.PSU__ENET1__TSU__ENABLE {0} \
- CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET2__PTP__ENABLE {0} \
- CONFIG.PSU__ENET2__TSU__ENABLE {0} \
- CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
- CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
- CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
- CONFIG.PSU__ENET3__PTP__ENABLE {0} \
- CONFIG.PSU__ENET3__TSU__ENABLE {0} \
- CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
- CONFIG.PSU__EN_EMIO_TRACE {0} \
- CONFIG.PSU__EP__IP {0} \
- CONFIG.PSU__EXPAND__CORESIGHT {0} \
- CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
- CONFIG.PSU__EXPAND__GIC {0} \
- CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
- CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
- CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
- CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__FPGA_PL0_ENABLE {1} \
- CONFIG.PSU__FPGA_PL1_ENABLE {0} \
- CONFIG.PSU__FPGA_PL2_ENABLE {0} \
- CONFIG.PSU__FPGA_PL3_ENABLE {0} \
- CONFIG.PSU__FP__POWER__ON {1} \
- CONFIG.PSU__FTM__CTI_IN_0 {0} \
- CONFIG.PSU__FTM__CTI_IN_1 {0} \
- CONFIG.PSU__FTM__CTI_IN_2 {0} \
- CONFIG.PSU__FTM__CTI_IN_3 {0} \
- CONFIG.PSU__FTM__CTI_OUT_0 {0} \
- CONFIG.PSU__FTM__CTI_OUT_1 {0} \
- CONFIG.PSU__FTM__CTI_OUT_2 {0} \
- CONFIG.PSU__FTM__CTI_OUT_3 {0} \
- CONFIG.PSU__FTM__GPI {0} \
- CONFIG.PSU__FTM__GPO {0} \
- CONFIG.PSU__GEM0_COHERENCY {0} \
- CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM1_COHERENCY {0} \
- CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM2_COHERENCY {0} \
- CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM3_COHERENCY {0} \
- CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM__TSU__ENABLE {0} \
- CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
- CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
- CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
- CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
- CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
- CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
- CONFIG.PSU__GPU_PP0__POWER__ON {0} \
- CONFIG.PSU__GPU_PP1__POWER__ON {0} \
- CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__GT__LINK_SPEED {HBR} \
- CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
- CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
- CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
- CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
- CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
- CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
- CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
- CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
- CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
- CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
- CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
- CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
- CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
- CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
- CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
- CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
- CONFIG.PSU__L2_BANK0__POWER__ON {1} \
- CONFIG.PSU__LPDMA0_COHERENCY {0} \
- CONFIG.PSU__LPDMA1_COHERENCY {0} \
- CONFIG.PSU__LPDMA2_COHERENCY {0} \
- CONFIG.PSU__LPDMA3_COHERENCY {0} \
- CONFIG.PSU__LPDMA4_COHERENCY {0} \
- CONFIG.PSU__LPDMA5_COHERENCY {0} \
- CONFIG.PSU__LPDMA6_COHERENCY {0} \
- CONFIG.PSU__LPDMA7_COHERENCY {0} \
- CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
- CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
- CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__NAND_COHERENCY {0} \
- CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
- CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
- CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
- CONFIG.PSU__NUM_FABRIC_RESETS {1} \
- CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
- CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
- CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
- CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
- CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
- CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
- CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
- CONFIG.PSU__PCIE__BAR0_64BIT {0} \
- CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR0_VAL {} \
- CONFIG.PSU__PCIE__BAR1_64BIT {0} \
- CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR1_VAL {} \
- CONFIG.PSU__PCIE__BAR2_64BIT {0} \
- CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR2_VAL {} \
- CONFIG.PSU__PCIE__BAR3_64BIT {0} \
- CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR3_VAL {} \
- CONFIG.PSU__PCIE__BAR4_64BIT {0} \
- CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR4_VAL {} \
- CONFIG.PSU__PCIE__BAR5_64BIT {0} \
- CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR5_VAL {} \
- CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
- CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
- CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
- CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
- CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
- CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
- CONFIG.PSU__PCIE__DEVICE_ID {} \
- CONFIG.PSU__PCIE__ECRC_CHECK {0} \
- CONFIG.PSU__PCIE__ECRC_ERR {0} \
- CONFIG.PSU__PCIE__ECRC_GEN {0} \
- CONFIG.PSU__PCIE__EROM_ENABLE {0} \
- CONFIG.PSU__PCIE__EROM_VAL {} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
- CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
- CONFIG.PSU__PCIE__INTX_GENERATION {0} \
- CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
- CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
- CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
- CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
- CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MULTIHEADER {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
- CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
- CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
- CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
- CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
- CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
- CONFIG.PSU__PCIE__REVISION_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
- CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
- CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
- CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
- CONFIG.PSU__PCIE__VENDOR_ID {} \
- CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PL_CLK0_BUF {TRUE} \
- CONFIG.PSU__PL_CLK1_BUF {FALSE} \
- CONFIG.PSU__PL_CLK2_BUF {FALSE} \
- CONFIG.PSU__PL_CLK3_BUF {FALSE} \
- CONFIG.PSU__PL__POWER__ON {1} \
- CONFIG.PSU__PMU_COHERENCY {0} \
- CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
- CONFIG.PSU__PMU__GPI0__ENABLE {0} \
- CONFIG.PSU__PMU__GPI1__ENABLE {0} \
- CONFIG.PSU__PMU__GPI2__ENABLE {0} \
- CONFIG.PSU__PMU__GPI3__ENABLE {0} \
- CONFIG.PSU__PMU__GPI4__ENABLE {0} \
- CONFIG.PSU__PMU__GPI5__ENABLE {0} \
- CONFIG.PSU__PMU__GPO0__ENABLE {0} \
- CONFIG.PSU__PMU__GPO1__ENABLE {0} \
- CONFIG.PSU__PMU__GPO2__ENABLE {0} \
- CONFIG.PSU__PMU__GPO3__ENABLE {0} \
- CONFIG.PSU__PMU__GPO4__ENABLE {0} \
- CONFIG.PSU__PMU__GPO5__ENABLE {0} \
- CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
- CONFIG.PSU__PRESET_APPLIED {1} \
- CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__DEBUG {0} \
- CONFIG.PSU__PROTECTION__ENABLE {0} \
- CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
-SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
-SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |\
-SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
-subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
- CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
-Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
- CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
- CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
- CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
- CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
- CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
- CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
- CONFIG.PSU__QSPI_COHERENCY {0} \
- CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
- CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
- CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
- CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
- CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
- CONFIG.PSU__REPORT__DBGLOG {0} \
- CONFIG.PSU__RPU_COHERENCY {0} \
- CONFIG.PSU__RPU__POWER__ON {1} \
- CONFIG.PSU__SATA__LANE0__ENABLE {0} \
- CONFIG.PSU__SATA__LANE1__ENABLE {1} \
- CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
- CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
- CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
- CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
- CONFIG.PSU__SD0_COHERENCY {0} \
- CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SD0__RESET__ENABLE {0} \
- CONFIG.PSU__SD1_COHERENCY {0} \
- CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
- CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
- CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
- CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
- CONFIG.PSU__SD1__RESET__ENABLE {0} \
- CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
- CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
- CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
- CONFIG.PSU__TCM0A__POWER__ON {1} \
- CONFIG.PSU__TCM0B__POWER__ON {1} \
- CONFIG.PSU__TCM1A__POWER__ON {1} \
- CONFIG.PSU__TCM1B__POWER__ON {1} \
- CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
- CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
- CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRISTATE__INVERTED {1} \
- CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
- CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
- CONFIG.PSU__UART0__BAUD_RATE {115200} \
- CONFIG.PSU__UART0__MODEM__ENABLE {0} \
- CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
- CONFIG.PSU__UART1__BAUD_RATE {115200} \
- CONFIG.PSU__UART1__MODEM__ENABLE {0} \
- CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
- CONFIG.PSU__USB0_COHERENCY {0} \
- CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
- CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
- CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
- CONFIG.PSU__USB0__RESET__ENABLE {0} \
- CONFIG.PSU__USB1_COHERENCY {0} \
- CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB1__RESET__ENABLE {0} \
- CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
- CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
- CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
- CONFIG.PSU__USE__ADMA {0} \
- CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__AUDIO {0} \
- CONFIG.PSU__USE__CLK {0} \
- CONFIG.PSU__USE__CLK0 {0} \
- CONFIG.PSU__USE__CLK1 {0} \
- CONFIG.PSU__USE__CLK2 {0} \
- CONFIG.PSU__USE__CLK3 {0} \
- CONFIG.PSU__USE__CROSS_TRIGGER {0} \
- CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
- CONFIG.PSU__USE__DEBUG__TEST {0} \
- CONFIG.PSU__USE__EVENT_RPU {0} \
- CONFIG.PSU__USE__FABRIC__RST {1} \
- CONFIG.PSU__USE__FTM {0} \
- CONFIG.PSU__USE__GDMA {0} \
- CONFIG.PSU__USE__IRQ {0} \
- CONFIG.PSU__USE__IRQ0 {1} \
- CONFIG.PSU__USE__IRQ1 {0} \
- CONFIG.PSU__USE__M_AXI_GP0 {0} \
- CONFIG.PSU__USE__M_AXI_GP1 {0} \
- CONFIG.PSU__USE__M_AXI_GP2 {1} \
- CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
- CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__RST0 {0} \
- CONFIG.PSU__USE__RST1 {0} \
- CONFIG.PSU__USE__RST2 {0} \
- CONFIG.PSU__USE__RST3 {0} \
- CONFIG.PSU__USE__RTC {0} \
- CONFIG.PSU__USE__STM {0} \
- CONFIG.PSU__USE__S_AXI_ACE {0} \
- CONFIG.PSU__USE__S_AXI_ACP {0} \
- CONFIG.PSU__USE__S_AXI_GP0 {0} \
- CONFIG.PSU__USE__S_AXI_GP1 {0} \
- CONFIG.PSU__USE__S_AXI_GP2 {0} \
- CONFIG.PSU__USE__S_AXI_GP3 {0} \
- CONFIG.PSU__USE__S_AXI_GP4 {0} \
- CONFIG.PSU__USE__S_AXI_GP5 {0} \
- CONFIG.PSU__USE__S_AXI_GP6 {0} \
- CONFIG.PSU__USE__USB3_0_HUB {0} \
- CONFIG.PSU__USE__USB3_1_HUB {0} \
- CONFIG.PSU__USE__VIDEO {0} \
- CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
- CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
- CONFIG.QSPI_BOARD_INTERFACE {custom} \
- CONFIG.SATA_BOARD_INTERFACE {custom} \
- CONFIG.SD0_BOARD_INTERFACE {custom} \
- CONFIG.SD1_BOARD_INTERFACE {custom} \
- CONFIG.SPI0_BOARD_INTERFACE {custom} \
- CONFIG.SPI1_BOARD_INTERFACE {custom} \
- CONFIG.SUBPRESET1 {Custom} \
- CONFIG.SUBPRESET2 {Custom} \
- CONFIG.SWDT0_BOARD_INTERFACE {custom} \
- CONFIG.SWDT1_BOARD_INTERFACE {custom} \
- CONFIG.TRACE_BOARD_INTERFACE {custom} \
- CONFIG.TTC0_BOARD_INTERFACE {custom} \
- CONFIG.TTC1_BOARD_INTERFACE {custom} \
- CONFIG.TTC2_BOARD_INTERFACE {custom} \
- CONFIG.TTC3_BOARD_INTERFACE {custom} \
- CONFIG.UART0_BOARD_INTERFACE {custom} \
- CONFIG.UART1_BOARD_INTERFACE {custom} \
- CONFIG.USB0_BOARD_INTERFACE {custom} \
- CONFIG.USB1_BOARD_INTERFACE {custom} \
- ] $zynq_ultra_ps_e_0
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
# Create interface connections
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
@@ -1899,50 +1775,38 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
- connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
- connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
- connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
- connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
- connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
- connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
- connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
- connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
- connect_bd_net -net xlconstant_zero_dout [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins xlconstant_zero/dout]
- connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins nanosoc_chip_0/bist_in] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins xlconstant_zerox4/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
# Create address segments
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
+ validate_bd_design
+ save_bd_design
}
# End of create_root_design()
+##################################################################
+# MAIN FLOW
+##################################################################
-
-proc available_tcl_procs { } {
- puts "##################################################################"
- puts "# Available Tcl procedures to recreate hierarchical blocks:"
- puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
- puts "# create_root_design"
- puts "#"
- puts "#"
- puts "# The following procedures will create hiearchical blocks with addressing "
- puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
- puts "# will not be handled outside those blocks:"
- puts "#"
- puts "# create_root_design"
- puts "#"
- puts "##################################################################"
-}
-
-available_tcl_procs
+#create_root_design ""
diff --git a/fpga/targets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl b/fpga/targets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1ce92fac68668e843afa76c1c4a755e0cd465278
--- /dev/null
+++ b/fpga/targets/pynq_kv260/vivado_script/2024_1/nanosoc_design.tcl
@@ -0,0 +1,1812 @@
+
+################################################################
+# This is a generated script based on design: extio8x4_io
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
+
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source extio8x4_io_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
+
+ # Create instance: xlconst_zero, and set properties
+ set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
+ # Create instance: xlconstant_zero, and set properties
+ set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
+
+ # Create instance: xlconstant_zerox4, and set properties
+ set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+#create_root_design ""
diff --git a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
index 843182e2ea223b5a56112364c92c4ba3febfd7be..5b6771df2525f2742951c304a0c719378bfee601 100644
--- a/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
@@ -20,15 +20,21 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-# set scripts_vivado_version 2021.1
-# set current_vivado_version [version -short]
-#
-# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-# puts ""
-# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-#
-# return 1
-# }
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
+
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
################################################################
# START
@@ -37,6 +43,85 @@ set script_folder [_tcl::get_script_folder]
# To test this script, run the following commands from Vivado Tcl console:
# source extio8x4_io_script.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xc7z020clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
@@ -45,16 +130,17 @@ set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
soclabs.org:user:nanosoc_chip:1.0\
-xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
-soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
"
set list_ips_missing ""
@@ -142,172 +228,473 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_0
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
# Create instance: axi_gpio_1, and set properties
set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_1
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
# Create instance: axi_stream_io_0, and set properties
set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {64} \
- ] $axis_data_fifo_0
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
- # Create instance: extio8x4_axis_target_0, and set properties
- set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
- # Create instance: p1_extio_concat_o, and set properties
- set p1_extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_o ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_o
-
- # Create instance: p1_extio_concat_z, and set properties
- set p1_extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_z ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_z
-
- # Create instance: p1_o_bit0_ioreq1, and set properties
- set p1_o_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit0_ioreq1 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {0} \
- CONFIG.DIN_TO {0} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit0_ioreq1
-
- # Create instance: p1_o_bit1_ioreq2, and set properties
- set p1_o_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1_ioreq2 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {1} \
- CONFIG.DIN_TO {1} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit1_ioreq2
-
- # Create instance: p1_o_bit3_iodatata4, and set properties
- set p1_o_bit3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3_iodatata4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {6} \
- CONFIG.DIN_TO {3} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {4} \
- ] $p1_o_bit3_iodatata4
-
- # Create instance: pmoda_i_bit4, and set properties
- set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {4} \
- CONFIG.DIN_TO {4} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit4
-
- # Create instance: pmoda_i_bit7, and set properties
- set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {7} \
- CONFIG.DIN_TO {7} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit7
-
- # Create instance: pmoda_z_concat8, and set properties
- set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
- set_property -dict [ list \
- CONFIG.NUM_PORTS {8} \
- ] $pmoda_z_concat8
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
- set_property -dict [ list \
- CONFIG.NUM_MI {3} \
- CONFIG.NUM_SI {1} \
- ] $smartconnect_0
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
- # Create instance: xlconcat_0, and set properties
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {8} \
- CONFIG.IN1_WIDTH {8} \
- ] $xlconcat_0
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
# Create instance: xlconst_zero, and set properties
set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconst_zero
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
- # Create instance: xlconst_zerox8, and set properties
- set xlconst_zerox8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox8 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {8} \
- ] $xlconst_zerox8
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
# Create instance: xlconstant_1, and set properties
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
# Create interface connections
connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
- connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
- connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
- connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
- connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconst_zero/dout]
- connect_bd_net -net const1 [get_bd_pins p1_extio_concat_z/In0] [get_bd_pins p1_extio_concat_z/In1] [get_bd_pins xlconstant_1/dout]
- connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins p1_extio_concat_z/In3]
- connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout] [get_bd_pins xlconcat_0/In0]
- connect_bd_net -net p1_extio_concat_z_dout [get_bd_pins pmoda_tri_z] [get_bd_pins p1_extio_concat_z/dout]
- connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins p1_o_bit0_ioreq1/Dout]
- connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins p1_o_bit1_ioreq2/Dout]
- connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins p1_o_bit3_iodatata4/Dout]
- connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i]
- connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
- connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
- connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
- connect_bd_net -net xlconcat_0_dout [get_bd_pins p1_tri_i] [get_bd_pins xlconcat_0/dout]
- connect_bd_net -net xlconst_zerox8_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconst_zerox8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -320,6 +707,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
proc create_root_design { parentCell } {
variable script_folder
+ variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
@@ -363,6 +751,23 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
+ # Create instance: xlconstant_zero, and set properties
+ set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
+
+ # Create instance: xlconstant_zerox4, and set properties
+ set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
+
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
@@ -434,23 +839,11 @@ proc create_root_design { parentCell } {
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
] $processing_system7_0
- # Create instance: xlconstant_zero, and set properties
- set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconstant_zero
-
- # Create instance: xlconstant_zerox4, and set properties
- set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {4} \
- ] $xlconstant_zerox4
# Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
- connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
# Create port connections
connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
@@ -458,50 +851,40 @@ proc create_root_design { parentCell } {
connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
- connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
- connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
- connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
- connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
- connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
- connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
- connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
- connect_bd_net -net xlconstant_zero_dout [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins xlconstant_zero/dout]
- connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins nanosoc_chip_0/bist_in] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins xlconstant_zerox4/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins nanosoc_chip_0/clk_i]
# Create address segments
assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
+ validate_bd_design
+ save_bd_design
}
# End of create_root_design()
+##################################################################
+# MAIN FLOW
+##################################################################
+#create_root_design ""
-proc available_tcl_procs { } {
- puts "##################################################################"
- puts "# Available Tcl procedures to recreate hierarchical blocks:"
- puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
- puts "# create_root_design"
- puts "#"
- puts "#"
- puts "# The following procedures will create hiearchical blocks with addressing "
- puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
- puts "# will not be handled outside those blocks:"
- puts "#"
- puts "# create_root_design"
- puts "#"
- puts "##################################################################"
-}
-available_tcl_procs
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
index ff003e351d9178114809a19d9d5364def0e984c0..e11d1a3b2d3163c7ce02f80b20c77e398e2c36be 100644
--- a/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+++ b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
@@ -17,18 +17,24 @@ proc get_script_folder {} {
variable script_folder
set script_folder [_tcl::get_script_folder]
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-# set scripts_vivado_version 2021.1
-# set current_vivado_version [version -short]
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
+
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
-# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-# puts ""
-# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-# return 1
-# }
+## }
+
+## return 1
+##}
################################################################
# START
@@ -37,6 +43,86 @@ set script_folder [_tcl::get_script_folder]
# To test this script, run the following commands from Vivado Tcl console:
# source extio8x4_io_script.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
@@ -50,11 +136,12 @@ xilinx.com:ip:zynq_ultra_ps_e:3.5\
xilinx.com:ip:axi_gpio:2.0\
soclabs.org:user:axi_stream_io:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
-soclabs.org:slip:extio8x4_axis_target:1.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
"
set list_ips_missing ""
@@ -142,172 +229,473 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_0
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
# Create instance: axi_gpio_1, and set properties
set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
- set_property -dict [ list \
- CONFIG.C_GPIO2_WIDTH {16} \
- CONFIG.C_GPIO_WIDTH {16} \
- CONFIG.C_IS_DUAL {1} \
- ] $axi_gpio_1
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
# Create instance: axi_stream_io_0, and set properties
set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {64} \
- ] $axis_data_fifo_0
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
- # Create instance: extio8x4_axis_target_0, and set properties
- set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
- # Create instance: p1_extio_concat_o, and set properties
- set p1_extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_o ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_o
-
- # Create instance: p1_extio_concat_z, and set properties
- set p1_extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_z ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {1} \
- CONFIG.IN1_WIDTH {1} \
- CONFIG.IN2_WIDTH {1} \
- CONFIG.IN3_WIDTH {4} \
- CONFIG.IN4_WIDTH {1} \
- CONFIG.NUM_PORTS {5} \
- ] $p1_extio_concat_z
-
- # Create instance: p1_o_bit0_ioreq1, and set properties
- set p1_o_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit0_ioreq1 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {0} \
- CONFIG.DIN_TO {0} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit0_ioreq1
-
- # Create instance: p1_o_bit1_ioreq2, and set properties
- set p1_o_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1_ioreq2 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {1} \
- CONFIG.DIN_TO {1} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {1} \
- ] $p1_o_bit1_ioreq2
-
- # Create instance: p1_o_bit3_iodatata4, and set properties
- set p1_o_bit3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3_iodatata4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {6} \
- CONFIG.DIN_TO {3} \
- CONFIG.DIN_WIDTH {16} \
- CONFIG.DOUT_WIDTH {4} \
- ] $p1_o_bit3_iodatata4
-
- # Create instance: pmoda_i_bit4, and set properties
- set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {4} \
- CONFIG.DIN_TO {4} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit4
-
- # Create instance: pmoda_i_bit7, and set properties
- set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
- set_property -dict [ list \
- CONFIG.DIN_FROM {7} \
- CONFIG.DIN_TO {7} \
- CONFIG.DIN_WIDTH {8} \
- CONFIG.DOUT_WIDTH {1} \
- ] $pmoda_i_bit7
-
- # Create instance: pmoda_z_concat8, and set properties
- set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
- set_property -dict [ list \
- CONFIG.NUM_PORTS {8} \
- ] $pmoda_z_concat8
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
- set_property -dict [ list \
- CONFIG.NUM_MI {3} \
- CONFIG.NUM_SI {1} \
- ] $smartconnect_0
-
- # Create instance: xlconcat_0, and set properties
- set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
- set_property -dict [ list \
- CONFIG.IN0_WIDTH {8} \
- CONFIG.IN1_WIDTH {8} \
- ] $xlconcat_0
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
# Create instance: xlconst_zero, and set properties
set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconst_zero
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
- # Create instance: xlconst_zerox8, and set properties
- set xlconst_zerox8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox8 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {8} \
- ] $xlconst_zerox8
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
# Create instance: xlconstant_1, and set properties
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
# Create interface connections
connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
- connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
# Create port connections
- connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
- connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
- connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconst_zero/dout]
- connect_bd_net -net const1 [get_bd_pins p1_extio_concat_z/In0] [get_bd_pins p1_extio_concat_z/In1] [get_bd_pins xlconstant_1/dout]
- connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
- connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins p1_extio_concat_z/In3]
- connect_bd_net -net p1_extio_concat_o_dout [get_bd_pins pmoda_tri_o] [get_bd_pins p1_extio_concat_o/dout] [get_bd_pins xlconcat_0/In0]
- connect_bd_net -net p1_extio_concat_z_dout [get_bd_pins pmoda_tri_z] [get_bd_pins p1_extio_concat_z/dout]
- connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins p1_o_bit0_ioreq1/Dout]
- connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins p1_o_bit1_ioreq2/Dout]
- connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins p1_o_bit3_iodatata4/Dout]
- connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i]
- connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
- connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
- connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
- connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
- connect_bd_net -net xlconcat_0_dout [get_bd_pins p1_tri_i] [get_bd_pins xlconcat_0/dout]
- connect_bd_net -net xlconst_zerox8_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconst_zerox8/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
# Restore current instance
@@ -320,6 +708,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
proc create_root_design { parentCell } {
variable script_folder
+ variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
@@ -359,1536 +748,1023 @@ proc create_root_design { parentCell } {
# Create instance: nanosoc_chip_0, and set properties
set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
# Create instance: xlconstant_zero, and set properties
set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $xlconstant_zero
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
# Create instance: xlconstant_zerox4, and set properties
set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- CONFIG.CONST_WIDTH {4} \
- ] $xlconstant_zerox4
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
- set_property -dict [ list \
- CONFIG.CAN0_BOARD_INTERFACE {custom} \
- CONFIG.CAN1_BOARD_INTERFACE {custom} \
- CONFIG.CSU_BOARD_INTERFACE {custom} \
- CONFIG.DP_BOARD_INTERFACE {custom} \
- CONFIG.GEM0_BOARD_INTERFACE {custom} \
- CONFIG.GEM1_BOARD_INTERFACE {custom} \
- CONFIG.GEM2_BOARD_INTERFACE {custom} \
- CONFIG.GEM3_BOARD_INTERFACE {custom} \
- CONFIG.GPIO_BOARD_INTERFACE {custom} \
- CONFIG.IIC0_BOARD_INTERFACE {custom} \
- CONFIG.IIC1_BOARD_INTERFACE {custom} \
- CONFIG.NAND_BOARD_INTERFACE {custom} \
- CONFIG.PCIE_BOARD_INTERFACE {custom} \
- CONFIG.PJTAG_BOARD_INTERFACE {custom} \
- CONFIG.PMU_BOARD_INTERFACE {custom} \
- CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
- CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
- CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
- CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
- CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
- CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
- CONFIG.PSU_IMPORT_BOARD_PRESET {} \
- CONFIG.PSU_MIO_0_DIRECTION {out} \
- CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_0_POLARITY {Default} \
- CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_0_SLEW {fast} \
- CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_10_POLARITY {Default} \
- CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_10_SLEW {fast} \
- CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_11_POLARITY {Default} \
- CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_11_SLEW {fast} \
- CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_12_POLARITY {Default} \
- CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_12_SLEW {fast} \
- CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_13_POLARITY {Default} \
- CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_13_SLEW {fast} \
- CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_14_POLARITY {Default} \
- CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_14_SLEW {fast} \
- CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_15_POLARITY {Default} \
- CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_15_SLEW {fast} \
- CONFIG.PSU_MIO_16_DIRECTION {inout} \
- CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_16_POLARITY {Default} \
- CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_16_SLEW {fast} \
- CONFIG.PSU_MIO_17_DIRECTION {inout} \
- CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_17_POLARITY {Default} \
- CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_17_SLEW {fast} \
- CONFIG.PSU_MIO_18_DIRECTION {in} \
- CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_18_POLARITY {Default} \
- CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_18_SLEW {fast} \
- CONFIG.PSU_MIO_19_DIRECTION {out} \
- CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_19_POLARITY {Default} \
- CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_19_SLEW {fast} \
- CONFIG.PSU_MIO_1_DIRECTION {inout} \
- CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_1_POLARITY {Default} \
- CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_1_SLEW {fast} \
- CONFIG.PSU_MIO_20_DIRECTION {out} \
- CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_20_POLARITY {Default} \
- CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_20_SLEW {fast} \
- CONFIG.PSU_MIO_21_DIRECTION {in} \
- CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_21_POLARITY {Default} \
- CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_21_SLEW {fast} \
- CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_22_POLARITY {Default} \
- CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_22_SLEW {fast} \
- CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_23_POLARITY {Default} \
- CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_23_SLEW {fast} \
- CONFIG.PSU_MIO_24_DIRECTION {out} \
- CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_24_POLARITY {Default} \
- CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_24_SLEW {fast} \
- CONFIG.PSU_MIO_25_DIRECTION {in} \
- CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_25_POLARITY {Default} \
- CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_25_SLEW {fast} \
- CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_26_POLARITY {Default} \
- CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_26_SLEW {fast} \
- CONFIG.PSU_MIO_27_DIRECTION {out} \
- CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_27_POLARITY {Default} \
- CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_27_SLEW {fast} \
- CONFIG.PSU_MIO_28_DIRECTION {in} \
- CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_28_POLARITY {Default} \
- CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_28_SLEW {fast} \
- CONFIG.PSU_MIO_29_DIRECTION {out} \
- CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_29_POLARITY {Default} \
- CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_29_SLEW {fast} \
- CONFIG.PSU_MIO_2_DIRECTION {inout} \
- CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_2_POLARITY {Default} \
- CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_2_SLEW {fast} \
- CONFIG.PSU_MIO_30_DIRECTION {in} \
- CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_30_POLARITY {Default} \
- CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_30_SLEW {fast} \
- CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_31_POLARITY {Default} \
- CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_31_SLEW {fast} \
- CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_32_POLARITY {Default} \
- CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_32_SLEW {fast} \
- CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_33_POLARITY {Default} \
- CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_33_SLEW {fast} \
- CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_34_POLARITY {Default} \
- CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_34_SLEW {fast} \
- CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_35_POLARITY {Default} \
- CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_35_SLEW {fast} \
- CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_36_POLARITY {Default} \
- CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_36_SLEW {fast} \
- CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_37_POLARITY {Default} \
- CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_37_SLEW {fast} \
- CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_38_POLARITY {Default} \
- CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_38_SLEW {fast} \
- CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_39_POLARITY {Default} \
- CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_39_SLEW {fast} \
- CONFIG.PSU_MIO_3_DIRECTION {inout} \
- CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_3_POLARITY {Default} \
- CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_3_SLEW {fast} \
- CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_40_POLARITY {Default} \
- CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_40_SLEW {fast} \
- CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_41_POLARITY {Default} \
- CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_41_SLEW {fast} \
- CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_42_POLARITY {Default} \
- CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_42_SLEW {fast} \
- CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_43_POLARITY {Default} \
- CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_43_SLEW {fast} \
- CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_44_POLARITY {Default} \
- CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_44_SLEW {fast} \
- CONFIG.PSU_MIO_45_DIRECTION {in} \
- CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_45_POLARITY {Default} \
- CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_45_SLEW {fast} \
- CONFIG.PSU_MIO_46_DIRECTION {inout} \
- CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_46_POLARITY {Default} \
- CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_46_SLEW {fast} \
- CONFIG.PSU_MIO_47_DIRECTION {inout} \
- CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_47_POLARITY {Default} \
- CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_47_SLEW {fast} \
- CONFIG.PSU_MIO_48_DIRECTION {inout} \
- CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_48_POLARITY {Default} \
- CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_48_SLEW {fast} \
- CONFIG.PSU_MIO_49_DIRECTION {inout} \
- CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_49_POLARITY {Default} \
- CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_49_SLEW {fast} \
- CONFIG.PSU_MIO_4_DIRECTION {inout} \
- CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_4_POLARITY {Default} \
- CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_4_SLEW {fast} \
- CONFIG.PSU_MIO_50_DIRECTION {inout} \
- CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_50_POLARITY {Default} \
- CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_50_SLEW {fast} \
- CONFIG.PSU_MIO_51_DIRECTION {out} \
- CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_51_POLARITY {Default} \
- CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_51_SLEW {fast} \
- CONFIG.PSU_MIO_52_DIRECTION {in} \
- CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_52_POLARITY {Default} \
- CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_52_SLEW {fast} \
- CONFIG.PSU_MIO_53_DIRECTION {in} \
- CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_53_POLARITY {Default} \
- CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_53_SLEW {fast} \
- CONFIG.PSU_MIO_54_DIRECTION {inout} \
- CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_54_POLARITY {Default} \
- CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_54_SLEW {fast} \
- CONFIG.PSU_MIO_55_DIRECTION {in} \
- CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_55_POLARITY {Default} \
- CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_55_SLEW {fast} \
- CONFIG.PSU_MIO_56_DIRECTION {inout} \
- CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_56_POLARITY {Default} \
- CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_56_SLEW {fast} \
- CONFIG.PSU_MIO_57_DIRECTION {inout} \
- CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_57_POLARITY {Default} \
- CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_57_SLEW {fast} \
- CONFIG.PSU_MIO_58_DIRECTION {out} \
- CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_58_POLARITY {Default} \
- CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_58_SLEW {fast} \
- CONFIG.PSU_MIO_59_DIRECTION {inout} \
- CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_59_POLARITY {Default} \
- CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_59_SLEW {fast} \
- CONFIG.PSU_MIO_5_DIRECTION {out} \
- CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_5_POLARITY {Default} \
- CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_5_SLEW {fast} \
- CONFIG.PSU_MIO_60_DIRECTION {inout} \
- CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_60_POLARITY {Default} \
- CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_60_SLEW {fast} \
- CONFIG.PSU_MIO_61_DIRECTION {inout} \
- CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_61_POLARITY {Default} \
- CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_61_SLEW {fast} \
- CONFIG.PSU_MIO_62_DIRECTION {inout} \
- CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_62_POLARITY {Default} \
- CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_62_SLEW {fast} \
- CONFIG.PSU_MIO_63_DIRECTION {inout} \
- CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_63_POLARITY {Default} \
- CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_63_SLEW {fast} \
- CONFIG.PSU_MIO_64_DIRECTION {out} \
- CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_64_POLARITY {Default} \
- CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_64_SLEW {fast} \
- CONFIG.PSU_MIO_65_DIRECTION {out} \
- CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_65_POLARITY {Default} \
- CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_65_SLEW {fast} \
- CONFIG.PSU_MIO_66_DIRECTION {out} \
- CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_66_POLARITY {Default} \
- CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_66_SLEW {fast} \
- CONFIG.PSU_MIO_67_DIRECTION {out} \
- CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_67_POLARITY {Default} \
- CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_67_SLEW {fast} \
- CONFIG.PSU_MIO_68_DIRECTION {out} \
- CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_68_POLARITY {Default} \
- CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_68_SLEW {fast} \
- CONFIG.PSU_MIO_69_DIRECTION {out} \
- CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_69_POLARITY {Default} \
- CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_69_SLEW {fast} \
- CONFIG.PSU_MIO_6_DIRECTION {out} \
- CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_6_POLARITY {Default} \
- CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_6_SLEW {fast} \
- CONFIG.PSU_MIO_70_DIRECTION {in} \
- CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_70_POLARITY {Default} \
- CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_70_SLEW {fast} \
- CONFIG.PSU_MIO_71_DIRECTION {in} \
- CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_71_POLARITY {Default} \
- CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_71_SLEW {fast} \
- CONFIG.PSU_MIO_72_DIRECTION {in} \
- CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_72_POLARITY {Default} \
- CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_72_SLEW {fast} \
- CONFIG.PSU_MIO_73_DIRECTION {in} \
- CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_73_POLARITY {Default} \
- CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_73_SLEW {fast} \
- CONFIG.PSU_MIO_74_DIRECTION {in} \
- CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_74_POLARITY {Default} \
- CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_74_SLEW {fast} \
- CONFIG.PSU_MIO_75_DIRECTION {in} \
- CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_75_POLARITY {Default} \
- CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_75_SLEW {fast} \
- CONFIG.PSU_MIO_76_DIRECTION {out} \
- CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_76_POLARITY {Default} \
- CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_76_SLEW {fast} \
- CONFIG.PSU_MIO_77_DIRECTION {inout} \
- CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_77_POLARITY {Default} \
- CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_77_SLEW {fast} \
- CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_7_POLARITY {Default} \
- CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_7_SLEW {fast} \
- CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_8_POLARITY {Default} \
- CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_8_SLEW {fast} \
- CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
- CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
- CONFIG.PSU_MIO_9_POLARITY {Default} \
- CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
- CONFIG.PSU_MIO_9_SLEW {fast} \
- CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
-SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
-1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
-1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
-3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
-3}\
- CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
- CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
- CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
- CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
- CONFIG.PSU_SMC_CYCLE_T0 {NA} \
- CONFIG.PSU_SMC_CYCLE_T1 {NA} \
- CONFIG.PSU_SMC_CYCLE_T2 {NA} \
- CONFIG.PSU_SMC_CYCLE_T3 {NA} \
- CONFIG.PSU_SMC_CYCLE_T4 {NA} \
- CONFIG.PSU_SMC_CYCLE_T5 {NA} \
- CONFIG.PSU_SMC_CYCLE_T6 {NA} \
- CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
- CONFIG.PSU_VALUE_SILVERSION {3} \
- CONFIG.PSU__ACPU0__POWER__ON {1} \
- CONFIG.PSU__ACPU1__POWER__ON {1} \
- CONFIG.PSU__ACPU2__POWER__ON {1} \
- CONFIG.PSU__ACPU3__POWER__ON {1} \
- CONFIG.PSU__ACTUAL__IP {1} \
- CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
- CONFIG.PSU__AFI0_COHERENCY {0} \
- CONFIG.PSU__AFI1_COHERENCY {0} \
- CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
- CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
- CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
- CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
- CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
- CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
- CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
- CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
- CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
- CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
- CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
- CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
- CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
- CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
- CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
- CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
- CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
- CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
- CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {38} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
- CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
- CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
- CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
- CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
- CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
- CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
- CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
- CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
- CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
- CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
- CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
- CONFIG.PSU__CSU_COHERENCY {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
- CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
- CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__AL {0} \
- CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
- CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
- CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
- CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
- CONFIG.PSU__DDRC__CL {15} \
- CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
- CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
- CONFIG.PSU__DDRC__COMPONENTS {Components} \
- CONFIG.PSU__DDRC__CWL {14} \
- CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
- CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
- CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
- CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
- CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
- CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
- CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
- CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
- CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
- CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
- CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
- CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
- CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
- CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
- CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
- CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
- CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
- CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
- CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
- CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
- CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
- CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
- CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
- CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
- CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
- CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
- CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
- CONFIG.PSU__DDRC__ECC {Disabled} \
- CONFIG.PSU__DDRC__ECC_SCRUB {0} \
- CONFIG.PSU__DDRC__ENABLE {1} \
- CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
- CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
- CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
- CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
- CONFIG.PSU__DDRC__FGRM {1X} \
- CONFIG.PSU__DDRC__FREQ_MHZ {1} \
- CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
- CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
- CONFIG.PSU__DDRC__LP_ASR {manual normal} \
- CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
- CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
- CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
- CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
- CONFIG.PSU__DDRC__PLL_BYPASS {0} \
- CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
- CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
- CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
- CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
- CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
- CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
- CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
- CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
- CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
- CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
- CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
- CONFIG.PSU__DDRC__T_FAW {30.0} \
- CONFIG.PSU__DDRC__T_RAS_MIN {33} \
- CONFIG.PSU__DDRC__T_RC {47.06} \
- CONFIG.PSU__DDRC__T_RCD {15} \
- CONFIG.PSU__DDRC__T_RP {15} \
- CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
- CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
- CONFIG.PSU__DDRC__VREF {1} \
- CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_ENABLE {0} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
- CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
- CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
- CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
- CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
- CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
- CONFIG.PSU__DEVICE_TYPE {EV} \
- CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
- CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
- CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DLL__ISUSED {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
- CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
- CONFIG.PSU__DP__REF_CLK_FREQ {27} \
- CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
- CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
- CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET0__PTP__ENABLE {0} \
- CONFIG.PSU__ENET0__TSU__ENABLE {0} \
- CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET1__PTP__ENABLE {0} \
- CONFIG.PSU__ENET1__TSU__ENABLE {0} \
- CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
- CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__ENET2__PTP__ENABLE {0} \
- CONFIG.PSU__ENET2__TSU__ENABLE {0} \
- CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
- CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
- CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
- CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
- CONFIG.PSU__ENET3__PTP__ENABLE {0} \
- CONFIG.PSU__ENET3__TSU__ENABLE {0} \
- CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
- CONFIG.PSU__EN_EMIO_TRACE {0} \
- CONFIG.PSU__EP__IP {0} \
- CONFIG.PSU__EXPAND__CORESIGHT {0} \
- CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
- CONFIG.PSU__EXPAND__GIC {0} \
- CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
- CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
- CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
- CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
- CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__FPGA_PL0_ENABLE {1} \
- CONFIG.PSU__FPGA_PL1_ENABLE {0} \
- CONFIG.PSU__FPGA_PL2_ENABLE {0} \
- CONFIG.PSU__FPGA_PL3_ENABLE {0} \
- CONFIG.PSU__FP__POWER__ON {1} \
- CONFIG.PSU__FTM__CTI_IN_0 {0} \
- CONFIG.PSU__FTM__CTI_IN_1 {0} \
- CONFIG.PSU__FTM__CTI_IN_2 {0} \
- CONFIG.PSU__FTM__CTI_IN_3 {0} \
- CONFIG.PSU__FTM__CTI_OUT_0 {0} \
- CONFIG.PSU__FTM__CTI_OUT_1 {0} \
- CONFIG.PSU__FTM__CTI_OUT_2 {0} \
- CONFIG.PSU__FTM__CTI_OUT_3 {0} \
- CONFIG.PSU__FTM__GPI {0} \
- CONFIG.PSU__FTM__GPO {0} \
- CONFIG.PSU__GEM0_COHERENCY {0} \
- CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM1_COHERENCY {0} \
- CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM2_COHERENCY {0} \
- CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM3_COHERENCY {0} \
- CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__GEM__TSU__ENABLE {0} \
- CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
- CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
- CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
- CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
- CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
- CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
- CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
- CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
- CONFIG.PSU__GPU_PP0__POWER__ON {1} \
- CONFIG.PSU__GPU_PP1__POWER__ON {1} \
- CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__GT__LINK_SPEED {HBR} \
- CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
- CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
- CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
- CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
- CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
- CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
- CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
- CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
- CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
- CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
- CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
- CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
- CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
- CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
- CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
- CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
- CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
- CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
- CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
- CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
- CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
- CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
- CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
- CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
- CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
- CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
- CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
- CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
- CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
- CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
- CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
- CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
- CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
- CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
- CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
- CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
- CONFIG.PSU__L2_BANK0__POWER__ON {1} \
- CONFIG.PSU__LPDMA0_COHERENCY {0} \
- CONFIG.PSU__LPDMA1_COHERENCY {0} \
- CONFIG.PSU__LPDMA2_COHERENCY {0} \
- CONFIG.PSU__LPDMA3_COHERENCY {0} \
- CONFIG.PSU__LPDMA4_COHERENCY {0} \
- CONFIG.PSU__LPDMA5_COHERENCY {0} \
- CONFIG.PSU__LPDMA6_COHERENCY {0} \
- CONFIG.PSU__LPDMA7_COHERENCY {0} \
- CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
- CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
- CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
- CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
- CONFIG.PSU__NAND_COHERENCY {0} \
- CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
- CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
- CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
- CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
- CONFIG.PSU__NUM_FABRIC_RESETS {1} \
- CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
- CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
- CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
- CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
- CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
- CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
- CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
- CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
- CONFIG.PSU__PCIE__BAR0_64BIT {0} \
- CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR0_VAL {} \
- CONFIG.PSU__PCIE__BAR1_64BIT {0} \
- CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR1_VAL {} \
- CONFIG.PSU__PCIE__BAR2_64BIT {0} \
- CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR2_VAL {} \
- CONFIG.PSU__PCIE__BAR3_64BIT {0} \
- CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR3_VAL {} \
- CONFIG.PSU__PCIE__BAR4_64BIT {0} \
- CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR4_VAL {} \
- CONFIG.PSU__PCIE__BAR5_64BIT {0} \
- CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
- CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
- CONFIG.PSU__PCIE__BAR5_VAL {} \
- CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
- CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
- CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
- CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
- CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
- CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
- CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
- CONFIG.PSU__PCIE__DEVICE_ID {} \
- CONFIG.PSU__PCIE__ECRC_CHECK {0} \
- CONFIG.PSU__PCIE__ECRC_ERR {0} \
- CONFIG.PSU__PCIE__ECRC_GEN {0} \
- CONFIG.PSU__PCIE__EROM_ENABLE {0} \
- CONFIG.PSU__PCIE__EROM_VAL {} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
- CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
- CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
- CONFIG.PSU__PCIE__INTX_GENERATION {0} \
- CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
- CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
- CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
- CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
- CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
- CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
- CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
- CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
- CONFIG.PSU__PCIE__MULTIHEADER {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
- CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
- CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
- CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
- CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
- CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
- CONFIG.PSU__PCIE__REVISION_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
- CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
- CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
- CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
- CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
- CONFIG.PSU__PCIE__VENDOR_ID {} \
- CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PL_CLK0_BUF {TRUE} \
- CONFIG.PSU__PL_CLK1_BUF {FALSE} \
- CONFIG.PSU__PL_CLK2_BUF {FALSE} \
- CONFIG.PSU__PL_CLK3_BUF {FALSE} \
- CONFIG.PSU__PL__POWER__ON {1} \
- CONFIG.PSU__PMU_COHERENCY {0} \
- CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
- CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
- CONFIG.PSU__PMU__GPI0__ENABLE {0} \
- CONFIG.PSU__PMU__GPI1__ENABLE {0} \
- CONFIG.PSU__PMU__GPI2__ENABLE {0} \
- CONFIG.PSU__PMU__GPI3__ENABLE {0} \
- CONFIG.PSU__PMU__GPI4__ENABLE {0} \
- CONFIG.PSU__PMU__GPI5__ENABLE {0} \
- CONFIG.PSU__PMU__GPO0__ENABLE {0} \
- CONFIG.PSU__PMU__GPO1__ENABLE {0} \
- CONFIG.PSU__PMU__GPO2__ENABLE {0} \
- CONFIG.PSU__PMU__GPO3__ENABLE {0} \
- CONFIG.PSU__PMU__GPO4__ENABLE {0} \
- CONFIG.PSU__PMU__GPO5__ENABLE {0} \
- CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
- CONFIG.PSU__PRESET_APPLIED {1} \
- CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__DEBUG {0} \
- CONFIG.PSU__PROTECTION__ENABLE {0} \
- CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
-Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
- CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
-WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
-UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
-SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
-Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
-WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
-UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
- CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
- CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
- CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
- CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
- CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
- CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
- CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
- CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
- CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
- CONFIG.PSU__QSPI_COHERENCY {0} \
- CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
- CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
- CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
- CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
- CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
- CONFIG.PSU__REPORT__DBGLOG {0} \
- CONFIG.PSU__RPU_COHERENCY {0} \
- CONFIG.PSU__RPU__POWER__ON {1} \
- CONFIG.PSU__SATA__LANE0__ENABLE {0} \
- CONFIG.PSU__SATA__LANE1__ENABLE {1} \
- CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
- CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
- CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
- CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
- CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
- CONFIG.PSU__SD0_COHERENCY {0} \
- CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SD0__RESET__ENABLE {0} \
- CONFIG.PSU__SD1_COHERENCY {0} \
- CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
- CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
- CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
- CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
- CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
- CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
- CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
- CONFIG.PSU__SD1__RESET__ENABLE {0} \
- CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
- CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
- CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
- CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
- CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
- CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
- CONFIG.PSU__TCM0A__POWER__ON {1} \
- CONFIG.PSU__TCM0B__POWER__ON {1} \
- CONFIG.PSU__TCM1A__POWER__ON {1} \
- CONFIG.PSU__TCM1B__POWER__ON {1} \
- CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
- CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
- CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__TRISTATE__INVERTED {1} \
- CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
- CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
- CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
- CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
- CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
- CONFIG.PSU__UART0__BAUD_RATE {115200} \
- CONFIG.PSU__UART0__MODEM__ENABLE {0} \
- CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
- CONFIG.PSU__UART1__BAUD_RATE {115200} \
- CONFIG.PSU__UART1__MODEM__ENABLE {0} \
- CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
- CONFIG.PSU__USB0_COHERENCY {0} \
- CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
- CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
- CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
- CONFIG.PSU__USB0__RESET__ENABLE {0} \
- CONFIG.PSU__USB1_COHERENCY {0} \
- CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB1__RESET__ENABLE {0} \
- CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
- CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
- CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
- CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
- CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
- CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
- CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
- CONFIG.PSU__USE__ADMA {0} \
- CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__AUDIO {0} \
- CONFIG.PSU__USE__CLK {0} \
- CONFIG.PSU__USE__CLK0 {0} \
- CONFIG.PSU__USE__CLK1 {0} \
- CONFIG.PSU__USE__CLK2 {0} \
- CONFIG.PSU__USE__CLK3 {0} \
- CONFIG.PSU__USE__CROSS_TRIGGER {0} \
- CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
- CONFIG.PSU__USE__DEBUG__TEST {0} \
- CONFIG.PSU__USE__EVENT_RPU {0} \
- CONFIG.PSU__USE__FABRIC__RST {1} \
- CONFIG.PSU__USE__FTM {0} \
- CONFIG.PSU__USE__GDMA {0} \
- CONFIG.PSU__USE__IRQ {0} \
- CONFIG.PSU__USE__IRQ0 {1} \
- CONFIG.PSU__USE__IRQ1 {0} \
- CONFIG.PSU__USE__M_AXI_GP0 {0} \
- CONFIG.PSU__USE__M_AXI_GP1 {0} \
- CONFIG.PSU__USE__M_AXI_GP2 {1} \
- CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
- CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
- CONFIG.PSU__USE__RST0 {0} \
- CONFIG.PSU__USE__RST1 {0} \
- CONFIG.PSU__USE__RST2 {0} \
- CONFIG.PSU__USE__RST3 {0} \
- CONFIG.PSU__USE__RTC {0} \
- CONFIG.PSU__USE__STM {0} \
- CONFIG.PSU__USE__S_AXI_ACE {0} \
- CONFIG.PSU__USE__S_AXI_ACP {0} \
- CONFIG.PSU__USE__S_AXI_GP0 {0} \
- CONFIG.PSU__USE__S_AXI_GP1 {0} \
- CONFIG.PSU__USE__S_AXI_GP2 {0} \
- CONFIG.PSU__USE__S_AXI_GP3 {0} \
- CONFIG.PSU__USE__S_AXI_GP4 {0} \
- CONFIG.PSU__USE__S_AXI_GP5 {0} \
- CONFIG.PSU__USE__S_AXI_GP6 {0} \
- CONFIG.PSU__USE__USB3_0_HUB {0} \
- CONFIG.PSU__USE__USB3_1_HUB {0} \
- CONFIG.PSU__USE__VIDEO {0} \
- CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
- CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
- CONFIG.QSPI_BOARD_INTERFACE {custom} \
- CONFIG.SATA_BOARD_INTERFACE {custom} \
- CONFIG.SD0_BOARD_INTERFACE {custom} \
- CONFIG.SD1_BOARD_INTERFACE {custom} \
- CONFIG.SPI0_BOARD_INTERFACE {custom} \
- CONFIG.SPI1_BOARD_INTERFACE {custom} \
- CONFIG.SUBPRESET1 {Custom} \
- CONFIG.SUBPRESET2 {Custom} \
- CONFIG.SWDT0_BOARD_INTERFACE {custom} \
- CONFIG.SWDT1_BOARD_INTERFACE {custom} \
- CONFIG.TRACE_BOARD_INTERFACE {custom} \
- CONFIG.TTC0_BOARD_INTERFACE {custom} \
- CONFIG.TTC1_BOARD_INTERFACE {custom} \
- CONFIG.TTC2_BOARD_INTERFACE {custom} \
- CONFIG.TTC3_BOARD_INTERFACE {custom} \
- CONFIG.UART0_BOARD_INTERFACE {custom} \
- CONFIG.UART1_BOARD_INTERFACE {custom} \
- CONFIG.USB0_BOARD_INTERFACE {custom} \
- CONFIG.USB1_BOARD_INTERFACE {custom} \
- ] $zynq_ultra_ps_e_0
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
# Create interface connections
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
@@ -1899,50 +1775,40 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
- connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
- connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
- connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
- connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
- connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
- connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
- connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
- connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
- connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
- connect_bd_net -net xlconstant_zero_dout [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins xlconstant_zero/dout]
- connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins nanosoc_chip_0/bist_in] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins xlconstant_zerox4/dout]
- connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
# Create address segments
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
+ validate_bd_design
+ save_bd_design
}
# End of create_root_design()
+##################################################################
+# MAIN FLOW
+##################################################################
+#create_root_design ""
-proc available_tcl_procs { } {
- puts "##################################################################"
- puts "# Available Tcl procedures to recreate hierarchical blocks:"
- puts "#"
- puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
- puts "# create_root_design"
- puts "#"
- puts "#"
- puts "# The following procedures will create hiearchical blocks with addressing "
- puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
- puts "# will not be handled outside those blocks:"
- puts "#"
- puts "# create_root_design"
- puts "#"
- puts "##################################################################"
-}
-available_tcl_procs
diff --git a/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e11d1a3b2d3163c7ce02f80b20c77e398e2c36be
--- /dev/null
+++ b/fpga/targets/pynq_zcu104/vivado_script/2024_1/nanosoc_design.tcl
@@ -0,0 +1,1814 @@
+
+################################################################
+# This is a generated script based on design: extio8x4_io
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+##################################################################
+### Check if script is running in correct Vivado version.
+##################################################################
+##set scripts_vivado_version 2024.1
+##set current_vivado_version [version -short]
+
+##if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+## puts ""
+## if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+## } else {
+## catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+## }
+
+## return 1
+##}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source extio8x4_io_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xczu7ev-ffvc1156-2-e
+ set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name extio8x4_io
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+# create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+ # USE CASES:
+ # 1) Design_name not set
+
+ set errMsg "Please set the variable <design_name> to a non-empty value."
+ set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+ # USE CASES:
+ # 2): Current design opened AND is empty AND names same.
+ # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
+ # 4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+ if { $cur_design ne $design_name } {
+ common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+ set design_name [get_property NAME $cur_design]
+ }
+ common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+ # USE CASES:
+ # 5) Current design opened AND has components AND same names.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+ # USE CASES:
+ # 6) Current opened design, has components, but diff names, design_name exists in project.
+ # 7) No opened design, design_name exists in project.
+
+ set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+ set nRet 2
+
+} else {
+ # USE CASES:
+ # 8) No opened design, design_name not in project.
+ # 9) Current opened design, has components, but diff names, design_name not in project.
+
+ common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+ current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+ return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:zynq_ultra_ps_e:3.5\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+soclabs.org:slip:extio8x4_axis_target:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_0
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_0
+
+ # Create instance: extio_concat_z, and set properties
+ set extio_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_z
+
+ # Create instance: extio_i_bit1_ioreq2, and set properties
+ set extio_i_bit1_ioreq2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit1_ioreq2 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit1_ioreq2
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit1_ioreq2
+
+ # Create instance: extio_i_bit6to3_iodatata4, and set properties
+ set extio_i_bit6to3_iodatata4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit6to3_iodatata4 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {4} \
+ ] $extio_i_bit6to3_iodatata4
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit6to3_iodatata4
+
+ # Create instance: extio_i_bit0_ioreq1, and set properties
+ set extio_i_bit0_ioreq1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 extio_i_bit0_ioreq1 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {0} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $extio_i_bit0_ioreq1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_i_bit0_ioreq1
+
+ # Create instance: extio_concat_o, and set properties
+ set extio_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 extio_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {4} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.NUM_PORTS {5} \
+ ] $extio_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_concat_o
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $proc_sys_reset_0
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [list \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $smartconnect_0
+
+ # Create instance: soc_p1_i_concat16, and set properties
+ set soc_p1_i_concat16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 soc_p1_i_concat16 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $soc_p1_i_concat16
+
+
+ # Create instance: xlconst_zerox9, and set properties
+ set xlconst_zerox9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zerox9 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {8} \
+ ] $xlconst_zerox9
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zerox9
+
+ # Create instance: xlconst_zero, and set properties
+ set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconst_zero
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconst_zero
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_1
+
+ # Create instance: extio8x4_axis_target_0, and set properties
+ set extio8x4_axis_target_0 [ create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0 ]
+
+ # Create instance: p1_z6to0, and set properties
+ set p1_z6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_z6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_z6to0
+
+ # Create instance: p1_o6to0, and set properties
+ set p1_o6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $p1_o6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o6to0
+
+ # Create instance: pmoda_i_bit7_notrpimode, and set properties
+ set pmoda_i_bit7_notrpimode [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7_notrpimode ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7_notrpimode
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_i_bit7_notrpimode
+
+ # Create instance: rpi_extio_o, and set properties
+ set rpi_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_o
+
+ # Create instance: zynq_extio_o, and set properties
+ set zynq_extio_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_o
+
+ # Create instance: pmoda_mux_o, and set properties
+ set pmoda_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_o
+
+ # Create instance: rpi_enable8, and set properties
+ set rpi_enable8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rpi_enable8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $rpi_enable8
+
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_enable8
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ set_property SELECTED_SIM_MODEL rtl $axi_stream_io_1
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property CONFIG.FIFO_DEPTH {64} $axis_data_fifo_1
+
+
+ set_property SELECTED_SIM_MODEL rtl $axis_data_fifo_1
+
+ # Create instance: pmoda_concat_z, and set properties
+ set pmoda_concat_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_z ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_z
+
+ # Create instance: pmoda_concat_o, and set properties
+ set pmoda_concat_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_concat_o ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $pmoda_concat_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_concat_o
+
+ # Create instance: zynq_extio_z, and set properties
+ set zynq_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_z
+
+ # Create instance: rpi_extio_z, and set properties
+ set rpi_extio_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_extio_z ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_extio_z
+
+ # Create instance: pmoda_mux_z, and set properties
+ set pmoda_mux_z [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 pmoda_mux_z ]
+ set_property CONFIG.C_OPERATION {or} $pmoda_mux_z
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_mux_z
+
+ # Create instance: zynq_extio_i_maskx8, and set properties
+ set zynq_extio_i_maskx8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_extio_i_maskx8 ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_extio_i_maskx8
+
+ # Create instance: p1_o15to8, and set properties
+ set p1_o15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o15to8 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {8} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $p1_o15to8
+
+
+ set_property SELECTED_SIM_MODEL rtl $p1_o15to8
+
+ # Create instance: soc_p1_mux_o, and set properties
+ set soc_p1_mux_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 soc_p1_mux_o ]
+ set_property CONFIG.C_OPERATION {or} $soc_p1_mux_o
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_mux_o
+
+ # Create instance: rpi_p0_o, and set properties
+ set rpi_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rpi_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $rpi_p0_o
+
+ # Create instance: zynq_p0_o, and set properties
+ set zynq_p0_o [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 zynq_p0_o ]
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_p0_o
+
+ # Create instance: pmoda_6to0, and set properties
+ set pmoda_6to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_6to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {6} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {7} \
+ ] $pmoda_6to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $pmoda_6to0
+
+ # Create instance: pmod_I_8, and set properties
+ set pmod_I_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmod_I_8 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {7} \
+ CONFIG.IN1_WIDTH {1} \
+ ] $pmod_I_8
+
+
+ # Create instance: soc_p1_0_7to0, and set properties
+ set soc_p1_0_7to0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 soc_p1_0_7to0 ]
+ set_property -dict [list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {0} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {8} \
+ ] $soc_p1_0_7to0
+
+
+ set_property SELECTED_SIM_MODEL rtl $soc_p1_0_7to0
+
+ # Create instance: gpio1_concat_i, and set properties
+ set gpio1_concat_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 gpio1_concat_i ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {8} \
+ CONFIG.IN1_WIDTH {8} \
+ ] $gpio1_concat_i
+
+
+ set_property SELECTED_SIM_MODEL rtl $gpio1_concat_i
+
+ # Create instance: util_vector_logic_0, and set properties
+ set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {not} \
+ CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_0
+
+
+ # Create instance: not_rpi_enable9, and set properties
+ set not_rpi_enable9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 not_rpi_enable9 ]
+ set_property -dict [list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {1} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.NUM_PORTS {8} \
+ ] $not_rpi_enable9
+
+
+ set_property SELECTED_SIM_MODEL rtl $not_rpi_enable9
+
+ # Create instance: extio_ip_sel, and set properties
+ set extio_ip_sel [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_ip_sel ]
+ set_property CONFIG.C_SIZE {4} $extio_ip_sel
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_ip_sel
+
+ # Create instance: extio_op_sel1, and set properties
+ set extio_op_sel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_op_sel1 ]
+ set_property CONFIG.C_SIZE {4} $extio_op_sel1
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_op_sel1
+
+ # Create instance: extio_io_mux, and set properties
+ set extio_io_mux [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 extio_io_mux ]
+ set_property -dict [list \
+ CONFIG.C_OPERATION {or} \
+ CONFIG.C_SIZE {4} \
+ ] $extio_io_mux
+
+
+ set_property SELECTED_SIM_MODEL rtl $extio_io_mux
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins extio8x4_axis_target_0/axis_rx0]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins extio8x4_axis_target_0/axis_rx1] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axi_stream_io_1/rx]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx0]
+ connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1 [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins extio8x4_axis_target_0/axis_tx1]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net P1_op6to0_Dout [get_bd_pins p1_o6to0/Dout] [get_bd_pins pmoda_concat_o/In0]
+ connect_bd_net -net P1_ts6to0_Dout [get_bd_pins p1_z6to0/Dout] [get_bd_pins pmoda_concat_z/In0]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins p0_tri_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net const0 [get_bd_pins xlconst_zero/dout] [get_bd_pins swdio_tri_i] [get_bd_pins swdclk_i] [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins extio_concat_z/In2] [get_bd_pins pmoda_concat_o/In1] [get_bd_pins extio_concat_o/In4] [get_bd_pins pmod_I_8/In1]
+ connect_bd_net -net const1 [get_bd_pins xlconstant_1/dout] [get_bd_pins pmoda_concat_z/In1] [get_bd_pins extio_concat_z/In0] [get_bd_pins extio_concat_z/In1] [get_bd_pins extio_concat_z/In4]
+ connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins extio_concat_o/In2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_e [get_bd_pins extio8x4_axis_target_0/iodata4_e] [get_bd_pins extio_op_sel1/Op1]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins extio_op_sel1/Op2]
+ connect_bd_net -net extio8x4_axis_target_0_iodata4_t [get_bd_pins extio8x4_axis_target_0/iodata4_t] [get_bd_pins extio_concat_z/In3] [get_bd_pins extio_ip_sel/Op1]
+ connect_bd_net -net extio_concat_z_dout [get_bd_pins extio_concat_z/dout] [get_bd_pins zynq_extio_z/Op1]
+ connect_bd_net -net extio_io_mux_Res [get_bd_pins extio_io_mux/Res] [get_bd_pins extio_concat_o/In3]
+ connect_bd_net -net extio_ip_sel_Res [get_bd_pins extio_ip_sel/Res] [get_bd_pins extio_io_mux/Op2]
+ connect_bd_net -net extio_op_sel1_Res [get_bd_pins extio_op_sel1/Res] [get_bd_pins extio_io_mux/Op1]
+ connect_bd_net -net gpio1_concat_i_dout [get_bd_pins gpio1_concat_i/dout] [get_bd_pins axi_gpio_1/gpio_io_i]
+ connect_bd_net -net not_rpimode [get_bd_pins pmoda_i_bit7_notrpimode/Dout] [get_bd_pins not_rpi_enable9/In0] [get_bd_pins not_rpi_enable9/In1] [get_bd_pins not_rpi_enable9/In2] [get_bd_pins not_rpi_enable9/In3] [get_bd_pins not_rpi_enable9/In4] [get_bd_pins not_rpi_enable9/In5] [get_bd_pins not_rpi_enable9/In6] [get_bd_pins not_rpi_enable9/In7] [get_bd_pins util_vector_logic_0/Op1]
+ connect_bd_net -net not_rpimodex8 [get_bd_pins not_rpi_enable9/dout] [get_bd_pins zynq_extio_o/Op1] [get_bd_pins zynq_extio_i_maskx8/Op1] [get_bd_pins rpi_extio_z/Op2] [get_bd_pins zynq_p0_o/Op1]
+ connect_bd_net -net p1_o_bit0_ioreq1_Dout [get_bd_pins extio_i_bit0_ioreq1/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq1_a] [get_bd_pins extio_concat_o/In0]
+ connect_bd_net -net p1_o_bit1_ioreq2_Dout [get_bd_pins extio_i_bit1_ioreq2/Dout] [get_bd_pins extio8x4_axis_target_0/ioreq2_a] [get_bd_pins extio_concat_o/In1]
+ connect_bd_net -net p1_o_bit3_iodatata4_Dout [get_bd_pins extio_i_bit6to3_iodatata4/Dout] [get_bd_pins extio8x4_axis_target_0/iodata4_i] [get_bd_pins extio_ip_sel/Op2]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins p1_tri_o] [get_bd_pins p1_o6to0/Din] [get_bd_pins soc_p1_0_7to0/Din] [get_bd_pins p1_o15to8/Din]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z6to0/Din]
+ connect_bd_net -net pmod_i_6to0 [get_bd_pins pmoda_6to0/Dout] [get_bd_pins pmod_I_8/In0]
+ connect_bd_net -net pmod_i_8 [get_bd_pins pmod_I_8/dout] [get_bd_pins rpi_p0_o/Op2]
+ connect_bd_net -net pmod_tri_o [get_bd_pins pmoda_mux_o/Res] [get_bd_pins pmoda_tri_o]
+ connect_bd_net -net pmod_tri_z [get_bd_pins pmoda_mux_z/Res] [get_bd_pins pmoda_tri_z]
+ connect_bd_net -net pmoda_concat_o_dout [get_bd_pins pmoda_concat_o/dout] [get_bd_pins rpi_extio_o/Op2]
+ connect_bd_net -net pmoda_concat_z_dout [get_bd_pins pmoda_concat_z/dout] [get_bd_pins rpi_extio_z/Op1]
+ connect_bd_net -net pmoda_i_bit7_rpimode1_Dout [get_bd_pins p1_o15to8/Dout] [get_bd_pins gpio1_concat_i/In1]
+ connect_bd_net -net pmoda_tri_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_6to0/Din] [get_bd_pins pmoda_i_bit7_notrpimode/Din]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins extio8x4_axis_target_0/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins nrst]
+ connect_bd_net -net rpi_extio_o_Res [get_bd_pins rpi_extio_o/Res] [get_bd_pins pmoda_mux_o/Op1]
+ connect_bd_net -net rpi_extio_z_sel [get_bd_pins rpi_extio_z/Res] [get_bd_pins pmoda_mux_z/Op2]
+ connect_bd_net -net rpi_p0_o_Res [get_bd_pins rpi_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op1]
+ connect_bd_net -net rpimode [get_bd_pins util_vector_logic_0/Res] [get_bd_pins rpi_enable8/In0] [get_bd_pins rpi_enable8/In1] [get_bd_pins rpi_enable8/In2] [get_bd_pins rpi_enable8/In3] [get_bd_pins rpi_enable8/In4] [get_bd_pins rpi_enable8/In5] [get_bd_pins rpi_enable8/In6] [get_bd_pins rpi_enable8/In7]
+ connect_bd_net -net rpimodex8 [get_bd_pins rpi_enable8/dout] [get_bd_pins rpi_p0_o/Op1] [get_bd_pins rpi_extio_o/Op1] [get_bd_pins zynq_extio_z/Op2]
+ connect_bd_net -net soc_p1_0_7to0_Dout [get_bd_pins soc_p1_0_7to0/Dout] [get_bd_pins zynq_extio_i_maskx8/Op2]
+ connect_bd_net -net soc_p1_mux_o [get_bd_pins soc_p1_mux_o/Res] [get_bd_pins soc_p1_i_concat16/In0]
+ connect_bd_net -net soc_p1_tri_i16 [get_bd_pins soc_p1_i_concat16/dout] [get_bd_pins p1_tri_i]
+ connect_bd_net -net xlconst_zerox9 [get_bd_pins xlconst_zerox9/dout] [get_bd_pins soc_p1_i_concat16/In1]
+ connect_bd_net -net zynq_extio_o [get_bd_pins extio_concat_o/dout] [get_bd_pins zynq_extio_o/Op2] [get_bd_pins zynq_p0_o/Op2]
+ connect_bd_net -net zynq_extio_o_Res [get_bd_pins zynq_extio_o/Res] [get_bd_pins pmoda_mux_o/Op2]
+ connect_bd_net -net zynq_extio_z_sel [get_bd_pins zynq_extio_z/Res] [get_bd_pins pmoda_mux_z/Op1]
+ connect_bd_net -net zynq_p0_o [get_bd_pins zynq_p0_o/Res] [get_bd_pins soc_p1_mux_o/Op2]
+ connect_bd_net -net zynq_pmoda_i_maskx8 [get_bd_pins zynq_extio_i_maskx8/Res] [get_bd_pins extio_i_bit1_ioreq2/Din] [get_bd_pins extio_i_bit6to3_iodatata4/Din] [get_bd_pins extio_i_bit0_ioreq1/Din] [get_bd_pins gpio1_concat_i/In0]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins extio8x4_axis_target_0/clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ set_property SELECTED_SIM_MODEL rtl $nanosoc_chip_0
+
+ # Create instance: xlconstant_zero, and set properties
+ set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
+ set_property CONFIG.CONST_VAL {0} $xlconstant_zero
+
+
+ # Create instance: xlconstant_zerox4, and set properties
+ set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
+ set_property -dict [list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
+
+ set_property SELECTED_SIM_MODEL rtl $xlconstant_zerox4
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ]
+ set_property -dict [list \
+ CONFIG.CAN0_BOARD_INTERFACE {custom} \
+ CONFIG.CAN1_BOARD_INTERFACE {custom} \
+ CONFIG.CSU_BOARD_INTERFACE {custom} \
+ CONFIG.DP_BOARD_INTERFACE {custom} \
+ CONFIG.GEM0_BOARD_INTERFACE {custom} \
+ CONFIG.GEM1_BOARD_INTERFACE {custom} \
+ CONFIG.GEM2_BOARD_INTERFACE {custom} \
+ CONFIG.GEM3_BOARD_INTERFACE {custom} \
+ CONFIG.GPIO_BOARD_INTERFACE {custom} \
+ CONFIG.IIC0_BOARD_INTERFACE {custom} \
+ CONFIG.IIC1_BOARD_INTERFACE {custom} \
+ CONFIG.NAND_BOARD_INTERFACE {custom} \
+ CONFIG.PCIE_BOARD_INTERFACE {custom} \
+ CONFIG.PJTAG_BOARD_INTERFACE {custom} \
+ CONFIG.PMU_BOARD_INTERFACE {custom} \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_IMPORT_BOARD_PRESET {} \
+ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_0_SLEW {fast} \
+ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_10_SLEW {fast} \
+ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_11_SLEW {fast} \
+ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_12_SLEW {fast} \
+ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_13_SLEW {fast} \
+ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_14_SLEW {fast} \
+ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_15_SLEW {fast} \
+ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_16_SLEW {fast} \
+ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_17_SLEW {fast} \
+ CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_19_SLEW {fast} \
+ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_1_SLEW {fast} \
+ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_20_SLEW {fast} \
+ CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_22_SLEW {fast} \
+ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_23_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_24_SLEW {fast} \
+ CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_26_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_27_SLEW {fast} \
+ CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_29_SLEW {fast} \
+ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_2_SLEW {fast} \
+ CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_31_SLEW {fast} \
+ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_32_SLEW {fast} \
+ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_33_SLEW {fast} \
+ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_34_SLEW {fast} \
+ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_35_SLEW {fast} \
+ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_36_SLEW {fast} \
+ CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_37_SLEW {fast} \
+ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_38_SLEW {fast} \
+ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_39_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_3_SLEW {fast} \
+ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_40_SLEW {fast} \
+ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_41_SLEW {fast} \
+ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_42_SLEW {fast} \
+ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_43_SLEW {fast} \
+ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_44_SLEW {fast} \
+ CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_46_SLEW {fast} \
+ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_47_SLEW {fast} \
+ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_48_SLEW {fast} \
+ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_49_SLEW {fast} \
+ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_4_SLEW {fast} \
+ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_50_SLEW {fast} \
+ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_51_SLEW {fast} \
+ CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_54_SLEW {fast} \
+ CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_56_SLEW {fast} \
+ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_57_SLEW {fast} \
+ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_58_SLEW {fast} \
+ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_59_SLEW {fast} \
+ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_5_SLEW {fast} \
+ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_60_SLEW {fast} \
+ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_61_SLEW {fast} \
+ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_62_SLEW {fast} \
+ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_63_SLEW {fast} \
+ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_64_SLEW {fast} \
+ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_65_SLEW {fast} \
+ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_66_SLEW {fast} \
+ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_67_SLEW {fast} \
+ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_68_SLEW {fast} \
+ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_69_SLEW {fast} \
+ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_6_SLEW {fast} \
+ CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_76_SLEW {fast} \
+ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_77_SLEW {fast} \
+ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_7_SLEW {fast} \
+ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_8_SLEW {fast} \
+ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
+ CONFIG.PSU_MIO_9_SLEW {fast} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN 1#CAN\
+1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
+3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+\
+ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
+ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_SMC_CYCLE_T0 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T1 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T2 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T3 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T4 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T5 {NA} \
+ CONFIG.PSU_SMC_CYCLE_T6 {NA} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU_VALUE_SILVERSION {3} \
+ CONFIG.PSU__ACPU0__POWER__ON {1} \
+ CONFIG.PSU__ACPU1__POWER__ON {1} \
+ CONFIG.PSU__ACPU2__POWER__ON {0} \
+ CONFIG.PSU__ACPU3__POWER__ON {0} \
+ CONFIG.PSU__ACTUAL__IP {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
+ CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
+ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
+ CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
+ CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
+ CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.473682} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
+ CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
+ CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__DDRC__AL {0} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ECC_SCRUB {0} \
+ CONFIG.PSU__DDRC__ENABLE {1} \
+ CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+ CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
+ CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__FREQ_MHZ {1} \
+ CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__PLL_BYPASS {0} \
+ CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+ CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_ENABLE {0} \
+ CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
+ CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
+ CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DEVICE_TYPE {EV} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
+ CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
+ CONFIG.PSU__EN_EMIO_TRACE {0} \
+ CONFIG.PSU__EP__IP {0} \
+ CONFIG.PSU__EXPAND__CORESIGHT {0} \
+ CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
+ CONFIG.PSU__EXPAND__GIC {0} \
+ CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
+ CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+ CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+ CONFIG.PSU__FP__POWER__ON {1} \
+ CONFIG.PSU__FTM__CTI_IN_0 {0} \
+ CONFIG.PSU__FTM__CTI_IN_1 {0} \
+ CONFIG.PSU__FTM__CTI_IN_2 {0} \
+ CONFIG.PSU__FTM__CTI_IN_3 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_0 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_1 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_2 {0} \
+ CONFIG.PSU__FTM__CTI_OUT_3 {0} \
+ CONFIG.PSU__FTM__GPI {0} \
+ CONFIG.PSU__FTM__GPO {0} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
+ CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
+ CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
+ CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
+ CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
+ CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
+ CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
+ CONFIG.PSU__GPU_PP0__POWER__ON {0} \
+ CONFIG.PSU__GPU_PP1__POWER__ON {0} \
+ CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
+ CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
+ CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
+ CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
+ CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
+ CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
+ CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
+ CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
+ CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
+ CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
+ CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
+ CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
+ CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
+ CONFIG.PSU__L2_BANK0__POWER__ON {1} \
+ CONFIG.PSU__LPDMA0_COHERENCY {0} \
+ CONFIG.PSU__LPDMA1_COHERENCY {0} \
+ CONFIG.PSU__LPDMA2_COHERENCY {0} \
+ CONFIG.PSU__LPDMA3_COHERENCY {0} \
+ CONFIG.PSU__LPDMA4_COHERENCY {0} \
+ CONFIG.PSU__LPDMA5_COHERENCY {0} \
+ CONFIG.PSU__LPDMA6_COHERENCY {0} \
+ CONFIG.PSU__LPDMA7_COHERENCY {0} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
+ CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
+ CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
+ CONFIG.PSU__NUM_FABRIC_RESETS {1} \
+ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
+ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
+ CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
+ CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
+ CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
+ CONFIG.PSU__PCIE__DEVICE_ID {} \
+ CONFIG.PSU__PCIE__INTX_GENERATION {0} \
+ CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
+ CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
+ CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__PCIE__REVISION_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
+ CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
+ CONFIG.PSU__PCIE__VENDOR_ID {} \
+ CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PL__POWER__ON {1} \
+ CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__ENABLE {0} \
+ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
+Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
+SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
+; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+\
+ CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
+\
+ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
+ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+\
+ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__REPORT__DBGLOG {0} \
+ CONFIG.PSU__RPU_COHERENCY {0} \
+ CONFIG.PSU__RPU__POWER__ON {1} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
+ CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \
+ CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \
+ CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SD0__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
+ CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
+ CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TCM0A__POWER__ON {1} \
+ CONFIG.PSU__TCM0B__POWER__ON {1} \
+ CONFIG.PSU__TCM1A__POWER__ON {1} \
+ CONFIG.PSU__TCM1B__POWER__ON {1} \
+ CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
+ CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__TRISTATE__INVERTED {1} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__ADMA {0} \
+ CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__AUDIO {0} \
+ CONFIG.PSU__USE__CLK {0} \
+ CONFIG.PSU__USE__CLK0 {0} \
+ CONFIG.PSU__USE__CLK1 {0} \
+ CONFIG.PSU__USE__CLK2 {0} \
+ CONFIG.PSU__USE__CLK3 {0} \
+ CONFIG.PSU__USE__CROSS_TRIGGER {0} \
+ CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
+ CONFIG.PSU__USE__DEBUG__TEST {0} \
+ CONFIG.PSU__USE__EVENT_RPU {0} \
+ CONFIG.PSU__USE__FABRIC__RST {1} \
+ CONFIG.PSU__USE__FTM {0} \
+ CONFIG.PSU__USE__GDMA {0} \
+ CONFIG.PSU__USE__IRQ {0} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__IRQ1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
+ CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
+ CONFIG.PSU__USE__RST0 {0} \
+ CONFIG.PSU__USE__RST1 {0} \
+ CONFIG.PSU__USE__RST2 {0} \
+ CONFIG.PSU__USE__RST3 {0} \
+ CONFIG.PSU__USE__RTC {0} \
+ CONFIG.PSU__USE__STM {0} \
+ CONFIG.PSU__USE__S_AXI_ACE {0} \
+ CONFIG.PSU__USE__S_AXI_ACP {0} \
+ CONFIG.PSU__USE__S_AXI_GP0 {0} \
+ CONFIG.PSU__USE__S_AXI_GP1 {0} \
+ CONFIG.PSU__USE__S_AXI_GP2 {0} \
+ CONFIG.PSU__USE__S_AXI_GP3 {0} \
+ CONFIG.PSU__USE__S_AXI_GP4 {0} \
+ CONFIG.PSU__USE__S_AXI_GP5 {0} \
+ CONFIG.PSU__USE__S_AXI_GP6 {0} \
+ CONFIG.PSU__USE__USB3_0_HUB {0} \
+ CONFIG.PSU__USE__USB3_1_HUB {0} \
+ CONFIG.PSU__USE__VIDEO {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
+ CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
+ CONFIG.QSPI_BOARD_INTERFACE {custom} \
+ CONFIG.SATA_BOARD_INTERFACE {custom} \
+ CONFIG.SD0_BOARD_INTERFACE {custom} \
+ CONFIG.SD1_BOARD_INTERFACE {custom} \
+ CONFIG.SPI0_BOARD_INTERFACE {custom} \
+ CONFIG.SPI1_BOARD_INTERFACE {custom} \
+ CONFIG.SUBPRESET1 {Custom} \
+ CONFIG.SUBPRESET2 {Custom} \
+ CONFIG.SWDT0_BOARD_INTERFACE {custom} \
+ CONFIG.SWDT1_BOARD_INTERFACE {custom} \
+ CONFIG.TRACE_BOARD_INTERFACE {custom} \
+ CONFIG.TTC0_BOARD_INTERFACE {custom} \
+ CONFIG.TTC1_BOARD_INTERFACE {custom} \
+ CONFIG.TTC2_BOARD_INTERFACE {custom} \
+ CONFIG.TTC3_BOARD_INTERFACE {custom} \
+ CONFIG.UART0_BOARD_INTERFACE {custom} \
+ CONFIG.UART1_BOARD_INTERFACE {custom} \
+ CONFIG.USB0_BOARD_INTERFACE {custom} \
+ CONFIG.USB1_BOARD_INTERFACE {custom} \
+ ] $zynq_ultra_ps_e_0
+
+
+ set_property SELECTED_SIM_MODEL rtl $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins cmsdk_socket/ext_reset_in]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins nanosoc_chip_0/p0_o] [get_bd_pins cmsdk_socket/p0_tri_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins nanosoc_chip_0/p0_z] [get_bd_pins cmsdk_socket/p0_tri_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins nanosoc_chip_0/p1_o] [get_bd_pins cmsdk_socket/p1_tri_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins nanosoc_chip_0/p1_z] [get_bd_pins cmsdk_socket/p1_tri_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins cmsdk_socket/pmoda_tri_z] [get_bd_ports pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins nanosoc_chip_0/swdio_o] [get_bd_pins cmsdk_socket/swdio_tri_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins nanosoc_chip_0/swdio_z] [get_bd_pins cmsdk_socket/swdio_tri_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins cmsdk_socket/pmoda_tri_o] [get_bd_ports pmoda_tri_o]
+ connect_bd_net -net xlconstant_zero_dout [get_bd_pins xlconstant_zero/dout] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i]
+ connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins xlconstant_zerox4/dout] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins nanosoc_chip_0/bist_in]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+#create_root_design ""
+
+
diff --git a/nanosoc/socdebug_tech b/nanosoc/socdebug_tech
index 05574880d32139de3b4f3a8b5ff3b45f551751e5..049294a8aa4385e4b2e2a03210b315a574e2a787 160000
--- a/nanosoc/socdebug_tech
+++ b/nanosoc/socdebug_tech
@@ -1 +1 @@
-Subproject commit 05574880d32139de3b4f3a8b5ff3b45f551751e5
+Subproject commit 049294a8aa4385e4b2e2a03210b315a574e2a787
diff --git a/testcodes/dhry/makefile b/testcodes/dhry/makefile
index 1ae3ef6ee10ce0cca260b5a5e1b70518cfeee0bf..38500778f0a5042338041a2d1e51809cc75b790d 100644
--- a/testcodes/dhry/makefile
+++ b/testcodes/dhry/makefile
@@ -205,6 +205,7 @@ $(TESTNAME).ELF : dhry_1.o dhry_2.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.
armlink $(ARM_LINK_OPTIONS) -o $@ dhry_1.o dhry_2.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --bin $< --output $(TESTNAME).bin
fromelf --vhx --8x1 $< --output $@
diff --git a/testcodes/hello/makefile b/testcodes/hello/makefile
index e3f943a2d3647564624f9caf2a732d8b6a3a07f5..8a3b1379947ab8e8f5fb4d5be12d6ba39b322b0d 100644
--- a/testcodes/hello/makefile
+++ b/testcodes/hello/makefile
@@ -202,6 +202,7 @@ $(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o ua
armlink $(ARM_LINK_OPTIONS) $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o -o $@
$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --bin $< --output $(TESTNAME).bin
fromelf --vhx --8x1 $< --output $@
$(TESTNAME).lst : $(TESTNAME).ELF