diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8051159d9a5f00157c952e5020603bb341968a78..afbaa2f2f982bed4dd400e64e29ebd4e5ca92ca3 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -49,8 +49,8 @@ simulate-nanosoc:
build-job-Z2: # This job runs in the build stage, which runs first.
stage: build
script:
- # move to fpga_imp directory and run the fpga build script for pynq z2
- - cd .nanosoc_tech/fpga_imp/
+ # move to fpga directory and run the fpga build script for pynq z2
+ - cd .nanosoc_tech/fpga/
- source ../set_env.sh
- if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
@@ -63,16 +63,16 @@ build-job-Z2: # This job runs in the build stage, which runs first.
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
- - ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- - ./nanosoc_tech/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
+ - ./nanosoc_tech/fpga/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
+ - ./nanosoc_tech/fpga/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
tags:
- Vivado2021.1
build-job-ZCU104: # This job runs in the build stage, which runs first.
stage: build
script:
- # move to fpga_imp directory and run the fpga build script for pynq z2
- - cd ./nanosoc_tech/fpga_imp/
+ # move to fpga directory and run the fpga build script for pynq z2
+ - cd ./nanosoc_tech/fpga/
- source ../../set_env.sh
- if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
@@ -85,8 +85,8 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
- - ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- - ./nanosoc_tech/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
+ - ./nanosoc_tech/fpga/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
+ - ./nanosoc_tech/fpga/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
tags:
- Vivado2021.1
@@ -97,7 +97,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
# - echo "Deploying application to Z2"
# # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
# # could probably set this up as scp with RSA keys in future
-# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
# - then
# - echo "Connection to Z2 Board Failed"
@@ -106,7 +106,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
# - echo "Connection to Z2 Board successful"
# - fi
# - rm errorlog
-# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
+# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
# - then
# - echo "Connection to Z2 Board Failed"
@@ -115,7 +115,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
# - echo "Connection to Z2 Board successful"
# - fi
# - rm errorlog
-# - cd ./nanosoc/fpga_imp/CI_verification
+# - cd ./nanosoc/fpga/ci_tools
# - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' -E 2>errorlog
# - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
# - then
@@ -174,11 +174,11 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
- screen -r zynq -X stuff "./ZCU104_connect.sh\n"
- sleep 10
# use scp to copy over bit files and python script
- - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/CI_verification/load_bitfile.py ./ \n"
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga/ci_tools/load_bitfile.py ./ \n"
- sleep 2
- - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
- sleep 2
- - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
+ - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
- sleep 2
# Need root access to load the overlay onto the FPGA
- screen -r zynq -X stuff "sudo su\n"
@@ -196,7 +196,7 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
- screen -r zynq -X stuff "deactivate \n"
- screen -r zynq -X stuff "exit \n"
# test the screenlog for "Overlay Loaded"
- - cp ./nanosoc/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
+ - cp ./nanosoc/fpga/ci_tools/test_bitfile_ZCU104.sh ./
- chmod +x test_bitfile_ZCU104.sh
- ./test_bitfile_ZCU104.sh
diff --git a/fpga_imp/build_fpga.tcl b/fpga/build_fpga.tcl
similarity index 100%
rename from fpga_imp/build_fpga.tcl
rename to fpga/build_fpga.tcl
diff --git a/fpga_imp/build_nanosoc.tcl b/fpga/build_nanosoc.tcl
similarity index 100%
rename from fpga_imp/build_nanosoc.tcl
rename to fpga/build_nanosoc.tcl
diff --git a/fpga_imp/CI_verification/.gitkeep b/fpga/ci_tools/.gitkeep
similarity index 100%
rename from fpga_imp/CI_verification/.gitkeep
rename to fpga/ci_tools/.gitkeep
diff --git a/fpga_imp/CI_verification/load_bitfile.py b/fpga/ci_tools/load_bitfile.py
similarity index 100%
rename from fpga_imp/CI_verification/load_bitfile.py
rename to fpga/ci_tools/load_bitfile.py
diff --git a/fpga_imp/CI_verification/load_file_output b/fpga/ci_tools/load_file_output
similarity index 100%
rename from fpga_imp/CI_verification/load_file_output
rename to fpga/ci_tools/load_file_output
diff --git a/fpga_imp/CI_verification/run_ADP_verification.py b/fpga/ci_tools/run_ADP_verification.py
similarity index 100%
rename from fpga_imp/CI_verification/run_ADP_verification.py
rename to fpga/ci_tools/run_ADP_verification.py
diff --git a/fpga_imp/CI_verification/run_AES_verification.py b/fpga/ci_tools/run_AES_verification.py
similarity index 100%
rename from fpga_imp/CI_verification/run_AES_verification.py
rename to fpga/ci_tools/run_AES_verification.py
diff --git a/fpga_imp/CI_verification/test_bitfile_ZCU104.sh b/fpga/ci_tools/test_bitfile_ZCU104.sh
similarity index 100%
rename from fpga_imp/CI_verification/test_bitfile_ZCU104.sh
rename to fpga/ci_tools/test_bitfile_ZCU104.sh
diff --git a/fpga_imp/makefile b/fpga/makefile
similarity index 91%
rename from fpga_imp/makefile
rename to fpga/makefile
index 3afcaac1f36671376e07133fc4515ce0adb8050b..9c2fa1ba5c8694df00c94c08acc6dedc61518953 100644
--- a/fpga_imp/makefile
+++ b/fpga/makefile
@@ -56,7 +56,7 @@ VIVIADO_VERSION ?= 2021_1
TEMP_RTL_NANOSOC_DIR := $(IMP_DIR)/nanosoc_lib
RTL_SOCKET_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/socket/xilinx_lib
-NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga_imp
+NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
RUN_DIR := $(IMP_DIR)/run
PROJECT_DIR := $(IMP_DIR)/targets/$(BOARD_NAME)
@@ -68,7 +68,8 @@ TARGET_TCL_DIR ?= $(NANOSOC_FPGA_FLOW_DIR)/targets/$(BOARD_NAME)/vivado_script/$
ifeq ($(PLATFORM), bare)
OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)
else ifeq ($(PLATFORM), pynq)
- OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)/pynq/overlays/soclabs
+ OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)/overlays
+# OUTPUT_DIR ?= $(FPGA_IMP_DIR)/output/$(BOARD_NAME)/pynq/overlays/soclabs
endif
# FPGA_Flow
@@ -94,14 +95,18 @@ tcl_flist:
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(TEMP_RTL_NANOSOC_DIR);)
-build_fpga: tcl_flist clean_run
+build_fpga: tcl_flist clean_fpga
@echo Starting Vivado Run
@mkdir -p $(RUN_DIR)
@cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_fpga.tcl
@echo Vivado Build Complete
-clean_run:
+clean_fpga:
@echo Cleaning Previous Runs of $(BOARD_NAME)
@rm -rf $(PROJECT_DIR)
@rm -rf $(TEMP_RTL_NANOSOC_DIR)
- @rm -rf $(RUN_DIR)
\ No newline at end of file
+ @rm -rf $(RUN_DIR)
+
+clean_fpga_all:
+ @echo Cleaning FPGA Implementation Directory
+ @rm -rf $(IMP_DIR)
\ No newline at end of file
diff --git a/fpga_imp/targets/arm_mps3/fpga_pinmap.xdc b/fpga/targets/arm_mps3/fpga_pinmap.xdc
similarity index 100%
rename from fpga_imp/targets/arm_mps3/fpga_pinmap.xdc
rename to fpga/targets/arm_mps3/fpga_pinmap.xdc
diff --git a/fpga_imp/targets/arm_mps3/fpga_timing.xdc b/fpga/targets/arm_mps3/fpga_timing.xdc
similarity index 100%
rename from fpga_imp/targets/arm_mps3/fpga_timing.xdc
rename to fpga/targets/arm_mps3/fpga_timing.xdc
diff --git a/fpga_imp/targets/arm_mps3/nanosoc_design_wrapper.v b/fpga/targets/arm_mps3/nanosoc_design_wrapper.v
similarity index 100%
rename from fpga_imp/targets/arm_mps3/nanosoc_design_wrapper.v
rename to fpga/targets/arm_mps3/nanosoc_design_wrapper.v
diff --git a/fpga_imp/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
similarity index 100%
rename from fpga_imp/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
rename to fpga/targets/arm_mps3/vivado_script/2021_1/nanosoc_design.tcl
diff --git a/fpga_imp/targets/pynq_z2/fpga_pinmap.xdc b/fpga/targets/pynq_z2/fpga_pinmap.xdc
similarity index 100%
rename from fpga_imp/targets/pynq_z2/fpga_pinmap.xdc
rename to fpga/targets/pynq_z2/fpga_pinmap.xdc
diff --git a/fpga_imp/targets/pynq_z2/fpga_timing.xdc b/fpga/targets/pynq_z2/fpga_timing.xdc
similarity index 100%
rename from fpga_imp/targets/pynq_z2/fpga_timing.xdc
rename to fpga/targets/pynq_z2/fpga_timing.xdc
diff --git a/fpga_imp/targets/pynq_z2/nanosoc_design_wrapper.v b/fpga/targets/pynq_z2/nanosoc_design_wrapper.v
similarity index 100%
rename from fpga_imp/targets/pynq_z2/nanosoc_design_wrapper.v
rename to fpga/targets/pynq_z2/nanosoc_design_wrapper.v
diff --git a/fpga_imp/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
similarity index 100%
rename from fpga_imp/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
rename to fpga/targets/pynq_z2/vivado_script/2021_1/nanosoc_design.tcl
diff --git a/fpga_imp/targets/pynq_zcu104/fpga_pinmap.xdc b/fpga/targets/pynq_zcu104/fpga_pinmap.xdc
similarity index 100%
rename from fpga_imp/targets/pynq_zcu104/fpga_pinmap.xdc
rename to fpga/targets/pynq_zcu104/fpga_pinmap.xdc
diff --git a/fpga_imp/targets/pynq_zcu104/fpga_timing.xdc b/fpga/targets/pynq_zcu104/fpga_timing.xdc
similarity index 100%
rename from fpga_imp/targets/pynq_zcu104/fpga_timing.xdc
rename to fpga/targets/pynq_zcu104/fpga_timing.xdc
diff --git a/fpga_imp/targets/pynq_zcu104/nanosoc_design_wrapper.v b/fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v
similarity index 100%
rename from fpga_imp/targets/pynq_zcu104/nanosoc_design_wrapper.v
rename to fpga/targets/pynq_zcu104/nanosoc_design_wrapper.v
diff --git a/fpga_imp/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl b/fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
similarity index 100%
rename from fpga_imp/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
rename to fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl