From 84bfc87915fd5d5bf6129c99678dfe50edbf6aa7 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Sat, 28 Sep 2024 16:39:10 +0100
Subject: [PATCH] clean up test bench axis tracker HDL
---
verif/trace/verilog/soclabs_axis8_capture.v | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/verif/trace/verilog/soclabs_axis8_capture.v b/verif/trace/verilog/soclabs_axis8_capture.v
index 860e601..b98a00b 100644
--- a/verif/trace/verilog/soclabs_axis8_capture.v
+++ b/verif/trace/verilog/soclabs_axis8_capture.v
@@ -86,7 +86,7 @@ module soclabs_axis8_capture
reg [40*8-1:0] log_file; // File name can't be > *40* characters
-assign RXD_READY = rx_shift_reg[0]; // ready except for a cycle processing
+assign RXD8_READY = rx_shift_reg[0]; // ready except for a cycle processing
`define SimSTDOUT 32'h00000001
initial
@@ -128,7 +128,7 @@ assign RXD_READY = rx_shift_reg[0]; // ready except for a cycle processing
else if (rx_shift_reg[0]== 1'b0) // if LSB zero, preset a clock cycle later
rx_shift_reg <= {9{1'b1}};
else if (rx_shift_reg[0] & RXD8_VALID) //ready and valid data capture
- rx_shift_reg[9:0] <= {RXD8_DATA[7:0], 1'b0};
+ rx_shift_reg[8:0] <= {RXD8_DATA[7:0], 1'b0};
end
--
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