From 841f26fb5fe580ee8b1a51226cd42a2211eba228 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Mon, 15 Jan 2024 22:29:18 +0000
Subject: [PATCH] fix reset-bypass on APB reset
---
nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v | 9 ++++++---
nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v | 2 +-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
index 3c55d72..14a5431 100644
--- a/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
+++ b/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
@@ -115,9 +115,9 @@ module nanosoc_chip #(
assign SYS_SCANENABLE = scan_enable;
assign SYS_TESTMODE = scan_mode;
assign SYS_SCANINHCLK = 1'b1;
- assign scan_out = scan_in;
+/// assign scan_out = scan_in;
assign bist_out = bist_in;
- assign uart_txd_o = uart_rxd_i;
+/// assign uart_txd_o = uart_rxd_i;
`else
assign SYS_SCANENABLE = test_i & swdio_i;
assign SYS_TESTMODE = test_i;
@@ -171,7 +171,10 @@ module nanosoc_chip #(
assign p1_e[3] = 1'b1;
assign p1_z[3] = 1'b0;
- assign P1_IN_MUX[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
+ assign P1_IN_MUX[4] = (alt_mode) ? uart_txd_i : p1_i[4]; // RXD2
+ assign uart_txd_o = P1_OUT_MUX[5]; // TXD2
+
+ assign P1_IN_MUX[15:5] = p1_i[15:5]; // IO MUX controlled bidirectionals
assign p1_o[15:4] = P1_OUT_MUX[15:4];
assign p1_e[15:4] = P1_OUT_EN_MUX[15:4];
assign p1_z[15:4] = ~P1_OUT_EN_MUX[15:4];
diff --git a/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v b/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
index 98d9478..7a1d68d 100644
--- a/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
+++ b/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
@@ -96,7 +96,7 @@ module nanosoc_clkctrl #(
reset_sync_reg <= nxt_reset_sync;
end
- assign reset_n = reset_sync_reg[2];
+ assign reset_n = (RSTBYPASS) ? NRST : reset_sync_reg[2];
`ifdef CORTEX_M0DESIGNSTART
// AHB HRESETn
--
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