From 7fe0885755429c11fec99a0028d688a0e8b197c8 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Mon, 3 Jul 2023 17:28:08 +0100
Subject: [PATCH] Updated scripts for FPGA synthesis

---
 fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl   | 22 +++++-----
 .../scripts/build_mcu_fpga_pynq_zcu104.tcl    | 22 +++++-----
 fpga_imp/scripts/top_flist.tcl                | 44 +++++++++++++++++++
 3 files changed, 66 insertions(+), 22 deletions(-)
 create mode 100644 fpga_imp/scripts/top_flist.tcl

diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
index 469eb25..d4796d5 100644
--- a/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -63,17 +63,17 @@ read_verilog $importDir/design_1_wrapper.v
 source $importDir/design_1.tcl
 create_root_design ""
 
-set arm_ip_lib    $::env(ARM_IP_LIBRARY_PATH)/latest
-add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 
-add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 
-add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
-set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property is_global_include true [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
-
-set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
+#set arm_ip_lib    $::env(ARM_IP_LIBRARY_PATH)/latest
+#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 
+#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 
+#add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
+#set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+#set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+#set_property is_global_include true [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
+#
+#set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+#set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+#set_property file_type {Verilog Header} [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
 
 
 add_files $importDir/fpga_pinmap.xdc
diff --git a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
index 36e63b6..b421555 100644
--- a/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
+++ b/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -62,17 +62,17 @@ read_verilog $importDir/design_1_wrapper.v
 source $importDir/design_1.tcl
 create_root_design ""
 
-set arm_ip_lib    $::env(ARM_IP_LIBRARY_PATH)/latest
-add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 
-add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 
-add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
-set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property is_global_include true [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
-
-set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
+#set arm_ip_lib    $::env(ARM_IP_LIBRARY_PATH)/latest
+#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 
+#add_files -norecurse $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 
+#add_files -norecurse ../system/sldma230_tech/src/defines/pl230_defs.v
+#set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+#set_property is_global_include true [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+#set_property is_global_include true [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
+#
+#set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+#set_property file_type {Verilog Header} [get_files  $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+#set_property file_type {Verilog Header} [get_files  ../system/sldma230_tech/src/defines/pl230_defs.v]
 
 
 add_files $importDir/fpga_pinmap.xdc
diff --git a/fpga_imp/scripts/top_flist.tcl b/fpga_imp/scripts/top_flist.tcl
new file mode 100644
index 0000000..31cbcec
--- /dev/null
+++ b/fpga_imp/scripts/top_flist.tcl
@@ -0,0 +1,44 @@
+#-----------------------------------------------------------------------------
+# AUTOGENERATED: Compiled Filelist
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+#-----------------------------------------------------------------------------
+# Abstract : Verilog Command File with expanded system variables
+#-----------------------------------------------------------------------------
+
+set search_path $env(ACCELERATOR_DIR)/src/rtl
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v $env(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v $env(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v $env(SOCLABS_FPGA_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv $env(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_NANOSOC_TECH_DIR)/verif/control/verilog/nanosoc_clkreset.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_uart_capture.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_track_tb_iostream.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_ft1248x1_track.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_dma_log_to_file.v $env(SOCLABS_NANOSOC_TECH_DIR)/verif/trace/verilog/nanosoc_accelerator_ss_logger.v "
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog ]
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog ]
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog ]
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_NANOSOC_TECH_DIR)/verif/tb/verilog/nanosoc_tb.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_system/verilog/nanosoc_system.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/systable/verilog/nanosoc_region_systable.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v $env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v "
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog ]
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog ]
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ ]
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_flash_rom16.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_flash_rom32.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256x16.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256x8.v $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v "
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog ]
+set search_path [ concat $search_path $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog ]
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_alu.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_ctl.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_dec.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_gpr.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_mul.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_pfu.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_psr.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_spu.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_bpu.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_ctl.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_dwt.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_if.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_sel.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix_sel.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_main.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_reg.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_tarmac.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_clk.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_dbg.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_sys.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_cdc.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_mast.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_cdc.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_jtag.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_pwr.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_sw.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_rst_ctl.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_acg.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_capt_sync.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_addr.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_data.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_addr.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_data.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_reset.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_jt_cdc_comb_and.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dap_sw_cdc_capt_reset.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_acg.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_reset.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_set.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_reset.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_set.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers/CORTEXM0IMP.v $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers/CORTEXM0INTEGRATIONIMP.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0.v $env(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_prmu.v $env(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_stclkctrl.v $env(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_rstctrl.v $env(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_integration.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_adp_control.v $env(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_ahb.v $env(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_ft1248_control.v $env(SOCLABS_SOCDEBUG_TECH_DIR)/controller/verilog/socdebug_usrt_control.v "
+set search_path [ concat $search_path $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines/ ]
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v $env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v $env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_dma_data.v $env(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_udma.v "
+set search_path [ concat $search_path $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines ]
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_SLDMA230_TECH_DIR)/src/verilog/sldma230.v "
+add_files -norecurse -force -copy_to vivado/built_mcu_fpga/MCULIB "$env(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v "
+set_property include_dirs " $env(ACCELERATOR_DIR)/src/rtl $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/ $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog $env(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines/ $env(SOCLABS_SLDMA230_TECH_DIR)/src/defines" [current_fileset]
\ No newline at end of file
-- 
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