diff --git a/.gitignore b/.gitignore
index 1f0d18efffb892b16c38aa0c50656611a3a6f73b..2bdc47f06f7d1b06b2dc8d15cd382f43394c5cc7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,8 +8,12 @@
/software/*/*.o
# Compile Test Code Removal
-/systems/mcu/testcodes/*/*.elf
-/systems/mcu/testcodes/*/*.ELF
-/systems/mcu/testcodes/*/*.hex
-/systems/mcu/testcodes/*/*.lst
-/systems/mcu/testcodes/*/*.o
+/systems/nanosoc/testcodes/*/*.elf
+/systems/nanosoc/testcodes/*/*.ELF
+/systems/nanosoc/testcodes/*/*.hex
+/systems/nanosoc/testcodes/*/*.lst
+/systems/nanosoc/testcodes/*/*.o
+
+# Bootrom removal
+/systems/nanosoc/src/bootrom/verilog/*
+/systems/nanosoc/src/bootrom/bintxt/*
diff --git a/systems/mcu/src/bootrom/bootrom.v b/systems/mcu/src/bootrom/bootrom.v
deleted file mode 100644
index 95919b78af3dcc0a33c06a1b0aadedbd84e976dd..0000000000000000000000000000000000000000
--- a/systems/mcu/src/bootrom/bootrom.v
+++ /dev/null
@@ -1,277 +0,0 @@
-//------------------------------------------------------------------------------------
-// customised auto-generated synthesizable ROM module abstraction
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-// Date: 2302101100
-// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
-//------------------------------------------------------------------------------------
-module bootrom (
- input wire CLK,
- input wire EN,
- input wire [9:2] ADDR,
- output reg [31:0] RDATA );
-reg [9:2] addr_r;
-always @(posedge CLK) if (EN) addr_r <= ADDR;
-always @(addr_r) case(addr_r[9:2])
- 8'h00 : RDATA <= 32'h30000368; // 0x0000
- 8'h01 : RDATA <= 32'h10000335; // 0x0004
- 8'h02 : RDATA <= 32'h1000033d; // 0x0008
- 8'h03 : RDATA <= 32'h1000033f; // 0x000c
- 8'h04 : RDATA <= 32'h00000000; // 0x0010
- 8'h05 : RDATA <= 32'h00000000; // 0x0014
- 8'h06 : RDATA <= 32'h00000000; // 0x0018
- 8'h07 : RDATA <= 32'h00000000; // 0x001c
- 8'h08 : RDATA <= 32'h00000000; // 0x0020
- 8'h09 : RDATA <= 32'h00000000; // 0x0024
- 8'h0a : RDATA <= 32'h00000000; // 0x0028
- 8'h0b : RDATA <= 32'h10000341; // 0x002c
- 8'h0c : RDATA <= 32'h00000000; // 0x0030
- 8'h0d : RDATA <= 32'h00000000; // 0x0034
- 8'h0e : RDATA <= 32'h10000343; // 0x0038
- 8'h0f : RDATA <= 32'h10000345; // 0x003c
- 8'h10 : RDATA <= 32'h10000347; // 0x0040
- 8'h11 : RDATA <= 32'h10000347; // 0x0044
- 8'h12 : RDATA <= 32'h10000347; // 0x0048
- 8'h13 : RDATA <= 32'h10000347; // 0x004c
- 8'h14 : RDATA <= 32'h10000347; // 0x0050
- 8'h15 : RDATA <= 32'h10000347; // 0x0054
- 8'h16 : RDATA <= 32'h10000347; // 0x0058
- 8'h17 : RDATA <= 32'h10000347; // 0x005c
- 8'h18 : RDATA <= 32'h10000347; // 0x0060
- 8'h19 : RDATA <= 32'h10000347; // 0x0064
- 8'h1a : RDATA <= 32'h10000347; // 0x0068
- 8'h1b : RDATA <= 32'h00000000; // 0x006c
- 8'h1c : RDATA <= 32'h10000347; // 0x0070
- 8'h1d : RDATA <= 32'h10000347; // 0x0074
- 8'h1e : RDATA <= 32'h10000347; // 0x0078
- 8'h1f : RDATA <= 32'h10000347; // 0x007c
- 8'h20 : RDATA <= 32'h10000347; // 0x0080
- 8'h21 : RDATA <= 32'h10000347; // 0x0084
- 8'h22 : RDATA <= 32'h10000347; // 0x0088
- 8'h23 : RDATA <= 32'h10000347; // 0x008c
- 8'h24 : RDATA <= 32'h10000347; // 0x0090
- 8'h25 : RDATA <= 32'h10000347; // 0x0094
- 8'h26 : RDATA <= 32'h10000347; // 0x0098
- 8'h27 : RDATA <= 32'h10000347; // 0x009c
- 8'h28 : RDATA <= 32'h10000347; // 0x00a0
- 8'h29 : RDATA <= 32'h10000347; // 0x00a4
- 8'h2a : RDATA <= 32'h10000347; // 0x00a8
- 8'h2b : RDATA <= 32'h10000347; // 0x00ac
- 8'h2c : RDATA <= 32'h10000347; // 0x00b0
- 8'h2d : RDATA <= 32'h10000347; // 0x00b4
- 8'h2e : RDATA <= 32'h10000347; // 0x00b8
- 8'h2f : RDATA <= 32'h10000347; // 0x00bc
- 8'h30 : RDATA <= 32'hf802f000; // 0x00c0
- 8'h31 : RDATA <= 32'hf83ef000; // 0x00c4
- 8'h32 : RDATA <= 32'hc830a00c; // 0x00c8
- 8'h33 : RDATA <= 32'h18243808; // 0x00cc
- 8'h34 : RDATA <= 32'h46a2182d; // 0x00d0
- 8'h35 : RDATA <= 32'h46ab1e67; // 0x00d4
- 8'h36 : RDATA <= 32'h465d4654; // 0x00d8
- 8'h37 : RDATA <= 32'hd10142ac; // 0x00dc
- 8'h38 : RDATA <= 32'hf830f000; // 0x00e0
- 8'h39 : RDATA <= 32'h3e0f467e; // 0x00e4
- 8'h3a : RDATA <= 32'h46b6cc0f; // 0x00e8
- 8'h3b : RDATA <= 32'h42332601; // 0x00ec
- 8'h3c : RDATA <= 32'h1afbd000; // 0x00f0
- 8'h3d : RDATA <= 32'h46ab46a2; // 0x00f4
- 8'h3e : RDATA <= 32'h47184333; // 0x00f8
- 8'h3f : RDATA <= 32'h000002dc; // 0x00fc
- 8'h40 : RDATA <= 32'h000002fc; // 0x0100
- 8'h41 : RDATA <= 32'hd3023a10; // 0x0104
- 8'h42 : RDATA <= 32'hc178c878; // 0x0108
- 8'h43 : RDATA <= 32'h0752d8fa; // 0x010c
- 8'h44 : RDATA <= 32'hc830d301; // 0x0110
- 8'h45 : RDATA <= 32'hd501c130; // 0x0114
- 8'h46 : RDATA <= 32'h600c6804; // 0x0118
- 8'h47 : RDATA <= 32'h00004770; // 0x011c
- 8'h48 : RDATA <= 32'h24002300; // 0x0120
- 8'h49 : RDATA <= 32'h26002500; // 0x0124
- 8'h4a : RDATA <= 32'hd3013a10; // 0x0128
- 8'h4b : RDATA <= 32'hd8fbc178; // 0x012c
- 8'h4c : RDATA <= 32'hd3000752; // 0x0130
- 8'h4d : RDATA <= 32'hd500c130; // 0x0134
- 8'h4e : RDATA <= 32'h4770600b; // 0x0138
- 8'h4f : RDATA <= 32'hbd1fb51f; // 0x013c
- 8'h50 : RDATA <= 32'hbd10b510; // 0x0140
- 8'h51 : RDATA <= 32'hf915f000; // 0x0144
- 8'h52 : RDATA <= 32'hf7ff4611; // 0x0148
- 8'h53 : RDATA <= 32'hf000fff7; // 0x014c
- 8'h54 : RDATA <= 32'hf000f868; // 0x0150
- 8'h55 : RDATA <= 32'hb403f92d; // 0x0154
- 8'h56 : RDATA <= 32'hfff2f7ff; // 0x0158
- 8'h57 : RDATA <= 32'hf000bc03; // 0x015c
- 8'h58 : RDATA <= 32'h0000f933; // 0x0160
- 8'h59 : RDATA <= 32'h68012000; // 0x0164
- 8'h5a : RDATA <= 32'h6841468d; // 0x0168
- 8'h5b : RDATA <= 32'h00004708; // 0x016c
- 8'h5c : RDATA <= 32'h48532141; // 0x0170
- 8'h5d : RDATA <= 32'h61010149; // 0x0174
- 8'h5e : RDATA <= 32'h60812101; // 0x0178
- 8'h5f : RDATA <= 32'h60814851; // 0x017c
- 8'h60 : RDATA <= 32'h20204951; // 0x0180
- 8'h61 : RDATA <= 32'h47706188; // 0x0184
- 8'h62 : RDATA <= 32'h684a494e; // 0x0188
- 8'h63 : RDATA <= 32'hd1fc07d2; // 0x018c
- 8'h64 : RDATA <= 32'h07d2684a; // 0x0190
- 8'h65 : RDATA <= 32'h6008d100; // 0x0194
- 8'h66 : RDATA <= 32'h494a4770; // 0x0198
- 8'h67 : RDATA <= 32'h2b007803; // 0x019c
- 8'h68 : RDATA <= 32'h684ad009; // 0x01a0
- 8'h69 : RDATA <= 32'hd1fc07d2; // 0x01a4
- 8'h6a : RDATA <= 32'h07d2684a; // 0x01a8
- 8'h6b : RDATA <= 32'h600bd100; // 0x01ac
- 8'h6c : RDATA <= 32'h2b001c40; // 0x01b0
- 8'h6d : RDATA <= 32'h4770d1f2; // 0x01b4
- 8'h6e : RDATA <= 32'h4c44b510; // 0x01b8
- 8'h6f : RDATA <= 32'h48416821; // 0x01bc
- 8'h70 : RDATA <= 32'hd00a2900; // 0x01c0
- 8'h71 : RDATA <= 32'h781aa342; // 0x01c4
- 8'h72 : RDATA <= 32'hd0212a00; // 0x01c8
- 8'h73 : RDATA <= 32'h07c96841; // 0x01cc
- 8'h74 : RDATA <= 32'h6841d1fc; // 0x01d0
- 8'h75 : RDATA <= 32'hd01707c9; // 0x01d4
- 8'h76 : RDATA <= 32'ha341e017; // 0x01d8
- 8'h77 : RDATA <= 32'h2a00781a; // 0x01dc
- 8'h78 : RDATA <= 32'h6841d009; // 0x01e0
- 8'h79 : RDATA <= 32'hd1fc07c9; // 0x01e4
- 8'h7a : RDATA <= 32'h07c96841; // 0x01e8
- 8'h7b : RDATA <= 32'h6002d100; // 0x01ec
- 8'h7c : RDATA <= 32'h2a001c5b; // 0x01f0
- 8'h7d : RDATA <= 32'h2204d1f2; // 0x01f4
- 8'h7e : RDATA <= 32'h07c96841; // 0x01f8
- 8'h7f : RDATA <= 32'h6841d1fc; // 0x01fc
- 8'h80 : RDATA <= 32'hd10007c9; // 0x0200
- 8'h81 : RDATA <= 32'he7fe6002; // 0x0204
- 8'h82 : RDATA <= 32'h1c5b6002; // 0x0208
- 8'h83 : RDATA <= 32'hd1da2a00; // 0x020c
- 8'h84 : RDATA <= 32'h60202000; // 0x0210
- 8'h85 : RDATA <= 32'h8f4ff3bf; // 0x0214
- 8'h86 : RDATA <= 32'h8f6ff3bf; // 0x0218
- 8'h87 : RDATA <= 32'hffa2f7ff; // 0x021c
- 8'h88 : RDATA <= 32'hb510bd10; // 0x0220
- 8'h89 : RDATA <= 32'h48262141; // 0x0224
- 8'h8a : RDATA <= 32'h61010149; // 0x0228
- 8'h8b : RDATA <= 32'h60812101; // 0x022c
- 8'h8c : RDATA <= 32'h60814824; // 0x0230
- 8'h8d : RDATA <= 32'h21204a24; // 0x0234
- 8'h8e : RDATA <= 32'ha32f6191; // 0x0238
- 8'h8f : RDATA <= 32'h2a00781a; // 0x023c
- 8'h90 : RDATA <= 32'h6841d009; // 0x0240
- 8'h91 : RDATA <= 32'hd1fc07c9; // 0x0244
- 8'h92 : RDATA <= 32'h07c96841; // 0x0248
- 8'h93 : RDATA <= 32'h6002d100; // 0x024c
- 8'h94 : RDATA <= 32'h2a001c5b; // 0x0250
- 8'h95 : RDATA <= 32'h4c1dd1f2; // 0x0254
- 8'h96 : RDATA <= 32'h29006821; // 0x0258
- 8'h97 : RDATA <= 32'ha31cd00a; // 0x025c
- 8'h98 : RDATA <= 32'h2a00781a; // 0x0260
- 8'h99 : RDATA <= 32'h6841d021; // 0x0264
- 8'h9a : RDATA <= 32'hd1fc07c9; // 0x0268
- 8'h9b : RDATA <= 32'h07c96841; // 0x026c
- 8'h9c : RDATA <= 32'he017d017; // 0x0270
- 8'h9d : RDATA <= 32'h781aa31a; // 0x0274
- 8'h9e : RDATA <= 32'hd0092a00; // 0x0278
- 8'h9f : RDATA <= 32'h07c96841; // 0x027c
- 8'ha0 : RDATA <= 32'h6841d1fc; // 0x0280
- 8'ha1 : RDATA <= 32'hd10007c9; // 0x0284
- 8'ha2 : RDATA <= 32'h1c5b6002; // 0x0288
- 8'ha3 : RDATA <= 32'hd1f22a00; // 0x028c
- 8'ha4 : RDATA <= 32'h68412204; // 0x0290
- 8'ha5 : RDATA <= 32'hd1fc07c9; // 0x0294
- 8'ha6 : RDATA <= 32'h07c96841; // 0x0298
- 8'ha7 : RDATA <= 32'h6002d100; // 0x029c
- 8'ha8 : RDATA <= 32'h6002e7fe; // 0x02a0
- 8'ha9 : RDATA <= 32'h2a001c5b; // 0x02a4
- 8'haa : RDATA <= 32'h2000d1da; // 0x02a8
- 8'hab : RDATA <= 32'hf3bf6020; // 0x02ac
- 8'hac : RDATA <= 32'hf3bf8f4f; // 0x02b0
- 8'had : RDATA <= 32'hf7ff8f6f; // 0x02b4
- 8'hae : RDATA <= 32'h2000ff55; // 0x02b8
- 8'haf : RDATA <= 32'h0000bd10; // 0x02bc
- 8'hb0 : RDATA <= 32'h40006000; // 0x02c0
- 8'hb1 : RDATA <= 32'h4000e000; // 0x02c4
- 8'hb2 : RDATA <= 32'h40011000; // 0x02c8
- 8'hb3 : RDATA <= 32'h4001f000; // 0x02cc
- 8'hb4 : RDATA <= 32'h52202a2a; // 0x02d0
- 8'hb5 : RDATA <= 32'h70616d65; // 0x02d4
- 8'hb6 : RDATA <= 32'h41523e2d; // 0x02d8
- 8'hb7 : RDATA <= 32'h000a324d; // 0x02dc
- 8'hb8 : RDATA <= 32'h72724540; // 0x02e0
- 8'hb9 : RDATA <= 32'h203a726f; // 0x02e4
- 8'hba : RDATA <= 32'h414d4552; // 0x02e8
- 8'hbb : RDATA <= 32'h6c632050; // 0x02ec
- 8'hbc : RDATA <= 32'h65726165; // 0x02f0
- 8'hbd : RDATA <= 32'h00000a64; // 0x02f4
- 8'hbe : RDATA <= 32'h530a0a0a; // 0x02f8
- 8'hbf : RDATA <= 32'h414c434f; // 0x02fc
- 8'hc0 : RDATA <= 32'h203a5342; // 0x0300
- 8'hc1 : RDATA <= 32'h204d5241; // 0x0304
- 8'hc2 : RDATA <= 32'h74726f43; // 0x0308
- 8'hc3 : RDATA <= 32'h4d2d7865; // 0x030c
- 8'hc4 : RDATA <= 32'h616e2030; // 0x0310
- 8'hc5 : RDATA <= 32'h6f736f6e; // 0x0314
- 8'hc6 : RDATA <= 32'h00000a63; // 0x0318
- 8'hc7 : RDATA <= 32'h48034904; // 0x031c
- 8'hc8 : RDATA <= 32'h47706008; // 0x0320
- 8'hc9 : RDATA <= 32'h48014902; // 0x0324
- 8'hca : RDATA <= 32'h47706008; // 0x0328
- 8'hcb : RDATA <= 32'h05f5e100; // 0x032c
- 8'hcc : RDATA <= 32'h30000000; // 0x0330
- 8'hcd : RDATA <= 32'h47804807; // 0x0334
- 8'hce : RDATA <= 32'h47004807; // 0x0338
- 8'hcf : RDATA <= 32'he7fee7fe; // 0x033c
- 8'hd0 : RDATA <= 32'he7fee7fe; // 0x0340
- 8'hd1 : RDATA <= 32'he7fee7fe; // 0x0344
- 8'hd2 : RDATA <= 32'h49054804; // 0x0348
- 8'hd3 : RDATA <= 32'h4b064a05; // 0x034c
- 8'hd4 : RDATA <= 32'h00004770; // 0x0350
- 8'hd5 : RDATA <= 32'h10000325; // 0x0354
- 8'hd6 : RDATA <= 32'h100000c1; // 0x0358
- 8'hd7 : RDATA <= 32'h30000068; // 0x035c
- 8'hd8 : RDATA <= 32'h30000368; // 0x0360
- 8'hd9 : RDATA <= 32'h30000168; // 0x0364
- 8'hda : RDATA <= 32'h30000168; // 0x0368
- 8'hdb : RDATA <= 32'h47704770; // 0x036c
- 8'hdc : RDATA <= 32'h46754770; // 0x0370
- 8'hdd : RDATA <= 32'hf824f000; // 0x0374
- 8'hde : RDATA <= 32'h000546ae; // 0x0378
- 8'hdf : RDATA <= 32'h46534669; // 0x037c
- 8'he0 : RDATA <= 32'h00c008c0; // 0x0380
- 8'he1 : RDATA <= 32'hb0184685; // 0x0384
- 8'he2 : RDATA <= 32'hf7ffb520; // 0x0388
- 8'he3 : RDATA <= 32'hbc60ffdd; // 0x038c
- 8'he4 : RDATA <= 32'h08492700; // 0x0390
- 8'he5 : RDATA <= 32'h260046b6; // 0x0394
- 8'he6 : RDATA <= 32'hc5c0c5c0; // 0x0398
- 8'he7 : RDATA <= 32'hc5c0c5c0; // 0x039c
- 8'he8 : RDATA <= 32'hc5c0c5c0; // 0x03a0
- 8'he9 : RDATA <= 32'hc5c0c5c0; // 0x03a4
- 8'hea : RDATA <= 32'h00493d40; // 0x03a8
- 8'heb : RDATA <= 32'h4770468d; // 0x03ac
- 8'hec : RDATA <= 32'h4604b510; // 0x03b0
- 8'hed : RDATA <= 32'h46c046c0; // 0x03b4
- 8'hee : RDATA <= 32'hf7ff4620; // 0x03b8
- 8'hef : RDATA <= 32'hbd10fecc; // 0x03bc
- 8'hf0 : RDATA <= 32'h47704800; // 0x03c0
- 8'hf1 : RDATA <= 32'h30000004; // 0x03c4
- 8'hf2 : RDATA <= 32'h20184901; // 0x03c8
- 8'hf3 : RDATA <= 32'he7febeab; // 0x03cc
- 8'hf4 : RDATA <= 32'h00020026; // 0x03d0
- 8'hf5 : RDATA <= 32'h00004770; // 0x03d4
- 8'hf6 : RDATA <= 32'h100003f8; // 0x03d8
- 8'hf7 : RDATA <= 32'h30000000; // 0x03dc
- 8'hf8 : RDATA <= 32'h00000004; // 0x03e0
- 8'hf9 : RDATA <= 32'h10000104; // 0x03e4
- 8'hfa : RDATA <= 32'h100003fc; // 0x03e8
- 8'hfb : RDATA <= 32'h30000004; // 0x03ec
- 8'hfc : RDATA <= 32'h00000364; // 0x03f0
- 8'hfd : RDATA <= 32'h10000120; // 0x03f4
- 8'hfe : RDATA <= 32'h05f5e100; // 0x03f8
- 8'hff : RDATA <= 32'h00000000; // 0x03fc
- default : RDATA <=32'h0;
- endcase
-endmodule
diff --git a/systems/mcu/src/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr b/systems/mcu/src/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
deleted file mode 100644
index a4d2556a2ac45249fb037110a2a7b4e860c5be0b..0000000000000000000000000000000000000000
--- a/systems/mcu/src/gen_ahb_busmatrix/gen_soclabs_4x7_AhbMatrix.scr
+++ /dev/null
@@ -1,2 +0,0 @@
-bin/BuildBusMatrix.pl -notimescales -xmldir xml -cfg soclabs_ahb32_4x7.xml -ipxact -ipxactsrcdir=ipxact/src -ipxacttgtdir=ipxact/built -over -verbose >& soclabs_ahb32_4x7.log
-
diff --git a/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex b/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex
deleted file mode 100644
index 1ab6c31cc0bc29a13f3baf5d4cd2211c4b84252b..0000000000000000000000000000000000000000
--- a/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0.hex
+++ /dev/null
@@ -1,4996 +0,0 @@
-60
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diff --git a/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex b/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex
deleted file mode 100644
index 1ab6c31cc0bc29a13f3baf5d4cd2211c4b84252b..0000000000000000000000000000000000000000
--- a/systems/mcu/testcodes/rtx_demo/rtx_demo_cm0p.hex
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diff --git a/systems/mcu/aes/aes128_tests/aes128.h b/systems/nanosoc/aes/aes128_tests/aes128.h
similarity index 100%
rename from systems/mcu/aes/aes128_tests/aes128.h
rename to systems/nanosoc/aes/aes128_tests/aes128.h
diff --git a/systems/mcu/aes/aes128_tests/aes128_tests.c b/systems/nanosoc/aes/aes128_tests/aes128_tests.c
similarity index 100%
rename from systems/mcu/aes/aes128_tests/aes128_tests.c
rename to systems/nanosoc/aes/aes128_tests/aes128_tests.c
diff --git a/systems/mcu/aes/aes128_tests/dma_pl230_driver.c b/systems/nanosoc/aes/aes128_tests/dma_pl230_driver.c
similarity index 100%
rename from systems/mcu/aes/aes128_tests/dma_pl230_driver.c
rename to systems/nanosoc/aes/aes128_tests/dma_pl230_driver.c
diff --git a/systems/mcu/aes/aes128_tests/dma_pl230_driver.h b/systems/nanosoc/aes/aes128_tests/dma_pl230_driver.h
similarity index 100%
rename from systems/mcu/aes/aes128_tests/dma_pl230_driver.h
rename to systems/nanosoc/aes/aes128_tests/dma_pl230_driver.h
diff --git a/systems/mcu/aes/aes128_tests/makefile b/systems/nanosoc/aes/aes128_tests/makefile
similarity index 100%
rename from systems/mcu/aes/aes128_tests/makefile
rename to systems/nanosoc/aes/aes128_tests/makefile
diff --git a/systems/mcu/aes/verilog/soclabs_ahb_aes128_ctrl.v b/systems/nanosoc/aes/src/soclabs_ahb_aes128_ctrl.v
similarity index 100%
rename from systems/mcu/aes/verilog/soclabs_ahb_aes128_ctrl.v
rename to systems/nanosoc/aes/src/soclabs_ahb_aes128_ctrl.v
diff --git a/systems/mcu/verif/aes128_log_to_file.v b/systems/nanosoc/aes/verif/aes128_log_to_file.v
similarity index 100%
rename from systems/mcu/verif/aes128_log_to_file.v
rename to systems/nanosoc/aes/verif/aes128_log_to_file.v
diff --git a/systems/mcu/defines/pl230_defs.v b/systems/nanosoc/defines/pl230_defs.v
similarity index 100%
rename from systems/mcu/defines/pl230_defs.v
rename to systems/nanosoc/defines/pl230_defs.v
diff --git a/systems/mcu/fpga_imp/CI_verification/.gitkeep b/systems/nanosoc/fpga_imp/CI_verification/.gitkeep
similarity index 100%
rename from systems/mcu/fpga_imp/CI_verification/.gitkeep
rename to systems/nanosoc/fpga_imp/CI_verification/.gitkeep
diff --git a/systems/mcu/fpga_imp/CI_verification/load_bitfile.py b/systems/nanosoc/fpga_imp/CI_verification/load_bitfile.py
similarity index 100%
rename from systems/mcu/fpga_imp/CI_verification/load_bitfile.py
rename to systems/nanosoc/fpga_imp/CI_verification/load_bitfile.py
diff --git a/systems/mcu/fpga_imp/CI_verification/load_file_output b/systems/nanosoc/fpga_imp/CI_verification/load_file_output
similarity index 100%
rename from systems/mcu/fpga_imp/CI_verification/load_file_output
rename to systems/nanosoc/fpga_imp/CI_verification/load_file_output
diff --git a/systems/mcu/fpga_imp/CI_verification/run_ADP_verification.py b/systems/nanosoc/fpga_imp/CI_verification/run_ADP_verification.py
similarity index 100%
rename from systems/mcu/fpga_imp/CI_verification/run_ADP_verification.py
rename to systems/nanosoc/fpga_imp/CI_verification/run_ADP_verification.py
diff --git a/systems/mcu/fpga_imp/build_fpga_pynq_z2.scr b/systems/nanosoc/fpga_imp/build_fpga_pynq_z2.scr
similarity index 100%
rename from systems/mcu/fpga_imp/build_fpga_pynq_z2.scr
rename to systems/nanosoc/fpga_imp/build_fpga_pynq_z2.scr
diff --git a/systems/mcu/fpga_imp/build_fpga_pynq_zcu104.scr b/systems/nanosoc/fpga_imp/build_fpga_pynq_zcu104.scr
similarity index 100%
rename from systems/mcu/fpga_imp/build_fpga_pynq_zcu104.scr
rename to systems/nanosoc/fpga_imp/build_fpga_pynq_zcu104.scr
diff --git a/systems/mcu/fpga_imp/clean_fpga.scr b/systems/nanosoc/fpga_imp/clean_fpga.scr
similarity index 100%
rename from systems/mcu/fpga_imp/clean_fpga.scr
rename to systems/nanosoc/fpga_imp/clean_fpga.scr
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/bd/bd.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/component.xml
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/src/ADPmanager.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/bd/bd.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/component.xml
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
diff --git a/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl b/systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
similarity index 100%
rename from systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
rename to systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
similarity index 100%
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diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
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diff --git a/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip b/systems/nanosoc/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip
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rename from systems/mcu/src/gen_ahb_busmatrix/bin/BuildBusMatrix.pl
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/bin/BuildBusMatrix.pl
diff --git a/systems/mcu/src/gen_ahb_busmatrix/bin/lib/xmlparser.pm b/systems/nanosoc/src/nanosoc_ahb_busmatrix/bin/lib/xmlparser.pm
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/bin/lib/xmlparser.pm
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/bin/lib/xmlparser.pm
diff --git a/systems/nanosoc/src/nanosoc_ahb_busmatrix/gen_nanosoc_4x7_AhbMatrix.scr b/systems/nanosoc/src/nanosoc_ahb_busmatrix/gen_nanosoc_4x7_AhbMatrix.scr
new file mode 100755
index 0000000000000000000000000000000000000000..17cb306753570a5454c0e5b8cb0d492013d6a5b0
--- /dev/null
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/gen_nanosoc_4x7_AhbMatrix.scr
@@ -0,0 +1,2 @@
+bin/BuildBusMatrix.pl -notimescales -xmldir xml -cfg nanosoc_ahb32_4x7.xml -ipxact -ipxactsrcdir=ipxact/src -ipxacttgtdir=ipxact/built -over -verbose >& nanosoc_ahb32_4x7.log
+
diff --git a/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.xml
new file mode 100644
index 0000000000000000000000000000000000000000..aa85aa548f8b4404cda0cbf1c5663c9db800cbe8
--- /dev/null
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.xml
@@ -0,0 +1,4257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the main top of nanosoc_4x7_AhbMatrix -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>nanosoc_4x7_AhbMatrix</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__adp</spirit:name>
+ <spirit:description>Slave port _adp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__adp_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_adp unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_adp</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma</spirit:name>
+ <spirit:description>Slave port _dma</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__dma2</spirit:name>
+ <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__dma2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_dma2 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteTarget_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_cpu unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
+ <spirit:description>Master port _rom1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_rom1 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
+ <spirit:description>Master port _ram2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram2 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
+ <spirit:description>Master port _ram3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram3 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
+ <spirit:description>Master port _sys</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_sys unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
+ <spirit:description>Master port _ram8</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram8 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
+ <spirit:description>Master port _ram9</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_ram9 unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- HMASTER_exp unmapped -->
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
+ <spirit:description>_rom1 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
+ <spirit:description>_ram2 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
+ <spirit:description>_ram3 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
+ <spirit:description>_sys address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
+ <spirit:description>_ram8 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
+ <spirit:description>_ram9 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__adp_MM</spirit:name>
+ <spirit:description>_adp memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__adp_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma_MM</spirit:name>
+ <spirit:description>_dma memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__dma2_MM</spirit:name>
+ <spirit:description>_dma2 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteTarget_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteTarget_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>nanosoc_4x7_AhbMatrix bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>nanosoc_4x7_AhbMatrix</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>2</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>3</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <spirit:port>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:wire>
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+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for nanosoc_4x7_AhbMatrix</spirit:description>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MasterInput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_adp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_cpu.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_Arbiter.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_SlaveOutput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>nanosoc_4x7_AhbMatrix</spirit:description>
+
+</spirit:component>
diff --git a/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.xml
new file mode 100644
index 0000000000000000000000000000000000000000..39df5c3f083f440f68fa48ee8f7c53e15d4b8736
--- /dev/null
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.xml
@@ -0,0 +1,3902 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- The confidential and proprietary information contained in this file may -->
+<!-- only be used by a person authorised under and to the extent permitted -->
+<!-- by a subsisting licensing agreement from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- (C) COPYRIGHT 2001-2017 ARM Limited or its affiliates. -->
+<!-- ALL RIGHTS RESERVED -->
+<!-- -->
+<!-- This entire notice must be reproduced on all copies of this file -->
+<!-- and copies of this file may only be made by a person if such person is -->
+<!-- permitted to do so under the terms of a subsisting license agreement -->
+<!-- from ARM Limited or its affiliates. -->
+<!-- -->
+<!-- SVN Information -->
+<!-- -->
+<!-- Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ -->
+<!-- -->
+<!-- Revision : $Revision: 371321 $ -->
+<!-- -->
+<!-- Release Information : Cortex-M System Design Kit-r1p1-00rel0 -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+<!-- Purpose : IP-XACT description for the AHB-Lite wrapper of nanosoc_4x7_AhbMatrix_lite -->
+<!-- -->
+<!-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -->
+
+<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+ <spirit:vendor>arm.com</spirit:vendor>
+ <spirit:library>CoreLink</spirit:library>
+ <spirit:name>nanosoc_4x7_AhbMatrix_lite</spirit:name>
+ <spirit:version>r0p0_0</spirit:version>
+
+ <spirit:busInterfaces>
+
+ <!--Slave interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__adp</spirit:name>
+ <spirit:description>Slave port _adp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__adp_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_adp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma</spirit:name>
+ <spirit:description>Slave port _dma</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__dma2</spirit:name>
+ <spirit:description>Slave port _dma2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__dma2_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteInitiator_Slave__cpu</spirit:name>
+ <spirit:description>Slave port _cpu</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteInitiator" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteInitiator_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="AHBLiteInitiator_Slave__cpu_MM"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__rom1" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram2" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram3" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__sys" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram8" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__ram9" spirit:opaque="true"/>
+ <spirit:bridge spirit:masterRef="AHBLiteTarget_Master__exp" spirit:opaque="true"/>
+ </spirit:slave>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADY_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Master interfaces -->
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__rom1</spirit:name>
+ <spirit:description>Master port _rom1</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__rom1_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram2</spirit:name>
+ <spirit:description>Master port _ram2</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram2_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram3</spirit:name>
+ <spirit:description>Master port _ram3</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram3_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__sys</spirit:name>
+ <spirit:description>Master port _sys</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__sys_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_sys</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram8</spirit:name>
+ <spirit:description>Master port _ram8</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram8_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__ram9</spirit:name>
+ <spirit:description>Master port _ram9</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__ram9_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <spirit:busInterface>
+ <spirit:name>AHBLiteTarget_Master__exp</spirit:name>
+ <spirit:description>Master port _exp</spirit:description>
+ <spirit:busType spirit:library="AMBA3" spirit:name="AHBLiteTarget" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:abstractionType spirit:library="AMBA3" spirit:name="AHBLiteTarget_rtl" spirit:vendor="amba.com" spirit:version="r2p0_0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="AHBLiteTarget_Master__exp_AS"/>
+ </spirit:master>
+
+ <spirit:portMaps>
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <!-- Outputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSELx</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSEL_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HADDR_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HTRANS_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWRITE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HSIZE_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HBURST_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HPROT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HAUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HAUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HWUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <!-- Inputs -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRDATA_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADYOUT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESP_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRUSER</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRUSER_exp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ <!--Scan test dummy signals -->
+ <spirit:busInterface>
+ <spirit:name>DFTInterface_Slave</spirit:name>
+ <spirit:description>Scan test dummy signals, not connected until scan insertion</spirit:description>
+ <spirit:busType spirit:library="generic" spirit:name="DFTInterface" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:abstractionType spirit:library="generic" spirit:name="DFTInterface_rtl" spirit:vendor="arm.com" spirit:version="r0p0_1"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+
+ <!-- Clock/reset -->
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RESETn</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>HRESETn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSCANMODE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANENABLE</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSI</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANINHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DFTSO</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+
+ </spirit:busInterfaces>
+
+ <spirit:remapStates>
+
+ <spirit:remapState>
+ <spirit:name>remap_0</spirit:name>
+ <spirit:description>Remap state remap_0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">1</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+ <spirit:remapState>
+ <spirit:name>remap_n0</spirit:name>
+ <spirit:description>Remap state remap_n0</spirit:description>
+ <spirit:remapPorts>
+ <spirit:remapPort spirit:portNameRef="REMAP" spirit:portIndex="0">0</spirit:remapPort>
+ </spirit:remapPorts>
+ </spirit:remapState>
+
+ </spirit:remapStates>
+
+ <spirit:addressSpaces>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__rom1_AS</spirit:name>
+ <spirit:description>_rom1 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_rom1_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_rom1_0x10000000_0x1fffffff</spirit:name>
+ <spirit:addressOffset>0x10000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram2_AS</spirit:name>
+ <spirit:description>_ram2 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram2_0x00000000_0x0fffffff</spirit:name>
+ <spirit:addressOffset>0x00000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_ram2_0x20000000_0x2fffffff</spirit:name>
+ <spirit:addressOffset>0x20000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram3_AS</spirit:name>
+ <spirit:description>_ram3 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram3_0x30000000_0x3fffffff</spirit:name>
+ <spirit:addressOffset>0x30000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__sys_AS</spirit:name>
+ <spirit:description>_sys address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_sys_0x40000000_0x5fffffff</spirit:name>
+ <spirit:addressOffset>0x40000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_sys_0xf0000000_0xf003ffff</spirit:name>
+ <spirit:addressOffset>0xf0000000</spirit:addressOffset>
+ <spirit:range>0x000040000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram8_AS</spirit:name>
+ <spirit:description>_ram8 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram8_0x80000000_0x8fffffff</spirit:name>
+ <spirit:addressOffset>0x80000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__ram9_AS</spirit:name>
+ <spirit:description>_ram9 address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_ram9_0x90000000_0x9fffffff</spirit:name>
+ <spirit:addressOffset>0x90000000</spirit:addressOffset>
+ <spirit:range>0x010000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ <spirit:addressSpace>
+ <spirit:name>AHBLiteTarget_Master__exp_AS</spirit:name>
+ <spirit:description>_exp address space</spirit:description>
+ <spirit:range>4G</spirit:range>
+ <spirit:width>32</spirit:width>
+ <spirit:segments>
+ <spirit:segment>
+ <spirit:name>_exp_0x60000000_0x7fffffff</spirit:name>
+ <spirit:addressOffset>0x60000000</spirit:addressOffset>
+ <spirit:range>0x020000000</spirit:range>
+ </spirit:segment>
+ <spirit:segment>
+ <spirit:name>_exp_0xa0000000_0xdfffffff</spirit:name>
+ <spirit:addressOffset>0xa0000000</spirit:addressOffset>
+ <spirit:range>0x040000000</spirit:range>
+ </spirit:segment>
+ </spirit:segments>
+ <spirit:addressUnitBits>8</spirit:addressUnitBits>
+ </spirit:addressSpace>
+
+ </spirit:addressSpaces>
+
+ <spirit:memoryMaps>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__adp_MM</spirit:name>
+ <spirit:description>_adp memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__adp_remap_0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__adp_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_adp remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma_MM</spirit:name>
+ <spirit:description>_dma memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__dma2_MM</spirit:name>
+ <spirit:description>_dma2 memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ </spirit:memoryMap>
+
+ <spirit:memoryMap>
+ <spirit:name>AHBLiteInitiator_Slave__cpu_MM</spirit:name>
+ <spirit:description>_cpu memory map</spirit:description>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x10000000_0x1fffffff">
+ <!-- Address_region 0x10000000-0x1fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x10000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x10000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x20000000_0x2fffffff">
+ <!-- Address_region 0x20000000-0x2fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x20000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x20000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram3"
+ spirit:segmentRef="_ram3_0x30000000_0x3fffffff">
+ <!-- Address_region 0x30000000-0x3fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram3_0x30000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x30000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0x40000000_0x5fffffff">
+ <!-- Address_region 0x40000000-0x5fffffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0x40000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x40000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0x60000000_0x7fffffff">
+ <!-- Address_region 0x60000000-0x7fffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0x60000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x60000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram8"
+ spirit:segmentRef="_ram8_0x80000000_0x8fffffff">
+ <!-- Address_region 0x80000000-0x8fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram8_0x80000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x80000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram9"
+ spirit:segmentRef="_ram9_0x90000000_0x9fffffff">
+ <!-- Address_region 0x90000000-0x9fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram9_0x90000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0x90000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__exp"
+ spirit:segmentRef="_exp_0xa0000000_0xdfffffff">
+ <!-- Address_region 0xa0000000-0xdfffffff -->
+ <spirit:name>AHBLiteTarget_Master__exp_0xa0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xa0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__sys"
+ spirit:segmentRef="_sys_0xf0000000_0xf003ffff">
+ <!-- Address_region 0xf0000000-0xf003ffff -->
+ <spirit:name>AHBLiteTarget_Master__sys_0xf0000000_0_state_always_SM</spirit:name>
+ <spirit:baseAddress>0xf0000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+
+ <spirit:memoryRemap spirit:state="remap_0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__ram2"
+ spirit:segmentRef="_ram2_0x00000000_0x0fffffff">
+ <!-- Remapped region, active when REMAP bitcombination is 0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__ram2_0x00000000_0_state_remap_0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ <spirit:memoryRemap spirit:state="remap_n0">
+ <spirit:name>AHBLiteInitiator_Slave__cpu_remap_n0_remap_MM</spirit:name>
+ <spirit:description>_cpu remap_n0 remap</spirit:description>
+ <spirit:subspaceMap spirit:masterRef="AHBLiteTarget_Master__rom1"
+ spirit:segmentRef="_rom1_0x00000000_0x0fffffff">
+ <!-- Removable region, active only when REMAP bitcombination is n0 address_region 0x00000000-0x0fffffff -->
+ <spirit:name>AHBLiteTarget_Master__rom1_0x00000000_0_state_remap_n0_SM</spirit:name>
+ <spirit:baseAddress>0x00000000</spirit:baseAddress>
+ </spirit:subspaceMap>
+ </spirit:memoryRemap>
+
+ </spirit:memoryMap>
+
+ </spirit:memoryMaps>
+
+
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>verilogsource</spirit:name>
+ <spirit:description>nanosoc_4x7_AhbMatrix_lite bus matrix</spirit:description>
+ <spirit:envIdentifier>:*Simulation:</spirit:envIdentifier>
+ <spirit:envIdentifier>:*Synthesis:</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>nanosoc_4x7_AhbMatrix_lite</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>fs-verilogsource</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+
+ <spirit:ports>
+
+ <!-- Common clock and reset -->
+
+ <spirit:port>
+ <spirit:name>HCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESETn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Remap port -->
+ <spirit:port>
+ <spirit:name>REMAP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HADDR_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ <spirit:driver>
+ <spirit:defaultValue>0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Input signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYOUT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANENABLE</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SCANINHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Master interfaces -->
+
+ <spirit:port>
+ <spirit:name>HSEL_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_rom1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_sys</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_ram9</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSEL_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HADDR_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HTRANS_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWRITE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HSIZE_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HBURST_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>2</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HPROT_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>3</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWDATA_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HMASTLOCK_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADYMUX_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HAUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HWUSER_exp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Output signals of Slave interfaces -->
+
+ <spirit:port>
+ <spirit:name>HRDATA_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_adp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_dma2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRDATA_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>31</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HREADY_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRESP_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>HRUSER_cpu</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>1</spirit:left>
+ <spirit:right>0</spirit:right>
+ </spirit:vector>
+ </spirit:wire>
+ </spirit:port>
+
+ <!-- Scan test dummy signals; not connected until scan insertion -->
+
+ <spirit:port>
+ <spirit:name>SCANOUTHCLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>fs-verilogsource</spirit:name>
+ <spirit:displayName/>
+ <spirit:description>File list for nanosoc_4x7_AhbMatrix_lite</spirit:description>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ <spirit:isIncludeFile spirit:externalDeclarations="true">false</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_default_slave.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MasterInput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_adp.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma2.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_cpu.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_Arbiter.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>../../../verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_SlaveOutput.v</spirit:name>
+ <spirit:fileType>verilogSource-2001</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+
+ <spirit:description>nanosoc_4x7_AhbMatrix_lite</spirit:description>
+
+</spirit:component>
diff --git a/systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml
diff --git a/systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml
diff --git a/systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_ipxact.xml
diff --git a/systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/ipxact/src/cmsdk_ahb_busmatrix_lite_ipxact.xml
diff --git a/systems/nanosoc/src/nanosoc_ahb_busmatrix/nanosoc_ahb32_4x7.log b/systems/nanosoc/src/nanosoc_ahb_busmatrix/nanosoc_ahb32_4x7.log
new file mode 100644
index 0000000000000000000000000000000000000000..49ac38cdf6f52e748c3b2baf264940aa771bc353
--- /dev/null
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/nanosoc_ahb32_4x7.log
@@ -0,0 +1,60 @@
+
+==============================================================
+= The confidential and proprietary information contained in this file may
+= only be used by a person authorised under and to the extent permitted
+= by a subsisting licensing agreement from Arm Limited or its affiliates.
+=
+= (C) COPYRIGHT 2001-2013,2017 Arm Limited or its affiliates.
+= ALL RIGHTS RESERVED
+=
+= This entire notice must be reproduced on all copies of this file
+= and copies of this file may only be made by a person if such person is
+= permitted to do so under the terms of a subsisting license agreement
+= from Arm Limited or its affiliates.
+=
+= BuildBusMatrix.pl
+=
+= Run Date : 28/04/2023 14:54:35
+==============================================================
+
+Script accepted the following parameters:
+
+ - Configuration file : 'xml/nanosoc_ahb32_4x7.xml'
+ - Top-level name : 'nanosoc_4x7_AhbMatrix'
+ - Slave interfaces : 4
+ - Master interfaces : 7
+ - Architecture type : 'ahb2'
+ - Arbitration scheme : 'burst'
+ - Address map : user defined
+ - Connectivity mapping : _adp -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _dma -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _dma2 -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9,
+ _cpu -> _rom1, _ram2, _ram3, _sys, _exp, _ram8, _ram9
+ - Connectivity type : full
+ - Routing data width : 32
+ - Routing address width : 32
+ - User signal width : 2
+ - Timescales : no
+ - Configuration directory : './verilog/built'
+ - Source directory : './verilog/src'
+ - IPXact target directory : 'ipxact/built'
+ - IPXact source directory : 'ipxact/src'
+ - Overwrite mode : enabled
+
+Creating the bus matrix variant...
+
+ - Rendering 'nanosoc_4x7_AhbMatrix_default_slave.v'
+ - Rendering 'nanosoc_4x7_MatrixDecode_dma2.v'
+ - Rendering 'nanosoc_4x7_Arbiter.v'
+ - Rendering 'nanosoc_4x7_SlaveOutput.v'
+ - Rendering 'nanosoc_4x7_AhbMatrix.v'
+ - Rendering 'nanosoc_4x7_AhbMatrix_lite.xml'
+ - Rendering 'nanosoc_4x7_MasterInput.v'
+ - Rendering 'nanosoc_4x7_MatrixDecode_dma.v'
+ - Rendering 'nanosoc_4x7_AhbMatrix.xml'
+ - Rendering 'nanosoc_4x7_AhbMatrix_lite.v'
+ - Rendering 'nanosoc_4x7_MatrixDecode_adp.v'
+ - Rendering 'nanosoc_4x7_MatrixDecode_cpu.v'
+
+Done!
+
diff --git a/systems/mcu/src/gen_ahb_busmatrix/soclabs_ahb32_4x7.log b/systems/nanosoc/src/nanosoc_ahb_busmatrix/soclabs_ahb32_4x7.log
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/soclabs_ahb32_4x7.log
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/soclabs_ahb32_4x7.log
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.v
similarity index 98%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.v
index 6179e6075f7fc9e1b45fa9c32e09dfccb8fc2853..496b49ff0f4094139ab5a5cbbb3c113608268d6c 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix.v
@@ -43,7 +43,7 @@
-module soclabs_4x7_AhbMatrix (
+module nanosoc_4x7_AhbMatrix (
// Common AHB signals
HCLK,
@@ -971,7 +971,7 @@ module soclabs_4x7_AhbMatrix (
// -----------------------------------------------------------------------------
// Input stage for SI0
- soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_0 (
+ nanosoc_4x7_MasterInput u_nanosoc_4x7_MasterInput_0 (
// Common AHB signals
.HCLK (HCLK),
@@ -1016,7 +1016,7 @@ module soclabs_4x7_AhbMatrix (
// Input stage for SI1
- soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_1 (
+ nanosoc_4x7_MasterInput u_nanosoc_4x7_MasterInput_1 (
// Common AHB signals
.HCLK (HCLK),
@@ -1061,7 +1061,7 @@ module soclabs_4x7_AhbMatrix (
// Input stage for SI2
- soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_2 (
+ nanosoc_4x7_MasterInput u_nanosoc_4x7_MasterInput_2 (
// Common AHB signals
.HCLK (HCLK),
@@ -1106,7 +1106,7 @@ module soclabs_4x7_AhbMatrix (
// Input stage for SI3
- soclabs_4x7_MasterInput u_soclabs_4x7_MasterInput_3 (
+ nanosoc_4x7_MasterInput u_nanosoc_4x7_MasterInput_3 (
// Common AHB signals
.HCLK (HCLK),
@@ -1151,7 +1151,7 @@ module soclabs_4x7_AhbMatrix (
// Matrix decoder for SI0
- soclabs_4x7_MatrixDecode_adp u_soclabs_4x7_matrixdecode_adp (
+ nanosoc_4x7_MatrixDecode_adp u_nanosoc_4x7_matrixdecode_adp (
// Common AHB signals
.HCLK (HCLK),
@@ -1233,7 +1233,7 @@ module soclabs_4x7_AhbMatrix (
// Matrix decoder for SI1
- soclabs_4x7_MatrixDecode_dma u_soclabs_4x7_matrixdecode_dma (
+ nanosoc_4x7_MatrixDecode_dma u_nanosoc_4x7_matrixdecode_dma (
// Common AHB signals
.HCLK (HCLK),
@@ -1312,7 +1312,7 @@ module soclabs_4x7_AhbMatrix (
// Matrix decoder for SI2
- soclabs_4x7_MatrixDecode_dma2 u_soclabs_4x7_matrixdecode_dma2 (
+ nanosoc_4x7_MatrixDecode_dma2 u_nanosoc_4x7_matrixdecode_dma2 (
// Common AHB signals
.HCLK (HCLK),
@@ -1391,7 +1391,7 @@ module soclabs_4x7_AhbMatrix (
// Matrix decoder for SI3
- soclabs_4x7_MatrixDecode_cpu u_soclabs_4x7_matrixdecode_cpu (
+ nanosoc_4x7_MatrixDecode_cpu u_nanosoc_4x7_matrixdecode_cpu (
// Common AHB signals
.HCLK (HCLK),
@@ -1473,7 +1473,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI0
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_0 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_0 (
// Common AHB signals
.HCLK (HCLK),
@@ -1569,7 +1569,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI1
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_1 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_1 (
// Common AHB signals
.HCLK (HCLK),
@@ -1665,7 +1665,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI2
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_2 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_2 (
// Common AHB signals
.HCLK (HCLK),
@@ -1761,7 +1761,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI3
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_3 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_3 (
// Common AHB signals
.HCLK (HCLK),
@@ -1857,7 +1857,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI4
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_4 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_4 (
// Common AHB signals
.HCLK (HCLK),
@@ -1953,7 +1953,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI5
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_5 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_5 (
// Common AHB signals
.HCLK (HCLK),
@@ -2049,7 +2049,7 @@ module soclabs_4x7_AhbMatrix (
// Output stage for MI6
- soclabs_4x7_SlaveOutput u_soclabs_4x7_slaveoutput_6 (
+ nanosoc_4x7_SlaveOutput u_nanosoc_4x7_slaveoutput_6 (
// Common AHB signals
.HCLK (HCLK),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_default_slave.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_default_slave.v
index 156124e9f5ae70c06a0d4ef9e0517603eb826211..4d2fd4a9006c0c0274f133e1e455504dd5708ff9 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_default_slave.v
@@ -28,7 +28,7 @@
-module soclabs_4x7_AhbMatrix_default_slave (
+module nanosoc_4x7_AhbMatrix_default_slave (
// Common AHB signals
HCLK,
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.v
index f17138d10ed6515f84e2451985c6bc13832a8cc1..b4653fd3ffe57818632752d958ee1a2baccfbff9 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_AhbMatrix_lite.v
@@ -30,7 +30,7 @@
-module soclabs_4x7_AhbMatrix_lite (
+module nanosoc_4x7_AhbMatrix_lite (
// Common AHB signals
HCLK,
@@ -757,7 +757,7 @@ module soclabs_4x7_AhbMatrix_lite (
assign i_hresp_exp = {{1{tie_low}}, HRESP_exp};
// BusMatrix instance
- soclabs_4x7_AhbMatrix usoclabs_4x7_AhbMatrix (
+ nanosoc_4x7_AhbMatrix unanosoc_4x7_AhbMatrix (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REMAP (REMAP),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_Arbiter.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_Arbiter.v
index 062079a2940b40ecfb6c7b5e3a45279e1eefe13b..53832f60fe0d83e30b788a13db8ef389b6a28b0c 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_Arbiter.v
@@ -32,7 +32,7 @@
-module soclabs_4x7_Arbiter (
+module nanosoc_4x7_Arbiter (
// Common AHB signals
HCLK ,
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MasterInput.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MasterInput.v
index 4e083b9add91ea2addc9fa0c12d7bdec835ce4a4..0c2a3c172d09265352a1b209da921d6f2bc1a88a 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MasterInput.v
@@ -29,7 +29,7 @@
-module soclabs_4x7_MasterInput (
+module nanosoc_4x7_MasterInput (
// Common AHB signals
HCLK,
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_adp.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_adp.v
index bd40d1edc936f6ad218fcb41f04a09a4271bb219..19020129adcdfdf8935aa5b8baa417176c7b8370 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_adp.v
@@ -33,7 +33,7 @@
-module soclabs_4x7_MatrixDecode_cpu (
+module nanosoc_4x7_MatrixDecode_adp (
// Common AHB signals
HCLK,
@@ -300,7 +300,7 @@ module soclabs_4x7_MatrixDecode_cpu (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+ nanosoc_4x7_AhbMatrix_default_slave u_nanosoc_4x7_AhbMatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_cpu.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_cpu.v
index 50a072540d7df984c5cd5294fef055359c1e804d..383eb8292d27ee07eff044f2e2a9c1c9d978f2c2 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_cpu.v
@@ -33,7 +33,7 @@
-module soclabs_4x7_MatrixDecode_adp (
+module nanosoc_4x7_MatrixDecode_cpu (
// Common AHB signals
HCLK,
@@ -300,7 +300,7 @@ module soclabs_4x7_MatrixDecode_adp (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+ nanosoc_4x7_AhbMatrix_default_slave u_nanosoc_4x7_AhbMatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma.v
index 0f0e1e24575d2a3abbcd2fa3499f971eaf865eb5..8c18a1260c5515cfd2111098a54d6d632a475dbd 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma.v
@@ -33,7 +33,7 @@
-module soclabs_4x7_MatrixDecode_dma (
+module nanosoc_4x7_MatrixDecode_dma (
// Common AHB signals
HCLK,
@@ -292,7 +292,7 @@ module soclabs_4x7_MatrixDecode_dma (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+ nanosoc_4x7_AhbMatrix_default_slave u_nanosoc_4x7_AhbMatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma2.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma2.v
index a0acb7f6c15252af9c4f4dd14b4cc8b4d5b2e9db..74dd1af6c6ae16626fb3e319177d31be7d4db5d2 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_MatrixDecode_dma2.v
@@ -33,7 +33,7 @@
-module soclabs_4x7_MatrixDecode_dma2 (
+module nanosoc_4x7_MatrixDecode_dma2 (
// Common AHB signals
HCLK,
@@ -292,7 +292,7 @@ module soclabs_4x7_MatrixDecode_dma2 (
// Default slave (accessed when HADDR is unmapped)
//------------------------------------------------------------------------------
- soclabs_4x7_AhbMatrix_default_slave u_soclabs_4x7_AhbMatrix_default_slave (
+ nanosoc_4x7_AhbMatrix_default_slave u_nanosoc_4x7_AhbMatrix_default_slave (
// Common AHB signals
.HCLK (HCLK),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_SlaveOutput.v
similarity index 99%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_SlaveOutput.v
index a572d454ab493202d99c3edc4c46ed67f9373041..3521e530943c83630d3644ceb8a2666005db2e5f 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/built/nanosoc_4x7_AhbMatrix/nanosoc_4x7_SlaveOutput.v
@@ -32,7 +32,7 @@
-module soclabs_4x7_SlaveOutput (
+module nanosoc_4x7_SlaveOutput (
// Common AHB signals
HCLK,
@@ -341,7 +341,7 @@ module soclabs_4x7_SlaveOutput (
assign req_port3 = held_tran_op3 & sel_op3;
// Arbiter instance for resolving requests to this output stage
- soclabs_4x7_Arbiter u_output_arb (
+ nanosoc_4x7_Arbiter u_output_arb (
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v b/systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
diff --git a/systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_full.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/example2x3_full.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_full.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/example2x3_full.xml
diff --git a/systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_sparse.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/example2x3_sparse.xml
similarity index 100%
rename from systems/mcu/src/gen_ahb_busmatrix/xml/example2x3_sparse.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/example2x3_sparse.xml
diff --git a/systems/mcu/src/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml b/systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml
similarity index 96%
rename from systems/mcu/src/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
rename to systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml
index b1ddc80c117821e2174ec12d18de2336f0a78f60..10f7aa161092934c8d45da95bf08b891bf99537d 100644
--- a/systems/mcu/src/gen_ahb_busmatrix/xml/soclabs_ahb32_4x7.xml
+++ b/systems/nanosoc/src/nanosoc_ahb_busmatrix/xml/nanosoc_ahb32_4x7.xml
@@ -52,11 +52,11 @@
<routing_data_width>32</routing_data_width>
<routing_address_width>32</routing_address_width>
<user_signal_width>2</user_signal_width>
- <bus_matrix_name>soclabs_4x7_AhbMatrix</bus_matrix_name>
- <input_stage_name>soclabs_4x7_MasterInput</input_stage_name>
- <matrix_decode_name>soclabs_4x7_MatrixDecode</matrix_decode_name>
- <output_arbiter_name>soclabs_4x7_Arbiter</output_arbiter_name>
- <output_stage_name>soclabs_4x7_SlaveOutput</output_stage_name>
+ <bus_matrix_name>nanosoc_4x7_AhbMatrix</bus_matrix_name>
+ <input_stage_name>nanosoc_4x7_MasterInput</input_stage_name>
+ <matrix_decode_name>nanosoc_4x7_MatrixDecode</matrix_decode_name>
+ <output_arbiter_name>nanosoc_4x7_Arbiter</output_arbiter_name>
+ <output_stage_name>nanosoc_4x7_SlaveOutput</output_stage_name>
<!-- Slave interface definitions -->
diff --git a/systems/mcu/src/bootrom/ahb_bootrom.v b/systems/nanosoc/src/verilog/nanosoc_ahb_bootrom.v
similarity index 66%
rename from systems/mcu/src/bootrom/ahb_bootrom.v
rename to systems/nanosoc/src/verilog/nanosoc_ahb_bootrom.v
index 5031a98de8ff274fb846a9bc902ca595037db7ce..fe370eb275927568287b69ac0db0b3ae99864af7 100644
--- a/systems/mcu/src/bootrom/ahb_bootrom.v
+++ b/systems/nanosoc/src/verilog/nanosoc_ahb_bootrom.v
@@ -1,4 +1,15 @@
-module ahb_bootrom #(
+//-----------------------------------------------------------------------------
+// NanoSoC AHB to Bootrom Interface
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_ahb_bootrom #(
// Parameters
parameter AW = 10 // Address width
)
diff --git a/systems/mcu/src/cmsdk_ahb_cs_rom_table.v b/systems/nanosoc/src/verilog/nanosoc_ahb_cs_rom_table.v
similarity index 96%
rename from systems/mcu/src/cmsdk_ahb_cs_rom_table.v
rename to systems/nanosoc/src/verilog/nanosoc_ahb_cs_rom_table.v
index 505b097314327cc03b6bab280846541e518240a2..f6345a2650eaae984bc9504121afc017f93e1946 100644
--- a/systems/mcu/src/cmsdk_ahb_cs_rom_table.v
+++ b/systems/nanosoc/src/verilog/nanosoc_ahb_cs_rom_table.v
@@ -1,3 +1,14 @@
+//-----------------------------------------------------------------------------
+// NanoSoC AHB CoreSight ROM Table adapted from Arm CMSDK AHB CoreSight ROM Table
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
@@ -63,7 +74,7 @@
// ECOREVNUM bus should be easily identifiable and modifiable.
//-----------------------------------------------------------------------------
-module cmsdk_ahb_cs_rom_table
+module nanosoc_ahb_cs_rom_table
#(
// ------------------------------------------------------------
// ROM Table BASE Address
diff --git a/systems/mcu/src/cmsdk_apb_subsystem.v b/systems/nanosoc/src/verilog/nanosoc_apb_subsystem.v
similarity index 98%
rename from systems/mcu/src/cmsdk_apb_subsystem.v
rename to systems/nanosoc/src/verilog/nanosoc_apb_subsystem.v
index 3e42ff1065c0de483f8d0e06e6829c675cce373a..e3e46d37b66c56d86faaee04e022e4107db3ac21 100755
--- a/systems/mcu/src/cmsdk_apb_subsystem.v
+++ b/systems/nanosoc/src/verilog/nanosoc_apb_subsystem.v
@@ -1,3 +1,14 @@
+//-----------------------------------------------------------------------------
+// NanoSoC APB Subsystem adapted from Arm CMSDK APB Subsystem
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
@@ -23,7 +34,7 @@
//-----------------------------------------------------------------------------
// Abstract : APB sub system
//-----------------------------------------------------------------------------
-module cmsdk_apb_subsystem #(
+module nanosoc_apb_subsystem #(
// Enable setting for APB extension ports
// By default, all four extension ports are not used.
// This can be overriden by parameters at instantiations.
diff --git a/systems/mcu/src/cmsdk_apb_usrt.v b/systems/nanosoc/src/verilog/nanosoc_apb_usrt.v
similarity index 99%
rename from systems/mcu/src/cmsdk_apb_usrt.v
rename to systems/nanosoc/src/verilog/nanosoc_apb_usrt.v
index f695ecc23108654e6983c19fdd5e9ad049a6cd25..8df136a6aaa944ef5f3b5dc0c5e1d94586117960 100644
--- a/systems/mcu/src/cmsdk_apb_usrt.v
+++ b/systems/nanosoc/src/verilog/nanosoc_apb_usrt.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised top-level example Cortex-M0 controller
+// NanoSoC APB USRT adapted from Arm CMSDK APB UART
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
// 0x3E0 - 0x3FC ID registers
//-------------------------------------
-module cmsdk_apb_usrt (
+module nanosoc_apb_usrt (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
diff --git a/systems/mcu/src/nanosoc_chip.v b/systems/nanosoc/src/verilog/nanosoc_chip.v
similarity index 100%
rename from systems/mcu/src/nanosoc_chip.v
rename to systems/nanosoc/src/verilog/nanosoc_chip.v
diff --git a/systems/mcu/src/nanosoc_chip_pads.v b/systems/nanosoc/src/verilog/nanosoc_chip_pads.v
similarity index 100%
rename from systems/mcu/src/nanosoc_chip_pads.v
rename to systems/nanosoc/src/verilog/nanosoc_chip_pads.v
diff --git a/systems/mcu/src/nanosoc_cpu.v b/systems/nanosoc/src/verilog/nanosoc_cpu.v
similarity index 100%
rename from systems/mcu/src/nanosoc_cpu.v
rename to systems/nanosoc/src/verilog/nanosoc_cpu.v
diff --git a/systems/mcu/src/cmsdk_mcu_clkctrl.v b/systems/nanosoc/src/verilog/nanosoc_mcu_clkctrl.v
similarity index 97%
rename from systems/mcu/src/cmsdk_mcu_clkctrl.v
rename to systems/nanosoc/src/verilog/nanosoc_mcu_clkctrl.v
index a994d017f4cb9d304bd31559392446b796ef8379..80be7812559e3186ad7a5d7b20220ae96991adfb 100644
--- a/systems/mcu/src/cmsdk_mcu_clkctrl.v
+++ b/systems/nanosoc/src/verilog/nanosoc_mcu_clkctrl.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// NanoSoC Clock Controller adapted from ARM CMSDK Simple clock controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -37,7 +37,7 @@
// Note : Most of the clock gating are handled by the example PMU provided
// in the Cortex-M0/Cortex-M0+ deliverable.
-module cmsdk_mcu_clkctrl #(
+module nanosoc_mcu_clkctrl #(
parameter CLKGATE_PRESENT = 0)
(
input wire XTAL1, // Clock source
diff --git a/systems/mcu/src/cmsdk_mcu_pin_mux.v b/systems/nanosoc/src/verilog/nanosoc_mcu_pin_mux.v
similarity index 94%
rename from systems/mcu/src/cmsdk_mcu_pin_mux.v
rename to systems/nanosoc/src/verilog/nanosoc_mcu_pin_mux.v
index 82d0ae5d32d2233ac83213d5d1c1b94ebd6dd671..963807e1f57c6714cfcb567d1b1e06b17cd4d34d 100644
--- a/systems/mcu/src/cmsdk_mcu_pin_mux.v
+++ b/systems/nanosoc/src/verilog/nanosoc_mcu_pin_mux.v
@@ -1,3 +1,14 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Pin Multiplexing Controller adapted from ARM CMSDK Pin multiplexing control
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
@@ -25,7 +36,7 @@
// microcontroller
//-----------------------------------------------------------------------------
//
-module cmsdk_mcu_pin_mux (
+module nanosoc_mcu_pin_mux (
//-------------------------------------------
// I/O ports
//-------------------------------------------
diff --git a/systems/mcu/src/cmsdk_mcu_stclkctrl.v b/systems/nanosoc/src/verilog/nanosoc_mcu_stclkctrl.v
similarity index 83%
rename from systems/mcu/src/cmsdk_mcu_stclkctrl.v
rename to systems/nanosoc/src/verilog/nanosoc_mcu_stclkctrl.v
index 30221aa2af4c4e618d43a84b21db796883ad6ae8..b4ea23cad824aeaa73c5a8b8711e546b5fc9fa10 100644
--- a/systems/mcu/src/cmsdk_mcu_stclkctrl.v
+++ b/systems/nanosoc/src/verilog/nanosoc_mcu_stclkctrl.v
@@ -1,3 +1,14 @@
+//-----------------------------------------------------------------------------
+// NanoSoC SysTick controller adapted from Arm CMSDK Simple control for SysTick signals for Cortex-M processor
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
@@ -24,7 +35,7 @@
// Abstract : Simple control for SysTick signals for Cortex-M processor
//-----------------------------------------------------------------------------
-module cmsdk_mcu_stclkctrl #(
+module nanosoc_mcu_stclkctrl #(
// Ratio between FCLK and SysTck reference clock
parameter DIV_RATIO = 18'd01000,
diff --git a/systems/mcu/src/cmsdk_mcu_sysctrl.v b/systems/nanosoc/src/verilog/nanosoc_mcu_sysctrl.v
similarity index 98%
rename from systems/mcu/src/cmsdk_mcu_sysctrl.v
rename to systems/nanosoc/src/verilog/nanosoc_mcu_sysctrl.v
index 383b4af8544cb3249dba4825e6d44d61c7ff49fd..cfdf5d14ea1b10be9e4a49d55d64a9aa4aa9d01a 100644
--- a/systems/mcu/src/cmsdk_mcu_sysctrl.v
+++ b/systems/nanosoc/src/verilog/nanosoc_mcu_sysctrl.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// NanoSoC System Controller adapted from Arm CMSDK System Controller
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -52,7 +52,7 @@
//
//-------------------------------------
-module cmsdk_mcu_sysctrl #(
+module nanosoc_mcu_sysctrl #(
parameter BE = 0 // By default use little endian
)
diff --git a/systems/mcu/src/nanosoc_sys_ahb_decode.v b/systems/nanosoc/src/verilog/nanosoc_sys_ahb_decode.v
similarity index 97%
rename from systems/mcu/src/nanosoc_sys_ahb_decode.v
rename to systems/nanosoc/src/verilog/nanosoc_sys_ahb_decode.v
index 9bea4ac9e1b96428e54c1ccd27f57ce4c88d4309..15d6d07ced7a86532c57de25f370183d21234143 100644
--- a/systems/mcu/src/nanosoc_sys_ahb_decode.v
+++ b/systems/nanosoc/src/verilog/nanosoc_sys_ahb_decode.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// NanoSoC AHB decoder adapted from Arm CMSDK AHB decoder
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
diff --git a/systems/mcu/src/nanosoc_sysio.v b/systems/nanosoc/src/verilog/nanosoc_sysio.v
similarity index 99%
rename from systems/mcu/src/nanosoc_sysio.v
rename to systems/nanosoc/src/verilog/nanosoc_sysio.v
index 29306dc6980b8a69a41fd944ee79ae1f917ddf62..5b5f208fb3af232372de3de0865567e255898a08 100644
--- a/systems/mcu/src/nanosoc_sysio.v
+++ b/systems/nanosoc/src/verilog/nanosoc_sysio.v
@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -397,7 +397,7 @@ module nanosoc_sysio
);
// APB subsystem for timers, UARTs
- cmsdk_apb_subsystem #(
+ nanosoc_apb_subsystem #(
.APB_EXT_PORT12_ENABLE (1),
.APB_EXT_PORT13_ENABLE (1),
.APB_EXT_PORT14_ENABLE (1),
diff --git a/systems/mcu/src/cmsdk_clkreset.v b/systems/nanosoc/src/verilog/nanososc_clkreset.v
similarity index 91%
rename from systems/mcu/src/cmsdk_clkreset.v
rename to systems/nanosoc/src/verilog/nanososc_clkreset.v
index d30c3c8441cc413437ae5779d0827097bb97a8f0..c420e2dde4df7319c50bc2249ac2ae4b5c49a34f 100644
--- a/systems/mcu/src/cmsdk_clkreset.v
+++ b/systems/nanosoc/src/verilog/nanososc_clkreset.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised Cortex-M0 'nanosoc' controller
+// NanoSoC clock and power on generator adapted from Arm CMSDK Simple clock and power on reset generator
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -36,7 +36,7 @@
//-----------------------------------------------------------------------------
`timescale 1ns/1ps
-module cmsdk_clkreset(
+module nanosoc_clkreset(
output wire CLK,
output wire NRST);
diff --git a/test_io/adp_control/verilog/ADPcontrol_v1_0.v b/systems/nanosoc/test_io/adp_control/verilog/ADPcontrol_v1_0.v
similarity index 100%
rename from test_io/adp_control/verilog/ADPcontrol_v1_0.v
rename to systems/nanosoc/test_io/adp_control/verilog/ADPcontrol_v1_0.v
diff --git a/test_io/adp_control/verilog/ADPmanager.v b/systems/nanosoc/test_io/adp_control/verilog/ADPmanager.v
similarity index 100%
rename from test_io/adp_control/verilog/ADPmanager.v
rename to systems/nanosoc/test_io/adp_control/verilog/ADPmanager.v
diff --git a/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v b/systems/nanosoc/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
similarity index 100%
rename from test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
rename to systems/nanosoc/test_io/axi_stream_io/verilog/axi_stream_io_v1_0.v
diff --git a/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v b/systems/nanosoc/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
similarity index 100%
rename from test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
rename to systems/nanosoc/test_io/axi_stream_io/verilog/axi_stream_io_v1_0_axi_s.v
diff --git a/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v b/systems/nanosoc/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
similarity index 100%
rename from test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
rename to systems/nanosoc/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
diff --git a/systems/mcu/src/cmsdk_ft1248x1_adpio.v b/systems/nanosoc/test_io/nanosoc_ft1248x1_adpio.v
similarity index 97%
rename from systems/mcu/src/cmsdk_ft1248x1_adpio.v
rename to systems/nanosoc/test_io/nanosoc_ft1248x1_adpio.v
index 89ecfe668de15e22decfa5cc6e242e9427f6dde6..766afa1a5eb3c024a8739625711fd9300455444f 100644
--- a/systems/mcu/src/cmsdk_ft1248x1_adpio.v
+++ b/systems/nanosoc/test_io/nanosoc_ft1248x1_adpio.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// customised example Cortex-M0 controller UART with file logging
+// NanoSoC FT1248 ADP UART file logging
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2022, SoC Labs (www.soclabs.org)
+// Copyright � 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -15,7 +15,7 @@
//-----------------------------------------------------------------------------
-module cmsdk_ft1248x1_adpio
+module nanosoc_ft1248x1_adpio
#(parameter ADPFILENAME = "adp.cmd",
parameter VERBOSE = 0)
(
diff --git a/systems/mcu/testcodes/adp_demo/adp.cmd b/systems/nanosoc/testcodes/adp_demo/adp.cmd
similarity index 100%
rename from systems/mcu/testcodes/adp_demo/adp.cmd
rename to systems/nanosoc/testcodes/adp_demo/adp.cmd
diff --git a/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt b/systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
rename to systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
diff --git a/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj b/systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
similarity index 100%
rename from systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
rename to systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
diff --git a/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt b/systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt
similarity index 100%
rename from systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt
rename to systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvopt
diff --git a/systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvproj b/systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvproj
similarity index 100%
rename from systems/mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvproj
rename to systems/nanosoc/testcodes/apb_mux_tests/apb_mux_tests_cm0p.uvproj
diff --git a/systems/mcu/testcodes/apb_mux_tests/makefile b/systems/nanosoc/testcodes/apb_mux_tests/makefile
similarity index 100%
rename from systems/mcu/testcodes/apb_mux_tests/makefile
rename to systems/nanosoc/testcodes/apb_mux_tests/makefile
diff --git a/systems/mcu/testcodes/bootloader/bootloader_cm0.uvopt b/systems/nanosoc/testcodes/bootloader/bootloader_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/bootloader/bootloader_cm0.uvopt
rename to systems/nanosoc/testcodes/bootloader/bootloader_cm0.uvopt
diff --git a/systems/mcu/testcodes/bootloader/bootloader_cm0.uvproj b/systems/nanosoc/testcodes/bootloader/bootloader_cm0.uvproj
similarity index 100%
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rename to systems/nanosoc/testcodes/bootloader/bootloader_cm0.uvproj
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similarity index 100%
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rename to systems/nanosoc/testcodes/bootloader/bootloader_cm0p.uvopt
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similarity index 100%
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rename to systems/nanosoc/testcodes/bootloader/bootloader_cm0p.uvproj
diff --git a/systems/mcu/testcodes/bootloader/makefile b/systems/nanosoc/testcodes/bootloader/makefile
similarity index 100%
rename from systems/mcu/testcodes/bootloader/makefile
rename to systems/nanosoc/testcodes/bootloader/makefile
diff --git a/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvopt b/systems/nanosoc/testcodes/debug_tests/debug_tests_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvopt
rename to systems/nanosoc/testcodes/debug_tests/debug_tests_cm0.uvopt
diff --git a/systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvproj b/systems/nanosoc/testcodes/debug_tests/debug_tests_cm0.uvproj
similarity index 100%
rename from systems/mcu/testcodes/debug_tests/debug_tests_cm0.uvproj
rename to systems/nanosoc/testcodes/debug_tests/debug_tests_cm0.uvproj
diff --git a/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvopt b/systems/nanosoc/testcodes/debug_tests/debug_tests_cm0p.uvopt
similarity index 100%
rename from systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvopt
rename to systems/nanosoc/testcodes/debug_tests/debug_tests_cm0p.uvopt
diff --git a/systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvproj b/systems/nanosoc/testcodes/debug_tests/debug_tests_cm0p.uvproj
similarity index 100%
rename from systems/mcu/testcodes/debug_tests/debug_tests_cm0p.uvproj
rename to systems/nanosoc/testcodes/debug_tests/debug_tests_cm0p.uvproj
diff --git a/systems/mcu/testcodes/debug_tests/makefile b/systems/nanosoc/testcodes/debug_tests/makefile
similarity index 100%
rename from systems/mcu/testcodes/debug_tests/makefile
rename to systems/nanosoc/testcodes/debug_tests/makefile
diff --git a/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt b/systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
rename to systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
diff --git a/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj b/systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
similarity index 100%
rename from systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
rename to systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
diff --git a/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt b/systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt
similarity index 100%
rename from systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt
rename to systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvopt
diff --git a/systems/mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj b/systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj
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rename to systems/nanosoc/testcodes/default_slaves_tests/default_slaves_tests_cm0p.uvproj
diff --git a/systems/mcu/testcodes/default_slaves_tests/makefile b/systems/nanosoc/testcodes/default_slaves_tests/makefile
similarity index 100%
rename from systems/mcu/testcodes/default_slaves_tests/makefile
rename to systems/nanosoc/testcodes/default_slaves_tests/makefile
diff --git a/systems/mcu/testcodes/dhry/dhry_cm0.uvopt b/systems/nanosoc/testcodes/dhry/dhry_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/dhry/dhry_cm0.uvopt
rename to systems/nanosoc/testcodes/dhry/dhry_cm0.uvopt
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similarity index 100%
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rename to systems/nanosoc/testcodes/dhry/dhry_cm0.uvproj
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similarity index 100%
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similarity index 100%
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similarity index 100%
rename from systems/mcu/testcodes/dhry/makefile
rename to systems/nanosoc/testcodes/dhry/makefile
diff --git a/systems/mcu/testcodes/dhry/transcript b/systems/nanosoc/testcodes/dhry/transcript
similarity index 100%
rename from systems/mcu/testcodes/dhry/transcript
rename to systems/nanosoc/testcodes/dhry/transcript
diff --git a/systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvopt b/systems/nanosoc/testcodes/dma_tests/dma_tests_cm0.uvopt
similarity index 100%
rename from systems/mcu/testcodes/dma_tests/dma_tests_cm0.uvopt
rename to systems/nanosoc/testcodes/dma_tests/dma_tests_cm0.uvopt
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similarity index 100%
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rename to systems/nanosoc/testcodes/dma_tests/dma_tests_cm0.uvproj
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similarity index 100%
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similarity index 100%
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rename to systems/nanosoc/testcodes/dma_tests/dma_tests_cm0p.uvproj
diff --git a/systems/mcu/testcodes/dma_tests/makefile b/systems/nanosoc/testcodes/dma_tests/makefile
similarity index 100%
rename from systems/mcu/testcodes/dma_tests/makefile
rename to systems/nanosoc/testcodes/dma_tests/makefile
diff --git a/systems/mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt b/systems/nanosoc/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt
similarity index 100%
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rename to systems/nanosoc/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvproj
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rename to systems/nanosoc/testcodes/dualtimer_demo/dualtimer_demo_cm0p.uvproj
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similarity index 100%
rename from systems/mcu/testcodes/dualtimer_demo/makefile
rename to systems/nanosoc/testcodes/dualtimer_demo/makefile
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similarity index 100%
rename from systems/mcu/testcodes/generic/config_id.h
rename to systems/nanosoc/testcodes/generic/config_id.h
diff --git a/systems/mcu/testcodes/generic/mcu_debugtester_interface.c b/systems/nanosoc/testcodes/generic/mcu_debugtester_interface.c
similarity index 100%
rename from systems/mcu/testcodes/generic/mcu_debugtester_interface.c
rename to systems/nanosoc/testcodes/generic/mcu_debugtester_interface.c
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similarity index 100%
rename from systems/mcu/testcodes/generic/mcu_debugtester_interface.h
rename to systems/nanosoc/testcodes/generic/mcu_debugtester_interface.h
diff --git a/systems/mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt b/systems/nanosoc/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt
similarity index 100%
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diff --git a/systems/mcu/verif/ft1248x1_to_axi_streamio_v1_0.v b/systems/nanosoc/verif/ft1248x1_to_axi_stream_io_v1_0.v
similarity index 99%
rename from systems/mcu/verif/ft1248x1_to_axi_streamio_v1_0.v
rename to systems/nanosoc/verif/ft1248x1_to_axi_stream_io_v1_0.v
index e09c10337424d36584b15b137c0e0e8e4ebe070e..96ba001af4ac83c70af5558f18e61f79f0f73c5d 100644
--- a/systems/mcu/verif/ft1248x1_to_axi_streamio_v1_0.v
+++ b/systems/nanosoc/verif/ft1248x1_to_axi_stream_io_v1_0.v
@@ -13,7 +13,7 @@
// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
//-----------------------------------------------------------------------------
- module ft1248x1_to_axi_streamio_v1_0 #
+ module ft1248x1_to_axi_stream_io_v1_0 #
(
// Users to add parameters here
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diff --git a/systems/mcu/src/cmsdk_uart_capture.v b/systems/nanosoc/verif/nanosoc_uart_capture.v
similarity index 98%
rename from systems/mcu/src/cmsdk_uart_capture.v
rename to systems/nanosoc/verif/nanosoc_uart_capture.v
index cbc46f7ed04fd18feaa300f2e03dc542864feb42..4862d12b541afc65fee97fdff555c69916bf3282 100644
--- a/systems/mcu/src/cmsdk_uart_capture.v
+++ b/systems/nanosoc/verif/nanosoc_uart_capture.v
@@ -1,12 +1,12 @@
//-----------------------------------------------------------------------------
-// updated UART RXD capture with file logging
+// NanoSoC UART RXD capture with file logging adapted from Arm CMSDK Uart Capture
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
-// Copyright � 2021, SoC Labs (www.soclabs.org)
+// Copyright � 2021, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
@@ -51,7 +51,7 @@
// ESC - 0x12 Clear DEBUG_TESTER_ENABLE to 0
-module cmsdk_uart_capture
+module nanosoc_uart_capture
#(parameter LOGFILENAME = "uart.log",
parameter VERBOSE = 0)
(
diff --git a/systems/mcu/verif/tb_nanosoc.v b/systems/nanosoc/verif/tb_nanosoc.v
similarity index 100%
rename from systems/mcu/verif/tb_nanosoc.v
rename to systems/nanosoc/verif/tb_nanosoc.v
diff --git a/systems/mcu/verif/track_tb_iostream.v b/systems/nanosoc/verif/track_tb_iostream.v
similarity index 100%
rename from systems/mcu/verif/track_tb_iostream.v
rename to systems/nanosoc/verif/track_tb_iostream.v