From 7cba872f1d29fd09582c4b6bc6c20256293ecd0b Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 15 Feb 2023 11:37:11 +0000
Subject: [PATCH] update DMA and debug tests and RTL now diagnostics run and
 pass

---
 .../software/common/debug_tests/debug_tests.h |  2 +-
 .../software/common/retarget/uart_stdout.c    |  4 +-
 .../software/common/validation/dma_tests.c    |  2 +-
 .../mcu/testcodes/debug_tests/makefile        |  2 +-
 .../systems/mcu/verilog/nanosoc_chip.v        | 77 +++++++------------
 .../nanosoc/systems/mcu/verilog/nanosoc_cpu.v | 12 ++-
 .../nanosoc/systems/mcu/verilog/tb_nanosoc.v  | 34 --------
 7 files changed, 39 insertions(+), 94 deletions(-)

diff --git a/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h
index 3c4602e..cb90905 100644
--- a/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h
+++ b/Cortex-M0/nanosoc/software/common/debug_tests/debug_tests.h
@@ -73,7 +73,7 @@
 
 // A convenient way to access the AHB Default Slave
 // (1st word above top of RAM)
-#define AHBDEFAULTSLAVE ((volatile uint32_t *) ((uint32_t) 0x20010000))
+#define AHBDEFAULTSLAVE ((volatile uint32_t *) ((uint32_t) 0x40020000))
 
 
 //Function definition
diff --git a/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c
index a962275..c356bd0 100644
--- a/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c
+++ b/Cortex-M0/nanosoc/software/common/retarget/uart_stdout.c
@@ -57,8 +57,8 @@ void UartStdOutInit(void)
 // Output a character
 unsigned char UartPutc(unsigned char my_ch)
 {
-  while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
-  CMSDK_UART2->DATA = my_ch; // write to transmit holding register
+//  while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
+//  CMSDK_UART2->DATA = my_ch; // write to transmit holding register
   while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
   CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
   return (my_ch);
diff --git a/Cortex-M0/nanosoc/software/common/validation/dma_tests.c b/Cortex-M0/nanosoc/software/common/validation/dma_tests.c
index 5c06eb9..88e1567 100644
--- a/Cortex-M0/nanosoc/software/common/validation/dma_tests.c
+++ b/Cortex-M0/nanosoc/software/common/validation/dma_tests.c
@@ -407,7 +407,7 @@ int dma_interrupt_test(void)
   NVIC_EnableIRQ(DMA_IRQn);
 
   /* Generate DMA transfer to invalid memory location */
-  dma_memory_copy ((unsigned int) &source_data_array[0],0x1F000000, 2, 4);
+  dma_memory_copy ((unsigned int) &source_data_array[0],0xEF000000, 2, 4);
   delay();
   /* Can't guarantee that there is sleep support, so use a polling loop */
   do { /* Wait until PL230 DMA controller return to idle state */
diff --git a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile
index bb0cdf6..1c0d5f1 100644
--- a/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile
+++ b/Cortex-M0/nanosoc/systems/mcu/testcodes/debug_tests/makefile
@@ -29,7 +29,7 @@
 # Choose the core instantiated, can be
 #  - CORTEX_M0
 #  - CORTEX_M0PLUS
-CPU_PRODUCT = CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
 
 # Shared software directory
 SOFTWARE_DIR = ../../../../software
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
index fe5fd48..02d9255 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -55,12 +55,6 @@ module nanosoc_chip
   output wire  [15:0]  p1_o, // output port drive
   output wire  [15:0]  p1_e, // active high output drive enable (pad tech dependent)
   output wire  [15:0]  p1_z, // active low output drive enable (pad tech dependent)
-
-`ifdef ARM_CMSDK_INCLUDE_JTAG
-  input  wire          ntrst_i,
-  input  wire          tdi_i,
-  output wire          tdo_o,
-`endif
   input  wire          swdio_i,
   output wire          swdio_o,
   output wire          swdio_e,
@@ -184,13 +178,13 @@ localparam    CORTEX_M0 = 1;
     wire         PCLKEN;  // Clock divider for AHB to APB bridge
     wire         APBACTIVE;
   // event signals
-    wire              TXEV;
-    wire              RXEV;
-    wire               nTRST;            // JTAG - Test reset (active low)
-    wire               SWDI;          // JTAG/SWD - TMS / SWD data input
-    wire               SWCLK;         // JTAG/SWD - TCK / SWCLK
-    wire               SWDO;             // SWD - SWD data output
-    wire               SWDOEN;           // SWD - SWD data output enable
+    wire         TXEV;
+    wire         RXEV;
+    wire         nTRST;            // JTAG - Test reset (active low)
+    wire         SWDI;          // JTAG/SWD - TMS / SWD data input
+    wire         SWCLK;         // JTAG/SWD - TCK / SWCLK
+    wire         SWDO;             // SWD - SWD data output
+    wire         SWDOEN;           // SWD - SWD data output enable
     wire         SYSRESETREQ;    // processor system reset request
     wire         WDOGRESETREQ;   // watchdog system reset request
     wire         HRESETREQ;      // Combined system reset request
@@ -209,7 +203,7 @@ localparam    CORTEX_M0 = 1;
     wire         CDBGPWRUPREQ;     // Debug Power Up request to PMU
     wire         CDBGPWRUPACK;     // Debug Power Up ACK from PMU
     wire         SLEEPHOLDREQn;    // Sleep extension request from PMU
-    wire         SLEEPHOLDACKn;    // Sleep extension request to PMU    wire         SLEEPING;
+    wire         SLEEPHOLDACKn;    // Sleep extension request to PMU
     wire         SYSPWRDOWNACK;
     wire         DBGPWRDOWNACK;
     wire         SYSPWRDOWN;
@@ -292,13 +286,13 @@ localparam    CORTEX_M0 = 1;
   (// Inputs
    .GLOBALRESETn      (nrst_in),
    .FCLK              (FCLK),
-   .HCLK              (HCLK), //gated_hclk),
-   .DCLK              (DCLK), //gated_dclk),
+   .HCLK              (gated_hclk),
+   .DCLK              (gated_dclk),
    .SYSRESETREQ       (cmsdk_SYSRESETREQ),
    .PMUHRESETREQ      (PMUHRESETREQ),
    .PMUDBGRESETREQ    (PMUDBGRESETREQ),
-   .RSTBYPASS         (1'b0),
-   .SE                (1'b0),
+   .RSTBYPASS         (TESTMODE),
+   .SE                (SCANENABLE),
 
    // Outputs
    .PORESETn          (PORESETn),
@@ -1327,8 +1321,8 @@ localparam AWRAM9 = 14; // 16KB
   // Cortex-M0 integration level
   nanosoc_cpu
   u_nanosoc_cpu (
-    .HCLK             (HCLK),
-    .FCLK              (FCLK),
+    .HCLK             (gated_hclk), //HCLK),
+    .FCLK             (FCLK),
     .DCLK             (DCLK),
     .SCLK             (SCLK),
     .HRESETn          (HRESETn),
@@ -1362,6 +1356,10 @@ localparam AWRAM9 = 14; // 16KB
      .WAKEUP         (WAKEUP       ), // Wake up request from WIC
      .WICENREQ       (WICENREQ     ), // WIC enable request from PMU
      .WICENACK       (WICENACK     ), // WIC enable ack to PMU
+     .SLEEPHOLDREQn  (SLEEPHOLDREQn),
+     .SLEEPHOLDACKn  (SLEEPHOLDACKn),
+     .CDBGPWRUPACK   (CDBGPWRUPACK),
+     .CDBGPWRUPREQ   (CDBGPWRUPREQ),
      .LOCKUP         (LOCKUP),            // Core is locked-up
      .GATEHCLK       (GATEHCLK),
      .SYSRESETREQ    (SYSRESETREQ),       // System reset request
@@ -1493,15 +1491,6 @@ localparam AWRAM9 = 14; // 16KB
  assign exp12_pready = 1'b1;
  assign exp13_pready = 1'b1;
  
-  // Internal Debug signals
-  wire               i_trst_n;
-  wire               i_swditms;
-  wire               i_swclktck;
-  wire               i_tdi;
-  wire               i_tdo;
-  wire               i_tdoen_n;
-  wire               i_swdo;
-  wire               i_swdoen;
 
   // Serial wire debug is used.  nTRST, TDI and TDO are not needed
 
@@ -1510,19 +1499,11 @@ localparam AWRAM9 = 14; // 16KB
 // I/O port pin muxing and tristate
 //----------------------------------------
 
-
-  assign        i_swclktck    =  swdclk_in;
-  assign        i_swditms     =  swdio_in;
-  assign        swdio_out     =  i_swdo;
-  assign        swdio_out_en  =  i_swdoen;
-  assign        swdio_out_nen = !i_swdoen;
-
-  assign        swdclk_in     =  swdclk_i;
-  assign        swdio_in      =  swdio_i;
-
-  assign        swdio_o       =  swdio_out;
-  assign        swdio_e       =  swdio_out_en;
-  assign        swdio_z       =  swdio_out_nen;
+  assign        SWCLK         =  swdclk_i;
+  assign        SWDI          =  swdio_i;
+  assign        swdio_o       =  SWDO;
+  assign        swdio_e       =  SWDOEN;
+  assign        swdio_z       =  !SWDOEN;
 
   cmsdk_mcu_pin_mux
     u_pin_mux (
@@ -1554,14 +1535,14 @@ localparam AWRAM9 = 14; // 16KB
     .p1_altfunc       (p1_altfunc),
 
     // Debug
-    .i_trst_n         (i_trst_n),
+    .i_trst_n         ( ),
     .i_swditms        ( ), //i_swditms),
     .i_swclktck       ( ), //i_swclktck),
-    .i_tdi            (i_tdi),
-    .i_tdo            (i_tdo),
-    .i_tdoen_n        (i_tdoen_n),
-    .i_swdo           (i_swdo),
-    .i_swdoen         (i_swdoen),
+    .i_tdi            ( ),
+    .i_tdo            ( ),
+    .i_tdoen_n        ( ),
+    .i_swdo           ( ),
+    .i_swdoen         ( ),
 
     // IO pads
     .p1_out_mux       (p1_out_mux),
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
index c6185ea..29ee363 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
@@ -88,10 +88,14 @@ module nanosoc_cpu #(
   output wire          WAKEUP,           // Wake up request from WIC
   input  wire          WICENREQ,         // WIC enable request from PMU
   output wire          WICENACK,         // WIC enable ack to PMU
+  input  wire          SLEEPHOLDREQn,    // Sleep extension request from PM
+  output wire          SLEEPHOLDACKn,    // Sleep extension request to PMU
+  input  wire          CDBGPWRUPREQ,    // Sleep extension request from PM
+  output wire          CDBGPWRUPACK,    // Sleep extension request to PMU
   input  wire          SYSRESETREQ,      // System reset request
   input  wire          WDOGRESETREQ,     // Watchdog reset request
   input  wire          ADPRESETREQ,      // ADP Debug reset request
-  
+
   // Serial-Wire Debug
   input  wire          SWDI,             // SWD data input
   input  wire          SWCLK,            // SWD clock
@@ -111,12 +115,6 @@ module nanosoc_cpu #(
   wire               LOCKUPRESET;      // System Controller cfg - reset if lockup
   wire               PMUENABLE;        // System Controller cfg - Enable PMU
 
-  wire               CDBGPWRUPREQ;     // Debug Power Up request to PMU
-  wire               CDBGPWRUPACK;     // Debug Power Up ACK from PMU
-  wire               SLEEPHOLDREQn;    // Sleep extension request from PMU
-  wire               SLEEPHOLDACKn;    // Sleep extension request to PMU
-
-
   // SysTick timer signals
   wire              STCLKEN;
   wire     [25:0]   STCALIB;
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
index 19fedd8..8ab7912 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
@@ -109,11 +109,6 @@ SROM_Ax32
   .NRST       (NRST),   // active low reset
   .P0         (P0),
   .P1         (P1),
-`ifdef ARM_CMSDK_INCLUDE_JTAG
-  .nTRST      (nTRST),  // Not needed if serial-wire debug is used
-  .TDI        (TDI),    // Not needed if serial-wire debug is used
-  .TDO        (TDO),    // Not needed if serial-wire debug is used
-`endif
   .SWDIOTMS   (SWDIOTMS),
   .SWCLKTCK   (SWCLKTCK)
   );
@@ -428,21 +423,6 @@ wire ft_txd2uart;
  // --------------------------------------------------------------------------------
  // Debug tester connection -
  // --------------------------------------------------------------------------------
-
-  `ifdef CORTEX_M0DESIGNSTART
-   // No debug connection for Cortex-M0 DesignStart
-   assign nTRST    = NRST;
-   assign TDI      = 1'b1;
-   assign SWDIOTMS = 1'b1;
-   assign SWCLKTCK = 1'b1;
-
-   bufif1 (P0[31-16], debug_running, debug_test_en);
-   bufif1 (P0[30-16], debug_err, debug_test_en);
-
-   pullup (debug_running);
-   pullup (debug_err);
-
-  `else
   `ifdef ARM_CMSDK_INCLUDE_DEBUG_TESTER
 
   // Add pullups and pulldowns on Debug Interface
@@ -504,20 +484,6 @@ wire ft_txd2uart;
    .SWDIOTMS                            (SWDIOTMS)
    );
 
-
-  `else
-   assign nTRST    = NRST;
-   assign TDI      = 1'b1;
-   assign SWDIOTMS = 1'b1;
-   assign SWCLKTCK = 1'b1;
-
-   bufif1 (P0[31-16], debug_running, debug_test_en);
-   bufif1 (P0[30-16], debug_err, debug_test_en);
-
-   pullup(debug_running);
-   pullup(debug_err);
-
-  `endif
   `endif
 
  // --------------------------------------------------------------------------------
-- 
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